Device and method for processing an input signal voltage

Abstract

A method for processing an input signal voltage, comprising - storing a charge in a reference capacity (30); - setting an input capacitance (45) to the input signal voltage; - while the input capacitance (45) is set to the input signal voltage, carrying out a charge redistribution between the reference capacitance (30) and the input capacitance (45); and - based on the charge redistribution, deriving an output signal, wherein a product of the voltage across the reference capacitance (30) and the ratio of the size of the reference capacitance (30) and the size of the input capacitance (45) is based on the output signal.

Description

The present disclosure relates to a circuit for processing an input signal voltage using a threshold voltage.In recent years, voltage comparators have become typical devices in microcontrollers. Typically, the accuracy of the comparator is important.The accuracy of a comparator can be achieved at the time of manufacturing a device including the comparator. Given a given predetermined input voltage, the comparator may be set to provide an expected output. However, there is a need for comparators that are accurate over the long term, i.e., despite the long term effects that are negligible at the time of manufacture.There is often a need for a comparator to continuously sample an input signal. The comparators which continuously sample an input signal accurately tend to be complicated, and therefore such comparators are slow. However, there is also a need for comparators that are fast.Further, an output signal of continuous-time comparators tends to toggle when the input signal is close to a comparator threshold. Conventionally, a feedforward loop is used to reduce switching back and forth. However, a feedforward loop that is accurate and fast requires a lot of area and consumes a lot of power. There is a desire to reduce the surface area required for circuitry related to positive feedback and / or to reduce power consumption related to suppression of switching back and forth.US 2014 / 0 184 435 A1 discloses an analog-to-digital converter with registers for successive approximation with a plurality of circuits for capacitive sensing. A feedback circuit includes a comparator having a positive input coupled to a first node and a negative input coupled to a second node. The circuit includes a switch which, when closed, short circuits the inputs of the comparator. In a path from signal inputs into the circuit to the inputs of the comparator, the circuit in each case contains a capacitor which can be separated from the input into the circuit by first switches and from the respective input into the comparator by second switches. Further, feedback capacitors are coupled to the first node and the second node, respectively. During a feedback reset phase, the switch is closed and a select signal is applied to each feedback capacitor so that the difference between voltages is substantially reduced to zero. During a detection phase, input signals to the nodes are shifted by, among other things, opening the first switches while closing the second switches.The independent claims define the invention in various aspects. The dependent claims set forth the embodiments according to the invention in the various aspects. Hereinafter, the disclosure will be further explained and described by way of specific exemplary embodiments with reference to the accompanying drawings.In one aspect, a circuit for processing an input signal voltage includes an input capacitance coupled between an input node of the circuit and a sense node of a comparator and a reference capacitance coupled to the sense node of the comparator.In one aspect, a method for processing an input signal voltage includes configuring a reference capacitance coupled to an input capacitance; during a charging phase, charging the reference capacitance to a reference voltage of a first level and obtaining a threshold voltage at a sensing node between the reference capacitance and the input capacitance; during an operating phase, setting the input capacitance to the input signal voltage to obtain a sensing voltage at the sensing node; and forming a digital signal representing the sensing voltage being above or below the threshold voltage, e.g., positive or negative.In one aspect, a circuit for processing an input signal voltage includes a comparator including a sense node coupled to an input terminal for the input signal voltage and a reference capacitance coupled to the sense node, the reference capacitance configurable based on an output signal of the comparator.In one aspect, a method for processing an input signal voltage includes storing a charge in a reference capacitance; setting an input capacitance to the input signal voltage, the reference capacitance and the input capacitance sharing a common node; and setting a sensing node of a comparator to a voltage at the common node, wherein a charge redistribution between the input capacitance and the reference capacitance across the common node is based on an output signal of the comparator.In one aspect, a circuit for processing an input signal voltage includes a first comparator including a sense node of the first comparator and an output node of the first comparator; a second comparator including a sense node of the second comparator and an output node of the second comparator; a comparator selection switch coupled between a path input terminal of the circuit and the sense node of the first comparator and the sense node of the second comparator; and an output circuit coupled to the output of the first comparator and the output node of the second comparator; wherein the comparator selection switch is configured to connect the path input terminal to at least one of the sensing node of the first comparator and the sensing node of the second comparator, and wherein the output circuit is configured to form a comparator output signal of the circuit based on an output signal of the first comparator received from the output node of the first comparator and / or on an output signal of the second comparator received from the output node of the second comparator.In one aspect, a circuit for processing an input signal voltage comprises a first comparator including a sense node of the first comparator and a reference capacitance coupled to the sense node of the first comparator; a second comparator including a sense node of the second comparator; and a comparator selection switch coupled between a path input terminal of the circuit and the sense node of the first comparator and the sense node of the second comparator, wherein the comparator selection switch is configured to selectively couple the path input terminal to one of the sense node of the first comparator and the sense node of the second comparator.In one aspect, a circuit for processing a plurality of input signal voltages includes a plurality of path input terminals coupled to a plurality of path output terminals via a plurality of comparators arranged in parallel, the plurality of comparators including more comparators than there are path input terminals coupled to the path output terminals; and an output circuit coupled to a plurality of output nodes of the plurality of comparators, the output circuit configured to form a plurality of comparator output signals of the circuit based on a logical combination of a plurality of output signals received from the plurality of comparator output nodes.In one aspect, a circuit for processing multiple input signals includes multiple path input terminals coupled to multiple path output terminals via multiple comparators arranged in parallel, the multiple comparators including more comparators than there are path input terminals coupled to the path output terminals.In one aspect, a method for processing at least one input signal voltage in a circuit, wherein the circuit includes at least one path input terminal coupled to at least one path output terminal via a plurality of comparators, and wherein the plurality of comparators include more comparators than there are path input terminals coupled to the path output terminals, comprises selectively establishing, for each path input terminal, coupling via a comparator of two comparators provided in parallel to form a coupling path from the path input terminal to an associated path output terminal while interrupting the coupling via the other comparator.The novel features believed characteristic of the invention are set forth in the appended claims. Both the invention itself and a manner of use, but other objects and advantages thereof will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: FIG. 1 shows a block diagram schematically illustrating a circuit in a first embodiment. FIG. 2 shows a block diagram illustrating an example detail of the circuit shown in FIG. 1. FIG. 3 shows a block diagram illustrating an example detail of the circuit shown in FIG. 1. FIG. 4 shows a block diagram illustrating an example detail of the circuit shown in FIG. 1. FIG. 5 is a schematic diagram illustrating a circuit in a third embodiment. FIG. 6 is a table illustrating the states of the circuit in FIG. 5. FIG. 7 is a schematic diagram illustrating a circuit in a third embodiment. FIG. 8 is a table illustrating the states of the circuit in FIG. 7. FIG. 9 is a schematic diagram illustrating a circuit in a second embodiment. FIG. 10 is a table illustrating the states of the circuit in FIG. 9.The present disclosure will now be described with reference to the figures of the accompanying drawings, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures and devices are not necessarily drawn to scale. Like terms as used herein refer to like elements throughout the specification. In some instances, well-known features are omitted or simplified to clarify the description of the example implementations.In an embodiment, a circuit in a comparator unit for processing an input signal voltage VINusing a threshold voltage VTHincludes an input capacitance coupled between an input node of the circuit and a sensing node of a comparator and a reference capacitance provided as a capacitive network coupled to the sensing node of the comparator. The comparator unit is also referred to herein as a comparator function circuit block.FIG. 1 shows a block diagram schematically illustrating a circuit in an embodiment. The circuit is configured as a comparator function circuit block 100, also referred to briefly as a 'comparator block'. The comparator function circuit block 100 comprises an input section 44 coupled to an input terminal 10 of the comparator block 100 and to a ground terminal 11. The comparator block 100 includes a comparator circuit portion 50 coupled to the input portion 44 and to an output terminal 70. The comparator block 100 further includes a reference capacitance 30 coupled to the input portion 44 and to the comparator circuit portion 50 via a sense node 40.In some embodiments, in addition to coupling the reference capacitance 30 to the comparator circuit portion 50 via the sense node 40, a control connection 60 is provided to couple the comparator circuit portion 50 to the reference capacitance 30. In some embodiments, the control connection 60 is configured to provide an output signal from the comparator circuit portion 50 as a control signal of the reference capacitance 30, e.g., for use in controlling the capacitive network in the reference capacitance 30. In some embodiments, the control connection 60 includes a control unit 64 configured to process an output signal, e.g., a digital output signal voltage VOUT, received from the comparator circuit portion 50 and form the control signal based on the output signal. In some embodiments, the controller 64 is configured to process an external control signal provided to the controller 64 via an external control connection 62. In some embodiments, the controller 64 is configured to control the configuration of the capacitive network of the reference capacitance 30, e.g., the switch settings, based on at least one of the output signals from the comparator circuit 50 and the external control signal. In some embodiments, the controller 64 is configured to control the input section 44. The controller 64 may be any processing means, e.g., a microcontroller, or programmable logic device, particularly configured or configured to perform the acts described herein. The control unit 64 may be arranged in common with the comparator block 100 or may form a portion of the comparator block 100. In some embodiments, the controller 64 is external to the comparator block 100.Further, the reference capacitance 30 is coupled to a reference voltage node 33 of the first level and to a reference voltage node 34 of the second level. In some embodiments, reference capacitance 30 is coupled to one or more further level reference voltage nodes (not shown), such as a third level reference voltage node. The reference capacitance 30 may be provided as a capacitive network. Thus, the reference capacitance 30 may include multiple capacitances. Generally, the reference capacitance 30 may be configurable in terms of the magnitude of the capacitance connected to either the first level reference voltage node 33 or the second level reference voltage node 34. As described below in one example, at least one capacitance of the plurality of capacitances of the capacitive network may be provided as a switched capacitance that is selectively controllable to configure the capacitive network when the reference capacitance 30 is provided as a capacitive network.Now, the structure and operation of the comparator function circuit block 100 (the comparator block 100) will be described in more detail.FIG. 2 shows a block diagram illustrating an example detail of the circuit shown in FIG. 1. Generally, the comparator circuit portion 50 may include a comparator circuit 55 configured to operate as a differential comparator having a first sensing node and a second sensing node. In some embodiments, the first sense node of the comparator circuit 55 is also the sense node of the comparator circuit portion 50, whereas the second sense node of the comparator circuit 55 is used as a reference node that can be held within the comparator circuit portion 50. The comparator circuit 55 may be configured to form an output signal voltage VOUT representative of a voltage difference between the sense node and the reference node that is positive or negative. Thus, in fact, the output signal is digital, i.e. it represents a logic "0" and a logic "1.".Still referring to the embodiment illustrated in FIG. 2, now in more detail, the comparator circuit portion 50 includes the comparator circuit 55 having the first sense node 51, the second sense node 52, and an output node 57. The first sense node 51 may be set to a sense node voltage VSN. The second sensing node 52 may be set to a threshold voltage VTH. The comparator circuit 55 is configured to compare the sense node voltage VSNat the first sense node 51 with the threshold voltage VTHat the second sense node 52, and output an output signal voltage VOUTat the output node 57 indicating that either the sense node voltage VSNis greater than the threshold voltage VTHor the threshold voltage VTHis greater than the sense node voltage VSN. Thus, the output signal from the comparator circuit 55 is digital.Still referring to the embodiment illustrated in FIG. 2, the circuit may further include a common mode switch 54 coupled between the first sense node 51 and the second sense node 52 of the comparator circuit 55. The first sense node 51 and the second sense node 52 may be connected via the common mode switch 54.Output node 57 is coupled to control link 60 via branch node 53. Based on the output signal voltage VOUT, the control link 60 may transmit an output signal from the comparator circuit 55. The control connection may be implemented as a wire line. A wireless implementation may also be contemplated, e.g., to filter the noise from the output signal to be transmitted over the control link or to otherwise reduce an effect of the noise on the output signal. As discussed above with respect to FIG. 1, the control link 60 may include the controller 64 (not shown in FIG. 2 ). In some embodiments, the second sense node 52 of the comparator circuit 55 is coupled to a bias output node (not shown) of the comparator via the common mode switch 54. There may be at least one effect that offset of the comparator circuit 55 can be adjusted using an external bias voltage.In general, the circuit of the comparator function circuit block 100 may have an input terminal configured to be set to the input signal voltage VIN. An input switch may be coupled between the input terminal and the input node. In some embodiments, the circuit further comprises a reference terminal configured to be set to a reference input voltage and a reference switch coupled between a reference terminal and the input node, wherein the reference switch is configured to be closed when the common mode switch is closed. In some embodiments, the reference terminal is configured to be set to a supply voltage. In some embodiments, the reference terminal is configured to be set to a voltage at ground VGND.FIG. 3 shows a block diagram illustrating an exemplary detail of the circuit of the comparator function circuit block shown in FIG. 1. The input portion 44 of the circuit in the comparator block 100 includes an input capacitance 45 having a first conductor coupled to the input terminal 10 via an input node 43 and an input switch 41. Further, the first conductor is coupled to the ground terminal 11 via the input node 43 and a ground switch 42. The input capacitance 45 includes a second conductor coupled to the sense node 40. In some embodiments, the circuit is configured to have the input node 43 set to the input signal voltage VINwhile the common mode switch 54 is open. In some embodiments, the input switch 41 is configured to be open during a charging phase of 'refreshing' the charge in the input capacitance 45 and the reference capacitance 30, and to be closed during an operating phase of the circuit, e.g., in which the input signal voltage is to be sampled. In some embodiments, the comparator block 100 is configured to have the input capacitance 45 set to a reference input voltage level VGND, while the common mode switch 54 is closed. Thus, if the common mode switch 54 is closed, the first sense node 51 and the second sense node 52 are set to the same voltage, i.e., VTH=VSN. Further, the comparator block 100 may be configured to have an input capacitance 45 set to the reference input voltage level VGNDto charge the reference capacitance 30.In some embodiments, generally, the at least one switched capacitance is coupled to a reference node of the first level via a switch of the first level, while being coupled to a reference node of the second level via a switch of the second level. In some embodiments, the first level switch and / or the second level switch may be selectively controlled to configure the reference capacitance. In some embodiments, the first level switch and the second level switch are configured not to be simultaneously closed or simultaneously open. Nevertheless, it should be appreciated that in some implementations, during a process of switching, i.e., during a process of changing the setting of the switch from open to closed or from closed to open, a transient open state may occur in which both the first level switch and the second level switch are open; similarly, in some implementations, a transient closed state may occur in which both the first level switch and the second level switch are closed. In some embodiments, the first level switch and the second level switch are integrated to form a toggle switch configured to connect between the switched capacitance and either the first level reference node or the second level reference node.FIG. 4 shows a block diagram illustrating another exemplary detail of the circuit in the comparator function circuit block shown in FIG. 1. The reference capacitance capacitive network 30 includes a first switched capacitance 31 and a second switched capacitance 32. while in the embodiment illustrated in FIG. 4, the capacitive network includes two switched capacitances, any other number of switched capacitances may be implemented as desired. In the example illustrated in FIG. 4, a capacitance value of the first switched capacitance 31 and a capacitance value of the second switched capacitance 32 are the same. However, in another implementation, the capacitance value of the first switched capacitance 31 is twice as large as the capacitance value of the second switched capacitance 32. If the capacitive network includes multiple switched capacitances, these may generally be manufactured in a thermometer style, i.e., each has the same capacitance value, or they may be dimensioned in a binary style, i.e., with capacitance values that are a predetermined minimum capacitance value times a power of two, the capacitance values of neither two of the switched capacitances being no capacitance value and the same. A first conductor of the first switched capacitance 31 and a first conductor of the second switched capacitance 32 are coupled to the sense node 40. A second conductor of the first switched capacitance 31 is coupled to a reference voltage node 33 of the first level via a switch 35 of the first level. Further, a second conductor of the first switched capacitance 31 is coupled to the reference voltage node 34 of the second level via a second level switch 36. The second conductor of the second switched capacitance 32 is coupled to the reference voltage node 33 of the first level via a switch 37 of the first level. Further, the second conductor of the second switched capacitance 32 is coupled to the second level reference voltage node 34 via a second level switch 38. The first level switches 35, 37 and the second level switches 36, 38 are coupled to the control link 60 and configured to individually switch according to the control signal provided via the control link 60. In some implementations, a pair of the first-level switch 35 and the second-level switch 36 in the case of the first switched capacitance 31 (the first-level switch 37 and the second-level switch 38 in the case of the second switched capacitance 32) is configured such that the first-level switch and the second-level switch cannot be simultaneously closed. In some embodiments, the first level reference voltage node 33 is set to a first level reference voltage, e.g., a predetermined and / or constant positive reference voltage VRP, while the second level reference voltage node 34 is set to a second level reference voltage, e.g., a predetermined and / or constant negative reference voltage VRN. In some implementations, the voltage difference between the reference voltage of a first level and the reference voltage of a second level may be based on a semiconductor band gap.In some embodiments, the controller 64 (not shown in FIG. 4 ) is configured to control the reference capacitance 30. In particular, in some implementations, the control unit 64 is configured to control the at least one switched capacitance 31, 32. The control unit 64 may be configured to process a signal received from the comparator circuit portion 50 (not shown in FIG. 4 ) to configure the reference capacitance 30 based on the signal. The control unit 64 may be provided as a logic circuit, for example. In some implementations, the logic circuit is configured to process the signal received from the comparator circuit portion 50 as a digital signal. In some embodiments, the controller 64 is configured to base control of the at least one switched capacitance 31, 32 on the comparator output signal formed while the input node 43 is set to the reference input voltage level VGND. In some embodiments, the controller 64 is configured to control the switched capacitance 31, 32 to compensate for a comparator offset voltage at the sense node 51. In some embodiments, the switched capacitance controller is configured to control the switched capacitance 31, 32 to set an effective threshold voltage to a predetermined value. For example, the control unit 64 may be configured to output a plurality of digital switching signals, each digital switching signal controlling a switched capacitance of the plurality of switched capacitances 31, 32. In such an implementation, the control link 60 may include multiple control lines, each to connect to a different one of the first level switches 35, 37 and the second level switches 36, 38. In some embodiments, the switched capacitance controller is configured to control the common mode switch 54 to close the common switch 54 while the first level switch 35, 37 is closed. There may be at least one effect that the reference capacitance 30 may be charged, e.g., during a charging phase provided to recharge the reference capacitance to the reference voltage VRPof the first level. In some embodiments, the controller is configured to charge the reference capacitance 30 repeatedly. In some embodiments, the controller is configured to periodically charge the reference capacitance 30. A duration of a time period may be constant and predetermined. In some implementations, the duration may be subject to control by the controller 64.Now, in operation of the comparator function circuit block 100, the input terminal 10 is set to an input signal voltage VIN. Accordingly, the input signal voltage VIN is supplied to the input section 44. Further, the input portion 44 can tap a voltage to ground VGND using the ground terminal 11. In some embodiments, the method further includes during the charging phase, charging the input capacitance 45 to a reference input voltage level VGND. It should be appreciated that the voltage at ground VGNDmay be any reference voltage defined as ground for the purpose of a given implementation. The input section 44 contributes to a sense node voltage VSNat the sense node 40, which is also applied to the comparator circuit section 50. The comparator circuit portion 50 provides an output signal voltage VOUTto the output terminal 70 of the comparator function circuit block 100. Further, the comparator circuit section 50 sets the control connection 60 to a control signal. The control signal is applied to the reference capacitance 30. The reference capacitance 30 accesses the positive reference voltage VRPat the first level reference voltage node 33 and the negative reference voltage VRNat the second level reference voltage node 34. Further, the capacitive network of the reference capacitance 30 contributes to the sense node voltage VSNat the sense node 40. At least two modes, states, or phases of operation may be distinguished according to how the switches in the comparator block 100 are set. A charging phase and an operating phase are discussed in more detail below. Additionally, in at least some implementations, a calibration phase and / or one or more types of transition phases may be distinguished.First, the comparator function circuit block 100 is initialized. To this end, the charging phase is entered. During the charging phase, the ground switch 42 is closed in the input section 44, while the input switch 41 is open. This will be discussed further below when refreshing the charges in the capacitances 31, 32, 45 of the circuit is described. In the comparator circuit portion 50, the common mode switch 54 is closed. Consequently, the threshold voltage VTHis set to both the first sensing node 51 and the second sensing node 52. In the capacitive network of the reference capacitance 30, the first switched capacitance 31 and the second switched capacitance 32 may be controlled by a control signal. The control signal may be based on an output signal voltage VOUTof the comparator circuit 55 and provided via the signal connection 60. The control of the first switched capacitance 31 may be performed using the first-level switch 35 and the second-level switch 36. The control of the second switched capacitance 32 may be performed using the first-level switch 37 and the second-level switch 38. In some implementations, control is performed such that the charge in the first switched capacitance 31 and the second switched capacitance 32 contributes to the sense node voltage VSNto provide the effective threshold voltage of the comparator block 100 as needed. Consequently, the comparator block 100 may be set to an effective target threshold voltage. In some implementations, the initialization phase may be executed whenever adjustment of the effective threshold voltage is desired.In some implementations, the initialization is extended to perform further calibration of the comparator circuit portion 50 to account for, e.g., a comparator offset introduced when the common mode switch 54 is opened from the closed setting during the charging phase.Next, the operation phase is entered. During the operating phase, in the input section 44, the input switch 41 is closed, while the ground switch 42 is open. The input capacitance 45 is charged according to a difference from the sense node voltage VSNto the input signal voltage VIN. Thus, the input capacitance 45 actually divides the voltage VINto provide a voltage contribution VIN'=a* VINat the common node 40, where a is any factor that may be less than 1. In the comparator section, the common mode switch 54 is open. Thus, the comparator circuit 55 is operable to compare the sense node voltage VSNapplied to the first comparator sense node 51 with the threshold voltage VTHapplied to the second comparator sense node 52. Because the first comparator sensing node 51 and the second comparator sensing node 52 form high resistance elements, the first comparator sensing node 51 and the second comparator sensing node 52 hardly affect the sensing node voltage VSN. However, in the capacitive network of the reference capacitance 30, because the first switched capacitance 31 and the second switched capacitance 32 are individually switched to one of the first level reference voltage VRPand the second level reference voltage VRN, as described above with respect to the initialization, the charge of the first switched capacitance 31 and the second switched capacitance 32 may contribute to the sense node voltage VSN. There may be an effect that while the sense node voltage VSN folgt the input signal voltage VIN, the sense node voltage VSNmay be shifted by a constant voltage VCNwith respect to the input signal voltage VIN, such that VSN=a* VIN+VCN gilt. Thus, a difference deltaVIN in the input signal voltage is reflected in a difference deltaVS in the sense node voltage deltaVS=a*δVIN, wherein the constant voltage VCN causes a constant shift of the effective threshold voltage with respect to the threshold voltage VTH. While the constant voltage VCN is constant in the sense that it is not dependent on the input signal voltage VIN, it may nevertheless be varied by switching the first switched capacitance 31 and switching the second switched capacitance 32 to either the first level reference voltage VRPor the second level reference voltage VRN, as explained above with respect to the initialization phase, to store a charge of the capacitive network as a sum of the charge in the first switched capacitance 31 and in the second switched capacitance 32 together. There is no shift in sense node voltage VSNas long as the voltage across the input capacitance is constant. If the input signal voltage VINchanges, the comparator output signal voltage may change, and the controller 64 may provide a control signal to the capacitive network of the reference capacitance 30 to switch one or more of the first level switches and the second level switches. Consequently, the charge can be redistributed between the switched capacitances 31, 32 and the input capacitance 45 can be changed. Therefore, the constant voltage VCN is changed. Due to the re-balancing of the charges in the input capacitance 45 and in the capacitive network of the reference capacitance 30, a new effective threshold voltage of the comparator function circuit block 100 is obtained. Consequently, even when the input signal voltage VINis constant, switching one or more of the switched capacitances 31, 32 may change the output signal at the output node of the comparator 55.During the next charging phase, in the comparator section, the common mode switch 54 is again closed, wherein the comparator circuit 55 is operable to compare the sense node voltage VSNapplied to the first comparator sense node 51 with the threshold voltage VTHapplied to the second comparator sense node 52. In some implementations, for example, using coupling the second comparator sense node 52 to the comparator bias output node (not shown), the threshold voltage VTHmay be set to a bias point of the comparator 55. In the input portion 44, however, the input switch 41 is open. Therefore, the sense node voltage VSN is no longer based on the input signal voltage VIN. Meanwhile, the ground switch 42 is closed, and the input capacitance 45 is charged according to a difference from the sense node voltage VSNto the voltage on ground VGND, thereby refreshing a charge of the input capacitance in effect. Accordingly, the charging phase may also be referred to as a refresh phase. As described above, the charging phase is performed, for example, during initialization when the input capacitance 45 and / or the reference capacitance 30 are charged for use during the operating phase in which the comparator circuit 55 processes the input signal voltage VINto provide the sense node voltage VSNfor comparison with the threshold voltage VTH. Furthermore, the charging phase causes a refresh when the input capacitance 45 and / or the reference capacitance 30 are recharged in order to replace the charge that has leaked from the respective capacitance during a preceding operating phase, for example. In contrast, in a case where the reference capacitance 30 is provided as the plurality of capacitances, during the operation phase, the charge may be redistributed from one capacitance to another of the plurality of capacitances.An example method of processing the input signal voltage VINto provide the sense node voltage VSNfor comparison to the threshold voltage VTHincludes configuring the reference capacitance 30 coupled to the input capacitance 45; during the charging phase, charging the reference capacitance 30 to the first level reference voltage VRPto obtain the sense node voltage VSNat the sense node 40 between the reference capacitance 30 and the input capacitance 45; during the operating phase, setting the input capacitance 45 to the input signal voltage VINto obtain the sense node voltage VSNat the sense node 40; and forming an output signal voltage VOUTthat is digital and represents a difference between the threshold voltage VTHand the sense node voltage VSNthat is positive or negative. Another example method for processing the input signal voltage VINto compare the sense node voltage VSNto the threshold voltage VTHcomprises storing charge in the reference capacitance 30; setting the input signal voltage VINto the input capacitance 45, wherein the reference capacitance 30 and the input capacitance 45 share the sense node 40 as a common node; and setting the first sense node 51 of the comparator circuit 55 to the sense node voltage VSNat the sense node 40, wherein the charge of the reference capacitance 30 is based on the output signal VOUTof the comparator circuit 55. In some embodiments, configuring the reference capacitance 30 is based on the output signal VOUTof the comparator circuit 55. There may be at least one effect that a charge amount in the reference capacitance 30 may be controlled depending on a configuration of the reference capacitance 30.In some embodiments, the method generally includes a first mode of operation in which the comparator performs a comparison and a second mode of operation in which the comparator performs a reset. In some implementations, during the charging phase, the method includes configuring the reference capacitance 30 to compensate for the comparator offset voltage at the first sensing node 51 of the comparator circuit 55. In some embodiments where the reference capacitance is provided as the plurality of switched capacitances 31, 32, configuring the reference capacitance 30 includes selectively switching the switched capacitances 31, 32. the switched capacitances 31, 32 when charged may use one of at least a first reference voltage level VRPand a second reference voltage level VRN. Thus, in some embodiments, the method further comprises selectively setting the reference capacitance 30 to the second level reference voltage VRN, wherein the second level reference voltage VRN is below the first level reference voltage VRP and the input signal voltage VIN is above the reference input voltage level VGND, or wherein the second level reference voltage is above the first level reference voltage and the input signal voltage is below the reference input voltage. In some implementations, configuring the reference capacitance is performed when the comparator performs the comparison. The method may further include redistributing the charges in the reference capacitance 30 and the input capacitance 45 after storing the charge in the reference capacitance 30.In some embodiments, a difference between the first reference voltage level VRPand the second reference voltage level VRNis based on a band gap voltage. In some embodiments, the method includes, during the charging phase, feeding back an output signal voltage VOUTbased on the digital signal to the first sense node 51. The method further includes, in some implementations, with the comparator circuit being a differential comparator circuit, forming the digital signal to represent the voltage difference between the first sense node and the second sense node being positive or negative.In one implementation, control of redistribution of charge in the reference capacitance 30 and the input capacitance 45 may be used in a feedforward scheme sometimes referred to as hysteresis to avoid the digital output signal voltage VOUTschaltet. Conventionally, switching back and forth may occur in a situation where an ideal input signal voltage, i.e., having a smooth evolution with no noise over time, would simply "cross" the threshold voltage, i.e., increase close to the threshold voltage, be equal to the threshold voltage, and then be greater than the threshold voltage, or vice versa. In practice, however, the noise in the input signal voltage and / or in the threshold voltage near the crossing of the threshold voltage tends to provide a non-smooth development of the input signal voltage, which, when compared with the threshold voltage, results in a plurality of crosses within a short time interval. In this case, the digital output signal voltage switches back and forth. In contrast, the comparator function circuit block 100 described herein may be configured, in one implementation, such that upon detection of a change in the digital output signal voltage VOUT, the reference capacitance 30 is configured to effectively increase a difference between the sense node voltage VSN(the input signal voltage VIN) at the first sense node 51 of the comparator circuit 55 and the threshold voltage VTHat the second sense node 52 of the comparator circuit 55. In some implementations, the controller 64 is configured to provide a control signal to the reference capacitance 30 capacitive network that switches, e.g., the first switched capacitance 31 and / or the second switched capacitance 32. Thus, in some embodiments, most noise may be achieved not to affect the input signal voltage VINas much as the voltage difference from the sense node voltage VSNto the threshold voltage VTH. In some implementations, the comparator function circuit block may include a switched hysteresis capacitance configured to store a charge amount corresponding to a predetermined threshold voltage difference. In one example, the switched hysteresis capacitance forms part of the capacitive network of the reference capacitance 30. the switched hysteresis capacitance is implemented, for example, as the second switched capacitance 32 dedicated for use in suppressing the noise effects that, as described above, is switched regardless of the switching states of the other first switched capacitance(s) 31 of the capacitive network of the reference capacitance 30. In some implementations, the controller may be configured to switch back the switched hysteresis capacitance after a predetermined interval has elapsed from the switching of the switched hysteresis capacitance. Thus, after crossing is first detected, the predetermined interval may be used for future switching of the switched hysteresis capacitance if the input signal voltage periodically changes. In particular, in some implementations, the switching may be controlled to occur even slightly before the crossing occurs to further suppress any occurrence of switching the digital output voltage back and forth.More generally, in one aspect, a circuit for processing an input signal voltage includes a voltage processing device including a sense node coupled to an input terminal for the input signal voltage. The circuit includes an input capacitance coupled between the sense node and the input terminal in some embodiments. The circuit includes a reference capacitance coupled to the sense node. In some embodiments, the reference capacitance and the input capacitance share a common node coupled to the sense node. In some embodiments, the reference capacitance is configurable based on an output signal of the voltage processing device. In some embodiments, the input capacitance is configurable based on an output signal of the voltage processing device. The voltage processing device may be configured to form an output signal voltage based on a voltage at the sensing node. In some embodiments, the voltage processing device is provided as a comparator configured to form the output signal voltage based on a comparison of the voltage at the sensing node with a threshold voltage.Some embodiments of the circuit further comprise a control unit configured to configure the reference capacitance and / or the input capacitance based on the signal received from the voltage processing device. In some embodiments, the control unit is provided as a logic circuit configured to process the signal received from the voltage processing device as a digital signal. In some embodiments, the voltage processing device is configured to operate in at least a first mode of operation in which the voltage processing device performs the processing of the voltage at the sensing node to form the output signal voltage. The voltage processing device may be provided, for example, as a comparator configured to perform a comparison of the voltage at the sensing node with a threshold voltage. Further, the voltage processing device may be configured to operate in a second operation mode in which the circuit performs a reset. The voltage processing device performs, for example, reset. In some embodiments, the controller is configured to configure the reference capacitance to change a charge amount in the reference capacitance when the voltage processing device processes the voltage at the sensing node via a comparison of the voltage at the sensing node with the threshold voltage, e.g., when the voltage processing device is provided as a comparator.In some embodiments, the reference capacitance is coupled to a reference node of the first level via a switch of the first level. In some embodiments, the reference capacitance is coupled to a reference node of the second level via a second level switch. A difference between a voltage at the reference node of the first level and a voltage at the reference node of the second level may be based on a band gap voltage. In some embodiments, the difference of the voltage at the reference node of the first level and the voltage at the reference node of the second level is ratiometrically predetermined or determined ratiometrically during operation of the circuit.In some embodiments, the reference capacitance is configurable in size. For example, in some implementations, the reference capacitance is provided as multiple switched capacitances. In some embodiments, the input capacitance is configurable in size. For example, in some implementations, the input capacitance is provided as multiple switched capacitances. In some embodiments, both the reference capacitance and the input capacitance include at least one switched capacitance. The at least one switched capacitance can be controllable by the control unit. In some implementations, the controller is provided as a logic circuit configured to output a plurality of digital switching signals, control each digital switching signal to control a switched capacitance of the plurality of switched capacitances. In some embodiments, the reference capacitance or the input capacitance includes a switched hysteresis capacitance configured to contribute a predetermined charge to charge redistribution based on the output signal voltage.As described above with respect to the comparator function block, control of redistribution of charge in the reference capacitance and input capacitance may generally be used in a feedforward scheme. The feedforward scheme may be implemented in the embodiments of a circuit that includes a voltage processing device configured to form an output signal voltage based on the voltage at the sensing node to prevent the digital output signal voltage from switching back and forth. In one aspect, therefore, a method of processing an input signal voltage includes storing charge in a reference capacitance and setting an input capacitance to the input signal voltage. The method further includes performing a charge redistribution between the reference capacitance and the input capacitance. The method further comprises deriving an output signal based on the charge redistribution. In some implementations, a product of the voltage across the reference capacitance and the ratio of the magnitude of the reference capacitance and the magnitude of the charge in the input capacitance and the magnitude of the charge in the reference capacitance is based on the output signal.In some implementations, the method further comprises setting a first voltage across the input capacitance to a first predetermined reset voltage value. In some implementations, the method further comprises setting a second voltage across the reference capacitance to a second predetermined reset voltage value. In some implementations, the deriving of the output signal is performed during a first operating mode. In some implementations, the setting of the first voltage across the input capacitance and the setting of the second voltage across the reference capacitance are performed during a second mode of operation different from the first mode of operation. In some implementations, the method further comprises scheduling the first mode of operation and the second mode of operation in an alternating sequence.In some implementations, the method further comprises, based on the output signal, at least one of configuring the magnitude of the reference, configuring the magnitude of the input capacitance, and setting the voltage across the reference capacitance. In some implementations, the reference capacitance is provided as multiple switched capacitances, wherein configuring the reference capacitance includes selectively switching the switched capacitances. In some implementations, the switched capacitors, when charged, use one of at least a first reference voltage level and a second reference voltage level. In some implementations, a difference between the first reference voltage level and the second reference voltage level is based on one of a group comprising a band gap voltage and a ratiometric determined voltage.In some implementations, deriving the output signal includes comparing a voltage at a node between the input capacitance and the reference capacitance to a threshold voltage. In some implementations, the method further comprises forming the output signal based on a result of the comparing.Now, further implementations of the circuits and methods described above are disclosed in a more comprehensive perspective. Generally, an example circuit for processing an input signal voltage includes a first comparator including a sense node of the first comparator and an output node of the first comparator, and a second comparator including a sense node of the second comparator and an output node of the second comparator. The circuit further includes a comparator selection switch coupled between a common input terminal of the circuit, also referred to herein as a path input terminal, and the sense node of the first comparator and the sense node of the second comparator. The circuit further includes an output circuit coupled to the output of the first comparator and to the output node of the second comparator. In some implementations, the comparator selection switch is configured to connect the path input terminal to at least one of the sensing node of the first comparator and the sensing node of the second comparator. Furthermore, the output circuit is configured to form a comparator output signal of the circuit based on an output signal of the first comparator received from the output node of the first comparator and / or an output signal of the second comparator received from the output node of the second comparator. In some embodiments, the second comparator is provided structurally as the first comparator. In some embodiments, the second comparator is configured to operatively supplement the first comparator. At least one effect will be exemplified below: when the first and second comparators are used in a complementary manner, a continuous comparison operation can be achieved in a case where one or both of the first and second comparators operate discontinuously.In some embodiments, if the setting of the comparator selection switch is to connect the path input terminal to a single one of the sensing node of the first comparator and the sensing node of the second comparator, the output circuit is configured to form the comparator output signal based on a corresponding single one of the output signal of the first comparator and the output signal of the second comparator. In some embodiments, the circuit further includes an input capacitance coupled between the comparator selection switch and the sensing node of the first comparator. In some embodiments, the comparator selection switch is configured to set the input signal voltage to the input capacitance while the at least one switched capacitance is controlled to redistribute the charge in the input capacitance and the charge in the reference capacitance.In some embodiments, the output circuit is configured to form the comparator output signal of the circuit based on a logical combination of the output signal of the first comparator and the output signal of the second comparator. In some embodiments, the logical combination is a logical AND. In some embodiments, the output circuit is configured to form the comparator output signal based on a setting of the comparator selection switch. In some embodiments, the output circuit is configured to form the comparator output signal based on the logical combination if the setting of the comparator selection switch is such as to connect the input terminal to both the sensing node of the first comparator and the sensing node of the second comparator.In some embodiments, the circuit further comprises a reference capacitance coupled to the sensing node of the first comparator, the reference capacitance comprising at least one switched capacitance that is selectively controllable. In some embodiments, the comparator selection switch is configured to disconnect the input terminal from the sensing node of the first comparator while the at least one switched capacitance is controlled to set an effective threshold voltage to a predetermined value.FIG. 5 shows a schematic diagram illustrating a circuit 500 in an embodiment configured to process an input signal voltage VINusing an (internal) threshold voltage VTH. Circuit 500 includes a common input terminal, also referred to herein as a path input terminal 511, a first comparator function circuit block (comparator block) 515 having a first comparator sense node 514 coupled to path input terminal 511 via a first comparator select switch 512 and a second comparator block 525 having a second comparator sense node 524 coupled to path input terminal 511 via a second comparator select switch 522. In some embodiments, the second comparator block 525 is provided structurally as the first comparator block 515. The first comparator block 515 and / or the second comparator block 525 are configured as the comparator function circuit block 100 described above with respect to FIGS. 1-4. In particular, a first reference capacitance may be coupled to the sensing node 514 of the first comparator. In some embodiments, the second comparator block 525 includes a second reference capacitance; the second reference capacitance may be coupled to the sensing node 524 of the second comparator. In some embodiments, the input switch of the comparator function circuit block 515, 525 implements or forms the comparator select switch 512, 522.In the example illustrated in FIG. 5, the first comparator selection switch 512 is controllable to couple the path input terminal 511 to the sensing node 514 of the first comparator, while the second comparator selection switch 522 is controllable to couple the path input terminal 511 to the sensing node 524 of the second comparator. In some embodiments, the first comparator selection switch 512 and the second comparator selection switch 522 are collectively provided as a toggle switch (not shown). In some embodiments, circuit 500 further includes a first input capacitance coupled between the comparator selection switch and the sensing node 514 of the first comparator. The first comparator selection switch 512 may be configured and / or controlled to set the input signal voltage VINto the input capacitance while the first comparator block 515 performs the comparison. Similarly, circuit 500 may include a second input capacitance coupled between second comparator select switch 522 and second comparator sense node 524. The second comparator selection switch 522 may be configured and / or controlled to apply the input signal voltage VINto the input capacitance while the first comparator block 525 performs a comparison operation.In some embodiments, a filter (not shown in FIG. 5 ) is coupled between the path input terminal 511 and the sensing node 514 of the first comparator and / or the sensing node 524 of the second comparator. In some implementations, the filter may be provided as a low pass filter configured to remove the high frequency noise resulting, for example, when the input switch of the comparator function circuit block and / or the first and / or second comparator selection switch are actuated. The filter may be configured to remove the noise during switching of the first comparator selection switch 512 and / or the second comparator selection switch 522. In some embodiments, the filter is controllable. There may be at least one effect that a filter bandwidth can be controlled. In some embodiments, the filter includes a plurality of switchable resistive elements.Circuit 500 further includes an output multiplexer 518 coupled to an output node 516 of first comparator block 515 and to an output node 526 of second comparator block 525. The output multiplexer 518 is configured to form a multiplexed output signal, i.e., selectively output a voltage signal output VOUT empfangene by the first comparator block 515 and / or the second comparator block 525 to a common output terminal, also referred to herein as a path output terminal 519, coupled to the output multiplexer 518.The first comparator block 515 and / or the second comparator block 525 are configured to operate at least in a first operating mode in which the first comparator block 515 (the second comparator block 525) performs a comparison and in a second operating mode in which the first comparator block 515 (the second comparator block 525) performs a reset. Further, the first comparator block 515 (the second comparator block 525) is configured to alternate the first operating mode and the second operating mode, such that the first comparator block 515 (the second comparator block 525) performs the comparison intermittently. The phrase 'reset' as used herein includes recharging the capacitances, e.g., to replace a charge that has leaked from the capacitance during the first mode of operation, for example; recharging the capacitances is also referred to as 'capacitance refresh'. Resetting may also include readjustment, e.g., to accommodate fluctuation of the comparator offset due to a temperature change of the comparator. Reset may also include reconfiguration of the reference capacitance in some cases. Accordingly, while an interval during which the first comparator block 515 is operated in the first operating mode is referred to herein as an "operating phase" of the first comparator block 515, an interval during which the first comparator block 515 is operated in the second operating mode is also referred to as a "charging phase" of the first comparator block 515. Similarly, while an interval during which the second comparator block 525 is operated in the first operating mode is referred to herein as an operating phase of the second comparator block 525, the interval during which the second comparator block 525 is operated in the second operating mode is also referred to as a 'charging phase' of the second comparator block 525. In some embodiments, the first comparator selection switch 512 is configured to disconnect the path input terminal 511 from the sensing node 514 of the first comparator while the first comparator block 515 performs the reset. Similarly, the second comparator selection switch 522 is configured to disconnect the path input terminal 511 from the sensing node 524 of the second comparator while the second comparator block 525 performs the reset.FIG. 6 shows a table 600 illustrating the states of the circuit in FIG. 5. Table 600 provides an example overview of both the settings of first comparator select switch (labeled COMP_SEL_1 in the table) 512 and second comparator select switch (labeled COMP_SEL_2 in the table) 522 and the states of first comparator block 515 and second comparator block 525. In one phase (in the table: PHASE_ 1), both the first comparator selection switch 512 and the second comparator selection switch 522 are closed. Accordingly, both the first comparator block 515 and the second comparator block 525 are in an operating mode (referred to in the table as SAMPLE). However, in some embodiments, the second comparator block 525 is configured to operatively supplement the first comparator block 515. This can be seen in the other phases (in the table: PHASE_ 2 and PHASE_ 3) in which the first comparator selection switch 512 is closed while the second comparator selection switch 522 is open (PHASE_ 2) and in which correspondingly the first comparator block 515 is in the operating mode (SCAN) while the second comparator block 525 is in the charging mode (which is referred to in the table as REFRESH), or vice versa (PHASE_ 3). There may be at least one effect that, as long as the circuit 500 is operated according to any of the modes described above, the output multiplexer 518 may select an output signal voltage VOUTprovided at the path output terminal 519 based on the input signal voltage VIN. In yet another phase (in the table: PHASE_ 4), both the first comparator selection switch 512 and the second comparator selection switch 522 are open. In some implementations, this may occur during starting of circuit 500 or other initialization of circuit 500 when no comparator block 515, 525 is operational. Should this operating mode be implemented in the further operation of the circuit, a further comparator (not shown in FIG. 5 ) could be connected in parallel with the circuit shown in FIG. 5 to provide an output signal voltage at the path output terminal 519 that is continuously based on the input signal voltage VIN. This will be described below with respect to an implementation illustrated in FIG. 7.Generally, an example circuit for processing multiple input signal voltages includes multiple path input terminals coupled to multiple path output terminals via multiple comparators arranged in parallel, where the multiple comparators include more comparators than there are path input terminals coupled to the path output terminals. The example circuit further includes an output circuit coupled to a plurality of output nodes of the plurality of comparators. The output circuit is configured to form a plurality of comparator output signals of the circuit based on a logical combination of a plurality of output signals received from the plurality of comparator output nodes. At least one effect may be a reduction in the error in a digital output signal. One effect may be to provide a continuous time digital output signal regardless of discontinuous comparator operation. Because some discontinuous comparator concepts as explained above, e.g., with respect to the embodiments illustrated in FIGS. 1 to 5, provide more accurate comparison results than conventional continuous time comparators, an effect in continuous time operation may be to achieve more accurate comparison results.In some embodiments, each path input port is associated with a different path output port via a coupling path uniquely associated with the path input port. Each of the coupling paths may be configured to connect between the path input terminal and the path output terminal. Consequently, each path output terminal is uniquely associated with a different path input terminal via the respective coupling path. In some implementations, the circuit further includes, in each coupling path between the path input terminals and the path output terminals, at least two comparators and a comparator selection switch coupled between the path input terminal and the comparators. The comparator selection switch may be controllable to establish the connection from the path input terminal to at least one of the comparators.In some implementations, in each coupling path, at least one of the at least two comparators is provided with a reference capacitance coupled to an input node of the comparator. In some implementations, the reference capacitance includes at least one switched capacitance that is selectively controllable. The circuit may further comprise a controller configured to selectively disconnect a connection between the path input terminal and the path output terminal via the at least one comparator, wherein at least one switched capacitance is controlled to set an effective threshold voltage to a predetermined value. In some embodiments, at least two coupling paths comprise a common comparator. In some implementations, the at least two coupling paths further comprise an input multiplexer coupled between the path input ports of the at least two coupling paths and the common comparator, wherein the input multiplexer is configured to combine the input received at the path input ports of the at least two coupling paths into a combined input provided to the common comparator.In some embodiments, the at least two coupling paths include an output selection switch coupled between the common comparator and the output circuits of the at least two coupling paths. The output selection switch may be controllable to connect from the common comparator to a selected one of the output circuits of the at least two coupling paths. In some implementations, the output circuit is configured to form a comparator output signal for each coupling path based on a setting of the comparator selection switch. The output circuit may be configured in each coupling path to form the comparator output signal based on the logical combination of the output signals received from the plurality of comparator output nodes of the at least two comparators if the setting of the comparator selection switch is such as to connect the path input terminal to more than one comparator. In some implementations, the output circuit is configured to form, in each coupling path, the comparator output signal based on an output signal of the single one of the plurality of comparators if the setting of the comparator selection switch in each coupling path is such as to connect the path input terminal to a single one of the comparators. Examples of the above-described embodiments and example implementations of the underlying concepts will now be discussed with reference to FIGS. 7 to 10.FIG. 7 is a schematic diagram illustrating a circuit 700 in a third embodiment. The circuit is configured to process multiple input signal voltages VIN_ 1 and VIN_ 2 using multiple associated threshold voltages. The circuit 700 includes a plurality of path input terminals (in the example illustrated in FIG. 7, these are a first path input terminal 711 and a second path input terminal 721) coupled to a plurality of output terminals (in the example illustrated in FIG. 7, these are a first comparator block 715, a second comparator block 725 and a third comparator block 735) via a plurality of comparators arranged in parallel (in the example illustrated in FIG. 7, these are a first path output terminal 719 and a second path output terminal 729). It should be noted that the number of comparator function circuit blocks 715, 725, 735 (three in the example of FIG. 7 ) exceeds the number of path input terminals 711, 721 coupled to a first path output terminal 719 and a second path output terminal 729 (thus two path terminals in the example of FIG. 7 ) in the example. Generally, each of the path input ports 711, 721 is associated with a different path output port 719, 729. The assignment is established via a respective coupling path 710, 720 (which is indicated merely schematically in FIG. 7 with a circumcirculation with an elliptical dashed line), which is uniquely assigned to the path input connection 711, 721. Consequently, each path output terminal 719, 729 is uniquely assigned to another path input terminal 711, 721 via the respective coupling path 710, 720.The coupling paths between the path input terminals 711, 721 and the path output terminals 719, 729 each comprise at least two comparators. In some implementations, each coupling path is configured to selectively establish a connection between the path input terminal and the path output terminal only by a comparator. In the example illustrated in FIG. 7, the first path input terminal 711 is coupled to the first path output terminal 719 via a first coupling path 710. Generally, the coupling paths for each of the at least two comparators include an associated comparator selection switch coupled between the path input terminal and an associated one of the at least two comparators. The comparator selection switch may be controllable to establish the connection from the path input terminal to the associated one of the at least two comparators of the coupling path. As shown with respect to the example illustrated in FIG. 7, the first coupling path 710 extends via a first comparator selection switch 712 to a sense node 714 of the first comparator in the first comparator block 715 and via a second comparator selection switch 722 and an input multiplexer 713 to a sense node 724 of the second comparator in the second comparator block 725. Generally, in some embodiments, the at least two coupling paths further comprise an input multiplexer coupled between the input terminals of the at least two coupling paths and the common comparator. In some embodiments, the input multiplexer may be configured to select the input received at the input ports of the at least two coupling paths into a multiplexed input provided to the common comparator.Referring now to FIG. 7, the first comparator block 715 and the second comparator block 725 are both coupled to the first path output terminal 719 via a first output multiplexer 718 to complete the first coupling path 710. Similarly, the second path input terminal 721 is coupled to the second path output terminal 729 via a second coupling path 720. The second coupling path 720 extends via a third comparator selection switch 732 and the input multiplexer 713 to the sensing node 724 of the second comparator in the second comparator block 725 and via a fourth comparator selection switch 742 to a sensing node 734 of the third comparator in a third comparator block 735. The second comparator block 725 and the third comparator block 735 are both coupled to the second path output terminal 729 via a second output multiplexer 728. Generally, the output multiplexer is configured to select one of the outputs received from the at least two comparators to form a multiplexed output signal provided at the path output port.Generally, at least two coupling paths may comprise a common comparator. While both the first coupling path 710 and the second coupling path 720 include two comparators, the two coupling paths also share one comparator (the second comparator block 725). Accordingly, a control unit (not shown in FIG. 7 ) configured to control the settings of the comparator selection switches 722, 732 to avoid a situation where the second comparator block 725 is simultaneously connected to the first coupling path 710 and the second coupling path 720, at least at the time when the first input signal voltage VIN_ 1 and the second input signal voltage VIN_ 2 are set to the first path input terminal 711 and the second path input terminal 721, respectively. In general, the control unit may be configured to control the comparator selection switch and / or the output selection switch to selectively establish or interrupt the coupling path via the common comparator between the path input terminal and the path output terminal. The controller may be configured to control the comparator selection switches such that the multiplexed output signal seamlessly combines the output from the comparators of the coupling path. It may be at least one effect that the multiplexed output signal is continuously based on the input signal at the path input terminal associated with the respective path output terminal. As described above, the control unit may be configured to control the comparator selection switch and / or the output selection switch such that the combined output at a time is the output of only one comparator. In some implementations, the controller is provided as a state machine.Generally, at least one of the at least two comparators in a coupling path may be configured to operate at least in a first mode of operation in which the at least one of the at least two comparators makes a comparison and in a second mode of operation in which the at least one of the at least two comparators makes a reset, also referred to herein as a refresh. As already discussed above with respect to the circuit illustrated in the example in FIG. 7, the control unit (not shown in FIG. 7 ) may be further implemented to control the settings of the comparator selection switches 712, 722, 732, and 742 to allow the first comparator block 715, the second comparator block 725, and / or the third comparator block 735 a period of time for refreshing the reference capacitance where such capacitance is implemented, e.g., in an implementation of the respective comparator according to the exemplary embodiment illustrated in FIGS. 1 to 4 and described above. Indeed, in the illustrated implementation, while a comparator block 715 is allowed a period of time for refresh, the other comparator blocks 725, 735 are each switched into a different one of the first coupling path 710 and the second coupling path 720. In some implementations, generally, the at least two coupling paths include an output selection switch coupled between the common comparator and the path output terminals of the at least two coupling paths. In some embodiments, the output selection switch is controllable to connect from the common comparator to a selected one of the path output terminals of the at least two coupling paths.FIG. 8 shows a table 800 illustrating the states of the circuit in FIG. 7 when operated, for example, as described above. Table 800 provides an example overview of the settings of first comparator select switch 712 (labeled COMP_SEL_ 1 in table 800), second comparator select switch 722 (COMP_SEL_ 2), third comparator select switch 732 (COMP_SEL_ 3), and fourth comparator select switch 742 (COMP_SEL_ 4). In an exemplary implementation discussed above, the operation of the circuit 700 includes, for each path input terminal 711, 721 selectively establishing coupling via one comparator of the two comparator blocks 715 and 725, 725 and 735 provided in parallel to establish a coupling path 710, 720 from the path input terminal 711, 721 to an associated output terminal 719, 729 when the coupling via the other comparator is interrupted. This is illustrated in table 800 which provides an example overview of the states of the first comparator block 715, the second comparator block 725, and the third comparator block 735. In a first phase (labeled PHASE_ 1 in table 800), the first comparator select switch 712 (COMP_SEL_ 1) is open while the second comparator select switch 722 (COMP_SEL_ 2) is closed. Accordingly, the first comparator block 715 (labeled COMP_ 1 in table 800) is in the charge mode (labeled REFRESH in table 800). The first input signal voltage VIN_ 1 is thus provided to the second comparator block 725 (COMP_ 2) that is in the operating mode (referred to as SAMPLE in the table 800). Meanwhile, the third comparator selection switch 732 (COMP_SEL_ 3) is open. Consequently, the second input signal voltage VIN_ 2 is kept away from the first coupling path 710. The fourth comparator selection switch 742 (COMP_SEL_ 4) is closed, thereby providing the second input signal voltage VIN_ 2 to the third comparator block 735 (COMP_ 3) that is in the operating mode (SAMPLE).However, in some embodiments, the second comparator block 725 is configured to operatively supplement the first comparator block 715 and / or the third comparator block 735. This can be seen in the other phases (PHASE_2 and PHASE_3). In the second phase (PHASE_ 2), the first comparator selection switch 712 and the fourth comparator selection switch 742 are closed, while the second comparator selection switch 722 and the third comparator selection switch 732 are open. Accordingly, the first comparator block 715 and the third comparator block 735 are in the operating mode (SCAN) while the second comparator block 725 is in the charging mode (REFRESH). Further, in a third phase (PHASE_ 3), the fourth comparator selection switch 742 is open while the third comparator selection switch 732 is closed. Accordingly, the third comparator block 735 (COMP_ 3) is in the charge mode (REFRESH). The second input signal voltage VIN_ 2 is thus provided to the second comparator block 525 (COMP_ 2) that is in the operating mode (SAMPLE). Meanwhile, the second comparator selection switch 722 is open. Consequently, the first input signal voltage VIN_ 1 is kept away from the second coupling path 720. The first comparator selection switch 712 is closed, thereby providing the first input signal voltage VIN_ 1 to the first comparator block 715 (COMP_ 1) that is in the operating mode. There may be at least one effect that, as long as the circuit 700 is operated according to any of the above-mentioned modes, in the first coupling path 710, the first output multiplexer 718 may receive, substantially continuously from either the first comparator block 715 or the second comparator block 725, an output signal voltage VOUT_ 1 provided to the first path output terminal 719, which is based on the first input signal voltage VIN_ 1. Similarly, in the second coupling path 720, the second output multiplexer 728 may receive, either from the second comparator block 725 or from the third comparator block 735, an output signal voltage VOUT_ 2 substantially continuously provided to the second path output terminal 729 based on the second input signal VIN_ 2.In a fourth phase (PHASE_ 4), the first comparator selection switch 712, the third comparator selection switch 732, and the fourth comparator selection switch 742 are closed while the second comparator selection switch 722 is open. The first coupling path 710 uses the first comparator block 715 to form the first output signal voltage VOUT_ 1. With respect to the second coupling path 720, both the second comparator block 725 and the third comparator block 735 are used, wherein the second output multiplexer 728 may select an output signal voltage VOUT_ 2 from either the second comparator block 725 or the third comparator block 735 provided to the second path output terminal 729. The operation of the second coupling path 720 is thus similar to the operation during the fourth phase PHASE_ 4 of table 600 in FIG. 6 discussed above with respect to FIG. 5. In some implementations, a logic circuit (not shown in FIG. 7 ) may base the output signal voltage VOUT_ 2 on a logical combination, e.g., an AND combination, of the output signal provided by the second comparator block 725 and the output signal provided by the third comparator block 735.In a fifth phase (PHASE_5), the first comparator select switch 712 and the fourth comparator select switch 742 are closed as in the fourth phase (PHASE_4), but the third comparator select switch 732 is open and the second comparator select switch 722 is closed. The difference from the operation in the fourth phase (PHASE_ 4) is thus that the roles of the first coupling path 710 and the second coupling path 720 are interchanged. In an implementation, the fourth and / or the fifth phase may be transition phases occurring during a transition between the first and the second phase and / or during a transition between the second and the third phase and / or during a transition between the third and the first phase. It should be appreciated that the phrase 'transition' as used herein is not to be understood as limiting with respect to relative length, in particular a duration of the transition phase (PHASE_ 4, PHASE_ 5) should be much shorter than a duration of the other phases (PHASE 1, PHASE_ 2, PHASE_ 3). Further, the sequential numbering should not be understood as limiting. For example, a transition phase could also be implemented to occur between the third phase and the second phase, or between the third phase and the first phase, or between the second phase and the first phase.FIG. 9 is a schematic diagram illustrating a circuit 900 in a fourth embodiment. Circuit 900 is configured to process multiple input signal voltages VIN_ 1, VIN_ 2, VIN_ 3 using multiple associated threshold voltages. The circuit 900 includes a first path input terminal 911, a second path input terminal 921, and a third path input terminal 931 connected to a first path output terminal 919, a second path output terminal 929, and a third path output terminal 939, via a plurality of comparators (in the example illustrated in FIG. 9, these are a first comparator block 915, a second comparator block 925, a third comparator block 935, and a fourth comparator block 945 that are arranged in parallel). Circuit 900 is similar to both circuit 700 illustrated as an example in FIG. 7 and circuit 500 illustrated as a basic example in FIG. 5. In particular, it should be noted that the number of comparator blocks 915, 925, 935, 945 (four in the example of FIG. 9, as assumed three in the example of FIG. 7 ) exceeds the number of input terminals 911, 921, 931 coupled to the path output terminals 919, 929, 939, by one. Generally, each of the input ports 911, 921, 931 is associated with another path output port 919, 929, 939 via a coupling path 910, 920, 930 each of which is uniquely associated with one of the path input ports 911, 921, 931, whereby each path output port 919, 929, 939 is uniquely associated with another input path input port 911, 921, 931 via the respective coupling path 910, 920, 930. The structure of the example circuit 900 is conceptually similar to the structure of the example circuits 500 and 700 discussed in detail above. Therefore, detailed description will be omitted. Instead, reference is made to the examples described above.FIG. 10 shows a table 1000 illustrating some example states of the circuit in FIG. 9 when operated, e.g., as described above. Table 1000 provides an example overview of the settings of the six comparator selection switches 912, 922, 932, 942, 952, 962 (labeled COMP_SEL_1,..., COMP_SEL_6 in the table). In an exemplary implementation, the operation of the circuit 900 includes, for each input terminal 911, 921, 931, selectively establishing coupling via one in a pair of comparator blocks 915 and 925, 925 and 935, 935 and 945 provided in parallel to form, in pairs, a coupling path 910, 920, 930 from the input terminal 911, 921, 931 to an associated output terminal 919, 929, 939, while interrupting the coupling via the other comparator block in the respective pair. This is illustrated in table 1000, which provides an example overview of the states of the first through fourth comparator blocks 915, 925, 935, and 945. In a first phase (labeled PHASE_ 1 in table 800), the first comparator select switch 912 is open while the second comparator select switch 922 is closed. Accordingly, the first comparator block 915 (COMP_ 1) is in the charge mode (REFRESH). Consequently, the first input signal voltage VIN_ 1 is provided to the second comparator block 925 (COMP_ 2) that is in the operating mode (SAMPLE). Thus, during the first phase, the first coupling path 910 (labeled PATH_ 1 in table 1000) uses the second comparator block 925 (COMP_ 2) but not the first comparator block 915. Meanwhile, the third comparator selection switch 932 is open. Consequently, the second input signal voltage VIN_ 2 is kept away from the first coupling path 910. The fourth comparator selection switch 942 is closed, thereby providing the second input signal voltage VIN_ 2 to the third comparator block 935 (COMP_ 3) that is in the operating mode. Thus, during the first phase, the second coupling path 920 (PATH_ 2) uses the third comparator block 935 (COMP_ 3) but not the second comparator block 925. Similarly, the fifth comparator select switch 952 is open. Consequently, the third input signal voltage VIN_ 3 is kept away from the second input coupling path 920. The sixth comparator selection switch 962 is closed, thereby providing the third input signal voltage VIN_ 3 to the fourth comparator block 945 (COMP_ 4) that is in the operating mode. Thus, during the first phase, the third coupling path 930 (PATH_ 3) uses the fourth comparator block 945 (COMP_ 4) but not the third comparator block 935.As described above with respect to FIGS. 7 and 8, in some embodiments, the second comparator block 925 may be configured to operatively supplement the first comparator block 915 and / or the third comparator block 935. In the embodiment illustrated in FIG. 9, the third comparator block 935 may be further configured to operatively supplement the second comparator block 925 and / or the fourth comparator block 945. An example operation of the first to fourth phases (PHASE_ 1, PHASE_ 2, PHASE_ 3, PHASE_ 4) will now be discussed. During the first phase (PHASE_ 1), the second comparator block 925 (COMP_ 2) is in the operating mode (SCAN) using it in the first coupling path 910 (PATH_ 1), whereby the first comparator block 915 (COMP_ 1) may be in the charging mode (REFRESH), e.g., to recharge its capacitances. During the third phase (PHASE_ 3), the second comparator block 925 (COMP_ 2) is in the operating mode (SCAN) using it in the second coupling path 920 (PATH_ 2), whereby the third comparator block 935 (COMP_ 3) may be in the charging mode (REFRESH), e.g., to recharge its capacitances. In contrast, during the second phase (PHASE_ 2), the second comparator block 925 is clipped from any input signal voltage because the second comparator select switch 922 (COMP_SEL_ 2) and the third comparator select switch 932 (COMP_SEL_ 3) are both open. This allows the second comparator selection block 925 (COMP_ 2) to be in the charge mode (REFRESH), e.g., to recharge its capacitances. Still during the second phase (PHASE_ 2), the third comparator block 935 (COMP_ 3) is in the operating mode (SCAN) being used in the second coupling path 920 (PATH_ 2), whereby the second comparator block 925 (COMP_ 2) may be in the charging mode (REFRESH), e.g., to recharge its capacitances. During the fourth phase (PHASE_ 4), the third comparator block 935 (COMP_ 3) is in the operating mode (SCAN) using it in the third coupling path 930 (PATH_ 3), whereby the fourth comparator block 945 (COMP_ 4) may be in the charging mode (REFRESH), e.g., to recharge its capacitances. In contrast, during the third phase (PHASE_ 3), the third comparator block 935 is cut off from any input signal voltage because the fourth comparator select switch 942 (COMP_SEL_ 4) and the fifth comparator select switch 952 (COMP_SEL_ 5) are both open. As a result, the third comparator block 935 (COMP_ 3) may be in the charging mode (REFRESH), for example, to recharge its capacitances. Thus, while each of the comparator blocks 915, 925, 935, 945 is not continuously operating in the operating mode, a continuous output signal voltage VOUT_ 1, VOUT_ 2, VOUT_ 3 is nevertheless provided for each coupling path 910, 920, 930 based on an associated input signal voltage VIN_ 1, VIN_ 2, VIN_ 3.Generally, a method for processing at least one input signal voltage in a circuit is disclosed herein. The circuit includes, as described with respect to the examples described above and illustrated in FIGS. 5, 7 and 9, at least one path input terminal coupled to at least one path output terminal via a plurality of comparators, the plurality of comparators including more comparators than there are path input terminals coupled to the path output terminals. The method comprises selectively establishing, for each path input terminal, coupling via one comparator of two comparators provided in parallel to form a coupling path from the path input terminal to an associated path output terminal while interrupting the coupling via the other comparator. In some implementations, the method further comprises sharing the one comparator between at least a first coupling path from a first path input terminal to a first path output terminal and a second coupling path from a second path input terminal to a second path output terminal. In some implementations, in the second coupling path, establishing coupling via the one comparator includes, in the first coupling path, interrupting coupling via the one comparator and, in the first coupling path, establishing coupling via the other comparator. In some implementations, the method further includes, while interrupting the coupling via the other comparator, charging a reference capacitance coupled to a sensing node of the other comparator.The arrangements and procedures of the described implementations may be implemented in a sensor system, special purpose computer, programmed microprocessor or microcontroller, and in a peripheral integrated circuit element(s), ASIC or other integrated circuit, digital signal processor of a flashable device, hardwired electronic or logic circuitry such as discrete element circuitry, programmable logic device such as a PLD, PLA, FPGA, PAL, modem, transmitter / receiver, any comparable device, or the like. The disclosed arrangements may be partially or fully implemented in hardware using logic circuits or a VLSI design.In the above description of the exemplary implementations, for purposes of explanation, specific numbers, material configurations, and other details are set forth in order to better explain the invention as claimed. It will be apparent, however, to one skilled in the art that the claimed invention may be practiced using details other than the exemplary details described herein. The example implementations / embodiments discussed herein may include various components compiled; however, it should be appreciated that the components of the assemblies may be combined into one or more devices. The terms 'circuit block' and 'circuit portion' as used herein should be functionally understood. Therefore, in some implementations, a circuit block may appear structurally as such in a circuit arrangement of a product; wherein the elements of the circuit block may be distributed at different locations of the circuit arrangement of the product. Likewise, a circuit portion may be distributed.The word "exemplary" as used herein means serving as an example, case, or illustration. Any aspect or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, use of the word is intended to be exemplary of the concepts and techniques being presented in a concrete manner. The term 'techniques' may refer to, for example, one or more devices, devices, systems, methods, articles of manufacture, and / or computer readable instructions as indicated by the context described herein.The terms "coupled" and "connected" as used herein may have been used to describe how various elements are connected. Unless expressly stated or at least otherwise implied, such described joining of various elements may be either direct or indirect.The terms "having", "containing", "comprising", "with" or variants thereof and similar terms as used herein are open ended terms that are intended inclusive. These terms indicate the presence of the stated elements or features, but do not exclude additional elements or features.The terms such as "first", "second", and the like, as used herein, are also used to describe various elements, regions, portions, etc., and are also not intended to be limiting. Where some implementations relating to first and second functionality have been described above, other implementations that are not illustrated may include only the first functionality (and not the second functionality) or may include only the second functionality (and not the first functionality).The phrase "continuously execute" as used herein is not necessarily to be understood as necessarily "always.". The conditions, such as a prerequisite for a particular continuous mode of operation, may be defined to be satisfied as a requirement for continuous execution. The continuous execution may be defined to continue as long as the conditions are satisfied. One condition may be activation of a continuous mode of operation that includes a predetermined condition for deactivation, such as completion of a predetermined duration.The term "or" as used herein is intended to mean an inclusive "or" rather than an exclusive "or.". That is, unless otherwise specified or clear from context, it is intended that 'X using A or B' means any of the natural inclusive permutations. That is, if X uses A; X uses B; or X uses both A and B, then under each of the previous cases 'X used A or B' is satisfied.The articles 'a' and 'an' as used herein should generally be construed to mean 'one or more' unless otherwise specified or clear from the context that they are directed to a singular form.The phrase "reset" as used herein includes recharging the capacitances to replace the charge that has leaked from the capacitance during, e.g., the first mode of operation; recharging the capacitances is also referred to as "capacitance refresh.". Resetting may also include readjustment to accommodate, for example, fluctuation of the comparator offset due to a change in temperature of the comparator. Reset may also include reconfiguration of the reference capacitance in some cases.In some embodiments, a programmable logic device (e.g., a field programmable gate array) may be used to perform some or all of the functionalities of the methods described herein. In some embodiments, a field programmable gate array may cooperate with a microprocessor to perform any of the methods described herein. In general, the methods may be performed by any hardware device.While the invention has been illustrated and described with respect to one or more implementations, changes and / or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. Specifically, with respect to the various functions performed by the above-described components or structures (arrangements, devices, circuits, systems, etc.), it is contemplated that the terms (including a reference to 'means') used to describe such components correspond, unless otherwise specified, to any component or structure that performs the specified function of the described component (e.g., that is functionally equivalent), even if not structurally equivalent to the disclosed structure that performs the function in the exemplary implementations of the invention illustrated herein. It should be appreciated that the features of the various embodiments described herein may be combined with each other unless specifically stated otherwise.

Claims

A method for processing an input signal voltage, comprising - storing a charge in a reference capacitance (30); - setting an input capacitance (45) to the input signal voltage; - while the input capacitance (45) is set to the input signal voltage, performing a charge redistribution between the reference capacitance (30) and the input capacitance (45); and - based on the charge redistribution, deriving an output signal, wherein a product of the voltage across the reference capacitance (30) and the ratio of the size of the reference capacitance (30) and the size of the input capacitance (45) is based on the output signal.The method of claim 1, further comprising setting a first voltage across the input capacitance (45) to a first predetermined reset voltage value; and setting a second voltage across the reference capacitance (30) to a second predetermined reset voltage value.The method of claim 2, wherein deriving the output signal is performed during a first mode of operation, and wherein setting the first voltage across the input capacitance (45) and setting the second voltage across the reference capacitance (30) are performed during a second mode of operation different from the first mode of operation.The method of claim 3, scheduling the first mode of operation and the second mode of operation in an alternating sequence.The method of any of claims 1 to 4, further comprising, based on the output signal, configuring the magnitude of the reference capacitance (30), configuring the magnitude of the input capacitance (45), and setting the voltage across the reference capacitance (30).The method of claim 5, wherein the reference capacitance (30) is provided as a plurality of switched capacitances (31, 32), wherein configuring the reference capacitance (30) includes selectively switching the switched capacitances (31, 32).The method of claim 6, wherein the switched capacitors (31, 32) when charged use one of at least a first reference voltage level and a second reference voltage level.The method of claim 7, wherein a difference between the first reference voltage level and the second reference voltage level is based on one of a group consisting of a band gap voltage and a ratiometric determined voltage.The method according to any of claims 1 to 8, wherein deriving the output signal includes - comparing a voltage at a node (40) between the input capacitance (45) and the reference capacitance (30) with a threshold voltage and - based on a result of the comparing, forming the output signal.A circuit for processing an input signal voltage, the circuit comprising a voltage processing device (50) including a sense node (40) coupled to an input terminal (10) for the input signal voltage, an input capacitance (45) coupled between the sense node (40) and the input terminal (10), and a reference capacitance (30) coupled to the sense node (40), wherein the reference capacitance (30) or the input capacitance (45) is configurable based on an output signal of the voltage processing device (50); and wherein the circuit is configured to redistribute charge between the input capacitance (45) and the reference capacitance (30) while the input capacitance (45) is set to the input signal voltage.The circuit of claim 10, wherein the circuit further comprises a controller (64) configured to configure the reference capacitance (30) or the input capacitance (45).The circuit of claim 11, wherein the controller (64) is configured to process a signal received from the voltage processing device (50) and configure the reference capacitance (30) based on the signal received from the voltage processing device (50).The circuit of claim 12, wherein the control unit (64) is provided as a logic circuit configured to process the signal received from the voltage processing device (50) as a digital signal.The circuit according to claim 12 or 13, wherein the voltage processing device (50) is provided as a comparator (55) configured to operate in at least a first operation mode in which the comparator (55) performs comparison and a second operation mode in which the comparator (55) performs reset, and wherein the control unit (64) is configured to configure the reference capacitance (30) to change a charge amount of the reference capacitance (30) when the comparator performs comparison.The circuit of any of claims 10 to 14, wherein the reference capacitance (30) is coupled to a reference node of the first level (33) via a first level switch (35, 37).The circuit of claim 15, wherein the reference capacitance (30) is coupled to a second level reference node (34) via a second level switch (36, 38), wherein a difference between a voltage at the first level reference node (33) and a voltage at the second level reference node (34) is based on one of a group consisting of a band gap voltage and a ratiometric determined voltage.The circuit of any of claims 10 to 16, wherein the reference capacitance (30) or the input capacitance (45) is configurable in size.The circuit according to any one of claims 10 to 17, wherein the reference capacitance or the input capacitance (45) is provided as a plurality of switched capacitances (31, 32).The circuit of claim 18, wherein the control unit (64) is provided as a logic circuit configured to output a plurality of digital switching signals, each digital switching signal, to control a switched capacitance of the plurality of switched capacitances (31, 32).The circuit of claim 19, wherein the reference capacitance (30) or the input capacitance (45) includes a switched hysteresis capacitance configured to selectively contribute a predetermined charge to charge redistribution based on the output signal.The circuit of any of claims 10 to 20, wherein the reference capacitance (30) and the input capacitance (45) share a common node coupled to the sense node (40).

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