Level converter circuit, as well as measuring arrangement and chip with such a level converter circuit

Abstract

Level converter circuit (1300a, 1700b, 1800, 2000), comprising: • a signal source (1302); • a level converter (1304); • wherein the signal source (1302) is capacitively coupled on the output side to an input of the level converter (1304); and • wherein the signal source (1302) and the level converter (1304) are galvanically isolated from each other; • wherein the signal source (1302) comprises a push-pull generator configured to provide two push-pull signals which are capacitively coupled to the level converter (1304); • wherein the level converter (1304) has an inverter structure (1366) which is connected to the input of the level converter (1304) on the input side and / or provides an output of the level converter on the output side; • wherein the level converter (1304) comprises a first charge pump (1362) configured to provide a voltage difference for switching the inverter structure (1366).

Description

The invention relates to a level converter circuit, and to a measuring arrangement and a chip comprising such a level converter circuit.Generally, integrated circuits (also referred to as a chip or microchip) may be used to process digital or analog signals. An integrated circuit may include a plurality of circuit modules, each circuit module providing one or more functions of the integrated circuit. The more circuit modules the integrated circuit or chip has, the more complex it and its circuit modules can be. For example, a complex chip may require a voltage supply, a voltage rectification, a level conversion, a DC voltage conversion, a clock generation, a power amplification, a readout amplification or the like, which may be provided by means of a respective circuit module.In general, a signal processing chip is sought which has a signal-to-noise ratio that is clearly as high as possible. This can depend on all circuit modules of a chip, since their noise is superimposed along the signal chain of the chip to form a complex interaction, which ultimately limits the technically achievable signal-to-noise ratio, for example to approximately 60 decibels or less. For example, the noise of a power supply may be picked up by a power amplifier and further amplified, such that a signal output by the power amplifier has an even greater noise than the power supply. In particular, the circuit module that generates the greatest noise may dominate the signal-to-noise ratio of the chip.Conventionally, circuit modules are being sought which generate as low a noise as possible along the signal chain. In order to achieve the highest possible signal-to-noise ratio, the signal chain is usually supplied with the lowest possible low-noise voltage. In a continuously signal processing sensor circuit of a chip, for example, MOSFET amplifier circuits or simple source follower amplifier circuits are used.The most critical parameter of the sensor circuit for the signal-to-noise ratio is the so-called pink noise (also referred to as 1 / f noise, also referred to as flicker noise in English), which increases with decreasing frequency. Conventionally, pink noise is optimized by increasing the gate area of the amplifying transistor, but a greater need for required chip area and a difficult manufacturing process must be accepted.Alternatively to an alternating voltage, a direct voltage can be used to supply the sensor circuit. However, in order to generate the electrical DC voltage on the chip itself (also referred to as on-chip generation), conventionally a low efficiency has to be accepted, which increases the waste heat of the chip and thus the need for active cooling of the chip. Furthermore, inaccuracies in the timing, for example in the control of the switches for chopping the electrical DC voltage, and increased power consumption by the required timing, must be accepted. Therefore, in order to minimize the power consumption and the waste heat of the chip, a direct voltage which is as low as possible is usually used for supplying the amplifier circuit, for example a direct voltage of 2.5 volts or less.Alternatively, the electrical direct voltage and / or its generation on the chip itself is dispensed with. Instead, either an alternating voltage or a direct voltage generated externally (outside the chip) is used to supply the amplifier circuit or the signal chain.EP 1 154 564 A2 describes a two-stage amplifier, the first and second stages of which are connected in series to one another via a coupling capacitor in terms of direct voltage, the first stage having a transconductance amplifier.DE 10 2005 038 001 A1 describes a two-stage voltage level converter circuit for generating a word line signal, wherein the voltage level converter circuit has a first stage which receives an input signal and a second stage which outputs corresponding output signals, which are electrically conductively coupled to one another.US 2006 / 0 087 470 A1 describes a circuit arrangement having an input circuit which is related to a ground voltage. Further described are a ground voltage and an output circuit that is capacitively coupled to the input circuit at another ground voltage.US 2008 / 0 191 800 A1 describes a circuit arrangement which, by the combination of a mixed modulation clock and a dual chopper amplifier circuit (DCA), provides low-noise read-out circuits with a high dynamic range and low power loss for capacitive sensors with a low sampling capacitance and low converter sensitivity. The mixed modulation clock is generated by exclusive OR (XOR) of a high frequency clock and a low frequency clock. With the mixed modulation clock, an input signal is doubly modulated by the high frequency clock and the low frequency clock, respectively. The DCA amplifies the input signal in two amplification stages. The first amplification stage amplifies the doubly modulated signal and then demodulates the amplified signal with the high frequency clock. The second amplification stage then amplifies the signal as a conventional chopper amplifier with the low frequency clock as the chopper clock. Low pass filters connected downstream of the two gain stages filter out the offset of the modulated circuit and the low frequency flicker noise.The invention is defined in the independent claims. Further developments are evident from the dependent claims.According to various embodiments, a circuit architecture for a chip and its circuit modules is provided, which may reduce power consumption, allow a more accurate timing, greater edge steepness, and / or a greater signal-to-noise ratio, e.g. a signal-to-noise ratio (also referred to as SNR) of at least 75 dB (decibels). Illustratively, the circuit architecture enables a greater electrical DC voltage to be generated on the chip itself (on-chip generation), by means of which an amplifier circuit and / or signal chain of the chip can be supplied, such that the upper limit for the SNR is increased. By means of the circuit architecture, a clearly particularly low-noise measuring arrangement can be realized.Illustratively, according to various embodiments, an electric mixed voltage source for electrically supplying the signal chain is provided, which provides an electric mixed voltage having a peak-to-valley value of greater than twice the electric supply voltage, e.g. of more than 6 volts.Illustratively, according to various embodiments, a charge pump stage and a charge pump are provided for the circuit architecture, e.g. for the mixed voltage electric source, which requires a smaller chip area and / or which has a lower power consumption. The charge pump stage may be configured to generate a negative electrical voltage and / or may be manufactured completely in one conductivity type (e.g. p-type or n-type). Alternatively or additionally, the required electrical voltage stability of the switches installed therein can be reduced. Illustratively, the charge pump stage or charge pump provided enables the drain-source electrical voltage to be halved, such that the full electrical voltage swing of the charge storage device can be used for charge pumping.Illustratively, according to various embodiments, a level converter circuit is provided for the circuit architecture, e.g. for its chopper, which requires a smaller chip area and / or has a lower power consumption.According to various embodiments, a measuring arrangement may include: a micromechanical sensor having a capacitance; a bridge circuit having a plurality of capacitances, at least one capacitance of which is the capacitance of the micromechanical sensor (i.e. that it represents the micromechanical sensor); an amplifier which is coupled on the input side to an output of the bridge circuit; an electrical DC voltage source which is configured to provide an electrical DC voltage; a chopper which has at least one first charge store and a switch structure; wherein the switch structure is configured to couple the first charge store alternately to the electrical DC voltage and the bridge circuit for coupling an electrical mixed voltage into the bridge circuit.According to various embodiments, a measuring arrangement may include: a micromechanical sensor having a capacitance; a bridge circuit having a plurality of capacitances, at least one capacitance of which is the capacitance of the micromechanical sensor; an amplifier, which is coupled on the input side to an output of the bridge circuit and has an electrical working voltage; an electrical mixed voltage source, which is configured to couple an electrical mixed voltage having a peak-to-valley value of more than the electrical working voltage (e.g. more than 6 volts) into the bridge circuit, e.g. of more than twice the electrical working voltage, e.g. of more than three times the electrical working voltage. Alternatively or additionally, the working voltage can also be a working voltage of the micromechanical sensor, the logic of a chip in which the measuring arrangement is implemented, and / or a charge pump of the measuring arrangement.According to various embodiments, the micromechanical sensor may have a working voltage; wherein the mixed voltage source is configured to provide the mixed electric voltage with a peak-to-valley value of approximately twice the working voltage.According to various embodiments, the mixed voltage source may include a first charge pump configured to provide a first electrical potential of a DC voltage.According to various embodiments, the mixed voltage source may comprise at least one second charge pump which is configured to provide a second electrical potential of the DC voltage.According to various embodiments, the mixed voltage source may include a switch structure configured to discharge the capacitances (e.g. multiple capacitors) when the mixed voltage has reached its extreme value.According to various embodiments, the mixed voltage source may include or be formed from a chopper and / or a DC voltage source.According to various embodiments, the mixed voltage source may comprise a DC voltage source which is configured to provide an electrical DC voltage.According to various embodiments, the mixed voltage source may include a chopper including at least a first charge storage and a switch structure; wherein the switch structure is configured to couple the first charge storage alternately to the DC voltage and the bridge circuit for coupling an electric mixed voltage into the bridge circuit.According to various embodiments, the mixed voltage source may include a switch structure configured to discharge the plurality of capacitances (e.g. a plurality of capacitors) when the mixed voltage has reached its extreme value.According to various embodiments, the mixed electrical voltage may have a peak-to-valley value of about 6 volts or more (e.g. of about 8 volts or more, e.g. of about 10 volts or more, e.g. of about 12 volts or more, e.g. of about 14 volts or more, e.g. of about 16 volts or more, e.g. of about 18 volts or more) and / or about 30 volts or less.According to various embodiments, the electrical supply voltage may be a DC voltage and may be about 5 volts or less (e.g. about 4 volts or less, e.g. about 3 volts or less, e.g. about 2 volts or less, e.g. about 1.5 volts or less, e.g. about 1 volt) and / or about 0.5 volts or more.The electrical supply voltage can be present at the charge pump, at a processor (e.g. its logic) and / or at the micromechanical sensor) at the measuring arrangement.The micromechanical sensor may have a pressure sensor (e.g. for measuring a tire pressure or air pressure) and / or a sound sensor or be formed therefrom (or expressed more generally: a sound transducer). Alternatively, the micromechanical sensor may include or be formed from an acceleration sensor, a chemical sensor (e.g., a humidity sensor and / or a gas sensor), a force sensor, a position sensor, a particle sensor, a fill level sensor and / or gas sensor.According to various embodiments, the chopper may be configured to provide, in a steady state, at least one of the following: a mixed electrical voltage noise of less than 200 μV (e.g. at a peak-to-valley value of the mixed electrical voltage of exactly 18 volts or more); a mixed electrical voltage signal-to-noise ratio of less than 10 5; and / or a mixed electrical voltage noise of less than 10 -5 of a peak-to-valley value of the mixed electrical voltage.According to various embodiments, the chopper may be configured to provide, in a steady state, a first harmonic of the mixed electrical voltage with a peak-to-valley value of less than 200 μV (microvolt) and / or less than 10 -5 of the peak-to-valley value of the mixed electrical voltage.According to various embodiments, the chopper may be configured to provide the mixed electric voltage with a trapezoidal characteristic (e.g. rectangular characteristic) and / or a triangular characteristic. The trapezoidal characteristic (e.g. the rectangular characteristic) can deviate slightly from an ideal geometric shape, e.g. with an exponential function flank (i.e. curved legs) or rounded corners. The area enclosed by the signal profile of the mixed electrical voltage can be maximized.According to various embodiments, the DC electric voltage source may include a first charge pump configured to provide a first electric potential of the DC electric voltage.According to various embodiments, the electrical DC voltage source may comprise at least one second charge pump which is configured to provide a second electrical potential of the electrical DC voltage. Alternatively, the second electrical potential of the mixed electrical voltage can be an electrical reference potential, e.g. electrical ground. The DC electric voltage may correspond to the difference between the first electric potential and the second electric potential.According to various embodiments, a peak-to-valley value of the mixed electric voltage may be less than the direct electric voltage.According to various embodiments, the switch structure may be configured to discharge the plurality of capacitances, e.g. a plurality of capacitors (e.g. relative to one another or to electrical ground) when the first charge storage is decoupled from the bridge circuit. Mutually discharged can be understood to mean that the charges stored therein cancel one another at least partially (by means of an exchange of charge with one another). In other words, the plurality of capacitances (e.g. capacitors) may be coupled to one another such that the energy stored therein is released.According to various embodiments, the switch structure may be configured to drive the first charge storage according to a charge transfer cycle of the chopper, wherein the charge transfer cycle comprises: a first phase (also referred to as first chopper phase) in which the first charge storage is coupled to the electrical DC voltage and decoupled from the bridge circuit; a second phase (also referred to as second chopper phase) in which the first charge storage is decoupled from the electrical DC voltage and coupled to the bridge circuit.According to various embodiments, the chopper may include a second charge storage, wherein the switch structure is configured to drive the second charge storage according to the charge transfer cycle of the chopper; wherein in the first phase the second charge storage is decoupled from the electrical DC voltage and coupled to the bridge circuit; wherein in the second phase the second charge storage is coupled to the electrical DC voltage and decoupled from the bridge circuit.According to various embodiments, the chopper may be configured to provide a first clock signal of the mixed electrical voltage by means of the first charge storage device and a second clock signal of the mixed electrical voltage by means of the second charge storage device, which clock signals oscillate in a push-pull manner.According to various embodiments, the at least two (complementary) clock signals may be matched to one another in time such that an electrical voltage fluctuation at the output of the bridge circuit caused by the electrical mixed voltage alone is less than 200 mV and / or less than 10 -2 of the peak-to-valley value of the electrical mixed voltage. Illustratively, this may be provided by means of one level converter or a plurality of level converters which provide the at least two clock signals (as two complementary level converter signals).According to various embodiments, the at least two clock signals may be matched to one another in time such that a superposition of the two signals has an electrical voltage fluctuation of less than 200 mV and / or less than 10 -2 of the peak-to-valley value of the electrical mixed voltage. Illustratively, the noise may decrease with the electric voltage variation.According to various embodiments, the switch structure may be further configured to drive the bridge circuit according to the charge transfer cycle; wherein the charge transfer cycle comprises a third phase (also referred to as third chopper phase) in which the plurality of capacitances (e.g. plurality of capacitors) are coupled to each other for discharging and the first charge storage and / or the second charge storage are decoupled from the bridge circuit.According to various embodiments, the chopper may include an additional first charge storage device that is switched (i.e. driven) by the switch structure synchronously with the first charge storage device, wherein the first charge storage device is coupled in the first phase to the first electrical potential of the electrical DC voltage and in the second phase to a first capacitance of the plurality of capacitances (e.g. a first capacitor of the plurality of capacitors); and wherein the additional first charge storage device is coupled in the first phase to a second electrical potential of the electrical DC voltage and in the second phase to a second capacitance of the plurality of capacitances (e.g. a second capacitor of the plurality of capacitors).According to various embodiments, the chopper may be configured to provide the first clock signal of the mixed electrical voltage by means of the additional first charge storage.According to various embodiments, the chopper may include an additional second charge storage device, which is switched (i.e. driven) by the switch structure synchronously with the second charge storage device, wherein the second charge storage device is coupled in the first phase to the second capacitance of the plurality of capacitances (e.g. to the second capacitor of the plurality of capacitors) and in the second phase to the second electrical potential of the electrical DC voltage; and wherein the additional second charge storage device is coupled in the first phase to the first capacitance of the plurality of capacitances (e.g. to the first capacitor of the plurality of capacitors) and in the second phase to the second electrical potential of the electrical DC voltage.According to various embodiments, the chopper may be configured to provide the second clock signal of the mixed electrical voltage by means of the additional second charge storage.According to various embodiments, the charge stores of the chopper may be the same in capacitance; and / or the charge stores of the chopper may have a larger capacitance than the bridge circuit (i.e. the sum of the capacitive electrical voltage dividers of the bridge circuit).According to various embodiments, the micromechanical sensor may have an electrical working voltage; wherein each charge store of the chopper has a first capacitance; wherein the bridge circuit has a second capacitance, which represents the capacitive sum (i.e. according to the interconnection) of the plurality of capacitances (e.g. of the plurality of capacitors); and wherein the chopper and the bridge circuit are configured with respect to one another such that a ratio of the electrical DC voltage to the electrical working voltage is greater than 2 by at least a ratio of the second capacitance to the first capacitance.According to various embodiments, the micromechanical sensor may have a working voltage; the DC voltage source being configured to generate the electrical DC voltage greater than twice the working voltage.According to various embodiments, the measuring arrangement may further comprise a voltage regulator which is configured to compare the mixed electrical voltage with an electrical reference potential and to regulate the mixed electrical voltage on the basis of the comparison.According to various embodiments, the voltage regulator may be configured to control and / or regulate at least one charge pump of the DC electric voltage source on the basis of the comparison.According to various embodiments, the voltage regulator of the voltage regulators may be configured to start and / or stop at least one charge pump of the DC electric voltage source on the basis of the comparison.According to various embodiments, the voltage regulator may be configured to regulate at least one of the following variables of the mixed electrical voltage: a peak-to-valley value; a peak value; and / or a DC value (corresponding to the temporal mean value).According to various embodiments, a chip may include the measurement arrangement as described herein, e.g. implemented in a substrate of the chip.According to various embodiments, the measuring arrangement may further comprise an electric supply voltage source (which provides the electric supply voltage). For example, the electrical supply voltage source can be configured for contactless transmission of electrical energy (e.g. by means of magnetic induction). Alternatively, the electrical DC voltage source and / or the electrical supply voltage source can be provided by means of a separate chip (illustratively an external electrical voltage source).According to various embodiments, a level converter circuit may include: a signal source; a level converter (also referred to as second level converter); wherein the signal source is capacitively coupled on the output side to an input of the level converter; and wherein the signal source and the level converter are galvanically separated from one another, wherein the signal source includes a push-pull generator configured to provide two push-pull signals which are capacitively coupled into the level converter; wherein the level converter (1304) includes an inverter structure (1366) which is present on the input side to the input of the level converter (1304) and / or provides an output of the level converter on the output side; wherein the level converter (1304) includes a first charge pump (1362) configured to provide a voltage difference for switching the inverter structure (1366).According to various embodiments, the signal source may include an additional level converter (also referred to as a first level converter) configured to provide a first level converter signal that is capacitively coupled to the level converter.According to various embodiments, the signal source may comprise a push-pull generator configured to provide two push-pull signals which are capacitively coupled into the level converter.According to various embodiments, the level converter may be configured to provide the second level converter signal; wherein the first level converter signal or the two push-pull signals and the second level converter signal coincide in a frequency.According to various embodiments, a level converter circuit may include: a push-pull generator; a level converter (also referred to as second level converter); wherein the push-pull generator is capacitively coupled on the output side to an input of the level converter; and wherein the push-pull generator and the level converter are galvanically separated from one another.According to various embodiments, the push-pull generator may include or be formed from a level converter (also referred to as first level converter). For example, the first level converter may be configured to generate two level-converted push-pull signals, i.e. two signals that are push-pull to each other (i.e. that are complementary).According to various embodiments, a level converter circuit may include: a push-pull generator for providing two complementary signals (also referred to as two push-pull signals); a level converter; wherein the push-pull generator is coupled to the level converter such that the two complementary signals are capacitively coupled to the level converter; and wherein the push-pull generator and the level converter are galvanically separated from each other.According to various embodiments, a level converter circuit may include: a first level converter; a second level converter; wherein the first level converter is capacitively coupled on the output side to an input of the second level converter; and wherein the first level converter and the second level converter are galvanically isolated from one another.According to various embodiments, a level converter circuit may include: a first level converter for providing a level converter signal; a second level converter; wherein the first level converter is coupled to the second level converter such that the level converter signal is capacitively coupled to the second level converter; and wherein the first level converter and the second level converter are galvanically separated from each other.According to various embodiments, the first level converter may be configured to provide a first level converter signal, which is capacitively coupled into the second level converter.According to various embodiments, the push-pull generator may be configured to provide two push-pull signals which are capacitively coupled into the second level converter. Each push-pull signal of the two push-pull signals can optionally comprise or be formed from a level converter signal.According to various embodiments, the second level converter may be configured to provide a second level converter signal having at least one of: a larger amplitude than the first level converter signal and / or than the two push-pull signals; a larger peak-to-valley value than the first level converter signal and / or than the two push-pull signals; a larger peak value than the first level converter signal; and / or a larger average value than the first level converter signal and / or than the two push-pull signals.According to various embodiments, the second level converter may be configured to provide the second level converter signal; wherein the first level converter signal or the two push-pull signals and the second level converter signal coincide in a frequency.According to various embodiments, the level converter circuit may further comprise a charge storage device which capacitively couples the signal source (e.g. its first level converter and / or its push-pull generator) on the output side to an input of the (second) level converter.According to various embodiments, the second level converter may have an inverter structure which is coupled on the input side to the input of the second level converter and / or provides an output of the second level converter on the output side.According to various embodiments, the second level converter may include a first charge pump configured to provide an electrical voltage difference for switching the inverter structure, e.g. an electrical voltage difference of more than the electrical supply voltage.According to various embodiments, the signal source (e.g. its first level converter and / or its push-pull generator) may be capacitively coupled on the output side to a clock input of the first charge pump.According to various embodiments, the inverter structure may further be present on the input side at the clock input of the first charge pump for switching the inverter structure according to a clock (in other words according to a charge transfer cycle) of the first charge pump.According to various embodiments, the second level converter may include a second charge pump which is connected between the inverter structure and the signal source (e.g. its first charge pump and / or its push-pull generator), wherein the inverter structure is further present on the input side at a clock input of the second charge pump stage (e.g. including cross-coupled inverters or formed therefrom) for switching the inverter structure according to a clock of the second charge pump (i.e. according to a charge transfer cycle of the second charge pump).According to various embodiments, the level converter circuit may further comprise an additional signal source which is capacitively coupled on the output side to the clock input of the second charge pump.According to various embodiments, the additional signal source may include an even additional level converter (also referred to as third level converter) configured to provide a third level converter signal that is capacitively coupled to the level converter.According to various embodiments, the additional signal source may include an additional push-pull generator configured to provide two additional push-pull signals that are capacitively coupled into the level converter.According to various embodiments, the level converter circuit may further comprise an additional push-pull generator, which is capacitively coupled on the output side to the clock input of the second charge pump.According to various embodiments, the additional push-pull generator may include or be formed from a third level converter.According to various embodiments, the additional push-pull generator may be configured to provide two additional push-pull signals which are capacitively coupled into the second level converter.According to various embodiments, the level converter circuit may further comprise a third level converter, which is capacitively coupled on the output side to the clock input of the second charge pump.According to various embodiments, the third level converter may be configured to provide a third level converter signal, which is capacitively coupled into the second level converter.According to various embodiments, the third level converter may be configured to provide a second level converter signal having at least one of: a larger amplitude than the third level converter signal and / or than the two additional push-pull signals; a larger peak-to-valley value than the third level converter signal and / or than the two additional push-pull signals; a larger peak value than the third level converter signal; and / or a larger average value than the third level converter signal and / or than the two additional push-pull signals.According to various embodiments, the second level converter may be configured to provide a second level converter signal; wherein the third level converter signal and / or the two additional push-pull signals and the second level converter signal coincide in a frequency.According to various embodiments, a level converter circuit may include: a signal source; an inverter structure; a charge pump having a charge storage; wherein the signal source is capacitively coupled on the output side to an input of the inverter structure by means of the charge storage; and wherein the inverter structure and the signal source are galvanically separated from one another, wherein the signal source includes a push-pull generator configured to provide two push-pull signals which are capacitively coupled into the level converter.According to various embodiments, the signal source may include a level converter configured to provide a first level converter signal that is capacitively coupled to the inverter structure.According to various embodiments, the signal source may include a push-pull generator configured to provide two push-pull signals that are capacitively coupled into the inverter structure.According to various embodiments, the level converter circuit may further include: an additional signal source which is coupled on the output side to a charge storage of the additional charge pump.According to various embodiments, the additional signal source may include an additional level converter configured to provide a third level converter signal coupled to the additional charge pump.According to various embodiments, the additional signal source may include an additional push-pull generator configured to provide two additional push-pull signals coupled to the additional charge pump.According to various embodiments, a level converter circuit may include: a level converter and / or a push-pull generator; an inverter structure; a charge pump including a charge storage; wherein the level converter and / or the push-pull generator is capacitively coupled on the output side to an input of the inverter structure by means of the charge storage; and wherein the inverter structure and the level converter and / or the push-pull generator are galvanically separated from each other.According to various embodiments, the level converter may be configured to provide a first level converter signal which is capacitively coupled into the inverter structure.According to various embodiments, the push-pull generator may be configured to provide two push-pull signals which are capacitively coupled into the inverter structure.According to various embodiments, the inverter structure may be configured to provide a second level converter signal having at least one of: a larger amplitude than the first level converter signal and / or than the two push-pull signals; a larger peak-to-valley value than the first level converter signal; a larger peak value than the first level converter signal and / or than the two push-pull signals; and / or a larger average value than the first level converter signal and / or than the two push-pull signals.According to various embodiments, the inverter structure may be configured to provide a second level converter signal; wherein the first level converter signal and / or the two push-pull signals and the second level converter signal coincide in a frequency.According to various embodiments, the charge pump may be configured to switch the inverter structure according to a charge transfer cycle of the charge storage.According to various embodiments, the charge pump may be configured to provide an electrical voltage difference for switching the inverter structure.According to various embodiments, the level converter circuit may further include an additional charge pump configured to provide an electrical voltage difference for switching the inverter structure; wherein the charge pump is connected between the inverter structure and the additional charge pump.According to various embodiments, the level converter circuit may further include an additional signal source which is coupled on the output side to a charge storage of the additional charge pump.According to various embodiments, the additional signal source may include an additional level converter configured to provide a third level converter signal coupled to the additional charge pump.According to various embodiments, the additional signal source may include an additional push-pull generator configured to provide two additional push-pull signals coupled to the additional charge pump.According to various embodiments, the level converter circuit may further comprise an additional level converter and / or an additional push-pull generator, which is coupled on the output side to a charge storage of the additional charge pump.According to various embodiments, the additional level converter may be configured to provide a third level converter signal which is coupled to the additional charge pump.According to various embodiments, the additional push-pull generator may be configured to provide two additional push-pull signals which are coupled into the additional charge pump.According to various embodiments, the inverter structure may be configured to provide a second level converter signal having at least one of: a larger amplitude than the third level converter signal and / or the two additional push-pull signals; a larger peak-to-valley value than the third level converter signal and / or the two additional push-pull signals; a larger peak value than the third level converter signal; and / or a larger average value than the third level converter signal and / or the two additional push-pull signals.According to various embodiments, the inverter structure may be configured to provide a second level converter signal; wherein the third level converter signal and / or the two additional push-pull signals and the second level converter signal coincide in a frequency.According to various embodiments, a measuring arrangement may comprise a level converter circuit according to various embodiments, e.g. implemented in a substrate of the measuring arrangement.According to various embodiments, a chip may include a level converter circuit according to various embodiments, e.g. implemented in a substrate of the chip.According to various embodiments, a charge pump stage may include: a charge storage; and a switch structure configured to drive the charge storage according to a charge transfer cycle of the charge storage, the charge transfer cycle including: a first phase (also referred to as a first sub-stage phase) in which the charge storage is coupled to an input of the charge pump stage, a second phase (also referred to as a second sub-stage phase) in which the charge storage is decoupled from the input and from an output of the charge pump stage; and a third phase (also referred to as a third sub-stage phase) in which the charge storage is coupled to the output of the charge pump stage.According to various embodiments, a charge pump stage may include: a charge storage; and a switch structure including a first switch (including or formed from a first transistor) and a second switch (including or formed from a second transistor); a first control circuit configured to drive the charge storage according to a charge transfer cycle of the charge storage, wherein the charge transfer cycle includes: a first phase in which the charge storage is coupled to an input of the charge pump stage via the first switch, a second phase in which the first switch and the second switch are simultaneously in a switching operation; and a third phase in which the charge storage is coupled to an output of the charge pump stage via the second switch; wherein the first switch and the second switch (e.g. their transistors) have the same channel conductivity type (e.g. PMOS or NMOS).According to various embodiments, the switch structure may include: a first switch connected between the charge storage and the input; a second switch connected between the charge storage and the output of the charge pump stage; and a first control circuit configured to close the first switch in the first phase and open it in the second and third phases, and open the second switch in the first and second phases and close it in the third phase.According to various embodiments, the control circuit may be capacitively coupled to the first switch and / or to the second switch (i.e. by means of a capacitive coupling). In other words, the control circuit can provide at least one control signal which is capacitively coupled into the first switch and / or the second switch.According to various embodiments, the control circuit may be connected to the first switch by means of a first capacitive coupling and / or to the second switch by means of a second capacitive coupling.According to various embodiments, the switch structure may further include: a leveling circuit configured to couple the first capacitive coupling to the charge storage in the second phase and / or in the third phase; and / or to couple the second capacitive coupling to the output of the charge pump stage in the second phase and / or in the first phase.According to various embodiments, the leveling circuit may include: a third switch connected between the first control circuit and the charge storage, a second control circuit configured to open the third switch at least in the first phase and / or the second phase, and to close at least once in the third phase.According to various embodiments, the leveling circuit may include: a fourth switch connected between the second control circuit and the charge storage, wherein the first control circuit is configured to switch the fourth switch synchronously with the first switch.According to various embodiments, the leveling circuit may include: a fifth switch configured to electrically connect the first control circuit to the charge storage device in the second and / or third phase, e.g. as long as a voltage at the input of the charge pump stage satisfies a predetermined criterion.According to various embodiments, the leveling circuit may include: a sixth switch configured to electrically connect the first control circuit to the output of the charge pump stage in the second and / or first phase, e.g. as long as an electrical voltage provided by the charge storage meets a predetermined criterion.According to various embodiments, a charge pump stage may further include: an additional charge storage; an additional switch structure configured to couple the additional charge storage to an output of the charge pump stage in the first phase, to decouple the additional charge storage from the input of the charge pump stage and the output of the charge pump stage in the second phase, and to couple the additional charge storage to the input of the charge pump stage in the third phase. In other words, the additional charge storage and the charge storage can be controlled in a complementary manner to one another and / or can be connected in parallel to one another.According to various embodiments, the switch structure and the additional switch structure may comprise a common control circuit.According to various embodiments, a charge pump stage may further include: an additional charge storage; and an additional switch structure configured to drive the additional charge storage in a push-pull manner to the charge storage (such that the input of the charge pump stage is coupled to and / or decoupled from either the charge storage or the additional charge storage in the second phase).According to various embodiments, a charge pump stage may further include: an additional charge storage; and an additional switch structure; wherein the switch structure and the additional switch structure are arranged in a push-pull relationship to each other such that the input of the charge pump stage is coupled to either the charge storage or the additional charge storage and / or is decoupled therefrom in the second phase.According to various embodiments, the switches of the switch structure and / or of the additional switch structure may be formed in low-voltage technology.According to various embodiments, the switches of the switch structure and / or the additional switch structure may be formed in the same well and / or have the same channel conduction type.According to various embodiments, the charge pump stage may further include a clock controller configured to provide a clock signal according to the charge transfer cycle and to couple the clock signal into the charge storage and / or the switch structure.According to various embodiments, the charge pump stage may further include a substrate, wherein the switch structure and the charge storage are formed in the substrate.According to various embodiments, the substrate may be doped with a dopant of a first type (e.g. p-doped) and may include a well doped with a dopant of a second type (e.g. n-doped), wherein each switch of the switch structure includes a channel provided by the well. The channel may then be doped with the second type dopant (i.e., having a second type conductivity). The dopant of the first type may be p-type, for example, and the dopant of the second type may be n-type, for example, or vice versa. For example, an n-doped substrate can have a p-well. Each switch of the switch structure (e.g., PMOS switch) may be disposed in the p-well. For example, a positive charge pump can be provided by means of PMOS switches.According to various embodiments, the substrate may be doped with a dopant of a first type (e.g. n-doped) and may include a first well doped with a dopant of a second type (e.g. p-doped) and a second well doped with a dopant of a first type (e.g. n-doped) (also referred to as triple well), wherein each switch of the switch structure includes a channel provided by the second well. The channel may then be doped with a dopant or dopant of the first type (i.e., having a conductivity type of the first type). The dopant of the first type may be p-type, for example, and the dopant of the second type may be n-type, for example, or vice versa. For example, the second well may be disposed in the first well. For example, a p-doped substrate can have an n-well in which a p-well is arranged. Each switch of the switch structure (e.g., NMOS switch) may be disposed in the p-well. For example, a negative charge pump can be provided by means of NMOS switches. Optionally, the second well and the substrate may comprise different dopants of the first type.A negative charge pump or negative charge pump stage can be understood to mean that it provides a lower electrical potential than is coupled into it (e.g. lower than the electrical reference potential and / or lower than the electrical supply voltage), e.g. a negative voltage. A positive charge pump or positive charge pump stage can be understood to mean that it provides a greater electrical potential than is coupled into it (e.g. greater than the electrical reference potential and / or greater than the electrical supply voltage), e.g. a positive voltage.According to various embodiments, a charge pump may include a plurality of charge pump stages that are serially interconnected with each other and each charge pump stage is configured according to one or more embodiments.According to various embodiments, a charge pump stage may include: two sub-stages connected in parallel to each other between the input and the output of the charge pump stage, each sub-stage including: a charge storage; a switch structure configured to drive the charge storage according to a charge transfer cycle of the charge storage, wherein the charge transfer cycle includes: a first phase in which the charge storage is coupled to an input of the charge pump stage, a second phase in which the charge storage is decoupled from the input of the charge pump stage and an output of the charge pump stage; and a third phase in which the charge storage is coupled to the output of the charge pump stage; wherein the charge transfer cycles of the two sub-stages are set up in a push-pull relationship with respect to one another, such that the input of the charge pump stage is alternately coupled to the charge stores of the two sub-stages and / or is decoupled therefrom in the second phase.According to various embodiments, a charge pump stage may include: two sub-stages connected in parallel to each other between the input and the output of the charge pump stage, each sub-stage including: a charge storage; a switch structure including a first switch (e.g. including or formed from a first transistor) and a second switch (e.g. including or formed from a second transistor) configured to drive the charge storage according to a charge transfer cycle of the charge storage, wherein the charge transfer cycle includes: a first phase in which the charge storage is coupled to an input of the charge pump stage by means of the first switch, a second phase in which the first switch and the second switch are simultaneously in a switching operation; and a third phase, in which the charge storage device is coupled to an output of the charge pump stage by means of the second switch; wherein the first switch and the second switch have the same channel conduction type; wherein the charge transfer cycles of the two sub-stages are configured in a push-pull manner with respect to one another, such that the input of the charge pump stage is alternately coupled to the charge storage devices of the two sub-stages and / or is decoupled therefrom in the second phase.According to various embodiments, the switch structures of the two sub-stages may each include: a first switch connected between the charge storage and the input of the charge pump stage; a second switch connected between the charge storage and the output of the charge pump stage; a first control circuit configured to close the first switch in the first phase and to open it in the second and third phases; and to open the second switch in the first and second phases and to close it in the third phase.According to various embodiments, the control circuit of each sub-stage may be capacitively coupled to the first switch and / or to the second switch of the respective sub-stage.According to various embodiments, the control circuit of each substep may be connected to the first switch by means of a first capacitive coupling and / or to the second switch of the respective substep by means of a second capacitive coupling.According to various embodiments, the switch structures of the two sub-stages may each further comprise: a leveling circuit configured to couple the first capacitive coupling to the charge storage in the second phase and / or in the third phase; and / or to couple the second capacitive coupling to the output of the charge pump stage in the second phase and / or in the first phase.According to various embodiments, the leveling circuits of the two sub-stages may each further comprise: a third switch connected between the first control circuit and the charge storage, a second control circuit configured to open the third switch at least in the first phase and / or the second phase, and to close at least once in the third phase.According to various embodiments, the leveling circuits of the two sub-stages may each further include: a fourth switch connected between the second control circuit and the charge storage, wherein the first control circuit is configured to switch the fourth switch synchronously with the first switch.According to various embodiments, the leveling circuits of the two sub-stages may each further comprise: a fifth switch configured to electrically connect the first control circuit to the charge storage device in the second and / or third phase, e.g. as long as an electrical voltage at the input of the charge pump stage satisfies a predetermined criterion.According to various embodiments, the leveling circuits of the two sub-stages may each further comprise: a sixth switch configured to electrically connect the first control circuit to the output of the charge pump stage in the second and / or first phase, e.g. as long as an electric voltage provided by the charge storage meets a predetermined criterion.According to various embodiments, the two sub-stages may include a first sub-stage and a second sub-stage; wherein the first control circuit of the first sub-stage is configured to synchronously switch the first switch of the first sub-stage and the second switch of the second sub-stage; and wherein the first control circuit of the second sub-stage is configured to synchronously switch the second switch of the first sub-stage and the first switch of the second sub-stage.According to various embodiments, the switches of the switch structure and / or of the additional switch structure may be formed in low-voltage technology.According to various embodiments, the switches of the switch structure may be formed in the same well and / or may have the same channel conduction type.According to various embodiments, the charge pump stage may further include a clock controller configured to provide a clock signal to each of the two sub-stages, respectively, according to the charge transfer cycle of the respective sub-stage and to couple the clock signal into the respective charge storage and / or the respective switch structure.According to various embodiments, the charge pump stage may further include a substrate, wherein the two sub-stages (or at least their switch structure and / or at least their charge storage) are formed in the substrate.According to various embodiments, the substrate may be doped with a dopant of a first type and may include a well doped with a dopant of a second type, wherein each switch of the switch structure of each of the two sub-stages includes a channel provided by the well.According to various embodiments, a charge pump may include a plurality of charge pump stages that are serially interconnected with each other and each charge pump stage is configured according to various embodiments.According to various embodiments, a charge pump may include: a plurality of charge pump stages connected in series with each other and of which a first charge pump stage includes a first charge storage and a second charge pump stage includes a second charge storage; a switch structure configured to drive the first charge storage and the second charge storage according to a charge transfer cycle of the plurality of charge pump stages, the charge transfer cycle including: a first phase in which the first charge storage is coupled to the second charge pump stage, a second phase in which the first charge storage is decoupled from the second charge pump stage and the second charge storage is decoupled from the first charge pump stage; and a third phase in which the second charge storage is coupled to the first charge pump stage.According to various embodiments, a charge pump may include: a plurality of charge pump stages connected in series with each other and of which a first charge pump stage includes a first charge storage and a second charge pump stage includes a second charge storage; a switch structure including a first transistor and a second transistor; a first control circuit configured to drive the first charge storage and the second charge storage according to a charge transfer cycle of the plurality of charge pump stages, the charge transfer cycle including: a first phase in which the first charge storage is coupled to the second charge pump stage via the second transistor, a second phase in which the first transistor and the second transistor are simultaneously in a switching operation; and a third phase in which the second charge storage is coupled to the first charge pump stage via the first transistor.According to various embodiments, the switch structure may include: a first switch connected between the first charge storage and the second charge pump stage; a second switch connected between the second charge storage and the first charge pump stage; a first control circuit configured to close the first switch in the first phase and to open it in the second and third phases; and to open the second switch in the first and second phases and to close it in the third phase.According to various embodiments, the control circuit may be connected to the first switch by means of a first capacitive coupling and / or to the second switch by means of a second capacitive coupling.According to various embodiments, the switch structure may further include: a leveling circuit configured to couple the first capacitive coupling to the second charge storage in the second phase and / or in the third phase; and / or to couple the second capacitive coupling to the second charge pump stage in the second phase and / or in the first phase.According to various embodiments, the leveling circuit may include: a third switch connected between the first control circuit and the second charge storage, a second control circuit configured to open the third switch at least in the first phase and / or the second phase, and to close at least once in the third phase.According to various embodiments, the leveling circuit may include: a fourth switch connected between the second control circuit and the second charge storage, wherein the first control circuit is configured to switch the fourth switch synchronously with the first switch.According to various embodiments, the leveling circuit may include: a fifth switch configured to electrically connect the first control circuit to the second charge storage device in the second and / or third phase, e.g. as long as an electrical voltage at the input of the second charge pump stage meets a predefined criterion.According to various embodiments, the leveling circuit may include: a sixth switch configured to electrically connect the first control circuit to the output of the first charge pump stage in the second and / or first phase, e.g. as long as an electrical voltage provided by the first charge storage meets a predetermined criterion.According to various embodiments, the switches of the switch structure may be formed in low-voltage technology.According to various embodiments, the switches of the switch structure may be formed in the same well and / or may have the same channel conduction type.According to various embodiments, the first control circuit may push-pull drive the first charge storage and the second charge storage.According to various embodiments, the charge pump stage may further include: a clock controller configured to provide a first clock signal and a second clock signal according to the charge transfer cycle; wherein the clock controller is configured to couple the first clock signal into the first charge storage and / or the switch structure; and / or wherein the clock controller is configured to couple the second clock signal into the second charge storage and / or the switch structure.The first clock signal and the second clock signal may be complementary to each other.According to various embodiments, the charge pump may further include: a substrate, wherein the switch structure, the first charge storage and / or the second charge storage are formed in the substrate.According to various embodiments, the substrate may be doped with a dopant of a first type and may include a well doped with a dopant of a second type, wherein each switch of the switch structure includes a channel provided by the well.According to various embodiments, a measurement arrangement may include a charge pump stage and / or charge pump of one or more embodiments.According to various embodiments, each switch of the switch structure may include or be formed from a field effect transistor.According to various embodiments, a chip may include a charge pump stage and / or charge pump according to one or more embodiments, e.g. implemented in a substrate of the chip.According to various embodiments, a charge pump stage may include: a charge storage; a first transistor connected between the charge storage and the input; and a second transistor connected between the charge storage and the output of the charge pump stage; wherein the first transistor and the second transistor have the same channel conduction type; a control circuit configured to provide a first control signal for controlling the first transistor and a second control signal for controlling the second switch in a push-pull manner with respect to each other.According to various embodiments, a plurality of control circuits may be implemented by a common control circuit. For example, a separate control circuit may be used to provide two control signals for each. Alternatively or additionally, at least two (e.g. complementary) control signals can be provided by means of a common control circuit.According to various embodiments, the second control signal may be delayed and / or inverted with respect to the first control signal, e.g. by means of a delay circuit or an inverting circuit.According to various embodiments, a readout circuit may include: a capacitive bridge circuit, which is configured to couple at least one terminal for coupling a capacitance of a sensor; an amplifier, which is coupled on the input side to an output of the bridge circuit; an electric DC voltage source, which is configured to provide an electric DC voltage; a chopper, which includes at least one charge storage device and a switch structure; wherein the switch structure is configured to couple the charge storage device alternately to the electric DC voltage and the bridge circuit for coupling an electric mixed voltage into the bridge circuit. Illustratively, the measuring arrangement can have the readout circuit and the sensor coupled therein.According to various embodiments, two circuit modules connected in series, e.g. two level converters (e.g. the first level converter and the second level converter) and / or the measuring bridge and the amplifier, may form two members of a signal chain. Two circuit modules connected in parallel to one another can form two branches of a signal chain.According to various embodiments, an element which is connected between two elements can be understood to mean that the three elements are connected in series, i.e. along a series circuit. Switching a switch can be understood to be from an open state to a closed state or vice versa.According to various embodiments, a method may include: providing two push-pull signals (e.g. a first level converter signal and / or two push-pull signals) by means of a signal source (e.g. by means of a first level converter and / or by means of a push-pull generator); capacitively coupling the two push-pull signals into a level converter (also referred to as second level converter).According to various embodiments, a method for operating a micromechanical sensor may include: providing a DC voltage; charging a charge storage device by means of an electrical DC voltage; and discharging the charge storage device by means of a bridge circuit, wherein the bridge circuit includes a plurality of capacitances, of which at least one capacitance represents the micromechanical sensor.According to various specific embodiments, a method for operating a micromechanical sensor may include: coupling an electrical mixed voltage into a bridge circuit which includes a plurality of capacitances, at least one capacitance of which represents the micromechanical sensor; detecting a signal of the micromechanical sensor by means of an amplifier, the amplifier being operated by means of an electrical voltage which is less than a peak-to-valley value of the electrical mixed voltage.According to various embodiments, a method for transferring charge may include: first transferring charge from a first electrical potential to the charge storage; second transferring charge from the charge storage to a second electrical potential larger in amount than the first electrical potential; and decoupling the charge storage from the first electrical potential and from the second electrical potential between the first transferring and the second transferring.Decoupling the charge storage from the first electrical potential and from the second electrical potential may be simultaneous.Exemplary embodiments of the invention are illustrated in the figures and are explained in more detail below.They show FIGS. 1A, 2A, 3A and 4 each show a charge pump stage according to various embodiments in a schematic circuit diagram; FIGS. 1B, 2B, 3B and 5 each show a charge transfer cycle according to various embodiments in a schematic flow diagram; FIGS. 6, 7 and 9 each show a charge pump stage according to various embodiments in a schematic circuit diagram; FIGS. 8 and 10 each show a signal profile according to various embodiments in a schematic diagram; FIGS. 11A, 11B, 12A and 12B each show an electrical potential profile according to various embodiments in a schematic diagram; FIG. 13A shows a level converter circuit according to various embodiments in a schematic circuit diagram; FIGS. 13B, 14A, 14B, 15, 16A, 16B and 17A each show a level converter according to various embodiments in a schematic circuit diagram; FIGS. 17B, 18, 19A, 19B and 20 each show a level converter circuit according to various embodiments in a schematic circuit diagram; FIGS. 21A and 21B each show a signal profile according to various embodiments in a schematic diagram; FIGS. 22A, 22B, 23 and 25 each show a measuring arrangement according to various embodiments in a schematic circuit diagram; FIG. 24 shows a signal profile according to various embodiments in a schematic diagram; FIGS. 26, 27 and 28 each show a charge transfer cycle according to various embodiments in a schematic flow diagram; FIGS. 29A and 29B each show a measuring arrangement according to various embodiments in a schematic circuit diagram; FIGS. 30A and 30B each show a measuring arrangement according to various embodiments in a schematic circuit diagram; FIG. 31 shows a signal profile according to various embodiments in a schematic diagram; FIGS. 32 and 34 each show a charge pump stage according to various embodiments in a schematic circuit diagram; FIGS. 33A and 33B each show a control circuit according to various embodiments in a schematic circuit diagram; FIGS. 35 and 37 each show a signal profile according to various embodiments in a schematic diagram; FIGS. 36A, 36B and 36C each show a micromechanical sensor according to various embodiments in a schematic cross-sectional view; FIGS. 38A and 38B each show an electrical potential profile according to various embodiments in a schematic diagram; and FIG. 39 shows a chopper according to various embodiments in a schematic circuit diagram.In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, components of embodiments may be positioned in a number of different orientations, which is for purposes of illustration and is not in any way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. It should be understood that the features of the various exemplary embodiments described herein may be combined with each other, unless specifically stated otherwise. The following detailed description is therefore not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.In the context of this description, the terms "connected", "connected" and "coupled" are used to describe both a (e.g. electrical) direct and an indirect connection (e.g. ohmic and / or electrically conductive, e.g. an electrically conductive connection), a direct or indirect connection and a direct or indirect coupling.According to various embodiments, the term "coupled" or "coupling" may be understood in the sense of a (e.g. direct or indirect) electrical connection and / or electrical interaction, including a physical connection or interaction. The interaction can be mediated, for example, by means of an electric current which flows along the current path provided by means of the coupling. An electrical connection may comprise an electrically conductive connection, i.e. having an ohmic behavior, e.g. provided by means of a metal or a degenerate semiconductor material, e.g. in the absence of a pn junction in the electrical current path. An indirect electrical connection may include additional components in the electrical current path that do not alter or leave substantially unchanged the operation of the circuit.In general, relations such as "smaller" and "larger" can be understood with respect to the sign, i.e., a negative value is smaller than a positive value and a more negative (lower) value is smaller than a more positive (higher) value. When indicated (e.g., by "amount by" or amount by"), relations such as "less" and "greater" may be related to the amount of a value.A plurality of elements may be coupled to one another, for example, along an interaction chain, e.g., a signal chain. A coupling may be configured to transmit an electrical signal between the two elements coupled together. The term "decoupled" can be understood as meaning that the coupling is or is canceled. For example, decoupling second elements from each other may cause an electrically conductive connection between them to be canceled (e.g. converted into an electrically insulating connection), e.g. by opening a switch (i.e. being brought into an open state).In the figures, identical or similar elements are provided with identical reference numerals, as appropriate.According to various embodiments, a readout circuit for a micromechanical capacitive sensor is provided, e.g. for a silicon microphone, e.g. for a capacitor microphone in microsystem technology (also referred to as micromechanical capacitor microphone or micromechanical capacitive microphone). The readout circuit may be based on a bridge circuit, e.g. a full bridge circuit or a half bridge circuit. Furthermore, the read-out circuit can have an amplifier, for example a differential amplifier (also referred to as subtractor or "fully differential amplifier"), which has cross-connected switches at both output terminals. Alternatively or additionally, the readout circuit can have an electrical DC voltage supply for electrically supplying the bridge circuit, e.g. a capacitive bridge circuit.The readout circuit may include a chopper (or use a chopper method) for reducing low frequency noise components so that a larger SNR is achieved, e.g., a larger SNR in the audio frequency band (in the range of about 20 Hz to about 40 kHz) and / or speech band (in the range of about 200 Hz to about 4 kHz).According to various embodiments, the principle of an electric DC voltage supply and an improved circuit architecture for a charge pump (also referred to as "charge pump") and a level converter (also referred to as "level converter" or "level shifter") may be clearly merged, which facilitates operating the readout circuit up to an electric voltage of 8 volts or more. Alternatively or additionally, the readout circuit may comprise a thermal noise optimized CMOS amplifier (i.e. an amplifier in self-complementing metal oxide semiconductor technology) and / or an integrated trimming circuit for all capacitors of the bridge circuit.The read-out circuit enables a lower power consumption, a greater edge steepness (or the temporal fit thereof) of the switches of the chopper (also referred to as chopper switches) and / or an SNR of 75 dB or more for the output-side amplifier signal.According to various embodiments, illustrative:• An improved dynamic level-shifting circuit is provided for controlling and / or regulating the chopper switches for as little time delay as possible, an improved time fit and as low power consumption as possible;• an improved negative charge pump provided for as efficient an area occupancy (i.e. required chip area) and efficient power consumption as possible;• at least one charge storage (also referred to as holding capacitance) provided for the electrical operating voltage of the bridge circuit, for as low a power consumption as possible and as low a noise as possible, without requiring external (off-chip) capacitors, in order to provide an electrical supply voltage according to a positive electrical working voltage (Vbiasp, i.e. positive Vbias) and / or a negative electrical working voltage (Vbiasn, i.e. negative Vbias);• special AC (DC) feedback for reducing the output side ripple (i.e. ripple) of the amplifier;• a complex trimming array (also referred to as trimming circuit) for correcting deviations of the capacitances of the measuring bridge from each other, at the amplifier input and / or at the input (input node) of the measuring bridge.The electrical supply voltage (also referred to as VDD) can generally denote an electrical voltage which is coupled into a circuit or a chip from the outside, for example by means of corresponding contacts of the chip or by means of contactless transmission. An electrical working voltage can be understood as a value which indicates at which a component or a circuit module is to be operated in order to ensure its function. An operating electrical voltage may refer to the electrical voltage at which a component or circuit module is actually operated.An electrical voltage (e.g. the operating voltage, the supply voltage and / or the working voltage) can be understood as a discrete value and / or as a voltage range around the discrete value, e.g. a voltage range of ±10% of the discrete value.In general, an integrated circuit, e.g. an analog circuit, can have a plurality of circuit modules (also referred to as circuit domains) which differ in their electrical working voltage (i.e. the required electrical operating voltage). The required electrical operating voltages can be provided, i.e. generated from, the integrated circuit itself using the electrical supply voltage, e.g. by means of voltage conversion and / or voltage pumps. Generally, a charge pump may be integrated in a chip, e.g. for generating an electric voltage greater than the electric supply voltage, e.g. for doubling or multiplying the electric supply voltage.For example, a first circuit module (also referred to as main module or main domain) may require a first electrical operating voltage (illustratively an electrical core voltage), e.g. the electrical supply voltage. A second circuit module may require a second electrical operating voltage (also referred to as VDDH or positive high voltage electrical voltage) greater than the first electrical operating voltage (e.g., VDDH> VDD). Alternatively or additionally, a third circuit module may require a third electrical operating voltage (also referred to as VSSLor negative high-voltage electrical voltage) less than the negative of the first electrical operating voltage (e.g., VSSH<-VDD).A clearly efficient circuit architecture for a charge pump may be provided by means of a so-called latching charge pump (also referred to as a Pelliconi charge pump). Alternatively, a self-charging Dicken charge pump (also referred to as bootstrap Dicken charge pump or Dicken charge pump for short) can be used.Each charge pump stage of a Pelliconi charge pump may include or be formed from a latch. The charge pump stage or the latch can have two CMOS inverters (i.e. inverters in complementary metal oxide semiconductor technology), each of which has two switches which differ in their channel conduction type (i.e. having at least one NMOS switch and at least one CMOS switch). The switches can thus be controlled by means of a common clock signal without having to accept switching delays between them. Positive and negative electrical voltages can be generated by means of a Pelliconi charge pump. However, a large electrical voltage swing may require more effort in implementing the Pelliconi charge pump into a substrate, as an additional isolated well (e.g., n-well) is needed per charge pump stage.A bootstrap circuit (e.g. a bootstrap Dicken charge pump) denotes an electrical circuit in which an electrical potential change in one part of the circuit becomes effective with a clearly small time delay in another part of the circuit (clearly this has an internal feedback). The switches of a bootstrap circuit can have the same channel conduction type. A bootstrap circuit can thus require less effort if a large electrical voltage swing is to be generated.A latch (also referred to as a latch) may refer to a state-controlled flip-flop (i.e., a bistable flip-flop). A latch may have, in addition to an input and an output, at least one additional input (also referred to as a control input or gate), by means of which the latch can be switched back and forth between two states: a first state (also referred to as a transparent state), in which the output of the latch follows the input of the latch, i.e. is coupled thereto; and a second state (also referred to as a holding state), in which the electrical potential of the output (on entering the second state) is retained (i.e. is retained). In contrast to a clock edge controlled flip-flop, a latch is transparent throughout the active clock phase, i.e. an input change can affect the output signal immediately.The latch may comprise two cross-connected (e.g., digital) CMOS inverters and (in the case of a charge pump) optionally two pump capacitors per charge pump stage.According to various embodiments, the switches of a charge pump may be formed in a substrate, e.g. a p-doped substrate. The n-channel switches (e.g., NMOS switches) may be formed directly in the substrate while an n-well is needed to form p-channel switches (e.g., PMOS switches). In operation, the substrate may be at a reference electrical potential, e.g., at electrical ground (at zero volts). In the case of a charge pump that generates a positive electrical voltage, an electrical voltage difference of the p-channel switches to the substrate per stage is increased by the electrical voltage swing of the charge pump, so that one well is more required for each stage. For example, a triple well process may be used, in which an additional p-well is provided in the n-well.The main module (e.g., digital integrated circuit logic, e.g., a processor) may use the core electrical voltage. For controlling and / or regulating another circuit module (e.g. comprising an analog switch and / or a transmission gate) which requires a different electrical operating voltage, the clock signal and / or corresponding control signal used for this purpose are converted (i.e. transformed) to the other electrical operating voltage. For conversion (level conversion), a cross-coupled latch may be used (see, for example, FIG. 13B ).Therefore, when VDDH is in a range of about two times to about three times the VDD, a simple, fast switching, reliable level conversion having an acceptable power consumption can be achieved. If high-voltage MOS components (high-voltage metal oxide semiconductor components) are used as cascades for operating low-voltage components, the latch can also be used for even larger VDDH (e.g. larger than three times VDD), compare for example FIG. 14A. However, a compromise between switching delay and power consumption must be accepted for this purpose. As the width of the components of the cross-coupled latch decreases, its switching delay increases. As the width of the components of the cross-coupled latch increases, the switching delay may be reduced, but this increases its power consumption. Furthermore, high-voltage level converters have an increasing power consumption with a decreasing switching delay, which should be as low as possible, in particular, for the use of complementary clock generators (also referred to as push-pull generators).Optionally, additional cascade devices in the cross-coupled latches may be used for level conversion (see, for example, FIG. 15 ) controlled by a low voltage electrical signal, which reduces power consumption with equal switching delay. However, the power consumption of such level conversion circuit architectures increases sharply with increasing VDD. Further, the switching delay and delay adjustment of the inverting or noninverting output is comparatively large.According to various embodiments, a Pelliconi charge pump, e.g. comprising exactly one charge pump stage, is used to generate the control signal for the high-voltage MOS components in an inverter structure. The gate-to-source electrical voltage of the NMOS device (n-channel MOS device) and / or PMOS device (p-channel MOS device) of the inverter structure (output inverter) may thus be reduced to a swing of less than or equal to twice the VDD, e.g., of less than or equal to the VDD (see, for example, FIG. 16B ). This allows the cross electric current to be reduced during the switching of the devices, for example even when the PMOS device switches simultaneously with the NMOS device. This clearly allows the power consumption to be reduced, the switching to be accelerated, a smaller deviation of the complementary level converter outputs (Yp and Y_n) to be achieved, a sufficient PSSR, a more stable operating point and / or an improved starting behavior compared with previously described level converters to be achieved.According to various embodiments, a charge pump or its charge pump stage may be implemented in a readout circuit (e.g. in an application specific integrated circuit). The readout circuit may be implemented together with a sensor (e.g., a sound sensor such as a MEMS microphone) in a chip (integrated circuit) or a chip module (circuit module). The performance of the readout circuit may affect the total power consumption and the size of the application specific integrated circuit chip. By means of the circuit architecture provided, an application-specific integrated circuit can be made possible according to predetermined specifications.According to various embodiments, the provided circuit architecture may reduce the maximum required electric voltage swing (peak-to-valley value of the electric voltage or electric potential) of the charge transfer signal coupled into each charge pump stage. This makes it possible to use the electrical core voltage (i.e. the working voltage of the digital logic of the integrated circuit) for operating the charge pump stage. Additional components for generating the charge transfer signal can thus be avoided.According to various embodiments, the use of a bootstrap circuit for the charge pump may prevent an electrical voltage loss of Vth per charge pump stage of the charge pump. In turn, fewer charge pump stages per charge pump may be needed to achieve a predetermined electrical voltage difference (e.g., four or less than four per 18 volts electrical voltage difference).According to various embodiments, a cycle (e.g. a charge transfer cycle) may be understood as a sequence of phases which runs periodically. The cycle may have a period corresponding to the smallest time interval after which the sequence repeats. The phases may denote periods of the cycle between which, for example, a state of a system changes.According to various embodiments, a semiconductor region may be processed to form one or more chips in the semiconductor region. A chip may have an active chip area. The active chip area may be arranged in a part of the semiconductor region and may include at least one device (one device or more devices) such as a transistor, a resistor, a capacitor, a diode or the like. The at least one component or an interconnection of a plurality of components can be configured to carry out logical operations, e.g. arithmetic operations or storage operations. Alternatively or additionally, the at least one circuit element or an interconnection of a plurality of components can be configured to carry out switching operations, signal processing and / or amplification operations. Various components, such as a transistor, a capacitor and / or a diode, for example, can be or can be configured for high-voltage applications (also referred to as a high-voltage diode or high-voltage transistor).According to various embodiments, a chip (also referred to as a semiconductor chip or integrated circuit) may be singulated from the semiconductor region by removing material from a kerf (also referred to as a kerf) of the semiconductor region (also referred to as dicing or dicing the semiconductor region). For example, the removal of material from the cut line of the semiconductor region can be effected by scribing and breaking, splitting, blade dicing, plasma dicing, laser dicing or mechanical sawing (for example using a dicing saw). After the chip has been separated, it can be electrically contacted and encapsulated, for example by means of a molding material and / or in a chip carrier (also referred to as chip package), which are then suitable for use in electronic devices. For example, the chip may be connected on a chip carrier by means of wires, and the chip carrier may be soldered on a circuit board and / or on a lead frame.According to various embodiments, a substrate (e.g. a wafer, e.g. a reconfigured wafer) and / or a semiconductor region may include or be formed from a semiconductor material of one type or different types, including group IV semiconductors (e.g. silicon or germanium), compound semiconductors, e.g. group III-V compound semiconductors (e.g. gallium arsenide), group III semiconductors, group V semiconductors or polymers. In several embodiments, the substrate and / or the semiconductor region may be formed of silicon (doped or undoped). In several alternative embodiments, the substrate and / or semiconductor region may be a silicon-on-insulator (SOI) wafer. Alternatively, any other suitable semiconductor material may be used for the substrate and / or the semiconductor region, for example a semiconductor compound (semiconducting chemical compounds) such as gallium phosphide (GaP), indium phosphide (InP), silicon carbide (SiC) or gallium nitride (GaN), but also any suitable ternary semiconductor compound or quaternary semiconductor compound such as indium gallium arsenide (InGaAs).FIG. 1A illustrates a charge pump stage 100 aaccording to various embodiments in a schematic circuit diagram.The charge pump stage 100 amay include a charge storage 102 a(also referred to as first charge storage 102 a); a switch structure 104, an input 110 and an output 112. The charge storage 102 aand the switch structure 104 may be part of or form a sub-stage 120 aof the charge pump stage 100 a(also referred to as sub-stage switch structure 104 in the case). The switch structure 104 may be configured to drive the charge storage 102 aaccording to a charge transfer cycle 100 bof the charge storage 102 aand the sub-stage 120 a, respectively (compare FIG. 1B ). The switch structure 104 may include multiple switches according to various embodiments, as will be described in more detail below.The or each switch of the switch structure 104 can / can be provided by means of transistors (e.g. high-voltage transistors, i.e. high-voltage-resistant transistors), the gate terminal of which can provide a control input of the switch structure 104, for example. The transistors or each transistor of the switch structure 104 may have the same channel conduction type (e.g., n-channel transistor or p-channel transistor). The or each switch of the switch structure 104 can be high-voltage switches.According to various embodiments, a high voltage can be understood to mean an electrical voltage greater than the electrical supply voltage (e.g. the electrical core voltage). A high-voltage component (e.g. a high-voltage transistor or a high-voltage switch) can denote a component which has an electrical withstand voltage greater than the electrical supply voltage, i.e. an electrical breakdown voltage (e.g. gate breakdown voltage, dielectric breakdown voltage or a pn breakdown voltage) greater than the electrical supply voltage. A low-voltage device (e.g., a low-voltage transistor) may refer to a device having an electrical withstand voltage equal to or less than the electrical supply voltage, i.e., an electrical breakdown voltage equal to or less than the electrical supply voltage. The electrical withstand voltage or electrical breakdown voltage can denote an electrical voltage, at the exceedance of which an electrical current (e.g. an electrical reverse current) through the component rises sharply.A high-voltage transistor can have, for example, a greater thickness of the gate oxide (gate thickness) than a low-voltage transistor, e.g. more than twice the gate thickness, e.g. approximately three times the gate thickness. Alternatively or additionally, a high-voltage transistor can have a greater length of the channel (channel length) than a low-voltage transistor, e.g. approximately twice the channel length or more. A high voltage transistor may have a greater threshold electrical voltage (also referred to as an electrical switching voltage) than a low voltage transistor, e.g., about 1.5 volts or more. Therefore, for safe switching of high voltage transistors, it may be necessary to use a control signal having a greater peak-to-valley value, e.g., having a peak-to-valley value of greater than about 1.5 volts, e.g., greater than about 2 volts, e.g., greater than about 3 volts, e.g., greater than about 4 volts.According to various embodiments, different transistor types may be used (e.g. for implementing the switches of the switch structure 104). For example, a transistor may include or be formed from at least one of the following transistor types: a bipolar transistor (BJT), a heterojunction BJT, a Schottky BJT, an insulated gate BJT (IGBT), a field effect transistor (FET), a junction FET, a metal oxide semiconductor FET (MOSFET), a dual gate MOSFET, a power field effect transistor (e.g., fast-reverse or fast-recovery epitaxial diode FET), a tunnel FET, etc.The input 110 may include or be formed from an input node, e.g. if the charge pump stage 100 ais connected with its input 110 to an additional circuit, e.g. to an additional charge pump stage. The output 112 may include or be formed from an output node, e.g. when the charge pump stage 100 ais connected with its output 112 to another additional circuit, e.g. to an additional charge pump stage.During operation of the charge pump stage 100 a, a first electrical voltage coupled into the input 110 or the input node (also referred to as an electrical input voltage or the associated electrical potential) can be smaller than a second electrical voltage coupled out at the output 112 or the output node (also referred to as an electrical output voltage or the associated electrical potential). The electrical voltage difference between output 112 and input 110 may correspond to the electrical voltage Vp provided per charge pump stage 100 a(also referred to as electrical voltage swing of the charge pump stage 100 a).Generally, a charge pump may include or be formed from one charge pump stage 100 aor a plurality of serially connected charge pump stages 100 a. Each or the charge pump stage 100 aof the charge pump may comprise or be formed from exactly one sub-stage 120 aor two sub-stages 120 aconnected in parallel. The two parallel-connected sub-stages 120 acan be connected to one another in a push-pull manner (also referred to as two push-pull sub-stages).For driving the charge pump stage 100 aand the sub-stage 120 athereof, a charge transfer signal can be coupled into the charge storage 102 a, as will be described in more detail below.FIG. 1B illustrates a charge transfer cycle 100 bof a charge pump stage 100 aand its sub-stage 120 aaccording to various embodiments in a schematic flow diagram.The charge transfer cycle 100 bmay include: a first phase 151 (also referred to as first sub-stage phase 151) in which the charge storage 102 ais coupled to an input 110 of the charge pump stage and / or is decoupled from the output 112 of the charge pump stage.The charge transfer cycle 100 bmay further include: a second phase 153 (also referred to as second sub-stage phase 153) in which the charge storage 102 ais decoupled from the input 110 of the charge pump stage and the output 112 of the charge pump stage.The charge transfer cycle 100 bmay alternatively include: a second phase 153 (also referred to as second sub-stage phase 153) in which the switch structure 104 is in a switching operation. For example, a first switch 104 aof the switch structure 104 and a second switch 104 bof the switch structure 104 may be simultaneously in a switching operation (see FIG. 6 ).Illustratively, a switching operation of a switch 104 a, 104 bmay define a time interval that the switch 104 a, 104 btakes for switching (also referred to as a switching interval). At the same time, in a switching operation, it can be understood according to various embodiments that the switching operations (or the switching intervals) of the two switches 104 a, 104 btakes place over time, e.g. to an extent of more than approximately 10%, e.g. to an extent of more than approximately 25%, e.g. to an extent of more than approximately 50%, e.g. to an extent of more than approximately 75%, e.g. to an extent of more than approximately 90%, e.g. to an extent of more than approximately 99%.During the switching operation, the switch 104 a, 104 bchanges between an open state (i.e. this is electrically insulating) to a closed state (i.e. this is electrically conductive), which is also referred to as switching. The switching operation (or its time interval) can begin at the time t 1, at which a control signal coupled into the switch has a predefined criterion (e.g. greater than or less than an electrical threshold voltage). Upon reaching the criterion, the switch may change (e.g., increase or decrease) its electrical resistance. The switching operation (or its time interval) can be ended at the point in time t 2 at which the electrical resistance of the switch reaches a limit value (i.e. has converged to a limit value). The convergence criterion may be about 90% of the threshold.The change from the open state to the closed state can also be referred to as an activation process. From the time t 1 to the time t 2, the electric current intensity can increase through the switch. From time t 2, the electrical current flow may be saturated (i.e., the electrical current may have converged to the threshold).The change from the closed state to the open state can also be referred to as the switch-off process. From the time t 1 to the time t 2, the electric current intensity can decrease through the switch, i.e. converge towards zero. From time t 2, the electrical current flow may stop (i.e., the electrical current may have converged to zero).The charge transfer cycle 100 bmay further include: a third phase 155 (also referred to as third sub-stage phase 155) in which the charge storage 102 ais coupled to the output 112 of the charge pump stage and / or is decoupled from the input 110 of the charge pump stage.The second substep phase 153 may be temporally after the first substep phase 151, e.g. subsequent thereto. Alternatively or additionally, the second substep phase 153 may be temporally after the third substep phase 155, e.g. subsequent thereto. In other words, the charge transfer cycle may optionally include two second sub-stage phases 153.A first sub-stage of the two push-pull sub-stages can be in the first sub-stage phase 151 if a second sub-stage of the two push-pull sub-stages is in the third sub-stage phase 155 and vice versa. Alternatively or additionally, the two push-pull sub-stages can be simultaneously in the second sub-stage phase 153.By means of the circuit architecture of the charge pump stage 100 a, it can be achieved that an electrical voltage dropping across each switch of the switch structure 104 (e.g. in each phase of the charge transfer cycle 100 b) is equal to or less than the electrical supply voltage of the charge pump stage 100 a.The second sub-stage phase 153 may be shorter than the first sub-stage phase 151 and / or than the third sub-stage phase 155, e.g. shorter than about 50% (e.g. 25%, 10%, 5%, 1% or 0.5%) of the first sub-stage phase 151 and / or the third sub-stage phase 155. The shorter the second sub-stage phase 153, the more efficiently the charge pump 100 acan operate. For example, the second sub-stage phase 153 may be shorter than about 100 ns (nanoseconds), e.g. shorter than about 10 ns, e.g. shorter than about 1 ns.Optionally, the first sub-stage phase 151 and the third sub-stage phase 155 can be of the same length, for example if two push-pull sub-stages (which operate in push-pull) are used or a plurality of series-connected charge pump stages are used (which operate in push-pull in pairs).FIG. 2A illustrates a charge pump 200 aaccording to various embodiments in a schematic circuit diagram.The charge pump stage 200 bmay include two sub-stages 120 a, 120 b(first sub-stage 120 aand second sub-stage 120 b) which are connected in parallel to one another between the input 110 and the output 112, e.g. two push-pull sub-stages 120 a, 120 b.Each of the sub-stages 120 a, 120 bmay include a charge storage 102 aand a switch structure 104. The switch structure 104 may be configured to drive the respective charge storage 102 aaccording to a charge transfer cycle 100 bof the respective charge storage 102 a.The charge transfer cycle 200 bof the charge pump 200 a(compare FIG. 2B ) can be configured such that the two sub-stages 120 a, 120 b(or their switch structures 104) are driven in a push-pull manner with respect to one another. Illustratively, the input 110 of the charge pump stage 200 bmay be alternately coupled to the charge storage 104 of the first sub-stage 120 aand to the charge storage 104 of the second sub-stage 120 b. Alternatively or additionally, the output 112 of the charge pump stage 200 bmay be alternately coupled to the charge storage 104 of the first sub-stage 120 aand to the charge storage 104 of the second sub-stage 120 b.For driving the first sub-stage 120 a, a first charge transfer signal may be coupled into the charge storage 102 aof the first sub-stage 120 a, which is in push-pull relationship with a second charge transfer signal coupled into the charge storage 102 aof the second sub-stage 120 b.FIG. 2B illustrates a charge transfer cycle 200 bin accordance with various embodiments in a schematic flow diagram.The charge transfer cycle 200 bmay include a first phase 251 in which the first sub-stage 120 ais in its first sub-stage phase 151 and the second sub-stage 120 bis in its third sub-stage phase 155. For example, the charge storage 102 aof the first sub-stage 120 amay be coupled to the input 110 of the charge pump stage 200 aand the charge storage 102 aof the second sub-stage 120 bmay be coupled to the output 112 of the charge pump stage 200 a. Alternatively or additionally, the charge storage 102 aof the first sub-stage 120 amay be decoupled from the output 112 of the charge pump stage 200 aand the charge storage 102 aof the second sub-stage 120 bmay be decoupled from the input 110 of the charge pump stage 200 a.The charge transfer cycle 200 bmay further include: a second phase 253 in which the first sub-stage 120 ais in its second sub-stage phase 153 and the second sub-stage 120 bis in its second sub-stage phase 153. For example, the charge storage 102 aof the first sub-stage 120 aand the second sub-stage 120 bmay be decoupled from the output 112 of the charge pump stage 200 aand from the input 110 of the charge pump stage 200 a. Alternatively or additionally, the switch structures 104 of both sub-stages 120 a, 120 b(the first sub-stage 120 aand the second sub-stage 120 b) can be in a switching process. For example, a first switch 104 aof both sub-stages 120 a, 120 band / or a second switch 104 bof both sub-stages 120 a, 120 bmay be simultaneously in a switching operation (compare FIG. 6 ).The charge transfer cycle 200 bmay further include: a third phase 255, in which the first sub-stage 120 ais in its third sub-stage phase 155 and the second sub-stage 120 bis in its first sub-stage phase 151. For example, the charge storage 102 aof the second sub-stage 120 bmay be coupled to the input 110 of the charge pump stage 200 aand the charge storage 102 aof the first sub-stage 120 amay be coupled to the output 112 of the charge pump stage 200 a. Alternatively or additionally, the charge storage 102 aof the second sub-stage 120 bmay be decoupled from the output 112 of the charge pump stage 200 aand the charge storage 102 aof the first sub-stage 120 amay be decoupled from the input 110 of the charge pump stage 200 a.The second phase 253 may be temporally after the first phase 251, e.g. subsequent thereto. Alternatively or additionally, the second phase 253 may be temporally after the third phase 255, e.g. subsequent thereto.FIG. 3A illustrates a charge pump 300 aaccording to various embodiments in a schematic circuit diagram.The charge pump stage 300 amay include a plurality of charge pump stages 220 a, 220 b(e.g., a first charge pump stage 220 aand a second charge pump stage 220 b) connected in series with each other. The first charge pump stage 220 amay include a first charge storage 102 a. The second charge pump stage 220 bmay include a second charge storage 102 b.The charge pump stage 300 amay include a switch structure 204 which may include a plurality of switches 104 a, 104 b. The switch structure 204 may be configured to drive the first charge storage 102 aand the second charge storage 102 bin a push-pull relationship to one another, e.g. according to a charge transfer cycle 300 bof the plurality of charge pump stages 220 a, 220 b(cf. FIG. 3B ).Optionally, the first switch 104 aand the second switch 104 acan be actuated synchronously with one another, e.g. by means of a common control signal.FIG. 3B illustrates a charge transfer cycle 300 bin accordance with various embodiments in a schematic flow diagram.The charge transfer cycle 300 bmay include: a first phase 351 in which the first charge storage 102 ais coupled to the second charge pump stage, e.g. to its input 110.The charge transfer cycle 300 bmay further include: a second phase 353 in which the first charge storage 102 ais decoupled from the second charge pump stage 220 band the second charge storage 102 bis decoupled from the first charge pump stage 220 a.The charge transfer cycle 300 bmay alternatively include: a second phase 353 in which the switch structure 204 is in a switching operation. For example, a first switch 104 aof the second charge pump stage 220 band a second switch 104 bof the first charge pump stage 220 amay be simultaneously in a switching operation (see FIG. 6 ).The charge transfer cycle 300 bmay further include: a third phase 355, in which the second charge storage 102 bis coupled to the first charge pump stage 220 a, e.g. to its output 112.The first phase 351 and the third phase 355 may be simultaneous such that electrical charge is transferred from the first charge pump stage 220 ato the second charge pump stage 220 b.The voltage difference arising between the two charge stores 102 a, 102 bmay correspond to twice the voltage swing Vp of each of the charge pump stages 120 a, 120 b, e.g. in the second phase 353. In the second phase 353, the first switch 104 aand the second switch 104 bmay be closed. Thus, a voltage drop across each of the switches 104 a, 104 bmay be halved (i.e., may correspond to or be less than the voltage swing Vp). Thus, low-voltage switches can be used for the two switches 104 a, 104 b.FIG. 4 illustrates a charge pump 400 according to various embodiments in a schematic circuit diagram.The charge pump stage 400 may include a plurality of charge pump stages 220 a, 220 b(e.g., a first charge pump stage 220 aand a second charge pump stage 220 b) that are serially interconnected with each other. The first charge pump stage 220 amay include two sub-stages 120 a, 120 b. The second charge pump stage 220 bmay include two sub-stages 120 a, 120 b.The charge pump 400 may include a switch structure 204 including the at least one switch 104 a, 104 bper sub-stage 120 a, 120 b(also referred to as sub-stage switch structure 204 in the case). The switch structure 204 may be configured to drive the charge stores 102 a, 102 bof the four sub-stages 120 a, 120 bin accordance with a charge transfer cycle of the charge pump 400 (compare FIG. 5 ).The sub-stage switch structure 104 may be or may be coupled 110,112 to each other, e.g. by means of a pump stage connection 110,112 (comprising an input-output node 110,112) of the charge pump 400.FIG. 5 illustrates a charge transfer cycle 500 according to various embodiments in a schematic flow diagram.The charge transfer cycle 500 may include a first phase 551 in which the two first sub-stages 120 aare in their first sub-stage phase 151 and the two second sub-stages 120 bare in their third sub-stage phase 155. For example, the second sub-stage 120 b(or its charge storage 102 a) of the first charge pump stage 220 amay be coupled to the second charge pump stage 220 b, e.g. by means of the pump stage connection 110, 112. Alternatively or additionally, the first sub-stage 120 a(or its charge store 102 b) of the second charge pump stage 220 bmay be coupled to the first charge pump stage 220 a, e.g. by means of the pump stage connection 110, 112.The charge transfer cycle 500 may further include: a second phase 553 in which the two first sub-stages 120 aare in their second sub-stage phase 153 and the two second sub-stages 120 bare in their second sub-stage phase 153.For example, each charge storage 102 a, 102 bmay be decoupled from the pump stage connection 110, 112 (also referred to as input-output connection 110, 112). In other words, each charge storage 102 a, 102 bmay be decoupled from the respective other charge pump stage 220 a, 220 b. Alternatively or additionally, one or each first switch 104 aand / or one or each second switch 104 bof the two first charge pump stages 220 a, 220 bmay be simultaneously in a switching operation (compare FIG. 6 ).The charge transfer cycle 500 may further include: a third phase 555, in which the two first sub-stages 120 aare in their third sub-stage phase 155 and the two second sub-stages 120 bare in their first sub-stage phase 151. For example, the first sub-stage 120 a(or its charge store 102 a) of the first charge pump stage 220 acan be coupled to the second charge pump stage 220 b. Alternatively or additionally, the second sub-stage 120 a(or its charge store 102 b) of the second charge pump stage 220 bmay be coupled to the first charge pump stage 220 a, e.g. by means of the pump stage connection 110, 112.The second phase 553 may be temporally after the first phase 551, e.g. subsequent to it. Alternatively or additionally, the second phase 553 can be temporally after the third phase 553, e.g. subsequent to it.FIG. 6 illustrates a charge pump stage 600 according to various embodiments in a schematic circuit diagram, e.g. one of the charge pump stages described above or its first sub-stage 120 aand / or second sub-stage 120 b.The switch structure 104 may include a first switch 104 aand a second switch 104 b. Further, the switch structure 104 may include a control circuit 602 (also referred to as first control circuit 602).The control circuit 602 may be configured to control 602 sthe first switch 104 aand the second switch 104 bin accordance with a charge transfer cycle. In other words, the control circuit 602 may be configured to couple or decouple the charge storage 102 a, 102 bto or from the input 110 and the output 112 of the charge pump stage 600 a, respectively, by means of the first switch 104 aand the second switch 104 bin accordance with the charge transfer cycle.The charge transfer cycle may be configured as described herein (e.g., above).The shorter a time interval at which the first switch 104 aand the second switch 104 bare switched (i.e. change between an open state and a closed state) (i.e. the better their time fit is), the shorter the second substep phase 153 of the charge transfer cycle can be. If the first switch 104 aand the second switch 104 bhave the same channel conduction type, a first control signal can be provided for controlling the first switch 104 a, which control signal is in push-pull relationship with a second control signal, by means of which the second switch 104 bis controlled. This allows simultaneous switching of the first switch 104 aand the second switch 104 b(i.e. they are simultaneously in a switching process). In a push-pull manner, in this context, it can be understood that the first control signal reaches the switching threshold (illustratively a threshold electrical voltage) of the first switch 104 aand the second control signal reaches the switching threshold of the second switch 104 bwith a time delay that is less than approximately 1% of the duration of the charge transfer cycle (e.g. less than approximately 0.1% of the duration of the charge transfer cycle) and / or less than approximately 25% of the switching interval (e.g. less than 10% of the switching interval) of the two switches 104 a, 104 b. Illustratively, in this case, decoupling the charge storage from the output 112 and from the input 110 may be omitted.For providing the push-pull configured control signals (first control signal and second control signal), the charge pump stage 600 (e.g. its switch structure 104) may optionally comprise a push-pull generator 602 g. The push-pull generator 602 gmay, for example, comprise or be formed from at least one inverter (e.g. two cascaded inverters), at least one transistor-transistor gate (e.g. in a totem-pole circuit or in the form of a quasi-complementary output stage) and / or at least one transformer. In the following, still other possible implementations of the push-pull generator 602g are described, which may be used.For example, the push-pull generator 602 gmay be configured to invert the first control signal (which is coupled in, e.g., by the control circuit 602) or to delay it by half a period and to provide the inverted or delayed first control signal as a second control signal, as is described in more detail below, for example.Alternatively or additionally, a base control signal (e.g. a reference clock) can be coupled into the push-pull generator 602 g, which base control signal has twice the peak-to-valley value of the first control signal and / or of the second control signal, wherein the push-pull generator 602 gis configured to split off the first control signal and the second control signal from the base control signal, e.g. by means of a voltage divider (e.g. having a bridge circuit or formed therefrom).According to various embodiments, the charge pump stage 600 may include two sub-stages 120 a, 120 bconnected in parallel (analogous to FIG. 2A ) in a similar configuration. In yet a similar configuration according to various embodiments, the second switches 104 bof the two sub-stages 120 a, 120 bmay be cross-connected (i.e. form a cross-switch), cf. for example FIGS. 25 and 39.FIG. 7 illustrates a charge pump stage 700 according to various embodiments in a schematic circuit diagram, e.g. one of the charge pump stages described above or its first sub-stage 120 aand / or its second sub-stage 120 b.The charge storage 102 a, 102 b(e.g. the first charge storage 102 aor the second charge storage 102 b) may include or be formed from at least one capacitive component, e.g. a capacitor C 1. The charge storage 102 a, 102 bmay include an electrical capacitance.The charge storage 102 a, 102 b(e.g. the first charge storage 102 aor the second charge storage 102 b) may be coupled to the switch structure 104 by means of a node 702 k(also referred to as charge storage node 702 k).The first switch 104 aand the second switch 104 bmay be switched (i.e. driven) by means of the first control circuit 602 according to the charge transfer cycle, e.g. in a push-pull relationship to each other. The first switch 104 aand the second switch 104 bmay, for example, comprise or be formed from at least one transistor M 1, M 2, the gate of which is coupled to the first control circuit 602 (e.g. capacitively 704 a, 704 b), e.g. by means of the control inputs 602 a, 602 b(first control input 602 aand second control input 602 b).Generally, a capacitive coupling 704 a, 704 b, 704 cand / or the charge storage 102 a, 102 bmay be provided by means of a capacitive device. The capacitive component may have a capacitive reactance, i.e. a capacitance (e.g. a gate-source capacitance) and / or a frequency-dependent impedance. The capacitive component can have, for example, at least one capacitor C 2, C 3, C 4 and / or at least one transistor (e.g. its gate-source capacitance). In other words, alternatively or in addition to a capacitor, e.g. with a low required capacitance, the gate-source capacitance of a transistor may be used to provide the capacitive coupling.When the control circuit 602 is capacitively (i.e. by means of a first capacitive coupling 704 a) coupled to the first switch 104 a, the switch structure 104 may optionally include a first leveling circuit 104 d, 104 c, 104 e. The first capacitive coupling 704 acan be provided, for example, by means of a capacitor C 2. The first leveling circuit 104 d, 104 c, 104 emay be configured to couple a first capacitive coupling 704 ato the charge storage 102 a, 102 bin the second sub-stage phase 153 and / or in the third sub-stage phase 155. This can achieve, for example, that an electrical potential of the first capacitive coupling 704 ais set cyclically to a reference value (i.e. one of these drifting is prevented), which is defined by the charge storage device 102 a, 102 b, for example.The first leveling circuit 104 d, 104 c, 104 emay include, for example, a third switch 104 cconnected between the first control input 602 aand the charge storage 102 a, 102 b. The first leveling circuit 104 d, 104 c, 104 emay further include a second control circuit 612 for controlling the third switch 104 c. The third switch 104 cmay include, for example, at least one transistor M 4, the gate of which is coupled to the second control circuit 612 (e.g. capacitively 704 c), e.g. by means of the third control terminal 612 a. For example, the third switch 104 cmay be closed in the third sub-stage phase 155 and may otherwise be opened.The first leveling circuit 104 d, 104 c, 104 emay optionally include a fourth switch 104 dconnected between the third control terminal 612 aand the charge storage 102 a, 102 b. The fourth switch 104 dmay be controlled by means of the first control circuit 602, e.g. by means of the first control input 602 a(i.e. the fourth switch 104 dmay be synchronously clocked with the first switch 104 a, i.e. configured in common mode therewith). The fourth switch 104 dmay, for example, comprise at least one transistor M 5, the gate of which is coupled to the first control input 602 a.The first leveling circuit 104 d, 104 c, 104 emay optionally include a fifth switch 104 econnected between the first control input 602 aand the charge storage 102 a, 102 b. The fifth switch 104 emay include, for example, at least one transistor M 3, the gate of which is coupled to the input 110. This makes it possible to achieve the effect that the fifth switch 104 econnects the first control input 602 ato the charge storage 102 a, 102 bin the second and / or third phase in an electrically conductive manner, for example as long as an electrical voltage at the input 110 meets a predefined criterion, for example is greater than a predefined threshold value (i.e. that it is controlled indirectly by means of the charge transfer signal).When the control circuit 602 is capacitively (i.e., via a second capacitive coupling 704 b) coupled to the second switch 104 b, the switch structure 104 may optionally include a second leveling circuit 104 f. The second capacitive coupling 704 bmay be provided, for example, by means of a capacitor C 4. The second leveling circuit 104 fmay be configured to couple a second capacitive coupling 704 bto the output 112 in the second sub-stage phase 153 and / or in the first sub-stage phase 151. This can achieve, for example, setting an electrical potential of the second capacitive coupling 704 bto a reference value which is defined, for example, by the output 112.The second leveling circuit 104 fmay, for example, comprise or be formed from a sixth switch 104 f, which is connected between the second control input 602 band the output 112. The sixth switch 104 fmay include, for example, at least one transistor M 6, the gate of which is coupled to the charge storage 102 a, 102 b. This can achieve that the sixth switch 104 fconnects the second control input 602 bto the charge storage device 102 a, 102 bin the second and / or first phase in an electrically conductive manner, e.g. as long as an electrical voltage provided by the charge storage device 102 a, 102 bcontains a predefined criterion, e.g. is greater than a predefined threshold value (i.e. that it is controlled indirectly by means of the charge transfer signal).The charge pump stage 700 may be interconnected in a bootstrap configuration.During operation of the charge pump stage 700, a first control signal clk 2 p(e.g. a first control clock), e.g. capacitive 704 a, can be coupled into the first switch 104 a, e.g. by means of the first control input 602 a. A second control signal clk 1 p(e.g. a second control clock), e.g. capacitive 704 b, can be coupled into the second switch 104 b, e.g. by means of the second control input 602 b. The first control circuit 602 may be configured to provide the first control signal clk 2 pand / or the second control signal clk 1 p. The first control signal clk 2 pand the second control signal clk 1 pmay be shifted with respect to one another in time, for example by half the charge transfer cycle (i.e. its cycle half) and / or together by the duration of the first sub-stage phase 151 and the second sub-stage phase 153. Alternatively or additionally, the first control signal clk 2 pand the second control signal clk 1 pmay be complementary to one another (i.e. configured in a push-pull manner with respect to one another).A third control signal clk 2 n(e.g. a third control clock), e.g. capacitive 704 c, can be coupled into the first leveling circuit 104 d, 104 c, 104 e(e.g. its fourth switch 104 d), e.g. by means of the third control input 612 a. The second control circuit 612 may be configured to provide the third control signal clk 2 n.A fourth control signal pclk (also referred to as a charge transfer signal, e.g. a fourth control clock) can be coupled into the charge storage 102 a, 102 b, e.g. by means of a fourth control input 622 a. The charge pump stage 700 may include a third control circuit 622, which may be configured to provide the fourth control signal pclk. Illustratively, the fourth control input 622 aand the fourth control circuit 622 can be or can be capacitively coupled to the switch structure 104 by means of the charge storage 102 a, 102 b.The fourth control input 622 a(also referred to as clock input 622 a) may include or be formed from a clock input node, e.g. when the charge pump stage 700 is connected by its fourth control input 622 ato an additional circuit, e.g. to the third control circuit 622.The fourth control input 622 amay be capacitively coupled to the charge storage node 702 kor the switch structure 104 (for transferring electrical charge by means of the charge storage node according to a charge transfer signal coupled in by means of the control input 622 a.By means of the first switch 104 a, the charge storage node 702 kor the charge storage device 102 a, 102 bfor absorbing electrical charge can be electrically conductively connected to the input node or the input 110, for example in the first sub-stage phase 151 (also referred to as charging phase 151) of the charge transfer cycle. By means of the first switch 104 b, the input 110 (or an electrical voltage present at the input 110, also referred to as "Vin") can be decoupled from the charge storage device 102 a, 102 bor from the fourth control signal, e.g. in at least the third sub-stage phase 753 and in the second sub-stage phase 753.By means of the second switch 104 b, the charge storage node 702 kor the charge storage device 102 a, 102 bmay be electrically conductively connected to the output node or the output 112 for delivering electrical charge, e.g. in the third sub-stage phase 755 (also referred to as discharge phase 755) of the charge transfer cycle. By means of the second switch 104 b, the output 112 (or an electrical voltage present at the output 112, also referred to as "Vout") can be decoupled from the charge storage device 102 a, 102 bor from the fourth control signal, e.g. in at least the first sub-stage phase 751 and in the second sub-stage phase 753.The electrical voltage difference Vp(Vp=Vout-Vin) provided per charge pump stage 700 may approximately correspond to the peak-to-valley value of the charge transfer signal (pclk) (e.g., in no-load operation). The peak-to-valley value of the charge transfer signal may correspond to the electrical supply voltage, for example.FIG. 8 illustrates a signal profile 800 according to various embodiments in a schematic diagram in which a signal characteristic 801 (e.g. an electrical voltage of the signal, in arbitrary units) is illustrated over time 803 (in arbitrary units).The first control circuit 602 may be configured to provide a first control signal 802 (also referred to as clk 2 p) and the second control signal 804 (also referred to as clk 1 p).The second control circuit 612 may be configured to provide the third control signal 806.The fourth control circuit 622 may be configured to provide the charge transfer signal 808.According to the charge transfer signal 808, an electrical potential at the charge storage 102 a, 102 bor the charge storage node 702 k(or a resulting electrical voltage) may be changed. The electrical voltage of the charge storage 102 a, 102 bor at the charge storage node 702 k(also referred to as "Vint" or internal electrical voltage) may be shifted between Vin and Vout according to the charge storage cycle. The electrical voltage difference Vd provided per charge pump stage may approximately correspond to the peak-to-valley value of the charge transfer signal 808 (e.g., in no-load operation).According to various embodiments, an electrical voltage can be understood as an electrical potential difference (difference of two electrical potentials), e.g. between an output and an input. For example, an electrical voltage across a device (i.e., the electrical voltage dropping across the device) may be understood as the difference in electrical potentials on opposite sides (e.g., at the terminals) of the device. An electrical voltage at a node (e.g., a terminal, input, output, or the like) may be understood as the difference of the electrical potential at the node from an electrical reference potential (e.g., electrical ground). Indications about a plurality of electrical voltages in a circuit may relate to the same reference electrical potential.If the electrical voltage at a node is positive, its electrical potential is greater than the reference electrical potential. If the electrical voltage at a node is negative, its electrical potential is lower than the reference electrical potential. The greater the voltage at a node, the greater its electrical potential. An electrical voltage difference (e.g. between two nodes) can be understood as the difference between two electrical voltages which, when the two electrical voltages are related to the same electrical reference potential, corresponds to the difference between the corresponding electrical potentials (e.g. between the two nodes) (i.e. indicated independently of the electrical reference potential).The charge transfer signal 808 may include a first cycle portion 808 a(e.g., a first cycle half 808 a) and a second cycle portion 808 b(e.g., a second cycle half 808 b).A negative charge pump (or its negative charge pump stage) may be driven as follows: During the first cycle section 808 a, the charge transfer signal 808 may be configured such that an electrical potential (or an electrical voltage resulting therefrom) provided at the charge storage 102 a, 102 b(or charge transfer node 702 k) is equal to or greater than approximately the electrical potential of the input 110 (or a electrical voltage resulting therefrom of the input 110). During the second cycle section 808 b, the charge transfer signal 808 may be configured such that an electrical potential (or a resulting electrical voltage) provided at the charge storage 102 a, 102 b(or charge transfer node) is equal to or less than approximately the electrical potential of the output 112 (or a resulting electrical voltage of the output 112). The negative charge pump can provide a voltage on the output side, for example, which is smaller than the voltage coupled into the latter on the input side. The input 110 of the input-side charge pump stage of a charge pump may be at the smallest available electrical potential, e.g. at the reference potential (e.g. at 0 volts). The or each switch of the negative charge pump may be provided by means of NMOS transistors, for example.The first cycle section 808 amay include or consist of the first phase 151 and optionally a second phase 153. The second cycle section 808 amay include or consist of the third phase 155 and optionally an additional second phase 153.The first control signal 802 (a negative charge pump) may be configured such that the charge storage 102 a, 102 bis electrically conductively connected to the input 110 by means of the switch structure 104 (in the charging phase 151) if the charge storage 102 a, 102 bhas a greater electrical potential than the input 110. When the charge storage device 102 a, 102 bis electrically conductively connected to the input 110 by means of the switch structure 104, electrical charge can be emitted from the input 110 by the charge storage device 102 a, 102 b(also referred to as charge emission).The second control signal 804 can be configured such that the charge storage 102 a, 102 bis electrically conductively connected to the output 112 by means of the switch structure 104 (in the discharge phase 855) if the charge storage 102 a, 102 bhas a lower electrical potential than the output 112. When the charge storage device 102 a, 102 bis electrically conductively connected to the output 112 by means of the switch structure 104, electrical charge can be absorbed by the charge storage device 102 a, 102 bto the output 112 (also referred to as charge absorption). The charge absorption and the charge delivery can take place cyclically (also referred to as charge pumps), i.e. according to the charge transfer cycle.A positive charge pump (or its positive charge pump stage) can be or can be controlled in a complementary manner to the negative charge pump. In other words, the signals (i.e., the charge transfer signal 808 and the control signals may be inverted from the illustrated waveform. The positive charge pump can provide a voltage on the output side, for example, which is greater than the voltage coupled into the latter on the input side. The input 110 of the input-side charge pump stage of a charge pump may be at the largest available electrical potential, e.g. at the supply voltage. The or each switch of the positive charge pump can be provided, for example, by means of PMOS transistors.According to various embodiments, a low-noise voltage swing may be provided. For example, an electrical voltage coupled in at the input 110 and / or an electrical voltage coupled out at the output 112 may have a ripple of less than 300 mV (millivolt), e.g. in a range from about 100 mV to about 300 mV, with respect to about 200 mV.When the charge pump stage is operated free of load (i.e., without load or current load applied to the load), the internal electrical voltage Vint of the charge pump stage has a peak-to-valley value (e.g., an amplitude) equal to or less than the peak-to-valley value of the charge transfer signal 808. The peak-to-valley value of the charge transfer signal 808 (also referred to as charge transfer swing or electrical voltage swing) may be approximately VDD. Then, the electrical voltage difference between the input 110 and the output 112 of the charge pump stage may be equal to the charge transfer swing (in other words, Vp=Vout-Vin=VDD).According to various embodiments, the charging phase 151 and the discharging phase 155 may be spaced apart from each other in time (by means of the second phase 153), e.g. according to the duration of the second phase 153. This allows decoupling from an electrical potential of the output 112, so that an electrical voltage drop across the first switch 104 ais reduced. Illustratively, the first switch 104 aand the second switch 104 bfunction as voltage dividers which subdivide the electrical potential difference (electrical voltage) between the output 112 and the input 110, such that an electrical voltage across the first switch 104 aand / or across the second switch 104 bis less than or equal to the electrical voltage Vp from the input 110 to the output 112. Thus, less voltage-proof switches (e.g. low-voltage switches) can be used, e.g. the same switches that are used for operating the logic (e.g. the chip logic). Optionally, the cross-sectional area (i.e. the occupied chip area) of the switches may be reduced or alternatively or additionally the VDD may be increased. Furthermore, the power consumption of the charge pump stage can be reduced, illustratively since the switches can be controlled by means of a control signal which is at VDD level, and / or a bootstrap circuit for the switches can be dispensed with. Alternatively or additionally, the gate capacitance of the switches 104 a, 104 b(e.g. of the transistors M 1, M 2) can be reduced with the same switching resistance, which further reduces the power consumption of the charge pump stage.FIG. 9 illustrates a charge pump stage 900 according to various embodiments in a schematic circuit diagram. The charge pump stage 900 includes a first sub-stage 120 aand a second sub-stage 120 bcoupled in parallel to each other between the output 112 and the input 110 (e.g., push-pull sub-stages 120 a, 120 b).The two sub-stages 120 a, 120 bmay each include a charge storage 102 a, 102 b(e.g. the first charge storage 102 aor the second charge storage 102 b), e.g. provided by means of capacitors C 1, C 11.The first control input 602 aand the second control input 602 bmay be interconnected in a crossed manner. In other words, the first control input 602 aof the first sub-stage 120 amay be coupled to the second control input 602 bof the second sub-stage 120 b. Alternatively or additionally, the first control input 602 aof the second sub-stage 120 bmay be coupled to the second control input 602 bof the first sub-stage 120 a.The first switch 104 a(e.g. comprising transistor M 2) of the first sub-stage 120 aand the second switch 104 b(e.g. comprising transistor M 11) of the second sub-stage 120 bmay each be coupled to (i.e. may be configured for synchronously switching) the first control input 602 aof the first sub-stage 120 a. The first switch 104 a(e.g. comprising transistor M 12) of the second sub-stage 120 band the second switch 104 b(e.g. comprising transistor M 1) of the first sub-stage 120 amay each be coupled to the second control input 602 bof the first sub-stage 120 a(i.e. these may be configured for synchronously switching).For example, the first switches 104 aof the two sub-stages 120 bmay be switched offset from one another by one cycle half, e.g. in a push-pull manner. Alternatively or additionally, the second switches 104 aof the two sub-stages 120 bmay be switched offset from one another by one cycle half, e.g. in a push-pull manner.The configuration of the charge pump stage 900 may also be referred to as a push-pull configuration (also referred to as a "push-pull configuration"). Illustratively, the two charge transfer signals coupled into the charge stores 102 a, 102 bof the charge pump stage 900 may be push-pull with respect to one another.The capacitive couplings can be provided by means of capacitors C 2, C 3, C 4, C 12, C 13, C 14. The switches may be provided by transistors M 3, M 4, M 5, M 6, M 13, M 14, M 15, M 16.FIG. 10 illustrates a signal profile 1000 according to various embodiments in a schematic diagram in which a signal characteristic 801 (e.g. an electrical voltage of the signal, in arbitrary units) is illustrated over time 803 (in arbitrary units).A first control signal 802 (e.g. a first control clock 802) can be coupled into the first control input 602 aof the first sub-stage 120 aand / or into the second control input 602 bof the second sub-stage 120 b. A second control signal 804 (e.g. a second control clock 804) can be coupled into the first control input 602 aof the second sub-stage 120 band / or into the second control input 602 bof the first sub-stage 120 a. For example, the first control circuit 602 may be configured to provide the first control signal 802 and the second control signal 804. The first control signal 802 and the second control signal 804 may correspond in terms of their signal characteristic and / or be provided in a manner offset in time with respect to one another, for example offset in time by a cycle section 808 a, 808 bof the charge transfer cycle, for example offset in time by half the duration of the charge transfer cycle (i.e. by half the cycle thereof). For example, the first control signal 802 and the second control signal 804 may be phase shifted from each other, e.g., by the first phase 151 and by the second phase 153.A third control signal 806 (e.g. a third control clock 806) can be coupled into the third control input 612 aof the first sub-stage 120 a. The second control circuit 612 may be configured to provide the third control signal. The third control signal 806 may be coupled to the leveling circuit 104 c, 104 d, 104 eof the first sub-stage 120 aand may be configured such that its leveling circuit 104 c, 104 d, 104 ein the second phase 153 of the first cycle section 808 acouples its first capacitive coupling 704 ato its charge storage 102 a, 102 b.An additional third control signal 816 (e.g. a third control clock 806) can be coupled into the third control input 612 aof the second sub-stage 120 b. The second control circuit 612 may be configured to provide the additional third control signal 816. The additional third control signal 816 may be coupled to the leveling circuit 104 c, 104 d, 104 eof the second sub-stage 120 band may be configured such that its leveling circuit 104 c, 104 d, 104 ein the second phase 153 of the second cycle section 808 bcouples its first capacitive coupling 704 ato its charge storage 102 a, 102 b.The third control signal 806 and the additional third control signal 816 may be the same in their signal characteristic and / or phase shifted with respect to one another, e.g. by half the duration of the charge transfer cycle (also referred to as cycle half).A fourth control signal 808 (e.g. a fourth control clock 808) may be coupled into a fourth control input 622 aof the first sub-stage 120 a(also referred to as a first charge transfer signal 808). The third control circuit 622 may be configured to provide the fourth control signal 808.An additional fourth control signal 818 (e.g. an additional fourth control clock 818) may be coupled into a fourth control input 622 aof the second sub-stage 120 b(also referred to as second charge transfer signal 818). The third control circuit 622 may be configured to provide the additional fourth control signal 808.The fourth control signal 808 and the additional fourth control signal 818 may correspond in terms of their signal characteristic (e.g. peak-to-valley value, period duration, temporal mean value, signal shape) and / or be phase-shifted with respect to one another, e.g. by half the cycle. The electrical voltage difference Vd provided per charge pump stage may correspond approximately to the peak-to-valley value of the fourth control signal 808 and the additional fourth control signal 818, respectively (e.g., in no-load operation).The charge transfer cycle can be provided, e.g. synchronized, or can be provided by means of a reference clock 1002 (also referred to as a "clock"). The reference clock 1002 may be provided by means of a clock generator. The reference clock 1002 may be coupled into the charge pump stage control circuitry 602, 612, 622. This allows the control circuits 602, 612, 622 of the charge pump stage to run synchronously with one another.Generally, a clock signal (e.g., the reference clock) may have one of different waveforms, e.g., a trapezoidal waveform, a rectangular waveform, a triangular waveform, or a superposition thereof.A negative charge pump (or its negative charge pump stage) may be driven as follows: The charge transfer signal 808 may differ between the first cycle section 808 aand the second cycle section 808 b. During the first cycle section 808 a, the first charge transfer signal 808 may be configured such that an electrical potential (or a resulting electrical voltage) provided at the charge storage 102 a, 102 b(or charge transfer node) of the first substep 120 ais equal to or greater than approximately the electrical potential of the input 110 (or a resulting electrical voltage of the input 110). During the second cycle section 808 b, the first charge transfer signal 808 may be configured such that an electrical potential (or a resulting electrical voltage) provided at the charge storage 102 a, 102 b(or charge transfer node) of the first substep 120 ais equal to or less than approximately the electrical potential of the output 112 (or a resulting electrical voltage of the output 112).The second charge transfer signal 818 may be different between the first cycle portion 808 aand the second cycle portion 808 b. During the first cycle section 808 a, the second charge transfer signal 818 may be configured such that an electrical potential provided at the charge storage 102 a, 102 b(or charge transfer node) of the second sub-stage 120 b(or a resulting electrical voltage) is equal to or less than an electrical potential of the output 112 (or a resulting electrical voltage of the output 112) and / or of the charge storage 102 a, 102 b(or charge transfer node) of the first sub-stage 120 a. During the second cycle section 808 b, the second charge transfer signal 818 may be configured such that an electrical potential provided at the charge storage 102 a, 102 b(or charge transfer node) of the second sub-stage 120 b(or a resulting electrical voltage) is equal to or greater than an electrical potential of the input 110 (or a resulting electrical voltage of the input 110) and / or of the charge storage 102 a, 102 b(or charge transfer node) of the first sub-stage 120 a.The control signals (i.e. the first control signal 802, the second control signal 804 and the charge transfer signals 808, 818) can be configured such that the charge absorption of the first sub-stage 120 aand the charge output of the second sub-stage 120 bare effected simultaneously (push-pull). Alternatively or additionally, the control signals can be configured such that the charge absorption of the second sub-stage 120 band the charge delivery of the first sub-stage 120 atakes place simultaneously. The charge absorption and the charge delivery can take place cyclically.Optionally, the second phase 153 of the first cycle portion 808 aand / or the second phase of the second cycle portion 808 bmay be omitted, e.g. when the second control signal 804 and the first control signal 802 are arranged in a push-pull relationship to each other (e.g. when the first control signal 802 and the second control signal 804 are inverted to each other).A positive charge pump (or its positive charge pump stage) can be or can be controlled in a complementary manner to the negative charge pump. In other words, the signals (i.e., the charge transfer signals 808, 818 and the control signals may be inverted from the illustrated waveform.FIG. 11A illustrates an electric potential profile 1100 aaccording to various embodiments in a schematic diagram in which an electric potential 801 (in arbitrary units) is illustrated over time 803 (in arbitrary units). For example, the electrical potential profile 1100 acan occur in a load-free state of a charge pump stage.The electrical potential 1112 of the output 112 (output-side electrical potential 1112, Vout) may be different from the electrical potential 1110 of the input 110 (input-side potential 1110, Vin), e.g. larger (in the case of a positive charge pump) or none (in the case of a negative charge pump) than the input-side electrical potential 1110. The electrical potential 1702 kof the charge storage 102 a, 102 b(or of the charge transfer node 702 k), also referred to as charge transfer potential 1702 k, can alternate back and forth between the input-side electrical potential 1110 and the output-side electrical potential 1112. The peak-to-valley value (e.g., amplitude) of the charge transfer potential 1702 kmay be approximately VDD.The electrical potential 1104 aof the first switch 104 a(controlled by means of the first switch signal 1104 a), e.g. at its control input 602 a, may differ from the charge transfer potential 1702 k(such that the first switch 104 ais closed) in the charging phase 151 and may otherwise be the same (such that the first switch 104 ais open). Alternatively or additionally, the first switch signal 1104 amay be different from the input-side potential 1110 and / or from the output-side potential 1112 (such that the first switch 104 ais open) in the charging phase 151.For example, output potential 1112 may be at about -8 volts and input potential 1110 may be at about -5.3 volts (e.g., with respect to electrical ground). The peak-to-valley value (e.g., amplitude) of the charge transfer potential 1702 k(and / or VDD) may be about 2.7 volts. In the no load state (i.e., unloaded), the charge pump stage may provide an electrical voltage swing Vp of about VDD.The duration of the charging phase 151 may be, for example, in a range from about 0.01 μs to about 0.1 μs, e.g., about 0.036 μs. Alternatively or additionally, the duration of the charging phase 151 may correspond to the duration of the discharging phase 155. The duration of the second sub-stage phase 153 may be less than about 100 ns (nanoseconds), e.g. shorter than about 10 ns, e.g. shorter than about 1 ns.FIG. 11B illustrates an electrical potential profile 1100 bin accordance with various embodiments in a schematic diagram, analogous to FIG. 11A.The electrical potential 1104 bof the second switch 104 b(controlled by means of the second control signal clk 1 p), e.g. coupled into its control input 602 b, can differ from the output-side potential 1112 in the discharge phase 155 (such that the second switch 104 bis closed) and otherwise be the same (such that the second switch 104 bis open). Alternatively or additionally, the second control signal 1104 bmay be different from the charge transfer potential 1702 kin the charging phase 151 and the discharging phase 155.FIG. 12A illustrates an electrical potential profile 1200 aaccording to various embodiments in a schematic diagram, analogously to FIG. 12A, for example in a loaded state of the charge pump stage (i.e. when an electrical load decreases the coupled-out Vout).FIG. 12B illustrates an electrical potential profile 1200 aaccording to various embodiments in a schematic diagram, analogously to FIG. 12B, for example in a loaded state of the charge pump stage.FIG. 13A illustrates a level converter circuit 1300 aaccording to various embodiments in a schematic circuit diagram.The level converter circuit 1300 amay include a signal source 1302 (e.g. including or formed from a first level converter 1302 and / or a push-pull generator 1302) and a second level converter 1304.According to various embodiments, the signal source 1302 may include or be formed from the first level converter 1302 (i.e. may be configured to provide one or more level converter signals, e.g. level-converted clock signals). The signal source 1302 does not necessarily have to be configured to provide two complementary signals, for example.In one or more embodiments, the signal source 1302 may include or be formed from a push-pull generator (i.e., configured to provide two complementary signals). For example, the signal source 1302 may not necessarily be configured to provide a level-converting signal (e.g., a level-converted clock signal).In one or more alternative embodiments, the signal source 1302 may include the push-pull generator and the first level converter (i.e., configured to provide two complementary level converter signals, e.g., complementary level-converted clock signals.The signal source 1302 (e.g. the first level converter 1302) may be or may be capacitively 1306 coupled on the output side 1302 ato an input 1304 eof the second level converter 1304. By means of the capacitive coupling 1306, the first level converter 1302 and the second level converter 1304 may be galvanically separated from one another.For example, the capacitive coupling 1306 may have a charge storage device (e.g. a transistor) which capacitively couples the first level converter 1302 on the output side to an input 1304 eof the second level converter 1304.According to various embodiments, the level shifter circuit 1300 amay require about 20% less (e.g., about 10% less) output power of the charge pumps supplying the level shifter circuit 1300 athan a conventional level shifter cascading. Thus, illustratively, about 10% to 20% less chip area may be required for the charge pumps and / or hold capacitors, which saves up to about 40% of the total chip area (e.g., about 2.38 mm 2) in total. The total power consumption of the chip can thus be reduced, e.g. to less than 6.6 milliwatts (e.g. a current consumption of less than 2.4 mA at 2.75 V). Only the charge pumps may cause about half the power consumption of the chip.Reference is now made to the first level converter 1302 and the first level converter signal generated by it. Analogously, the push-pull generator 1302 can be configured. For example, the first level converter signal can have two complementary level converter signals, i.e. a first level converter signal and a first level converter signal complementary thereto can be generated. Alternatively, instead of the first level converter signal, a non-level-converted push-pull signal (e.g. with a constant level as the associated input signal and / or to the level of the supply voltage) may be generated.FIG. 13B illustrates a level converter 1300 b, e.g. the first level converter 1302, according to various embodiments in a schematic circuit diagram.The level converter 1300 b(e.g. the first level converter 1302) may have a first terminal 1352 (also referred to as a high-voltage terminal 1352 or a VDDH terminal) and a second terminal 1354 (also referred to as a reference terminal 1354), between which a reference electrical voltage (e.g. a positive reference electrical voltage, e.g. a positive high-voltage electrical voltage, for example 3.3 volts or more) may be present. Electrical ground can be present at the second terminal 1354, for example.The level converter 1300 b(e.g. the first level converter 1302) can furthermore have, on the input side, a third terminal 1302 e(also referred to as signal input terminal or input 1302 e) and a fourth terminal 1358 (also referred to as supply voltage terminal 1358). A positive electrical supply voltage (for example, less than approximately 2.5 volts, e.g., approximately 1.5 volts) may be present between the supply voltage terminal 1358 and the reference terminal 1354, which is less than the electrical reference voltage, e.g., less than 50% of the electrical reference voltage. The reference voltage may be provided by means of a charge pump according to one or more embodiments.Further, the level converter 1300 b(e.g. the first level converter 1302) may include a push-pull generator 602 gcoupled to the operating voltage terminal 1358 and the signal input terminal 1302 e. For example, as illustrated in FIG. 13B, the push-pull generator 602 gmay include or be formed from two cascaded inverters (first inverter MP 1, MN 1 and second inverter MP 2, MN 2), e.g., CMOS inverters. The push-pull generator 602g may provide two counter-clocked (i.e. complementary) signals "abuf" and "xabuf" based on a signal (e.g. base control signal) coupled to the signal input terminal 1302e. For example, the push-pull generator 602 gmay be configured to invert the base control signal by means of the first inverter MP 1, MN 1 (for example comprising two transistors MP 1, MN 1 in CMOS configuration) and to provide the inverted control signal xabuf. In addition, the push-pull generator 602 gmay be configured to invert the inverted control signal xbuf by means of the second inverter MP 2, MN 2 (for example having two transistors MP 2, MN 2 in CMOS configuration) and to provide the additional inverted control signal abuf.Further, the level converter 1300 b(e.g., the first level converter 1302) may include a cross-coupled latch 1364 (e.g., including transistor pair MP 3, MN 3 in CMOS configuration and transistor pair MP 4, MN 4 in CMOS configuration) and an inverter structure 1366 (also referred to as output inverter). The inverter structure 1366 may include two switches 1366 sthat differ in conduction type (e.g., two transistors MP 5 and MN 5 in CMOS configuration).For example, the level converter 1300 bmay include a plurality of n-channel conductive type transistors (MN 1 to MN 5) and a plurality of p-channel conductive type transistors (MP 1 to MP 5).For example, transistors MP 3, MP 4, MN 3, MN 4 of cross-coupled latch 1364 and transistors MP 5, MN 5 of inverter structure 1366 may be high voltage transistors. Alternatively or additionally, the transistors MN 1, MN 2, MP 1, MP 2 of the push-pull generator 602 gmay be low-voltage transistors.FIG. 14A illustrates a level converter 1400 a, e.g. the first level converter, according to various embodiments in a schematic circuit diagram.For example, cross-coupled latch 1364 of level converter 1400 amay include three series-connected transistors (with additional transistors MP 6 and MP 7) between first terminal 1352 and second terminal 1354, which improves the switching speed of the latch (e.g., reduces switching delays) and / or reduces current consumption in the switching operation of the latch.Optionally, a larger electrical supply voltage (for example in a range from about 2 volts to about 2.7 volts) and / or a larger electrical reference voltage may be enabled (for example in a range from about 4 volts to about 6 volts, for example about 4 volts).For example, the transistors MP 3, MP 4, MP 6, MP 7, MN 3, MN 4 of the cross-coupled latch 1364 and the transistors MP 5, MN 5 of the inverter structure 1366 may be high voltage transistors. Alternatively or additionally, the transistors MN 1, MN 2, MP 1, MP 2 of the push-pull generator 602 gmay be low-voltage transistors.FIG. 14B illustrates a level converter 1400 b, e.g. the first level converter, according to various embodiments in a schematic circuit diagram.Level shifter 1400 bmay include n-channel (e.g., NMOS) transistors MN 1 to MN 10, and p-channel (e.g., PMOS) transistors MP 1 and MP 2.FIG. 15 illustrates a level converter 1500, e.g. the first level converter, according to various embodiments in a schematic circuit diagram.The level converter 1500 may include a first level converter stage 1500 aand a second level converter stage 1500 b(including resistors R 1, R 2) coupled together. Further, the level converter 1500 may include an inverter structure 1366 (including an output inverter MP 11, MN 11) including a plurality of inverters connected in series for reducing a phase difference of the two complementary signals Y and Y_n.Further, the level converter 1500 may include an additional terminal 1360 (also referred to as a back-up voltage terminal 1360). Between the additional terminal 1360 and the second terminal 1354, an electrical support voltage (for example in a range from approximately 2.5 volts to approximately 3 volts) may be present which is smaller than the electrical reference voltage, e.g. smaller than 50% of the electrical reference voltage, and / or larger than the electrical supply voltage. The electrical reference voltage can be, for example, more than 6 volts, e.g., approximately 8 V.The electrical support voltage may be provided by means of a charge pump according to various embodiments.Further, the level converter 1500 may include an additional reference terminal 1356 (also referred to as a VSSL terminal or second high voltage terminal 1356 or negative high voltage terminal 1356) to which an additional reference electrical voltage may be applied (e.g., a negative reference electrical voltage, e.g., a high voltage negative electrical voltage, for example -3.3 volts or more).The output 1304 aof the output inverter 1366 may include two complementary terminals Y, Y_n, a first terminal Y configured to couple out the input signal A according to the reference electrical voltage (e.g., a positive reference electrical voltage) and a second terminal Y_n configured to couple out the input signal A according to the additional reference electrical voltage (e.g., a negative reference electrical voltage).Level shifter 1500 may include n-channel (e.g., NMOS) transistors MN 1 through MN 14 and p-channel (e.g., PMOS) transistors MP 1 and MP 11.FIG. 16A illustrates a level converter 1600 a, e.g. the first level converter 1302 and / or the second level converter 1304, according to various embodiments in a schematic circuit diagram.The level shifter 1600 may include an input 1600 e(e.g., input 1304 eor input 1302 e) and an output 1600 a(e.g., output 1304 aor output 1302 a). The level converter 1600 may be configured to convert a first signal 1602 coupled into a second signal 1604 at the input 1600 eand to couple out at the output 1602 a. Illustratively, the level converter 1600 acan be configured to map the signal profile of the first signal 1602 from a first electrical voltage range into a second electrical voltage range different therefrom. The second signal 1604 (also referred to as a level converter signal 1604) may have a greater level 1604 p(signal level, also referred to as output level) than the first signal 1602 p, e.g. a level according to an electrical potential present at a high-voltage terminal 1606 (e.g. first high-voltage terminal 1352 or second high-voltage terminal 1354) of the level converter 1600 a.A level can be understood as a measure which represents a relative position of a signal with respect to an electrical reference potential, for example its peak-to-valley value, peak value, temporal mean value or amplitude. For example, the second signal 1604 can have a temporal average value according to the electrical potential present at a high-voltage terminal 1606, a peak-to-valley value according to the electrical potential present at a high-voltage terminal 1606, and / or a peak value according to the electrical potential present at a high-voltage terminal 1606.According to various embodiments, the first signal 1602 and the second signal 1604 may match in a signal characteristic, e.g. in at least one of a frequency, a spectrum, a signal waveform, a signal waveform, or the like.FIG. 16B illustrates a level converter 1600 b, e.g. a first level converter 1302 and / or a second level converter 1304, according to various embodiments in a schematic circuit diagram.The level converter 1600 bmay include a charge pump 1362, e.g. a Pelliconi charge pump. In the case of the second level converter 1304, the capacitive coupling 1306 may provide the charge storage 102 a, 102 bof the charge pump 1362.Further, the level converter 1600 bmay include an inverter structure 1366. The inverter structure 1366 may be connected between the input 1600 eof the level converter 1600 band the output 1600 aof the level converter 1600 b.The charge pump 1362 may be configured to provide an electrical voltage difference for switching the inverter structure 1366 (inverter switching electrical voltage). In other words, a charge storage node 702 kof the charge pump 1362 (or its charge pump stage) may be coupled to a control input 1366 eof the inverter structure 1366, e.g. to a gate of the transistors of the inverter structure 1366. For example, the charge pump 1362, or its charge pump stage, may be coupled with its clock input 622 aor charge storage node, to the input 1600 eof the level converter 1600 b. Thus, switching of the inverter structure 1366 may be performed according to a clock of the charge pump 1362 (i.e., according to the charge transfer cycle). The voltage swing Vp provided by the charge pump 1362 may correspond to the peak-to-valley value of the control signal coupled into the inverter structure 1366.The charge pump 1362, or its charge pump stage, can have a latch, i.e. two inverters cross-coupled to one another (e.g. CMOS inverters), e.g. a latch in Pelliconi configuration.FIG. 17A illustrates a level converter 1700 a, e.g. the first level converter 1302 and / or the second level converter 1304, according to various embodiments in a schematic circuit diagram.The charge pump 1362 may include two sub-stages 120 a, 120 b(first sub-stage 120 aand second sub-stage 120 b) which are connected in parallel to each other. The two sub-stages 120 a, 120 bmay be connected between the inverter structure 1366 and the input 1600 e. Thus, switching of the inverter structure 1366 may be performed according to a clock of the first sub-stage 120 aand the second sub-stage 120 b. For example, the first sub-stage 120 aand the second sub-stage 120 bmay be configured in a push-pull manner with respect to one another (also referred to as complementary sub-stages 120 a, 120 b).FIG. 17B illustrates a level converter circuit 1700 bin accordance with various embodiments in a schematic circuit diagram.The level converter circuit 1700 bmay include an additional signal source 1308 (e.g., a third level converter 1302 and / or an additional push-pull generator 1302) and the second level converter 1304.According to various embodiments, the additional signal source 1308 may include or be formed from the third level converter 1308 (i.e. may be configured to provide one or more level converter signals, e.g. level-converted data signals). The additional signal source 1308 does not necessarily have to be set up, for example, for providing two complementary signals.In one or more embodiments, the additional signal source 1308 may include or be formed from a push-pull generator (i.e., configured to provide two complementary signals). For example, the additional signal source 1308 may not necessarily be configured to provide a level-converting signal (e.g., level-converted data signals).In one or more alternative embodiments, the additional signal source 1308 may include the push-pull generator and the third level converter (i.e., configured to provide two complementary level converter signals, e.g., complementary level-converted data signals).The additional signal source 1308 (e.g. the third level converter 1308) may be capacitively coupled on the output side to a clock input 622 aof the second level converter 1304, e.g. to the clock input 622 aof the second charge pump of the second level converter 1304. The signal source 1302 (e.g., the first level converter 1302) may couple a periodic signal (e.g., a level-shifting signal) to the second level converter 1304, for example.The additional signal source 1308 (e.g. the third level converter 1308) can be coupled on the input side 1308 e(i.e. with its input 1308 e) to the input 1302 e(e.g. data input 1302 e) of the first level converter 1302, e.g. by means of a common connection 1704 or connection terminals 1704. The additional signal source 1308 (e.g. the third level converter 1308) may be configured to provide a third signal (e.g. a third level converter signal) which is capacitively coupled into the second level converter 1304. The additional signal source 1308 (e.g. the third level converter 1308) may couple an aperiodic signal (e.g. a data signal) and / or two complementary aperiodic signals (e.g. data signals) to the second level converter 1304, for example.The second level converter signal may have a greater level (signal level) than the third level converter signal (and / or the two additional push-pull signals). For example, the second level converter signal may have a greater amplitude than the third level converter signal (and / or the two additional push-pull signals), a greater temporal mean value than the third level converter signal (and / or the two additional push-pull signals), a greater peak-to-valley value than the third level converter signal and / or a greater peak value than the third level converter signal (and / or the two additional push-pull signals).According to various embodiments, the third level converter signal (and / or the two additional push-pull signals) and the second signal may coincide in a signal characteristic, e.g. in at least one frequency, a spectrum, or the like.Reference is now made to the third level converter 1308 and the third level converter signal generated by it. Analogously, the additional push-pull generator 1308 can be configured. For example, the third level converter signal can have two complementary level converter signals, i.e. a third level converter signal and a third level converter signal complementary thereto can be generated. Alternatively, instead of the third level converter signal, an additional push-pull signal that is not level-converted can be generated.FIG. 18 illustrates a level converter circuit 1800 according to various embodiments in a schematic circuit diagram.The level converter circuit 1800 may include a level converter 1302 (also referred to as a first level converter 1302) and an inverter structure 1366. The inverter structure 1366 may include or be formed from two complementary inverters (e.g., CMOS inverters), e.g., a first inverter MP 1, MN 1 and a second inverter MP 2, MN 2.The output 1302 aof the first level converter 1302 may include two complementary terminals Yp, Yn, of which a first terminal Yp may be configured to provide a first level converter signal clk 4 vp(e.g. a positive level converter signal) and an additional first terminal Yn may be configured to provide an additional first level converter signal clk 4 vn(e.g. a negative level converter signal). For example, the first level converter 1302 may include or be formed from a push-pull generator 602 g.Further, the level converter circuit 1800 may include a charge pump 1362, the charge storage 102 a, 102 bof which is connected between its switch structure 104 (e.g. including a first latch MN 5, MP 5, Mp 6, MN 6 and / or a second latch MN 3, MP 3, MP 4, MN 4 or formed therefrom) and the first level converter 1302. The charge pump 1362 may have two (e.g. complementary) sub-stages 120 a, 120 bconnected in parallel, of which a first sub-stage 120 amay be or may be coupled on the input side 622 ato the first terminal Yp of the output 1302 aand / or a second sub-stage 120 bmay be coupled on the input side 622 ato the additional first terminal Yn of the output 1302 a.The charge storage 102 aof the first sub-stage 120 aand / or the charge storage 102 bof the second sub-stage 120 bmay be part of the capacitive coupling 1306. Illustratively, the switch structure 104 of the first sub-stage 120 aand / or of the second sub-stage 120 btogether with the inverter structure 1366 may be part of the second level converter 1304. The second level converter 1304 may be or may be capacitively 1306 coupled on the input side 1304 eto the output 1302 aof the first level converter 1302.The output 1304 aof the second level converter 1304 (or the inverter structure 1366) may include two complementary terminals Y, Y_n, of which a second terminal Y may be configured to provide a second level converter signal (e.g. a positive level converter signal) and an additional second terminal Y_n may be configured to provide an additional second level converter signal (e.g. a negative level converter signal).At the supply voltage terminal 1358, an electric DC voltage VDD for supplying (i.e. a supply voltage) the first level converter 1302 may be applied. The electric supply voltage VDD may be, for example, the core electric voltage, e.g., 2.75 volts or less.The level converter circuit 1800 may be configured to convert an input signal clk, which is present at the input 1302 eof the first level converter 1302, into a second level converter signal, which has a first electrical voltage of the first high-voltage terminal 1352. The first electrical voltage at the first high voltage terminal 1352 may be greater (in magnitude) than the electrical supply voltage, e.g., about 10 volts or more. Alternatively or additionally, the level converter circuit 1800 may be configured to convert the input signal clk, which is present at the input 1302 eof the first level converter 1302, into an additional second level converter signal, which has a second electrical voltage of the second high-voltage terminal 1356. The second electrical voltage at the second high voltage terminal 1356 may be greater (in magnitude) than the electrical supply voltage, e.g., the magnitude of the second electrical voltage may be about 8 volts or more. For example, the second electrical voltage at the second high-voltage terminal 1356 may be negative (with sign attention) and / or less than the electrical supply voltage, e.g., the second electrical voltage may be about -8 volts or less (i.e., more negative).The first inverter MP 1, MN 1 of the inverter structure 1366 providing the additional second high voltage terminal Y_n may include two switches 1366 s(e.g. transistors MP 1, MP 2) that differ in conduction type. A second inverter MP 2, MN 2 of the inverter structure 1366 providing the second high voltage terminal Y may include two switches 1366 s(e.g., transistors MP 1, MN 1) that differ in conduction type. The first inverter MP 1, MN 1 may decouple the second level converter signal and the second inverter MP 2, MN 2 may decouple the additional second level converter signal.The switches MP 1, MP 2 of the inverter structure 1366 having a first conductivity type (e.g. PMOS switches MP 1, MP 2) may be controlled by means of the switch structure 104 of the first sub-stage 120 a(also referred to as first latch).The first sub-stage 120 aand the first latch can comprise or be formed from a Pelliconi charge pump and Pelliconi charge pump stage, respectively. In other words, the switch structure 104 of the first sub-stage 120 amay include two cross-coupled inverters, of which a first inverter MP 3, MN 3 controls a first transistor MP 1 of the first charge type, and of which a second inverter MP 4, MN 4 controls an additional first transistor MP 2 of the first charge type. The first sub-stage 120 amay be pumped by the first signals clk 4 vpand clk 4 vn(the first level converter signal clk 4 vpand the additional first level converter signal clk 4 vn), e.g. by means of the first charge storage 102 aof the capacitive coupling 1306 (also referred to as coupling capacitors C 3, C 4).The first sub-stage 120 acan be configured to provide a first electrical support voltage VDD_auxp(e.g. a positive electrical support voltage VDD_auxp), which can optionally be capacitively coupled on the output side to the second high-voltage terminal 1352, e.g. by means of a capacitor C 1 (alternatively by means of a transistor or its gate-source capacitance) for stabilizing (i.e. buffering) the first electrical support voltage VDD_auxp, also referred to as buffer coupling C 1.The first sub-stage 120 amay include two charge transfer nodes vgp 1, vgp 2 (also referred to as clock nodes) that may control the transistors MP 1, MP 2 of the inverter structure 1366 having the first conductivity type (e.g., PMOS transistors MP 1, MP 2), e.g., gates thereof. The two charge transfer nodes vgp 1, vgp 2 may have a smaller electrical voltage swing (i.e., a peak-to-valley value) than the output 1302 aof the first level shifter 1302, e.g., smaller than the first signals clk 4vp and clk 4vn, e.g., smaller than or equal to about 80% of the output 1302 a. When the first signals clk 4 vpand clk 4 vnhave an electrical voltage swing of about 5 volts (e.g., between 0 volts and 5 volts), the electrical voltage swing Vpof the two charge transfer nodes vgp 1, vgp 2may be about 4 volts (e.g., between VDDH and VDD_auxp). In other words, the electrical support voltage VDD_auxp may be about VDDH-Vp, e.g., about VDDH-4 volts.Due to the strong coupling by means of the capacitors C 3, C 4, the electrical voltage of the charge transfer nodes vgp 1, vgp 2 simultaneously falls and changes to the output 1302 aof the first level converter 1302, e.g. simultaneously to the first signals clk 4vp and clk 4vn. In other words, a speed loss in the switching operation can be almost zero.The second sub-stage 120 b(also referred to as second latch) (e.g. complementary to the first sub-stage 120 a) may be configured to control the transistors MN 1, MN 2 of the inverter structure 1366 having a second conductivity type (e.g. NMOS transistors MN 1, MN 2). The switch structure 104 of the second sub-stage 120 bmay include two inverters, of which a first inverter MP 5, MN 5 controls a second switch MN 1 of the second charge type, and of which a second inverter MP 6, MN 6 controls an additional second switch MN 2 of the second charge type. The second sub-stage 120 bmay be pumped by the first signals clk 4 vpand clk 4 vn(the first level converter signal clk 4 vpand the additional first level converter signal clk 4 vn), e.g. by means of the second charge storage 102 bof the capacitive coupling 1306 (also referred to as coupling capacitors C 5, C 6).The second sub-stage 120 bmay be configured to provide a second electrical support voltage VDD_auxn(e.g. a negative electrical support voltage VDD_auxn), which may optionally be capacitively coupled on the output side to the first high-voltage terminal 1356, e.g. by means of a capacitor C 2 (alternatively by means of a transistor or its gate-source capacitance) for stabilizing (i.e. buffering, also referred to as buffer coupling) the second electrical support voltage VDD_auxn, also referred to as buffer coupling C 2.The second sub-stage 120 bmay include two charge transfer nodes vgn 1, vgn 2 that may control the transistors MN 1, MN 2 of the inverter structure 1366 having the second conductivity type (e.g., NMOS transistors MN 1, MN 2), e.g., gates thereof. The two charge transfer nodes vgn 1, vgn 2 may have a smaller electrical voltage swing (i.e., a peak-to-valley value) than the output 1302 aof the first level converter 1302, e.g., smaller than the first signals clk 4vp and clk 4vn, e.g., smaller than or equal to about 80% of the output 1302 a. When the first signals clk 4 vpand clk 4 vnhave an electrical voltage swing of about 5 volts (e.g., between 0 volts and -5 volts), the electrical voltage swing Vpof the two charge transfer nodes vgp 1, vgp 2may be about 4 volts (e.g., between VSSL and VDD_auxn). In other words, the electrical support voltage VDD_auxn may be approximately VSSL+Vp, for example approximately VSSL+4 volts.If the two switches MP 1, MN 1 of the first inverter and / or the two switches MP 2, MN 2 of the second inverter have a switching threshold of approximately 1 volt, the power loss of the cross-current can therefore be within an acceptable range. In other words, the power loss of the cross-current electric would be more than 20 times greater if the switches of the inverter structure 1366 were controlled with an electric voltage swing corresponding to the electric voltage difference between the first high-voltage terminal 1352 and the second high-voltage terminal 1356 (such as at level shifter 1500). In other words, an electrical voltage for switching the inverter structure (electrical switching voltage) may be smaller (e.g. in magnitude) than VDDH, VSSL and / or their difference.The first (e.g. complementary) signals clk 4vp and clk 4vn may be provided by means of the first level converter 1302. The first level converter 1302 may be configured to convert the input signal from VDD=2.7 volts to VDD 4V=5 volts. The first level converter 1302 may have a different circuit architecture than the second level converter, e.g., one of the circuit architectures described herein.The back-up electrical voltage VDD 4V at the back-up voltage terminal 1360 may be optional, e.g., when fast switching of the inverter structure 1366 is required. Illustratively, an electrical supply voltage of VDD=2.7 volts, which reaches only 80% of the effective electrical voltage swing at the gates of the inverter structure 1366, may cause a slower switching than with an electrical voltage swing corresponding to the electrical support voltage VDD 4V. The back-up electrical voltage VDD 4V may be generated by a voltage doubler (not shown), e.g. by a single charge pump stage, or more generally by an amplifier, which converts, e.g. adjusts, VDD to VDD 4V.The circuit architecture of the level converter circuit 1800 may be clearly sufficient for high-voltage switches having a thin gate (core oxide) with an extended drain (high voltage drain extended).According to various embodiments, the electrical voltage for switching the inverter structure 1366 may be generated by means of the two sub-stages 120 a, 120 bwhich conform in their circuit architecture, or more generally in their charge pump type (e.g. Pelliconi or Dickinson). Thus, a static electric power supply for regulating the electric voltage can be dispensed with.Furthermore, by means of the level converter circuit 1800, a sufficiently good power supply rejection ratio (PSRR for short) for the electrical voltage difference for switching the inverter structure 1366 (also referred to as gate control signal) can be achieved. VDDH and / or VSSL may be generated on the chip itself, for example, by means of a respective on-chip charge pump. VDDH and / or VSSL may have a ripple of 1 volt or more, e.g., with a changing load. The PSSR depends on the ratio of the capacitances of the buffer coupling C1, C2 and the coupling capacitors C3 to C6.The input signal of the level converter circuit 1800 (which is coupled to the input 1302 eof the first level converter 1302) may be a periodic signal (e.g. a clock signal), i.e. have a frequency that is invariable over time. In the case of an aperiodic signal profile of the input signal, the operating point of the level converter circuit 1800 may drift, for example if long switching cycles (for example without a switching operation) result therefrom.The level conversion circuit 1800 or one of the level conversion circuits described above may be implemented in a readout circuit (e.g., in an application specific integrated circuit). The readout circuit can be integrated into or form a chip (integrated circuit) or a chip module (circuit module) together with a sensor (e.g. a sound sensor, such as a MEMS microphone). For example, the level converter circuit 1800 may be coupled into a chopper at the output side 1304 a, e.g. for switching the chopper, as will be described in more detail below. This can achieve the effect that a predefined signal-to-noise ratio can be obtained (clearly maximized). Clearly, the switches of the chopper may require as precise a time fit as possible with which they are switched, so that the ripple (switching pulses) produced by the switching at the input of the read-out circuit is as low as possible.Illustratively, a level converter circuit 1800 may use the capacitive coupling 1306 between the first level converter 1302 and the second level converter 1304 to transmit at least one control signal (i.e., one or more control signals) to the inverter structure 1366 of the second level converter 1304, e.g., the gates thereof. The peak-to-valley value (e.g. the amplitude) of the at least one control signal at the gates of the inverter structure 1366 may not necessarily have a large value. Therefore, the peak-to-valley value of the at least one control signal may be reduced, which may increase the speed of switching the inverter structure 1366 of the second level converter 1304, e.g. already due to general limitations of the slew rate (i.e. the temporal gradient) of the at least one control signal. Alternatively or additionally, this may reduce an overlap of two or more control signals, which saves electrical power, e.g. at the switches of the inverter structure 1366. The electrical support voltage VDD_auxp, VDD_auxn provided by the first latch and / or second latch may enable controlling the inverter structure 1366, e.g. the gates thereof, with the required peak-to-valley value and thus improve the PSSR.FIG. 19A illustrates a level converter circuit 1900 aaccording to various embodiments in a schematic circuit diagram. The level converter circuit 1900 may substantially correspond to the level converter circuit described above, wherein the charge pump 1362 (also referred to as first charge pump 1362) is configured to provide the first electrical support voltage VDD_auxp and / or the second electrical support voltage VDD_auxn.The first charge pump 1362 may be coupled to (e.g., into the clock input of) the level shifter signal of the first level shifter 1302. A second charge pump 1762 may be connected between the first charge pump 1362 and the inverter 1366. The second charge pump 1762 may be coupled to the level converter signal of a third level converter 1902 (e.g. into the clock input thereof), i.e. a third (e.g. aperiodic) level converter signal.A clock signal, i.e. a periodic first input signal clk, e.g. a square-wave signal, can be coupled into the first level converter 1302. Any second input signal D (also referred to as data signal D), e.g. an aperiodic or periodic input signal, can be coupled into the third level converter 1902. The level conversion circuit 1900 amay be configured to level convert the second input signal D to the output level. Illustratively, the first charge pump 1362, which is connected, for example, in parallel to the second charge pump 1762, can be used to prevent the first electrical support voltage VDD_auxp and / or the second electrical support voltage VDD_auxn from drifting.FIG. 19B illustrates a level converter circuit 1900 bin accordance with various embodiments in a schematic circuit diagram analogous to the level converter circuits described above, wherein the first charge pump 1362and the second charge pump 1762may each comprise two sub-stages 120 a, 120 b.The first charge pump 1362 and the first level converter 1302 may also be referred to as support circuit 1952. The second charge pump 1762 and the third level converter 1302 may also be referred to as data circuit 1954.The data circuit 1954 may be configured to level convert the second input signal D to the second level converter signal (which may be provided and / or coupled out at the output 1304 aof the second level converter 1304). The data circuit 1954 may be configured to provide and / or obtain the first electrical support voltage VDD_auxp and the second electrical support voltage VDD_auxn, e.g. by means of the first input signal clk coupled therein. For example, a first sub-stage 120 aof the first charge pump 1362 may be configured to provide the first electrical support voltage VDD_auxp. Alternatively or additionally, the second sub-stage 120 bof the first charge pump 1362 may be configured to provide the second electrical support voltage VDD_auxn.The first electrical support voltage VDD_auxp may be coupled to the first sub-stage 120 aof the second charge pump 1762. The second electrical support voltage VDD_auxn may be coupled to the second sub-stage 120 bof the second charge pump 1762.FIG. 20 illustrates a level converter circuit 2000 according to various embodiments in a schematic circuit diagram. The level conversion circuit 2000 can substantially correspond to the level conversion circuit described above.The capacitive coupling 1306 between the first level converter 1302 and the switch structure 104 of the first charge pump 1362 may be provided by means of the charge stores 102 a, 102 bof the first charge pump 1362 (e.g. comprising capacitors C 7 to C 10).The capacitive coupling 1306 between the second level converter 1902 and the switch structure 104 of the second charge pump 1762 may be provided by means of the charge stores 102 a, 102 bof the first charge pump 1762 (e.g. comprising capacitors C 3 to C 6).The buffer coupling may be provided by means of the capacitors C 1, C 2.FIG. 21A illustrates a signal waveform 2100 aaccording to various embodiments in a schematic diagram in which a signal characteristic 801 (e.g. an electrical voltage of the signal, in arbitrary units) is illustrated over time 803 (in arbitrary units), e.g. in the support circuit 1952.Line 2102 represents the temporal profile of a first signal (e.g. its electrical voltage or its electrical potential, illustratively an inverter switching signal) at a first charge transfer node vgp 1 of the first sub-stage 120 aof the first charge pump 1362, and line 2104 represents the temporal profile of a second signal (e.g. its electrical voltage or its electrical potential, illustratively an inverter switching signal) at a second charge transfer node vgp 2 of the first sub-stage 120 aof the second charge pump 1762. The first signal and the second signal may optionally be coupled to a first input 1366 eof the inverter structure 1366 (e.g., when no data circuit is needed). The first signal and the second signal can be configured in a push-pull manner with respect to one another.Line 2106 represents the time profile of the first level converter signal clk4vp and line 2108 represents the time profile of the additional first level converter signal clk4vn. The first level converter signal clk 4 vpand the additional first level converter signal clk 4 vnmay be configured in a push-pull manner and provided by means of the first level converter 1302.The first level shifter signal clk 4vpmay be coupled to the first charge storage 102 aof the first charge pump 1362. In other words, the first level converter signal clk 4vp can be capacitively coupled to the second level converter 1304.The additional first level converter signal clk 4 vnmay be coupled to the second charge storage 102 bof the first charge pump 1362. In other words, the additional first level converter signal clk4vnmay be capacitively coupled to the second level converter 1304.Line 2110 represents the time profile of a third signal (e.g. its electrical voltage or its electrical potential) at a first charge transfer node vgn1of the second sub-stage 120 bof the first charge pump 1362, and line 2112 represents the time profile of a fourth signal (e.g. its electrical voltage or its electrical potential) at a second charge transfer node vnclk2, vgn2of the second sub-stage 120 bof the first charge pump 1362. The third signal and the fourth signal may be coupled to a second input 1366 eof the inverter structure 1366. The third signal and the fourth signal can be configured in a push-pull manner.FIG. 21B illustrates a signal waveform 2100 bin accordance with various embodiments in a schematic diagram in which a signal characteristic 801 (e.g. an electrical voltage of the signal, in arbitrary units) is illustrated over time 803 (in arbitrary units), e.g. in the data circuit 1954.Line 2152represents the temporal profile of a first signal (e.g. its electrical voltage or its electrical potential, illustratively an inverter switching signal) at a first charge transfer node Vpp1of the first sub-stage 120 aof the second charge pump 1762, and line 2154represents the temporal profile of a second signal (e.g. its electrical voltage or its electrical potential, illustratively an inverter switching signal) at a second charge transfer node Vpp2of the first sub-stage 120 aof the second charge pump 1762. The first signal and the second signal may be coupled to a first input 1366 eof the inverter structure 1366. The first signal and the second signal can be configured in a push-pull manner.Line 2156 represents the time profile of the third level converter signal d4vp and line 2158 represents the time profile of the additional third level converter signal d4vn. The third level converter signal d 4vpand the additional third level converter signal d 4vnmay be configured in a push-pull manner and provided by means of the third level converter 1902.The third level shifter signal d 4vpmay be coupled to the first charge storage 102 aof the second charge pump 1762. In other words, the third level converter signal d 4vpmay be capacitively coupled to the second level converter 1304.The additional third level shifter signal d 4 vnmay be coupled to the second charge storage 102 bof the second charge pump 1762. In other words, the additional third level converter signal d 4 vnmay be capacitively coupled to the second level converter 1304.Line 2160 represents the temporal profile of a third signal (e.g. its electrical voltage or its electrical potential) at a first charge transfer node vnp 1 of the second sub-stage 120 bof the second charge pump 1762, and line 2162 illustrates the temporal profile of a fourth signal (e.g. its electrical voltage or its electrical potential) at a second charge transfer node vnp 2 of the second sub-stage 120 bof the second charge pump 1762. The third signal and the fourth signal may be coupled to a second input 1366 eof the inverter structure 1366. The third signal and the fourth signal can be configured in a push-pull manner.FIG. 22A illustrates a measurement arrangement 2200 aaccording to various embodiments in a schematic circuit diagram.The measuring arrangement 2200 acan have a bridge circuit 2202 of a plurality of capacitive two-poles (also referred to as capacitive bridge circuit 2202), of which at least one two-pole has a capacitance 2204 kof a micromechanical sensor.The measuring arrangement 2200 amay further include an amplifier 2204 and a DC electric voltage source 2206, and a chopper 2208 coupled between the bridge circuit 2202 and the DC electric voltage source 2206. The input-side capacitance of the amplifier 2204 may be approximately the same as the capacitance 2204 kof the micromechanical sensor, i.e. may deviate therefrom by less than approximately 50%, e.g. be equal to approximately 25% of the capacitance 2204 kor less, e.g. be equal to approximately 10% of the capacitance 2204 kor less, e.g. be equal to approximately 5% of the capacitance 2204 kor less.The chopper 2208 may include at least a charge storage 2210 and a switch structure 2212. The switch structure 2212 may be configured to couple the charge storage 2210 alternately to the DC electric voltage source 2206 and the bridge circuit 2202 such that a mixed electric voltage is coupled into the bridge circuit 2202. The switch structure 2212 may include or be formed from at least one cross switch (also referred to as pole turner).An electrical mixed voltage can be understood to mean a superposition (electrical sum voltage) of an electrical alternating voltage with an electrical direct voltage, for example by series connection of two corresponding electrical voltage sources. The electrical direct voltage can optionally be zero, then the electrical mixed voltage can be an electrical alternating voltage, i.e. an electrical voltage whose polarity changes over time (e.g. in regular repetition) and whose temporal mean value is zero.An operating electrical voltage of the amplifier 2204 may be approximately VDD.FIG. 22B illustrates a measuring arrangement 2200 bin accordance with various embodiments in a schematic flow diagram.According to various embodiments, the charge storage 2210 may be charged by means of the DC electric voltage source 2206 when the switch structure 2212 couples the charge storage 2210 to the DC electric voltage source 2206, i.e. in a charging phase 2251. Analogously, the charge storage 2210 may be discharged by means of the bridge circuit 2202 when the switch structure 2212 couples the charge storage 2210 to the bridge circuit 2202, i.e. in a discharge phase 2253.The chopper 2208 e.g. its switch structure 2212 may be driven by means of a level conversion circuit, e.g. by means of one of the level conversion circuits described herein. In other words, a level shifter signal may be coupled to the chopper 2208 (for controlling the chopper 2208).The signal coupled into the chopper 2208 (e.g., the level shifter signal) may have a frequency of greater than 50 kHz (kilohertz), e.g., in a range from about 50 kHz to about 5 MHz (megahertz), e.g., in a range from about 50 kHz to about 250 kHz. For example, the signal coupled into the chopper 2208 can have at least twice the frequency as the frequency band to be measured by means of the sensor.FIG. 23 illustrates a measurement arrangement 2300 according to various embodiments in a schematic circuit diagram.The DC electric voltage source 2206 may include a first charge pump 2206 aand / or a second charge pump 2206 b. For example, the first charge pump 2206a or the second charge pump 2206b may be omitted. The first charge pump 2206 aand / or the second charge pump 2206 bmay be configured as described herein. For example, the first charge pump 2206 aand / or the second charge pump 2206 bmay be configured according to the charge pump illustrated in FIG. 1, or another charge pump described herein.The first charge pump 2206 acan be configured to provide a first electrical potential VP 1 of the electrical DC voltage on the output side. If the first charge pump 2206 ais omitted, the first electrical potential VP 1 may be a reference potential (e.g. electrical ground) present at the reference terminal 2302. The second charge pump 2206 bmay be configured to provide a second electrical potential VP 2 of the electrical DC voltage on the output side. If the second charge pump 2206 bis omitted, the second electrical potential VP 2 may be a reference potential (e.g. electrical ground) present at the reference terminal 2302.The electrical direct voltage, i.e. the difference between the first electrical potential VP 1 and the second electrical potential VP 2, can be greater (in terms of its magnitude) than the electrical supply voltage, e.g. greater than VDD, VDDH, VSSL, e.g. greater than approximately 6 volts, e.g. greater than approximately 8 volts, e.g. greater than approximately 10 volts, e.g. greater than approximately 12 volts, e.g. greater than approximately 14 volts, e.g. greater than approximately 16 volts, e.g. greater than approximately 18 volts.For example, the first electrical potential VP 1 may be positive with respect to the reference electrical potential, e.g. +10 volts. Alternatively or additionally, the second electrical potential VP 2 can be negative with respect to the electrical reference potential, e.g. -8 volts.The bridge circuit 2202 may include multiple capacitances (e.g., C 1 to C 4) of which at least one capacitance (e.g., C 4) may include or be formed from a capacitance of the micromechanical sensor. Alternatively or additionally, at least one of the other capacitances (e.g. C 1, C 2 or C 3) may have an additional capacitance of the micromechanical sensor or be formed therefrom. In other words, the micromechanical sensor may have at least one capacitance (e.g. one, two, three, four, etc.), which is coupled into the measuring arrangement 2300 by means of the measuring bridge 2202.The bridge circuit 2202 can be coupled on the input side 2202 e(i.e. with its input 2202 e) to the chopper 2208 so that the mixed electrical voltage is coupled into the measuring bridge. The bridge circuit 2202 can be coupled on the output side 2202 a(i.e. with its output 2202 a) to the input 2204 eof the amplifier 2204, so that an output signal of the bridge circuit 2202 is coupled into the amplifier.The output of the bridge circuit 2202 may optionally be stabilized by means of a buffer coupling (comprising at least one capacitor C 5, C 6). The output of the bridge circuit 2202 can optionally be stabilized by means of an electrical support voltage 2306, e.g. ohmically by means of ohmic resistors R 1, R 2. The electrical support voltage can be generated by means of an additional electrical DC voltage source 2304. The additional DC electric voltage source 2304 may include at least one charge pump. The ohmic coupling 2306 may include at least one ohmic resistor R 1, R 2.In general, alternatively or in addition to an ohmic resistor (e.g. in the case of the ohmic resistors R 1, R 2), a resistor may comprise or be formed from a transistor which is operated at a suitable operating point.The input 2204 eof the amplifier 2204 may optionally be capacitively coupled to the output 2204 aof the amplifier 2204 (i.e. the amplifier 2204 may have capacitive feedback), e.g. by means of at least one capacitor C 9, C 10. Amplifier 2204 and capacitive feedback C9, C10 may form integrator 2204o (i.e., amplifier 2204 may be interconnected in integrator configuration). A voltage regulator 2310 (also referred to as voltage regulator 2310) may optionally be connected in parallel with amplifier 2204, which voltage regulator couples input 2204 eof amplifier 2204 to output 2204 aof amplifier 2204.The output 2204 aof the amplifier 2204 may be coupled to a rectifier 2308. Rectifier 2308 may be configured to rectify the signal coupled out by amplifier 2204. For example, rectifier 2308 may include or be formed from at least one cross-switch (e.g., including four cross-connected switches). The rectifier 2308 can optionally be coupled on the output side to a further buffer coupling C 11, C 12 (comprising at least one capacitor C 11, C 12). In other words, the (rectified) signal decoupled by means of the rectifier 2308 can be capacitively stabilized.The rectifier 2308 (e.g. its cross-switch) may be switched synchronously with the chopper 2208 (e.g. its cross-switch). Illustratively, rectifier 2308 may remodulate the signal modulated by the chopper.The pink noise (also referred to as 1 / f noise, also referred to as flicker noise in English) of the amplifier 2204 (comprising e.g. an operational amplifier) can be reduced or prevented by means of the cross switches. Clearly, the chopper 2208 e.g. its cross switch 2212 can be raised to the electrical supply voltage of the capacitive sensor (e.g. the micromechanical sensor), which makes it possible e.g. to operate it with a signal source which has a very high impedance.The capacitive bridge circuit 2202 can have, for example, four capacitors C 1 to C 4 with the same capacitance. Alternatively or in addition to the capacitors, other capacitive components (e.g. a transistor) having a capacitance can also be used. In other words, each branch of the bridge circuit 2202 may have a negative (i.e., capacitive) reactance.The measuring arrangement 2300 may be connected in a sample-and-hold circuit (sample-and-hold configuration).FIG. 24 illustrates a signal profile 2400 according to various embodiments in a schematic diagram in which a signal characteristic 801 (e.g. an electrical voltage of the signal, in arbitrary units) is illustrated over time 803 (in arbitrary units).The first electrical potential VP 1 (e.g., a positive electrical potential) and / or the second electrical potential VP 2 (e.g., a negative electrical potential) may be coupled to the chopper 2208. By means of the chopper 2208 a first mixed electrical voltage VM 1 and / or a second mixed electrical voltage VM 1 can be coupled out and / or coupled into the bridge circuit 2202. Optionally, instead of the first electric potential VP 1 or the second electric potential VP 2, a reference electric potential may be used. By means of the cross switch, the electrical voltage of the bridge output can be kept at a constant electrical potential.The first mixed electric voltage VM 1 and / or the second mixed electric voltage VM 2 may have a peak-to-valley value that approximately corresponds to the DC electric voltage of the DC electric voltage source 2206 (i.e., the difference between the first electric potential VP 1 and the second electric potential VP 2). The first mixed electrical voltage VM 1 and the second mixed electrical voltage VM 2 can be or can be set up in a push-pull manner by means of the chopper 2208. In other words, the first mixed electrical voltage VM 1 may be at the first electrical potential VP 1 while the second mixed electrical voltage VM 2 may be at the second electrical potential VP 2. When the chopper switches, the second mixed electric voltage VM 2 may be at the first electric potential VP 1 while the first mixed electric voltage VM 1 may be at the second electric potential VP 2.The first mixed electrical voltage VM 1 and / or the second mixed electrical voltage VM 2 may include or be formed from a square-wave signal (i.e. have a square-wave shape).The electrical support voltage Vcmi (or the associated electrical potential) which the additional electrical DC voltage source 2304 provides may lie between the first electrical potential VP 1 and the second electrical potential VP 2, for example at approximately half. The difference between the electrical support voltage Vcmiand the first electrical potential VP 1 and the second electrical potential VP 2, respectively, may be equal to or less than approximately Vbias(working electrical voltage) of the micromechanical sensor, e.g., equal to the allowable electrical voltage with which the micromechanical sensor may be read out (e.g., without damaging) or less. In other words, it may be VP1=Vcmi+Vbias and it may be VP2=Vci-Vbias. For example, Vbiasmay be greater than 2.5 volts, e.g., greater than 5 volts, e.g., greater than 7.5 volts, e.g., about 8 volts. For a Vbias of 8 volts, the electrical input voltage of the measuring bridge 2202 (or the electrical DC voltage of the electrical DC voltage source 2206) can be approximately 16 volts or less.If the measuring bridge 2202 is completely balanced (i.e. each capacitive dipole has the same capacitance), only the signal caused by the micromechanical sensor is coupled into the amplifier 2204. If the measuring bridge 2202 is incompletely compensated, a ripple of the signal coupled into the amplifier 2204 can result, which can be at least partially reduced, for example, by means of the buffer coupling C 5, C 6. Alternatively or additionally, either capacitor C 5 or capacitor C 6 may be used to establish the symmetry of the sensing bridge 2202 (e.g., by compensating for tolerances of parasitic capacitances). This may support a suppression of the ripple of the two mixed voltages (also referred to as common mode suppression of the measuring bridge 2202).According to various embodiments, the common mode rejection of the sensing bridge 2202 (e.g., when fully balanced) may reject noise of the supply voltage coupled into the sensor. The better the time fit of the mixed electrical voltages VM 1, VM 2 coupled into the measuring bridge 2202, the lower the noise that arises can be.The common-mode rejection ratio (CMRR) can be understood as a value that describes a change in an electrical output voltage in response to the two electrical input potentials changing uniformly (by the same value, i.e. in common mode), or if the one electrical input voltage, i.e. its temporal average value, shifts with respect to an electrical reference potential.In common mode, it can be understood that two electrical potentials, electrical signals, electrical voltages, etc. change by a value with the same sign, e.g. by the same amount. In the push-pull mode, it can be understood, for example, that two electrical potentials, electrical signals, electrical voltages, etc., change by a value with different signs, e.g., by the same amount.Alternatively to a rectangular signal waveform, other signal waveforms can be provided, for example a trapezoidal signal waveform and / or a triangular signal waveform, or a superposition thereof.FIG. 25 illustrates a measurement arrangement 2500 according to various embodiments in a schematic circuit diagram.The chopper 2208 may include a charge storage arrangement 2310 which may include a plurality of charge stores 2210 a, 2210 b, 2210 c, 2210 d, e.g. two first charge stores 2210 a, 2210 bforming a first charge storage pair 2210 a, 2210 band / or two second charge stores 2210 c, 2210 dforming a second charge storage pair 2210 c, 2210 d. Each charge storage 2210 a, 2210 b, 2210 c, 2210 dof the charge storage arrangement 2310 may include or be formed from at least one capacitive component, e.g. at least one capacitor. The charge storage arrangement 2310 may be necessary, for example, if the chopper 2208 is implemented together with the DC electric voltage source 2206 in one chip. If these are implemented by means of different chips, the charge storage arrangement 2310 can optionally be dispensed with.The switch structure 2212 may include a plurality of (e.g., cross-connected) switches 2212 a, 2212 b, 2212 c, 2212 d(also referred to as chopper switches), each switch of which may be connected between a charge storage 2210 a, 2210 b, 2210 c, 2210 dof the charge storage arrangement 2310 (i.e., different charge storages respectively) and the DC electric voltage source 2206.The switch structure 2212 may further include a first connection switch 2502 (e.g., including or formed from a first cross switch 2502) which may be connected between the first charge storage pair 2210 a, 2210 band the sensing bridge 2202. Alternatively or additionally, the switch structure 2212 may include a second first connection switch 2504 (e.g., including or formed from a second cross switch 2504), which may be connected between the second charge storage pair 2210 c, 2210 dand the sensing bridge 2202. Instead of the cross switches 2502, 2504, other switches in a crossed connection can also be used.Optionally, the switch structure 2212 may include an additional switch 2506 coupling the input terminals of the sensing bridge together and / or the output terminals of the chopper 2208 together. By means of the additional switch 2506, the plurality of capacitors C 1 to C 4 of the bridge circuit can be discharged with respect to one another.Illustratively, the sensing bridge 2202 may include two parallel-connected capacitive voltage dividers (first voltage dividers C 1, C 4 and second voltage dividers C 2, C 3), each providing an output terminal of the output 2202 aof the sensing bridge 2202. Each voltage divider of the measuring bridge 2202 can have two capacitive dipoles, between which the output terminal (or output node) is connected. The additional switch 2506 may be connected in parallel to the two voltage dividers of the measuring bridge 2202. The additional switch 2506 may connect each capacitive dipole of the sensing bridge 2202 to a mesh in a closed state.The measuring arrangement 2500 can optionally have a buffer coupling C 7, C 8 (having at least one capacitor C 7, C 8), between which the (two capacitive dipoles of) measuring bridge 2202 can be connected (can be).FIG. 26 illustrates a charge transfer cycle 2600 of a chopper 2208 according to various embodiments in a schematic flow diagram.Illustratively, the charge stores of the chopper 2208 may be driven similarly to the charge stores of a charge pump.The charge transfer cycle 2600 may include a first phase 2601 (also referred to as first chopper phase 2601), in which a first charge storage 2210 amay be coupled to the DC electric voltage source 2206, or its DC electric voltage, respectively, and decoupled from the bridge circuit 2202 (e.g. the first charge storage 2210 amay be in the first sub-stage phase 151). Alternatively or additionally, in the first phase 2601, a second charge storage 2210 dmay be decoupled from the electrical DC voltage source 2206, or its electrical DC voltage, and coupled to the bridge circuit 2202 (for example, the second charge storage 2210 dmay be in the third sub-stage phase 155).The charge transfer cycle 2600 may further include a second phase 2603 (also referred to as second chopper phase 2603), in which the first charge storage 2210 amay be decoupled from the DC electric voltage source 2206, or its DC electric voltage, respectively, and coupled to the bridge circuit 2202 (for example, the first charge storage 2210 amay be driven according to the third sub-stage phase 155). Alternatively or additionally, in the second phase 2603, the second charge storage 2210 dmay be coupled to the electrical DC voltage source 2206, or its electrical DC voltage, and decoupled from the bridge circuit 2202 (for example, the second charge storage 2210 dmay be driven according to the first sub-stage phase 151).Optionally, the charge transfer cycle 2600 may include a third phase 2605 (also referred to as third chopper phase 2605) in which the plurality of capacitors of the sensing bridge 2202 or their voltage dividers are coupled to each other (i.e. to form a mesh) for discharge (i.e. the input of the bridge circuit 2202 may be bridged), e.g. by means of the additional switch 2506. Alternatively or additionally, in the third chopper phase 2605, the first charge storage 2210 aand / or the second charge storage 2210 dmay be decoupled from the bridge circuit 2202 (for example, the first charge storage 2210 aand / or the second charge storage 2210 dmay be driven according to the second sub-stage phase 153).In the first chopper phase 2601 and / or in the second chopper phase 2603, the additional switch 2506 may be in an open state.According to various embodiments, the charge stores of a charge storage pair may be switched similar to those of a charge pump stage, with the difference that a time constant signal (instead of the charge transfer signal) is coupled into the charge stores 102 a, 102 b(i.e. that their clock input 622 a, 622 bis at a time constant electrical potential) and the second switches 104 bare cross-connected. For example, two charge pump stages (e.g. comprising each two sub-stages 120 a, 120 b) can be connected in parallel with one another.FIG. 27 illustrates a charge transfer cycle 2700 of a chopper 2208 according to various embodiments in a schematic flow diagram.In the first chopper phase 2601, the first charge storage 2210 acan be coupled (e.g. according to the first sub-stage phase 151) to the electrical potential VP 1 of the electrical DC voltage source 2206 (or the electrical DC voltage) and in the second chopper phase 2603 (e.g. according to the third sub-stage phase 155) to the measuring bridge 2202, e.g. to a first capacitor C 1 of the first voltage divider C 1, C 4 of the measuring bridge 2202 and / or to a first capacitor C 2 of the second voltage divider C 2, C 3 of the measuring bridge 2202.In the first chopper phase 2601, a third charge storage 2210 b(also referred to as additional first charge storage 2210 b) of the chopper 2208 (e.g. according to the first sub-stage phase 151) may be coupled to the second electrical potential VP 2 of the electrical DC voltage source 2206 (or the electrical DC voltage) and in the second chopper phase 2603 (e.g. according to the third sub-stage phase 155) may be coupled to the measuring bridge 2202, e.g. to a second capacitor C 4 of the first voltage divider C 1, C 4 of the measuring bridge 2202 and / or to a second capacitor C 3 of the second voltage divider C 2, C 3 of the measuring bridge 2202.Optionally, in the third chopper phase 2605, the first charge storage 2210 aand / or the third charge storage 2210 bmay be decoupled from the bridge circuit 2202 (e.g. according to the second sub-stage phase 153). Optionally, the plurality of capacitors of the measuring bridge 2202 or the voltage dividers thereof can be coupled to one another (i.e. to form a mesh) for discharging, e.g. by means of the additional switch 2506.FIG. 28 illustrates a charge transfer cycle 2800 of a chopper 2208 according to various embodiments in a schematic flow chart.In the second chopper phase 2603, the second charge storage 2210 cmay be coupled (e.g. according to the first sub-stage phase 151) to the second electrical potential VP 2 of the DC electrical voltage source 2206 (or the DC electrical voltage), and in the first chopper phase 2601 (e.g. according to the third sub-stage phase 155) may be coupled to the second capacitor C 4 of the first voltage divider C 1, C 4 of the measuring bridge 2202 and / or may be coupled to the second capacitor C 3 of the second voltage divider C 2, C 3 of the measuring bridge 2202.In the second chopper phase 2603, a fourth charge storage 2210 d(also referred to as additional second charge storage 2210 d) of the chopper 2208 (e.g. according to the first sub-stage phase 151) may be coupled to the second electrical potential VP 2 of the electric DC voltage source 2206 (or the electric DC voltage) and in the first chopper phase 2601 (e.g. according to the third sub-stage phase 155) may be coupled to the first capacitor C 1 of the first voltage divider C 1, C 4 of the measuring bridge 2202 and / or may be coupled to the first capacitor C 2 of the second voltage divider C 2, C 3 of the measuring bridge 2202.Optionally, in the third chopper phase 2605, the second charge storage 2210 cand / or the fourth charge storage 2210 dmay be decoupled from the bridge circuit 2202 (e.g. according to the second sub-stage phase 153). Optionally, the plurality of capacitors of the measuring bridge 2202 or the voltage dividers thereof can be coupled to one another (i.e. to form a mesh) for discharging, e.g. by means of the additional switch 2506.FIGS. 29A and 29B illustrate a measurement arrangement according to various embodiments in a schematic circuit diagram in a first chopper phase 2900 aand a second chopper phase 2900 bof the charge transfer cycle.For providing an electrical supply voltage according to the working electrical voltage (Vbias) of the micromechanical sensor, the charge stores 2210 a, 2210 b, 2210 c, 2210 dof the charge storage arrangement 2310 are used. This makes it possible to dispense with a very fast and low-noise control amplifier. Clearly, the charge storage arrangement 2310 enables a more cost effective and simpler circuit architecture.According to various embodiments, the charge storage arrangement 2310 may include a first charge storage pair 2210 a, 2210 band a second charge storage pair 2210 c, 2210 d, each charge storage pair including two charge stores.In the first chopper phase 2900 aand in the second chopper phase 2900 b(e.g. each approximately half a charge transfer cycle minus the switching operation), one of the charge storage pairs may be charged, e.g. to the required electrical voltage, and the other charge storage pair may be coupled to the sensing bridge 2202. The measuring bridge 2202 may be electrically insulated (e.g. electrically floating) from the electrical reference potential and / or the electrical DC voltage source 2206 (e.g. together with the other charge storage pair).With the or each transition between the first chopper phase 2900 aand the second chopper phase 2900 b, the polarity of the measuring bridge 2202 can be changed (i.e. interchanged or inverted), i.e. a switching operation can take place. For example, the charge transfer cycle between the first chopper phase 2900 aand the second chopper phase 2900 bmay each include a second sub-stage phase 153 in which the switch structure 2212 of the chopper 2208 is in a switching operation.In the first chopper phase 2900 a, the first connection switch 2502 may have an open state. In other words, the first charge storage pair 2210 a, 2210 bmay be decoupled from the measurement bridge 2202 by means of the first connection switch 2502. Furthermore, in the first chopper phase 2900 a, the second connection switch 2504 may have a first closed state. In other words, the second charge storage pair 2210 c, 2210 dmay be coupled to the sensing bridge 2202 by means of the second connection switch 2504.In the second chopper phase 2900 b, the second connection switch 2504 may have an open state. In other words, the second charge storage pair 2210 c, 2210 dmay be decoupled from the measurement bridge 2202 by means of the second connection switch 2504. Further, in the first chopper phase 2900 a, the first connection switch 2502 may be in a second closed state. In other words, the first charge storage pair 2210 a, 2210 bmay be coupled to the sensing bridge 2202 by means of the second connection switch 2504.The first closed state and the second closed state of the first connection switch 2502 and the second connection switch 2504, respectively, may differ in polarity (with respect to VP 1 and VP 2). In other words, the connection switch 2502, 2504 may invert the polarity of the sensing bridge 2202 at the transition between the two closed states. Thus, the connection switches 2502, 2504 may be configured such that the polarity of a first input node VB 1 of the sensing bridge 2202 and a second input node VB 2 of the sensing bridge 2202 are reversed at the transition between the first chopper phase 2900 aand the second chopper phase 2900 b. Between the first input node VB 1 of the measuring bridge 2202 and the second input node VB 2 of the measuring bridge 2202, the voltage dividers of the measuring bridge 2202 can be connected in parallel.Alternatively to the illustrated configuration, the second connection switch 2504 in the first chopper phase 2900 amay have the second closed state and the first connection switch 2502 in the first chopper phase 2900 bmay be in the first closed state.The or each transition between the first chopper phase 2900 aand the second chopper phase 2900 b, e.g. after the first chopper phase 2900 aand / or after the second chopper phase 2900 b, may optionally comprise the third chopper phase. In the optional third chopper phase (e.g. in a first step), all charge stores of the charge storage arrangement 2310 may be decoupled from the measuring bridge 2202. Alternatively or additionally, in the optional third chopper phase (e.g. in a second step), the measuring bridge 2202 can be discharged. For example, each half charge transfer cycle of the chopper (also referred to as a chopper cycle) may have a third chopper phase.According to various embodiments, the capacitance of the sensing bridge 2202 and the capacitance of the charge stores of the charge storage arrangement 2310 may be matched to one another such that, when the charge stores of the charge storage arrangement 2310 are coupled to the sensing bridge 2202, an electrical supply voltage according to the electrical working voltage is present at the capacitance of the micromechanical sensor, i.e. that the electrical supply voltage corresponds to Vbias.The electrical working voltage of a component (e.g. of the micromechanical sensor and / or of the amplifier) may be defined by a working point of the component. The operating point can clearly represent the parameters at which the component can be operated. For starting up and / or operating the component, an electrical supply voltage (VDD) equal to or greater than the electrical working voltage (Vbias) can be applied to the latter. The operating point of a component is the quiescent state in the absence of an injected signal. It is described by a certain point on the characteristic curve. From this point, the electric current or the electric voltage can change, for example, when a useful signal is injected. In order to achieve as undistorted as possible a symmetrical signal transmission, the operating point can be situated, for example, in the middle of the characteristic curve, i.e. between maximum and minimum electrical voltage or electrical current intensity.If the measuring bridge 2202 is incompletely compensated, a temporal mismatch of the signal coupled into the amplifier 2204 may result, which may be at least partially reduced, for example, by means of the buffer coupling C 7, C 8 (in other words, the temporal mismatch may be increased). Alternatively or additionally, either capacitor C 7 or capacitor C 8 may be used to establish the symmetry of the sensing bridge 2202 (e.g., by compensating for tolerances of parasitic capacitances). This may help suppress the temporal mismatch of the two mixed voltages (also referred to as common mode suppression of the sensing bridge 2202). For example, the buffer coupling C 7, C 8 may be configured such that edge steepness of VB 1 and VB 2 are substantially the same (i.e. differ by less than 10%) so that they are configured to be appropriate in time. Illustratively, the branches of the measuring bridge can have identical capacitances, so that the rise times of VB 1, VB 2 are approximately the same when switching over the cross switches. If the rise times differ too strongly from one another, voltage peaks can arise at the two bridge outputs 2202a during the switching.For example, each charge storage of the charge storage arrangement 2310 may have a first capacitance K 1, e.g. in a range from about 10 pF (picofarad) to about 500 pF, e.g. in a range from about 50 pF to about 100 pF, e.g. about 80 pF. Analogously, the sensing bridge 2202 may have a second capacitance K3=2·K2corresponding to the sum of the parallel-connected capacitive dipoles of the sensing bridge 2202, e.g. the sum of the capacitances of: the first voltage divider C 1, C 4 and the second voltage divider C 2, C 3 and optionally (i.e. if present) the capacitance of the buffer coupling C 7, C 8. For example, K2=C4+C3=C2+C1 or (if the buffer coupling C 7, C 8 is present) may be K2=C4+C3+C7=C2+C1+C8 respectively. Optionally, the capacitance of C7 and / or C8 may be zero.For example, the sum of the capacitances of the first voltage divider C 1, C 4 and the capacitor C 5 may be in a range from about 1 pF to about 50 pF, e.g. in a range from about 5 pF to about 25 pF, e.g. about 10 pF. Alternatively or additionally, the sum of the capacitances of the second voltage divider C 2, C 3 and the capacitor C 6 may be in a range from approximately 1 pF to approximately 50 pF, e.g. in a range from approximately 5 pF to approximately 25 pF, e.g. approximately 10 pF.In order that the required working voltage Vbias is or is (e.g. not exceeded) provided at the individual branches (two-poles) of the measuring bridge 2202 from the DC voltage Vk=VP1-VP2 provided by means of the electrical DC voltage source 2206, the capacitances of the measuring bridge 2202 and of the chopper 2208 can be matched to one another such that the electrical potentials VP 1, VP 2 with which the charge stores of the chopper 2208 are charged reduce to Vbias when they are discharged into the measuring bridge. In other words, Vbias≤ VB1-VB2≤ V, e.g., 2·Vbias= VB1-VB2≤ V and / or at least 2·Vbias≤ V.According to various embodiments, the DC voltage Vk may be greater than twice the working voltage Vbias. In other words, the ratio of Vk / Vbias may be greater than 2. for example, at least at each of the capacitors C 1, C 2, C 3, C 4 of the capacitive voltage dividers, an electrical voltage of Vbias or less may be present (i.e., 2·Vbias= VB1-VB 2), such that the sensor may be operated with its working voltage vbias or more (e.g., at most 10% less).The voltage charged to the charge stores of the chopper 2208 (e.g., equal to VP 1 and / or VP 2) may reduce to the ratio of capacitances to each other, namely K1 / (K 1+K 2), when discharging them into the sensing bridge (each charge store illustratively discharges into a branch of the first capacitive voltage divider and a branch of the second capacitive voltage divider). In order that approximately or at most the Vbias are present on each of the capacitors C1, C2, C3, C4 of the capacitive voltage dividers, Vk / (VB1-VB2) may be equal to (K1+K2) / K1 or more, resulting in 2·Vbias= VB1-VB2:In other words, Vbias·(K1+K2)≥0.5·V·K1or Vk≤ Vbis·(K1+K2) / (0.5·K1). The ratio (K1+K2) / (0.5·K1) can be rewritten as 2+2·K2 / K1=2+K3 / K1. In other words, the ratio of the DC voltage Vk to the working voltage Vbias can be greater than 2. K 3 denotes the capacitive sum of the plurality of capacitors of the measuring bridge 2202 by at most the ratio of the second capacitance K 3 to the first capacitance, i.e. its input capacitance K 3 (capacitance K 3 of the input of the measuring bridge 2202).By providing K2=C4+C3=C2+C1 (or K2=C4+C3+C7=C2+C1+C 8, respectively, when the buffer coupling C 7, C 8 is present), it can be achieved that the outputs 2202 aof the measuring bridge 2202 remain approximately at the same potential when reversing the polarity of the bridge voltages VB 1, VB 2 (i.e. when switching the connection switches 250 2, 2504).Illustratively, each charge storage of the charge storage arrangement 2310 may be charged to the DC electrical voltage Vk. If the charge storage device is then coupled to the measuring bridge 2202, the latter discharges partially into the measuring bridge 2202 (charge transfer into the measuring bridge 2202), wherein the electrical voltage thereof is reduced, namely in the ratio of the capacitances to one another.In case K2=C4+C3+C7=C2+C1+C8=10 is pF and the capacitance of each charge storage of the charge storage arrangement 2310 is approximately 80 pF, the charge storages of the charge storage arrangement 2310 may be charged to 9 / 8 of the working voltage. In other words, Vkmay be about 9 / 8·of the working voltage. For example, C4=C1=C7=C2=C3=C8 may be, e.g., about 3.5 pF.Optionally, an electrical (common mode) input voltage Vin_op of the amplifier 2204 may be different from zero, e.g., may be in a range from about 0.5 volts to about 5 volts, e.g., about 1.3 volts. Thus, it may be necessary to shift all the electric voltages by Vin_op. The mixed electrical voltage may then be provided with a temporal average of approximately Vin_op.For example, the first electrical potential VP 1 may be the reference electrical potential+Vin_op+K / 2, e.g., about 10.3 volts. For example, the second electrical potential VP 2 may be the reference electrical potential+Vin_op-Vk / 2, e.g., approximately -7.7 volts. At the 9 / 8 ratio above, in the first chopper phase, approximately +9.3 volts may be applied to VB1 and approximately -6.7 volts may be applied to VB2. Analogously, in the second chopper phase, approximately +9.3 volts can then be applied to VB2 and approximately -6.7 volts can be applied to VB1.The connection switches 2502, 2504 may have an approximately equal ohmic resistance. Alternatively or additionally, the connection switches 2502, 2504 can have approximately the same switching behavior, e.g. approximately the same switching times. Thus, a clearly sufficient slew rate and / or its time fit may be achieved, which avoids too large electrical voltage peaks, e.g. at the amplifier 2204.FIG. 30A illustrates a measuring arrangement 3000 aaccording to various embodiments in a schematic circuit diagram.The measuring arrangement 3000 acan have a clock generator 3002, which can be configured to provide a reference clock 1002 (e.g. 12.5 megahertz). Clock 3002 may be operated at VDD (e.g., in a range from about 2.6 volts to about 2.75 volts), for example.The measuring arrangement 3000 a(cf. also FIG. 39 ) can furthermore have a first charge pump 3004 awhich can be configured to provide the first electrical potential VP 1 (e.g. 10.3 volts). The first charge pump 3004 acan have, for example, four or more series-connected charge pump stages 220 a, 220 b, e.g. each charge pump stage has exactly one sub-stage 120 aor two parallel-connected sub-stages 120 a, 120 b. Alternatively or additionally, the measuring arrangement 3000 acan have a second charge pump 3004 b, which can be configured to provide the second electrical potential VP 2 (e.g. -7.7 volts). The second charge pump 3004 bmay include, for example, four or more series-connected charge pump stages 220 a, 220 b, e.g. each charge pump stage includes exactly one sub-stage 120 aor two parallel-connected sub-stages 120 a, 120 b.Optionally, the first charge pump 3004 amay be omitted when the first electrical potential VP 1 is equal to the reference electrical potential. Alternatively, the second charge pump 3004 bmay be omitted, e.g. when the second electrical potential VP 2 is equal to the reference electrical potential.The measuring arrangement 3000 acan furthermore have at least one first charge storage 3006 a(e.g. the first charge storage 2210 aand / or the third charge storage 2210 a) for providing a first potential of the mixed electrical voltage (e.g. approximately 9.3 volts). The first electrical potential VP 1 (e.g. in the first chopper phase) can be coupled into the at least one first charge storage 3006 aand the first electrical potential of the mixed electrical voltage (e.g. in the second chopper phase) can be coupled out (i.e. be coupled into the measuring bridge 2202). Alternatively or additionally, the measuring arrangement 3000 acan have at least one second charge storage 3006 b(e.g. the second charge storage 2210 band / or the fourth charge storage 2210 d) for providing a second electrical potential of the mixed electrical voltage (e.g. approximately -6.7 volts). The second electrical potential VP 2 (e.g. in the second chopper phase) can be coupled into the at least one second charge storage 3006 band the first electrical potential of the mixed electrical voltage (e.g. in the first chopper phase) can be coupled out (i.e. be coupled into the measuring bridge 2202).For example, the at least one first charge storage 3006 amay be omitted, e.g. if the first charge pump 3004 ais omitted. For example, the at least one second charge storage 3006 bmay be omitted or may be omitted if the second charge pump 3004 bis omitted.The measuring arrangement 3000 acan furthermore have a first voltage regulator 3008 afor regulating 3008 c(controlling and / or regulating) the electrical voltage coupled out (i.e. coupled into the measuring bridge 2202) by the at least one first charge storage device 3006 a, for example to 9.3 volts. Alternatively or additionally, the measuring arrangement 3000 acan have a second voltage regulator 3008 bfor regulating 3008 c(controlling and / or regulating) the electrical voltage coupled out (i.e. coupled into the measuring bridge 2202) by the at least one second charge storage 3006 b, for example to -6.7 volts.If the first electrical potential VP 1 is approximately 0 volts (i.e. it is at approximately the reference electrical potential), the second electrical potential VP 2 can have the negative electrical direct voltage -Vk (e.g. -18 volts). If the second electrical potential VP 2 is approximately 0 volts (i.e. it is at approximately the reference electrical potential), the first electrical potential VP 1 can have the positive electrical direct voltage +V (e.g. +18 volts). In order that the micromechanical sensor can be operated with a constant electrical voltage (for example at a temporal average value of the mixed electrical voltage of +8 volts or -8 volts) of less than or equal to Vbias, the input of the amplifier can be at the temporal average value of the mixed electrical voltage (for example at +8 volts). In this case, one of the two charge pumps and the two charge stores thereof can be dispensed with. However, uniform charging or transfer of charge to both sides (e.g. to +16 V and 0 V) can in turn be more difficult to realize.The first electrical potential VP 1 may be provided by means of the first charge pump 3004 a. The first charge pump 3004 amay include or be formed from a Pelliconi charge pump stage (e.g., when VP 1 is positive). Alternatively or additionally, the first charge pump 3004 amay include or be formed from a bootstrap Dicken charge pump or bootstrap Dicken charge pump stage, e.g., the charge pump illustrated in FIG. 1 (e.g., when VP 1 is negative).The second electrical potential VP 2 may be provided by means of the second charge pump 3004 b. The second charge pump 3004 bmay include or be formed from a Pelliconi charge pump (e.g., when VP 2 is positive). Alternatively or additionally, the first charge pump 3004 amay include or be formed from a bootstrap Dicken charge pump or bootstrap Dicken charge pump stage, e.g., the charge pump illustrated in FIG. 1 (e.g., when VP 2 is negative).According to various embodiments, the charging of the charge stores 2210 a, 2210 b, 2210 c, 2210 dof the charge storage arrangement 2310 may be controlled and / or regulated (e.g. by means of a controller) by switching the first charge pump 3004 aand / or the second charge pump 3004 bon and off. Thereafter, fine adjustment of the electrical potential of the charge stores 2210 a, 2210 b, 2210 c, 2210 dof the charge storage arrangement 2310 can be effected, for example by means of capacitively coupled-in voltage regulators 3008 a, 3008 b.FIG. 30B illustrates a measurement arrangement 3000 bin accordance with various embodiments in a schematic circuit diagram, which comprises one of the voltage regulators 3008 a, 3008 b.The voltage regulator 3008 a, 3008 bmay be capacitively coupled to the measurement bridge and / or to the at least one first charge storage 3006 aand the at least one second charge storage 3006 b, e.g. by means of the capacitive component 3054 (e.g. a capacitor).The voltage regulator 3008 a, 3008 bmay include an amplifier 3052 (e.g., comprising a comparator). Further, voltage regulator 3000 bmay include multiple capacitors CS 1 (e.g., having about 350 femtofarads (fF)), CS 2 (e.g., having about 2.77 picofarads (pF)), and CS 3 (e.g., having about 3 pF), which are connected to each other and to amplifier 3052 via switches 3508.When the charge storage 3008 a, 3008 b(the at least one first charge storage 3006 aor the at least one second charge storage 3006 b) is charged to VP 1 (e.g. to Vin_op+vk / 2, e.g. Vin_op+9 volts) and VP 2 (e.g. to Vin_op-vk / 2, e.g. to Vin_op-9 volts), respectively, it is decoupled from the charge pump 3004 a, 3004 b(e.g. controlled by the amplifier 3052). Thereafter, the voltage regulator 3008 a, 3008 bcontrols the electric potential of the charge storage 3006 a, 3006 bto a predefined value (e.g., to Vin_op-vbias and Vin_op+vbias, respectively). By coupling the charge storage 3006 a, 3006 bto the sensing bridge 2202, the electrical voltage of the charge storage 3006 a, 3006 bis scaled to the electrical potential associated with the working electrical voltage (e.g., to Vin_op-vbias and Vin_op+vbias, respectively).FIG. 31 illustrates a signal profile 3100 according to various embodiments in a schematic diagram in which a signal characteristic 801 (e.g. an electrical voltage of the signal, in arbitrary units) is illustrated over time 803 (in arbitrary units).Lines 3102 each represent the time profile of the signal (e.g. its electrical voltage) at the nodes VB 1 and VB 2 of the measuring bridge 2202. The signals 3102 at nodes VB 1 and VB 2 may be switched twice between VP 1 and VP 2 in the chopper cycle 3102 a. The rate of rise of the electrical potential change 3102 bof the signals 3102 can be configured such that they overlap in time (also referred to as a time fit), i.e. that the switches are simultaneously in a switching operation (i.e. in the switching interval 3110).Line 3104 represents the time profile of the signal (e.g., its electrical voltage of, e.g., approximately 1 volt or more) at the input of amplifier 2204 (without signal from the micromechanical sensor), which has a signal-to-noise ratio of more than approximately 10 5 (e.g., more than approximately 10 6) and / or has a noise (e.g., electrical voltage peaks of less than approximately 200 millivolt (mV), e.g., less than approximately 100 millivolt.Lines 3106 each represent the time profile of the signal (e.g. its electrical voltage), which is decoupled from the amplifier 2204, e.g. on the basis of a signal generated by means of the micromechanical sensor.Lines 3108 each represent the time profile of a signal (e.g. its electrical voltage) which is generated by means of the micromechanical sensor.FIG. 32 illustrates a charge pump stage 3200 in Pelliconi circuit architecture according to various embodiments in a schematic circuit diagram, i.e. a Pelliconi charge pump stage 3200. A charge pump in Pelliconi switching circuitry architecture may include or be formed from one or more serially connected charge pump stages in Pelliconi switching circuitry architecture.According to various embodiments, the charge pump stage 3200 may include a latch, e.g. a CMOS latch. The latch may include two cross-connected inverters (first inverter MP 1, MN 1 and second inverter MP 2, MN 2), and two charge stores C 1, C 2.The first inverter MP 1, MN 1 and the second inverter MP 2, MN 2 of the latch may be pumped by means of the charge stores C 1, C 2 (e.g. each comprising one or more capacitors, also referred to as pump capacitors). Complementary signals (i.e. signals set up in a push-pull manner), for example clock signals, can be coupled into the charge stores C1, C2. The charge pump stage 3200 may be configured to generate a positive electrical voltage swing Vp (e.g. of approximately VDD), i.e. the electrical potential difference Vp between input 110 and output 112 (but may not be suitable for generating a negative electrical voltage swing).In the no-load operation, the total generated electrical voltage swing of a charge pump (e.g., the Pelliconi charge pump) may be the positive electrical voltage swing Vp times the number of its series-connected charge pump stages 3200.Via the switches MP 1, MN 1, MP 2, MN 2 (each e.g. comprising a transistor or formed therefrom), an electrical voltage of Vp at most decreases. However, the n-channel switches MN 1, MN 2 require an isolated p-well (also referred to as p-well) and / or the p-channel switches MP 1, MP 2 require an isolated n-well (also referred to as n-well). Only the insulated p-well or n-well and the pump capacitors C 1, C 2 have to have a higher electrical voltage withstand capability than Vp. In particular cases, a negative electrical voltage may be generated for this purpose (which is applied to the substrate, for example) while the substrate of the charge pump stage 3200 remains or is grounded (e.g. at 0 volts). Conventional CMOS technology, e.g. based on a p-doped substrate, may provide an isolated p-well (e.g. by means of a triple-well) by means of the substrate, but not an isolated n-well for negative voltages (e.g. a negative charge pump). Therefore, a negative electric voltage cannot be applied to the insulated n-well or can be applied only with difficulty.FIGS. 33A and 33B illustrate a control circuit 3300 a, 3300 bin accordance with various embodiments in a schematic circuit diagram, respectively.The control circuit 3300 a, 3300 bmay include a push-pull generator 602 g. The control circuit 3300 a, 3300 bmay be coupled on the input side with a control signal clk (e.g. generated by means of a clock generator), e.g. a base control signal (e.g. a reference clock). The control circuit 3300 a, 3300 bmay be configured to provide two complementary control signals clkp, clkn (e.g. a first control signal clkn and a second control signal clkp complementary thereto), i.e. which oscillate in a push-pull manner.FIG. 34 illustrates a charge pump 3400 in Dicken circuit architecture according to various embodiments in a schematic circuit diagram, i.e. a Dicken charge pump 3400.The charge pump 3400 is illustrated in FIG. 34 with four series-connected charge pump stages 220 a, 220 b, 220 c, 220 d. According to various embodiments, the charge pump 3400 may alternatively include less than four charge pump stages 220 a, 220 b, 220 c, 220 d(e.g., one, two or three charge pump stages 220 a, 220 b, 220 c, 220 d) or more than four charge pump stages 220 a, 220 b, 220 c, 220 d.The switches MP 0, MP 1, MP 2, MP 3, MP 4, MP 5, MP 11, MP 12, MP 21, MP 22, MP 31, MP 32, MP 41, MP 42, MP 51, MP 52 of the switch structure 104 (e.g. each comprising or formed from a transistor) may comprise the same conductivity type (e.g. n-channel or p-channel) and / or be driven by means of four control signals clk 2 p, clk 2 n, clk 1 p, clk 1 n. The two control signals clk 2 p, clk 2 nmay be configured in a push-pull manner (i.e. configured in a complementary manner) and / or the two control signals clk 1 p, clk 1 nmay be configured in a push-pull manner.Complementary control signals pclk1, pclk2 can be coupled into the charge stores C 1, C 2, C 3, C 4 of successive charge pump stages 3400, respectively.Optionally, as described above, a second switch 104 bmay be connected between each charge storage C 1, C 2, C 3, C 4 and the subsequent charge pump stage. If the second switches 104 bare omitted, it may be necessary for the first switches 104 ato have a greater electrical voltage withstand capability, e.g. at least twice the electrical voltage Vp (e.g. twice VDD) generated per charge pump stage 220 a, 220 b, 220 c, 220 d.In the case, e.g., that a negative electrical voltage swing is to be generated, a Dicken charge pump 3400 or its Dicken charge pump stages 220 a, 220 b, 220 cmay be used, as described herein. The Dicken charge pump (or its charge pump stages) makes it possible to reduce the electrical voltage loss of Vth per charge pump stage of the charge pump, e.g. by using an actively controlled switch structure 104 (compare FIG. 1 ), e.g. NMOS switches 104 bactively controlled by means of a control signal. For controlling the switch structure 104, the four control signals clk 2 p, clk 2 n, clk 1 p, clk 1 nmay be coupled in, for example, capacitively coupled in by means of capacitors C 11, C 12, C 21, C 22, C 31, C 32, C 41, C 42Due to the circuit architecture of the self-charging Dicken charge pump 3400, it may be necessary for its transistors to have to withstand twice the electrical supply voltage. For a large electrical supply voltage (e.g. more than 0.5 volts), high-voltage transistors are therefore required for the Dicken charge pump, which transistors usually have a factor of ten times the required area occupation of the Dicken charge pump (i.e. the required chip area) compared to low-voltage transistors and increase the power consumption thereof. The use of high-voltage transistors may also make it necessary to internally feed back the control blocks (e.g. by means of a bootstrap circuit), since these usually have a greater electrical threshold voltage and a poorer GM. Alternatively, a lower electrical supply voltage (e.g., less than 0.5 volts) may be used. In contrast, this can be compensated for by means of a larger number of charge pump stages, which in turn increase the required area occupancy of the Dickenson charge pump and its power consumption.FIG. 35 illustrates a signal profile 3500 according to various embodiments in a schematic diagram in which a signal characteristic 801 (e.g. an electrical voltage of the signal, in arbitrary units) is illustrated over time 803 (in arbitrary units), e.g. without second switches 104 b.The signal characteristic 3502 of the charge storage node 702 kof the first charge pump stage 220 aand / or the third charge pump stage 220 cmay run according to the coupled charge transfer signal 808 (compare FIGS. 8 and 10 ). The signal characteristic 3504 of the charge storage node 702 k, of the second charge pump stage 220 band / or of the third charge pump stage 220 dmay run in accordance with the (e.g. capacitively) coupled-in charge transfer signal 818. The electrical voltage difference between the charge storage nodes 702 kof two successive charge pump stages may correspond to approximately twice the electrical voltage difference Vdprovided per charge pump stage. If the peak-to-valley value of the charge transfer signals 808, 818 is about VDD (e.g., about 1.5 volts), the electrical voltage difference between the charge storage nodes 702 kof two successive charge pump stages may be about twice VDD.If a second switch 104 b(e.g. a controlled NMOS switch) is switched between the charge storage of a charge pump stage and the subsequent charge pump stage, the required electrical voltage stability of the switches 104 a, 104 b(first switch 104 aand second switch 104 b) can be reduced, e.g. to a maximum of Vd. In other words, the charge storage of the charge pump stage can be decoupled from its input 110 and output 112 by means of the switches 104 a, 104 b. Thus, the charge pump stage can be formed with low voltage transistors having a smaller size. In turn, twice the quantity of switches 104 a, 104 bis required and an additional control signal for controlling the second switches 104 bper charge pump stage or per sub-stage is required, which however can be reused for the complementary charge pump stages. For example, the switches 104 a, 104 b, which are connected between the charge stores of adjacent charge pump stages, can be actuated by means of a common control signal.According to various embodiments, one or each charge pump stage (more generally one or each sub-stage) may be or may become scalable. In other words, a charge pump may have one or more charge pump stages (more generally one or more sub-stages), the operated number of which charge pump stages (more generally sub-stages) may be set (e.g. regulated and / or controlled) (e.g. during operation of the charge pump), e.g. by means of a configuration bit. Alternatively or additionally, a charge pump can have one or more charge pump stages (more generally one or more sub-stages), the charge storage (in its capacity) of which can be set (e.g. regulated and / or controlled) (e.g. during operation of the charge pump), e.g. by means of an additional configuration bit.Regardless of the use of the second switches 104 b, the charge pump may require two complementary charge transfer signals pclk 1, pclk 2 for the even and odd charge pump stages. One or each charge pump stage can have exactly one sub-stage or two sub-stages connected in parallel or can be formed therefrom. Regardless of the use of the second switches 104 b, the or each charge pump stage may require two complementary charge transfer signals pclk 1, pclk 2 for the two sub-stages connected in parallel. If two parallel-connected sub-stages are used for the or each charge pump stage, the ripple of the coupled-out signal can be reduced (illustratively since this enables charge transfer per half charge transfer cycle).Regardless of whether a charge pump has exactly one sub-stage or two sub-stages per charge pump stage, it may require the same capacitance of the charge storage device or devices per charge pump stage. Illustratively, the sum of the capacitance of the charge stores of the two parallel-connected sub-stages can be exactly the same as the capacitance of the charge store if exactly one sub-stage is used instead of the two parallel-connected sub-stages. For example, the charge storage device of the exactly one sub-stage can have two capacitors connected in parallel to one another. The area occupancy for the charge storage per charge pump stage can thus be maintained.According to various embodiments, a Dickinson charge pump may be used instead of a Pelliconi charge pump, e.g. for providing a positive electrical voltage (e.g. when no isolated p-well is available for the NMOS switches).FIGS. 36A, 36B and 36C illustrate in a schematic cross-sectional view a micromechanical sensor 3600 a, 3600 b, 3600 caccording to various embodiments, respectively.The micromechanical sensor 3600 a(general microelectromechanical sensor or MEMS sensor) may be configured for converting between mechanical energy and electrical energy. For example, micromechanical sensor 3600 acan convert a mechanical signal into an electrical signal and vice versa.Micromechanical sensor 3600 amay include a substrate 3604 (e.g., a semiconductor substrate, e.g., including silicon or formed therefrom), a membrane 124, and at least one counter plate 3622 (e.g., a counter plate 3622 or two counter plates 3622). The membrane 3624 may be separated from the at least one counter plate 3622 by a gap, e.g. by an air gap, and supported (e.g. in physical contact) by the substrate.The diaphragm 124 and the or each counter plate 3622 may form a capacitive device that provides capacitance of the sensor. If the diaphragm 124 oscillates, e.g. excited by a mechanical signal, the capacitance or each capacitance of the sensor can correspondingly change, which can be detected by means of an electrical contact structure 3606 (e.g. comprising a metal or formed therefrom).FIG. 37 illustrates a signal profile 3700 according to various embodiments in a schematic diagram in which a signal characteristic 801 (e.g. an electrical voltage of the signal, in arbitrary units) is illustrated over time 803 (in arbitrary units).In the second sub-stage phase 153 of the first cycle section 808 aand the second sub-stage phase 153 of the second cycle section 808 b, the second control signal 804 and the first control signal 802 may coincide in their state (a low state, illustratively an open state), such that the charge storage is decoupled from the input and an output of the charge pump stage. In the first sub-stage phase 151 and in the third sub-stage phase 155, the second control signal 804 and the first control signal 802 may be different from each other in their state (illustratively one in a low state and one in a high state).The first control signal 802 (clk 2p) and the optional second control signal 804 (clk 1p) may be offset from each other (e.g., by one cycle half) by the duration of the first cycle portion 808 a. The third control signal 806 (clk 2 n) and the optional additional third control signal 816 (clk 1 n) may be offset from one another (e.g. by one cycle half) by the duration of the first cycle section 808 a. The fourth control signal 808 (pclk or pclk1) and the optional additional fourth control signal 818 (pclk2) may be push-pull configured.The fourth control signal 808 (pclk or pclk1) and the optional additional fourth control signal 818 (pclk) may each be a power pumping clock ("Charge Transfer Signal") and / or capacitively coupled to that of the internal electrical voltage (also referred to as "Vint", "Vint1" or "Vint2"). The first control signal 802 (clk 2 p) may be capacitively coupled to (i.e., coupled to) the gate electrical voltage ("vg 2 p") of the first transistor M 2 and / or to (i.e., coupled to) the gate electrical voltage ("vg 2 p 2") of the additional second transistor M 16. The second control signal 804 (clk 1 p) may be capacitively coupled (i.e. coupled) to the gate electrical voltage ("vg 1 p 2") of the second transistor M 6 and / or to the gate electrical voltage ("vg 1 p") of the additional first transistor M 12 (compare FIGS. 7 and 9 ).The third control signal 806 (clk2n) may be an optional auxiliary signal and may be coupled (i.e., coupled) to the gate electrical voltage ("vg2n") of the third transistor M 4. The additional third control signal 816 (clk 1n) may be an additional optional auxiliary signal and may be coupled (i.e., coupled) to the gate electrical voltage ("vg 1n") of the additional third transistor M 14.The first switch 104 a(e.g. transistor M 2 and / or transistor M 12) may be a power switch for transferring electrical charge from the input 110 to the charge storage 102 a, 102 b(or to the charge transfer node 702 k), e.g. when or as long as the first control signal 802 (clk 2 p) has a high state.The second switch 104 b(e.g. transistor M 1 and / or transistor M 11) may be a power switch for transferring electrical charge from the charge storage 102 a, 102 b(or the charge transfer node 702 k) to the output 112, e.g. when or as long as the second control signal 804 (clk 1 p) has a high state.The first leveling circuit 104 d, 104 c, 104 e, e.g. its fifth switch 104 e(e.g. transistor M 3 and / or transistor M 13), may be configured to discharge the control input of the first switch 104 a(e.g. its gate electric voltage), e.g. when or as long as the fourth control signal 808 (pclk 1) and the additional fourth control signal 818 (pclk 2) respectively have a low state.The first leveling circuit 104 d, 104 c, 104 e, e.g. its third switch 104 c(e.g. transistor M 4 and / or transistor M 14), may be configured to discharge the control input of the first switch 104 a(e.g. its gate electric voltage), e.g. when or as long as the third control signal 806 (clk 2 n) or the additional third control signal 816 (clk 1 n) has a high state, e.g. when or as long as the fourth control signal 804 (pclk 2) or the additional fourth control signal 814 (pclk 2) has a high state.The first leveling circuit 104 d, 104 c, 104 e, e.g. its fourth switch 104 d(e.g. transistor M 5 and / or transistor M 15), may be configured to discharge the control input of the third switch 104 c(e.g. its gate electric voltage), e.g. when or as long as the first control signal 802 (clk 2 p) has a high state, e.g. when or as soon as the first switch 104 ais closed.The second leveling circuit 104 f, e.g. its sixth switch 104 f(e.g. transistor M 6 and / or transistor M 16), may be configured to discharge the control input of the second switch 104 b(e.g. its gate electrical voltage), e.g. when or as long as the fourth control signal 808 (clk 2 p) or the additional fourth control signal 818 (clk 1 p) has a high state, e.g. when or as soon as the second switch 104 bis or becomes open.The high state of the third control signal 806 (clk 2 n) or of the additional third control signal 816 (clk 1 n), in other words the closed state of the third switch 104 c, in conjunction with the high state of the first control signal 802 (clk 2 p), in other words the closing of the first switch 104 a, can make it possible to change the control input (or its electrical potential) of the first switch 104 a(vg 2 p) by VDD in two steps in each case.If a second sub-stage phase 153 is used, in which the first switch 104 aand the second switch 104 bare simultaneously in a switching operation, the first control signal 802 (clk 2 p) may be configured in common mode with the first charge transfer signal 808 (pclk 1 or pklc). Alternatively or additionally, the optional (if present) second control signal 804 (clk 1 p) may be configured in common mode with the (if present) second charge transfer signal 818 (pclk 2) and / or in differential mode with respect to the first control signal 802 (clk 2 p).FIGS. 38A and 38B each illustrate an electrical potential profile 3800 a, 3800 bin accordance with various embodiments in a schematic diagram, analogously to FIG. 12A, for example in an unloaded state of the charge pump stage, wherein the electrical potential 1104 cof the third switch 104 c, e.g. at its control input, may have its high state before the electrical potential 1104 aof the first switch 104 a.FIG. 39 illustrates a chopper 3900 according to various embodiments in a schematic circuit diagram analogous to FIG. 25.The chopper may include a first charge pump stage 3900 aand optionally a second charge pump stage 3900 b, which may each include two sub-stages 120 a, 120 b. The second switches 104 bof the or each charge pump stage 3900 a, 3900 bmay be cross-connected and driven in such a way that they interchange the output terminals 112 (node VB 1 and node VB 2) with one another in successive third sub-stage phases 155.The first switch 104 aand the second switch 104 bof the or each sub-stage 120 a, 120 bof the or each charge pump stage 3900 a, 3900 bmay be driven by means of a push-pull generator 602 g. The push-pull generator 602g may comprise one or more level converters as described herein.

Claims

Level converter circuit (1300a, 1700b, 1800, 2000), comprising: • a signal source (1302); • a level converter (1304); • wherein the signal source (1302) is capacitively coupled on the output side to an input of the level converter (1304); and • wherein the signal source (1302) and the level converter (1304) are galvanically separated from one another; • wherein the signal source (1302) comprises a push-pull generator which is configured to provide two push-pull signals which are capacitively coupled into the level converter (1304); • wherein the level converter (1304) comprises an inverter structure (1366) which is present on the input side to the input of the level converter (1304) and / or provides an output side of the level converter; • wherein the level converter (1304) comprises a first charge pump (1362) configured to provide a voltage difference for switching the inverter structure (1366).The level converter circuit (1300a, 1700b, 1800, 2000) of claim 1, wherein the signal source (1302) comprises an additional level converter (1302) configured to provide a first level converter signal that is capacitively coupled to the level converter (1304).Level converter circuit (1300a, 1700b, 1800, 2000) according to claim 1 or 2, wherein the push-pull generator comprises at least one inverter, at least one transistor-transistor gate and / or at least one transformer.The level converter circuit (1300a, 1700b, 1800, 2000) according to any one of claims 1 to 3, wherein the level converter (1304) is configured to provide a second level converter signal; and wherein the first level converter signal or the two push-pull signals and the second level converter signal match in frequency.The level converter circuit (1300a, 1700b, 1800, 2000) according to one of claims 1 to 4, further comprising: two charge stores (102a, 102b) which capacitively couple the signal source (1302) on the output side to an input of the level converter (1304).Level converter circuit (1300a, 1700b, 1800, 2000) according to one of claims 1 to 5, wherein the signal source (1302) is capacitively coupled on the output side to a clock input of the first charge pump (1362).The level converter circuit (1300a, 1700b, 1800, 2000) according to any one of claims 1 to 6, wherein the inverter structure (1366) is further coupled on the input side to the clock input of the first charge pump (1362) for switching the inverter structure (1366) according to a clock of the first charge pump (1362).The level converter circuit (1300a, 1700b, 1800, 2000) according to any one of claims 1 to 7, wherein the level converter (1304) comprises a second charge pump (1762) connected between the inverter structure (1366) and the first charge pump (1362), wherein the inverter structure (1366) is further connected on the input side to a clock input of the second charge pump stage for switching the inverter structure (1366) according to a clock of the second charge pump (1762).The level converter circuit (1300a, 1700b, 1800, 2000) according to claim 8, further comprising: an additional signal source (1308) which is capacitively coupled on the output side to the clock input of the second charge pump (1762).The level converter circuit (1300a, 1700b, 1800, 2000) of claim 9, wherein the additional signal source comprises a still additional level converter (1308) configured to provide a third level converter signal that is capacitively coupled to the level converter (1304).The level converter circuit (1300a, 1700b, 1800, 2000) according to claim 9 or 10, wherein the additional signal source (1308) comprises an additional push-pull generator configured to provide two additional push-pull signals that are capacitively coupled to the level converter.The level converter circuit (1300a, 1700b, 1800, 2000) according to claim 10 or 11, wherein the level converter (1304) is configured to provide a second level converter signal; and wherein the third level converter signal or the two additional push-pull signals and the second level converter signal coincide in frequency.Measuring arrangement comprising a level converter circuit (1300a, 1700b, 1800, 2000) according to one of Claims 1 to 12.A chip comprising a level conversion circuit (1300a, 1700b, 1800, 2000) according to any one of claims 1 to 12.Level converter circuit (1300a, 1700b, 1800, 2000) comprising: • a signal source (1302); • an inverter structure (1366); • a charge pump (1362) comprising a charge storage device (102a, 102b); • wherein the signal source (1302) is capacitively coupled on the output side by means of the charge storage device (102a, 102b) to an input of the inverter structure (1366); and • wherein the inverter structure (1366) and the signal source (1302) are galvanically separated from one another; • wherein the signal source (1302) comprises a push-pull generator (1302) which is configured to provide two push-pull signals which are capacitively coupled into the inverter structure (1366).The level converter circuit (1300a, 1700b, 1800, 2000) of claim 15, wherein the signal source (1302) comprises a level converter (1302) configured to provide a first level converter signal that is capacitively coupled to the inverter structure (1366).Level converter circuit (1300a, 1700b, 1800, 2000) according to claim 15 or 16, wherein the push-pull generator (1302) comprises at least one inverter, at least one transistor-transistor gate and / or at least one transformer.The level converter circuit (1300a, 1700b, 1800, 2000) according to any one of claims 16 to 17, wherein the inverter structure (1366) is configured to provide a second level converter signal; and wherein the first level converter signal or the two push-pull signals and the second level converter signal coincide in frequency.The level converter circuit (1300a, 1700b, 1800, 2000) according to any one of claims 15 to 18, wherein the charge pump (1362) is configured to switch the inverter structure (1366) according to a charge transfer cycle of the charge storage (102a, 102b).The level converter circuit (1300a, 1700b, 1800, 2000) according to any one of claims 15 to 19, wherein the charge pump (1362) is configured to provide a voltage difference for switching the inverter structure (1366).Measuring arrangement comprising a level converter circuit (1300a, 1700b, 1800, 2000) according to one of Claims 15 to 20.A chip comprising a level conversion circuit (1300a, 1700b, 1800, 2000) according to any one of claims 15 to 20.

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