HEMT transistor of the normally-off type with a trench containing a gate region and forming more than two stages

Abstract

HEMT transistor of the normally off type, having: - a semiconductor heterostructure (4, 6, 200) comprising at least a first layer (4) and a second layer (6), the second layer being arranged on top of the first layer, the first layer (4) being different from the second layer (6), and the first layer (4) being in direct contact with the second layer (6); - a trench (15) extending through the second layer and a region of the first layer; - a gate region (10) of conductive material extending into the trench; and - a dielectric region (18) extending into the trench and in contact with the semiconductor heterostructure; wherein the dielectric region (18) is arranged between the gate region and the semiconductor heterostructure; wherein a part of the trench is laterally bounded by a lateral structure (LS) comprising at least one first step (P b1 , P 11 , P b2 ), wherein the lateral structure (LS) has a stair-step shape; and wherein the semiconductor heterostructure has a first edge (E 1 ) and a second edge (E 2 ) of the first stage, wherein the first edge and the second edge are formed by the first layer; wherein the lateral structure (LS) further forms more than two steps, wherein a second step has a third edge (E 3 ) and a fourth edge (E 4 ; E x1 ), wherein the third edge is formed by the first layer (4) and the fourth edge is formed by the second layer (6) and is arranged above the third edge.

Description

[0001] The present invention relates to a high-electron-mobility transistor (HEMT) of the normally off type having a trench having a gate region and forming more than two stages.

[0002] As is well known, HEMT transistors, also known as heterostructure field-effect transistors (HFETs), are widely used because of their ability to operate at high frequencies and their high breakdown voltages.

[0003] For example, HEMT transistors are known that incorporate AlGaN / GaN heterostructures, but which are normally-on devices, i.e., such that current flows in the absence of a voltage at the respective gate terminals; accordingly, these transistors are said to operate in depletion mode. Since it is generally preferred to provide normally-off transistors (which, correspondingly, operate in enhancement mode), numerous variants have been proposed, such as the transistor described in US Pat. No. 8,587,031 B2.

[0004] More specifically, US Pat. No. 8,587,031 B2 describes a transistor with a heterostructure comprising a layer of aluminum gallium nitride (AlGaN) and a layer of gallium nitride (GaN) arranged in contact with each other. Furthermore, the transistor has a first gate region arranged in a recess extending into the AlGaN layer and enabling modulation of a normally-off channel.

[0005] Today, enhancement-mode HEMT transistors are available. However, these solutions are always affected by the so-called drain-induced barrier lowering (DIBL) phenomenon, also known as premature breakdown.

[0006] In contrast to breakdown, the DIBL phenomenon occurs at low drain-source voltages (typically between 10 V and 30 V) and, in the presence of a zero voltage between the gate and source, results in a sudden increase in the current circulating between the drain and source. More precisely, denoting the voltages between i) the gate and source and between ii) the drain and source as voltages V gs or V ds and the current flowing between the drain and the source at V gs = 0 circulates as leakage current when V ds < V dibl (where V dibl is the voltage at which the DIBL phenomenon occurs), the leakage current density is typically in the order of nanoamperes per millimeter. In contrast, when V gs = 0 and V ds greater than V diblThe leakage current density can even be on the order of microamperes per millimeter. Since the DIBL phenomenon causes premature turn-on of the transistor, there is a need to prevent the onset of this phenomenon or at least mitigate its effects.

[0007] From US 2011 / 0 057 257 A1 a HEMT transistor of the normally off type is already known, which has the following: - a semiconductor heterostructure comprising at least a first layer and a second layer, the second layer being arranged on top of the first layer; - a trench extending through the second layer and a portion of the first layer; - a gate region of conductive material extending into the trench; and - a dielectric region extending into the trench, covering the gate region and in contact with the semiconductor heterostructure; wherein a part of the trench is laterally delimited by a lateral structure forming at least a first step; and wherein the semiconductor heterostructure forms a first edge and a second edge of the first stage, the first edge being formed by the first layer, wherein the lateral structure has a stair-step shape, wherein the lateral structure further forms at least a second step forming a third edge and a fourth edge, the third edge being formed by the semiconductor heterostructure and the fourth edge being arranged above the third edge.

[0008] The object of the present invention is to provide a HEMT transistor with which the disadvantages of the relevant prior art can be at least partially overcome.

[0009] According to the present invention, there is provided a HEMT transistor as set out in claim 1.

[0010] For a better understanding of the present invention, some examples of HEMT transistors not falling within the scope of the claims, as well as a preferred embodiment of an HEMT transistor according to the invention, are described below by way of non-limiting examples and with reference to the accompanying drawings, in which: Fig. 1 is a schematic cross-sectional view (not to scale) of a portion of an illustrative example of a HEMT transistor not according to the invention, which does not fall within the scope of the claims; Fig. 2 a schematic perspective view (not to scale) of a trench of the Fig. 1 shown example of a HEMT transistor; Fig. 3 a schematic representation of a cross-section (not to scale) of an area of ​​the Fig. 1 shown example of a HEMT transistor; Fig. 4 shows two examples of diagrams of the leakage current as a function of the drain-source voltage for a HEMT transistor of a known type and a HEMT transistor according to the invention, respectively; Fig. 5 shows two examples of diagrams of the electric field versus the drain voltage for a HEMT transistor of a known type and for a HEMT transistor according to the invention, respectively; Fig. 6-7 and 15 are schematic sectional views (not to scale) of further examples of HEMT transistors not according to the invention; Fig. 8. a schematic sectional view (not to scale) of an embodiment of a HEMT transistor according to the invention, and Fig. 9-14 schematic sectional views (not to scale) of the Fig. 1 during successive steps of a manufacturing process.

[0011] Fig. 1 illustrates a first example of a HEMT transistor not according to the invention, which is designated by the reference numeral 1.

[0012] In detail, the HEMT transistor 1 includes a semiconductor body 2, which in turn has a first layer 4 and a second layer 6, which are referred to below as lower layer 4 and upper layer 6, respectively.

[0013] The lower layer 4 is formed from a first semiconductor material, for example from a first semiconductor alloy of elements from groups III and V of the periodic table; purely as an example, it is assumed below that the lower layer 4 is gallium nitride (GaN).

[0014] The upper layer 6 is provided over the lower layer 4, with which it is in direct contact, and is formed from a second semiconductor material, which may be, for example, a second semiconductor alloy composed of elements from groups III-V of the periodic table, this second semiconductor alloy being different from the first semiconductor alloy. For example only, the following assumes that the upper layer 6 is made of aluminum gallium nitride (AlGaN).

[0015] The lower layer 4 and the upper layer 6 are, for example, n-conducting. Furthermore, the lower layer 4 has a thickness of, for example, 20 nm to 7 µm, while the upper layer 6 has a thickness of, for example, 5 nm to 400 nm.

[0016] Although not shown, the semiconductor body 2 further comprises a substrate, which consists, for example, of silicon and on which the lower layer 4 is formed. Since this substrate is not relevant for the purposes of the present invention, it will not be explained further in the present description.

[0017] The HEMT transistor 1 further comprises a passivation region 8, which is provided in direct contact above the upper layer 6 and which consists, for example, of silicon nitride. The passivation region 8 has, for example, a thickness of 100 nm. The passivation region 8 forms a first surface S a of the HEMT transistor 1.

[0018] Furthermore, the HEMT transistor 1 has a gate region 10 that extends into a trench 15 and is made of conductive material; for example, the gate region 10 can be formed from one or more metal layers, which are formed, for example, from aluminum, nickel, or tungsten.

[0019] More specifically, the trench 15 extends through the passivation region 8, starting from the first surface S a , as well as through the upper layer 6. Furthermore, the trench 15 crosses an upper region of the lower layer 4, which is arranged in contact with the upper layer 6.

[0020] More precisely, the trench 15 is defined by a first side wall P 11 , a second side wall P 12 , a third side wall P 13 and a fourth side wall P 14 which are parallel to each other and to the first surface S aare perpendicular. In addition, the trench 15 is defined by a first bottom wall P b1 , a second floor wall P b2 and a third floor wall P b3 which are parallel to each other and to the first surface S a are.

[0021] More specifically, the first floor wall P b1 in the lower layer 4 to a first depth (measured e.g. with respect to the first surface S a ).

[0022] Furthermore, the second floor wall P b2 and the third floor wall P b3 in the lower layer 4 to the same depth, which is less than the above-mentioned first depth. Furthermore, the first side wall P 11 the first and second floor wall P b1 , P b2 with each other; however, the third side wall P connects 13 the first and third floor wall P b1 , P b3 with each other. In addition, the second side wall P12 the second floor wall P b2 with the first surface S a ; the fourth side wall P 14 connects the third floor wall P b3 with the first surface S a .

[0023] As in Fig. 2 is shown in more detail, form the first floor wall P b1 and the first side wall P 11 in practice a first edge E 1 ; furthermore, the first side wall P 11 and the second floor wall P b2 a second edge E 2 which is parallel to the first edge E 1 with which it is coplanar. Furthermore, the second bottom wall P b2 and the second side wall P 12 a third edge E 3 , which is parallel to the second edge E 2 with which it is coplanar. The second side wall P 12 in turn forms a fourth edge E 4 with the first surface S a (in Fig. 2 not shown).

[0024] In addition, the first floor wall P b1 and the third side wall P 13 a fifth edge E 5 ; furthermore, the third side wall P 13 and the third floor wall P b3 a sixth edge E 6 , which is parallel to the fifth edge E 5 with which it is coplanar. In addition, the third floor wall P b3 and the fourth side wall P 14 a seventh edge E 17 , which are parallel to the sixth edge E 6 with which it is coplanar. The fourth side wall P 14 in turn forms an eighth edge E 8 with the first surface S a .

[0025] The first and third side walls P are even more clearly illustrated. 11 , P 13 offset from each other by a distance equal to L 1 (measured in a direction perpendicular to the first and third side walls P 11 , P13 ) and thus the width of the first floor wall P b1 The widths of the second and third floor walls P b2 , P b3 are, however, with L 2 or L 3 In addition, the first and third side walls P 11 , P 13 a height equal to H 1 , measured in a direction perpendicular to the first floor wall P 11 . As in Fig. 1, each of the second and fourth side walls P 12 , P 14 a respective lower area, which extends from the third or seventh edge E 3 , E 7 extends to a contact with the upper layer 6, this area having a height H 2 has.

[0026] In practice, the trench 15 forms a first cavity 22 and a second cavity 24, which communicate with each other and have the same length. The first cavity 22 opens into the first surface S a , is arranged above the second cavity 24 and has a width equal to L 1 + L 2 + L 3 ; the second cavity 24 has a width equal to L 1 . As an example only, the widths L 1 , L 2 and L 3 each between 0.1 µm and 10 µm; furthermore, the height H 1 for example, in the range from 1 nm to 500 nm, while the height H 2 e.g. 0 to 500 nm.

[0027] In other words, the first side wall P 11 and the second floor wall P b2form a first step, ie a first shoulder of a lateral structure LS, which laterally delimits the trench 15 and extends from one side of the first floor surface P b1 More specifically, when the ensemble of the semiconductor body 2 and the passivation region 3 is referred to as the main body, the lateral structure LS is formed by the main body. Furthermore, the second bottom wall P b2 , the second side wall P 12 and the first surface S a a kind of second step of the aforementioned lateral structure LS. The first and second steps are arranged consecutively such that the lateral structure LS assumes a stair-step profile.

[0028] The HEMT transistor 1 further comprises a dielectric region 18, which may be made of, for example, aluminum nitride (AIN) or silicon nitride (SiN) or silicon oxide (SiO 2 ) and is applied as a coating to the first surface S ais applied or covers them. Furthermore, the dielectric region 18 forms an inner coating of the trench 15, ie it is applied as a coating, among other things, to the first, second and third bottom wall P b1 , P b2 , P b3 as well as the first, second, third and fourth side walls P 11 , P 12 , P 13 and P 14 In this context, as mentioned above, the first, second and third floor walls P b1 , P b2 , P b3 as well as the first and third side walls P 11 , P 13 formed by the lower layer 4, while the second and fourth side walls P 12 , P 14 are each formed by the lower layer 4, the upper layer 6 and the passivation region 8.

[0029] More specifically, the gate region 10 has a bottom region 11a arranged in the second cavity 24, and a central region 11b arranged in the first cavity 23 on the bottom region 11a, with which it is in direct contact. The dielectric region 18 surrounds the bottom region 11a and the central region 11b of the gate region 10, which are thus arranged further inward in the trench 15 than the dielectric region 18 and are covered by the latter. In particular, the dielectric region 18 insulates the bottom region 11a and the central region 11b of the gate region 10 from the semiconductor body 2 as well as from the passivation region 8.

[0030] Even more clearly, the bottom region 11a and the central region 11b of the gate region 10 are both cuboid-shaped and have a width D 1 or a width D 2 , where D 1 < L 1 is and D 2 > L 1Furthermore, the soil area 11a extends without any restriction of the general character to a depth W 11a (measured from the first surface S a ), which is greater than the maximum depth to which the upper layer 6 extends (with W 3 the central area 11b, however, extends to a depth W 11b < W 11a Without any limitation of the general nature, the Fig. 1 shown embodiment W 6 < W 11b .

[0031] In other words and as in Fig. 3, the gate area 10 is defined at the bottom by a first horizontal wall O 1 , a second horizontal wall O 2 and a third horizontal wall O 3 and by a first vertical wall V 1 and a second vertical wall V 2 More specifically, the first horizontal wall O1 at the bottom the bottom area 11a of the gate area 10, which is laterally defined by the first and second vertical walls V 1 , V 2 The central region 11b of the gate region 10 is (partially) bounded at the bottom by the second and third horizontal walls O 2 , O 3 The first vertical wall V 1 connects the first and second horizontal wall O 1 , O 2 , with which it forms a corresponding stage of the gate area 10. Similarly, the second vertical wall V 2 the first and third horizontal wall O 1 , O 3 , with which it forms a corresponding step of the gate region 10. Furthermore, the first horizontal wall O 1 and the first vertical wall V 1 a first edge G 1 of the gate area 10, which are parallel to the first edge E 1 of the trench 15, while the first vertical wall V 1and the second horizontal wall O 2 a second edge G 2 of the gate region 10, which are parallel to the second edge E 2 of trench 15.

[0032] As again in Fig. 3, the gate region 10 further has an upper region 11c extending onto the central region 11b with which it is in direct contact. Furthermore, the central region 11b of the gate region 10 is laterally enclosed by a third vertical wall V 3 and a fourth vertical wall V 4 which are parallel to each other and to the second and fourth side walls P 12 , P 14 of the trench 15. The third vertical wall V 3 forms a third edge G 3 and a fourth edge G 4 of the gate area 10 with the second horizontal wall O 2 or the upper area 11c of the gate area 10.

[0033] In practice, the dielectric region 18 generally has an approximately constant thickness within the trench 15; i.e., it forms a kind of conformal layer covering the walls of the trench 15; as a result, the part of the gate region arranged inside the trench 15 is delimited by a surface that follows the profile of the trench 15 (and thus the profile of the lateral structure LS). Thus, corresponding to the respective edge / step of the trench 15, there is an edge / step of the part of the gate region 10 contained in the trench 15.

[0034] With further reference to Fig. 1, is that region of the dielectric region 18 which is located on the first surface S a extends, above from a second surface S b which is substantially parallel to the first surface S a Furthermore, the upper region 11c of the gate region 10 has a greater width than L 1 + L2 + L 3 , and it projects laterally over both the second side wall P 12 as well as the fourth side wall P 14 Without any limitation of its general character, the Fig. 1, the upper region 11c of the gate region 10 is separated to a greater extent in the lateral direction from the second side wall P 12 away as the upper area 11c from the fourth side wall P 14 protrudes.

[0035] The HEMT transistor 1 further includes a source metallization 26 and a drain metallization 28, which are arranged on opposite sides of the trench 15 and of the upper region 11c of the gate region 10. The source metallization 26 and the drain metallization 28 each extend through the top of the front surface S aarranged region of the dielectric region 18 as well as the region lying below the passivation region 8 until they contact the upper layer 6. In a manner known per se, the source metallization 26 and the drain metallization 28 can, for example, each be formed by a corresponding plurality of metal layers (for example made of titanium, aluminum and tungsten); furthermore, a respective upper region of the source metallization 26 and the drain metallization 28 each extends to a height that is greater than the height of the second surface S b .

[0036] More precisely, the second and fourth side walls P 12 , P 14 of the trench 15 facing the drain metallization 28 or the source metallization 26.

[0037] In use, the gate region 10, the dielectric region 18 and the lower layer 4 form a MOSFET whose channel is located in the lower layer 4 below the first bottom wall P b1 This channel, which is the normally off type, can be modulated by applying a voltage to the gate region 10.

[0038] In a manner known per se, a so-called "two-dimensional electron gas" (2DEG) is formed below the interface between the lower layer 4 and the upper layer 6, and thus in the lower layer 4, which constitutes the channel (of the normally-on type) of the HEMT transistor 1. This channel is also modulated by the voltage present at the gate region 10, due to the fact that in the upper region 11c of the gate region 10 there is a projection which extends towards the drain metallization 28 with respect to the underlying central region 11b and is thus superimposed on a corresponding region of the two-dimensional electron gas. In other words, the upper layer 6 functions as a barrier layer, while the lower layer 4 functions as a buffer layer.

[0039] Due to the presence of the above-mentioned MOSFET, the HEMT transistor 1 thus has a channel of the normally off type. Furthermore, it can be shown that the HEMT transistor 1 has a leakage current of the Fig. 4, which further shows, as an example, the leakage current of a HEMT transistor of a known type.

[0040] In practice, the HEMT transistor 1 is not affected by the DIBL phenomenon. This is due to the fact that, due to the presence of the aforementioned first stage of the trench 15, the electric field at the aforementioned first edge E 1 shows a structure as a function of the drain voltage, which is the Fig. 5 (assuming zero gate and source voltage), which further represents an example of the corresponding electric field diagram generated in a HEMT transistor of a known type, in which the gate region is formed in a recess of traditional shape at a lower edge of this recess. In fact, the presence of the aforementioned first stage of the lateral structure in the semiconductor body 2 implies the presence of the third edge E 3 ; as a result, the electric field between the first and the third edge E 1 , E 3 roughly divided.

[0041] Furthermore, variations of the Fig. 1 are possible, but the trench 15 extends to different depths than those described so far. For example, in Fig. 6, it is possible that the first floor wall P b1of the trench 15 lies in the plane of the interface between the lower layer 4 and the upper layer 6. In this case, the gate region 10 is located entirely on top of the lower layer 4. As a result, the second edge E 2 of the trench 15 and the above-mentioned first step of the trench 15 is formed by the upper layer 6. The first edge E 1 is still in contact with the lower layer 4 and thus ensures the above-mentioned reduction of the electric field.

[0042] According to a further example of a transistor not according to the invention, as shown in Fig. 7, the HEMT transistor 1 is of the same type as that shown in Fig. 1, except for the fact that the second edge E 2of the trench 15 is formed by the upper layer 6. Without any restriction of the general character, assuming that the passivation region 8 extends to a depth W 8 extends, the relation W 11b > W 8 , although in any case changes are possible where W 11b = W 8 amounts.

[0043] In general, the Fig. 6 and Fig. 7, the examples of HEMT transistors not falling within the scope of the claims are characterized by low resistances between the source metallization 26 and the drain metallization 28, since in both cases a part of the channel of the MOSFET is formed in the upper layer 6; the resulting greater extension of the two-dimensional gas thus brings about a reduction of the so-called R ON or on-resistance.

[0044] Fig. Figure 8, however, shows an embodiment of a HEMT transistor according to the invention in which the lateral structure LS has more than two stages. Without any limitation of the general character, Fig. 8, the lateral structure LS in addition to the above-mentioned first and second stages (the upper edges of which E 2 , E 4 in Fig. 8) for example, there are three further steps whose upper edges are marked E x1 , E x2 or E x3 are labeled. Just as an example, the edges E x1 , E x2 and E x3 formed by the upper layer 6. The central region 11 of the gate region 10 thus forms three further corresponding additional steps, the upper edges of which are labeled G x1 , G x2 or G x3 without any limitation of the general nature of the Fig. 8 the edge G x3 coplanar with the interface between the lower layer 4 and the upper layer 6.

[0045] It can be shown that with increasing number of steps of the lateral structure LS, the electric field present between the gate region 10 and the drain metallization 28 becomes more evenly distributed along the lateral structure LS, since the corresponding peaks, manifested by the presence of the edges, reduce their own amplitude. This prevents any degradation of the HEMT transistor during turn-off steps, where the transistor is exposed to high drain voltages.

[0046] This HEMT transistor 1 according to the invention can be manufactured, for example, by implementing the manufacturing method described below. Without any limitation of the general nature and merely as a non-limiting example, a manufacturing method relating to the manufacture of the Fig. 1 shown non-inventive HEMT transistor.

[0047] As in Fig. 9, the main body is initially provided in a manner known per se, which includes the semiconductor body 2 and the passivation region 8.

[0048] Next, as in Fig. 10, a photolithographic process and a subsequent etching process are carried out in a manner known per se in order to selectively remove part of the passivation region 8, an underlying region of the upper layer 6 and an underlying region of the lower layer 4 in order to form a first recess 40 which has the shape of a cuboid and a greater depth than the above-mentioned depth W 11b The first recess 40 is delimited at the bottom by a flat surface SR, which is formed by the lower layer 4 and is designed to receive the central region 11b of the gate region 10 and the region of the dielectric region 18 covering it.

[0049] As in Fig. 11, a further photolithographic process and a subsequent etching process are next carried out in a manner known per se in order to selectively remove a part of the lower layer 4 starting from the planar surface SR. More specifically, a region of the lower layer 4 is removed, which region forms a central region of the planar surface SR, wherein the central region separates a pair of lateral regions of the planar surface SR, which in turn form the second and third bottom walls P b2 or P b3 of the trench 15. In this way, a second depression 42 is formed, which is bordered at the bottom by the first bottom wall P b1 and has a smaller width than the first recess 40. The second recess 42 is further delimited laterally by the first and third side walls P 11 , P 13and is designed to receive the lower region 11a of the gate region 10, so that it extends to a greater depth than the above-mentioned depth W 11a The first and second depressions 40, 42 form the trench 15.

[0050] As in Fig. 12, is next applied to the first surface S a and a dielectric layer 50, which is formed, for example, from aluminum nitride or silicon nitride, is formed inside the trench 15. The dielectric layer 50 is thus applied as a coating to the walls of the trench 15 and is formed, for example, by deposition.

[0051] Next, as in Fig. 13, the source metallization 26 and the drain metallization 28 are formed in a manner known per se. Although not shown in detail, it is possible for this purpose to carry out a further photolithographic process and a subsequent etching process to selectively remove regions of the dielectric layer 50 as well as underlying regions of the passivation region 8, thereby forming cavities designed respectively to accommodate the source metallization 26 and the drain metallization 28, which are subsequently formed inside these cavities by the so-called "lift-off technique." According to the lift-off technique, a resist mask is formed by a photolithographic process, which leaves exposed precisely those regions of the HEMT transistor 1 that are to be overlaid with the source metallization 26 and the drain metallization 28.Next, a metal material is deposited on the HEMT transistor 1; subsequent removal of the resist mask also involves removing the metal material overlying the actual resist mask. Once the source metallization 26 and drain metallization 28 are formed, what remains of the dielectric layer 50 forms the dielectric region 18.

[0052] Although not shown, a heating process is next carried out, for example at a temperature in the range of 500 °C to 900 °C, to form the contacts.

[0053] As in Fig. 14, the gate region 10 is formed next, the bottom region 11a and central region 11b of which extend into the trench 15. The gate region 10 can also be formed by a corresponding lift-off process, which includes forming a corresponding resist mask, applying conductive material both to the mask and to the region of the HEMT transistor 1 left free by the mask, and then removing the resist mask and the conductive material arranged on top of it.

[0054] What, however, are examples of the Fig. 8, i.e. embodiments in which the lateral structure LS forms more than two stages, these can be formed, for example, by carrying out the following steps (not shown): (a) selectively removing an upper portion of the main body to clear a corresponding recess defined by a bottom surface; b) starting from the above-mentioned bottom surface, selectively removing an underlying portion of the main body to form a further depression defined by a respective bottom surface, the further depression having a smaller width than the preceding depression and being laterally offset with respect to the side walls of the preceding depression; and c) Repeat step b) until the desired number of steps is formed.

[0055] In the case where the manufacturing method just described is used, the shape of the trench 15 can be different from that described in Fig. 8; in particular, the region of the trench 15 facing the source metallization 26 may have a number of steps equal to that of the lateral structure LS.

[0056] The above description and illustration clearly demonstrate the advantages that can be achieved with the present solution.

[0057] In particular, this HEMT transistor is essentially immune to the DIBL phenomenon because, in use, the electric field at the first edge E 1 (in contact with the first layer 4) due to the presence of at least the third edge E 3 in the semiconductor body 2 is reduced.

[0058] Finally, it is clear that modifications and changes may be made to the subject matter described and illustrated so far without departing from the scope of the present invention as defined in the appended claims.

[0059] For example, the source metallization 26 and the drain metallization 28 may each partially penetrate into the upper layer 6 and possibly also into an upper region of the lower layer 4.

[0060] The lower layer 4 may have a respective upper region and a respective lower region (not shown), which are doped, for example, with carbon atoms; in this case, the upper region is doped with carbon atoms to a lesser extent than the lower region and has the function of a so-called channel layer, while the lower region of the lower layer 4 serves as a buffer layer. In this case, if the second and third bottom walls P b2 , P b3 are formed by the lower layer 4, they can equally be formed by the upper region or the lower region of the lower layer 4.

[0061] The doping of the semiconductor body 2 may be of a different type than that described. For example, the lower layer 4 and the upper layer 6 may be p-conductive.

[0062] As for the trench 15, the trench formed between the first floor wall P b1and the source metallization 26 may have a different shape than that described. For example, embodiments of the Fig. 1 shown type is possible, but where the third floor wall P b3 is not present, in which case the third and fourth side walls P 13 , P 14 are replaced by a single sidewall. In this context, it can be noted that for the purposes of preventing the DIBL phenomenon, the shape of the further lateral structure laterally delimiting the trench 15 and opposite the lateral structure LS is largely irrelevant, since the electric field between the source metallization 26 and the gate region 10 is less strong than the electric field present between the gate region 10 and the drain metallization 28.

[0063] The passivation region 18 can be omitted, in which case the first surface S a formed by the upper layer 6.

[0064] As in Fig.15, a spacer layer 200 may again be present between the lower layer 4 and the upper layer 6, which spacer layer is formed, for example, from aluminum nitride and has a smaller thickness of, for example, 1 nm; the spacer layer 200 is provided for the purpose of improving the mobility of the two-dimensional electron gas. In general, there are thus further possible embodiments which correspond to the embodiments described so far, but additionally include the spacer layer 200. In these further embodiments, the spatial distribution of the steps and the edges of the lateral structure LS may, for example, correspond to that of the embodiments described herein in the sense that when an edge of a step is formed in an embodiment described above by a specific layer (e.g.the lower layer 4 or the upper layer 6), the corresponding edge in the corresponding further embodiment is again formed by this particular layer.

[0065] Referring again to the lateral structure LS, although orthogonal steps have been described so far, i.e. steps connecting pairs of horizontal surfaces by vertical surfaces, it is also possible for the vertical surfaces of one or more steps to be arranged transversely with respect to the corresponding horizontal surfaces and / or for one or both of the horizontal surfaces of one or more steps to be replaced by surfaces which are not parallel to the first surface S a In other words, the walls and vertical surfaces do not generally have to be perfectly orthogonal to the first surface S a be.

Claims

[1] HEMT transistor of the normally off type, having: - a semiconductor heterostructure (4, 6, 200) comprising at least a first layer (4) and a second layer (6), wherein the second layer is arranged on top of the first layer, wherein the first layer (4) is different from the second layer (6), and wherein the first layer (4) is in direct contact with the second layer (6); - a trench (15) extending through the second layer and a region of the first layer; - a gate region (10) of conductive material extending into the trench; and - a dielectric region (18) extending into the trench and in contact with the semiconductor heterostructure; wherein the dielectric region (18) is arranged between the gate region and the semiconductor heterostructure; wherein a part of the trench is laterally delimited by a lateral structure (LS) comprising at least one first step (P b1 , P 11 , P b2 ), wherein the lateral structure (LS) has a stair-step shape; and wherein the semiconductor heterostructure forms a first edge (E1) and a second edge (E2) of the first stage, the first edge and the second edge being formed by the first layer; wherein the lateral structure (LS) further forms more than two steps, wherein a second step has a third edge (E3) and a fourth edge (E4; E x1 ), wherein the third edge is formed by the first layer (4) and the fourth edge is formed by the second layer (6) and is arranged above the third edge. [2] HEMT transistor according to claim 1, which further comprises a first electrode region (26) and a second electrode region (28), wherein the trench (15) is arranged between the first and the second electrode region; and wherein the lateral structure (LS) is formed by a part of the semiconductor structure (4, 6, 200) which is arranged between the trench and one of the first and the second electrode region. [3] HEMT transistor according to one of the preceding claims, wherein the gate region (10) comprises a respective first region (11a, 11b) arranged in the trench (15) and which is bounded on a first side by a surface (V1, O2, V3) forming at least one step of the gate region, the step of the gate region being surrounded by the semiconductor heterostructure (4, 6, 200) from which it is physically separated. [4] The HEMT transistor of claim 3, wherein the gate region (10) further comprises a respective second region (11c) extending on the first region (11b, 11c) and projecting laterally from the trench (15). [5] HEMT transistor according to one of the preceding claims, wherein the trench (15) is formed at the bottom by a bottom wall (P b1 ) formed by the first layer (4), wherein the bottom wall forms the first edge (E1) of the lateral structure (LS); and wherein the dielectric region (18) covers the bottom wall and the lateral structure (LS). [6] HEMT transistor according to one of the preceding claims, wherein the first and second layers (4, 6) are formed from two materials such that, in use, a two-dimensional electron gas is generated in the first layer (4). [7] HEMT transistor according to one of the preceding claims, wherein the first and second layers (4, 6) are formed of gallium nitride and aluminum gallium nitride, respectively.

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