Method for manufacturing a semiconductor structure

Abstract

Method for manufacturing a semiconductor structure, comprising the following steps: Creating a dielectric layer (140) on a conductive structure (120) and Producing a metal hard mask (150) on the dielectric layer (140) by physical or chemical vapor deposition, wherein no degassing process is carried out between the production of the metal hard mask (150) and the production of the dielectric layer (140), and wherein an initial temperature of the dielectric layer (140) for producing the metal hard mask (150) is about 15 °C to about 30 °C; Structuring the metal hard mask, wherein structuring the metal hard mask (150) comprises the following steps: Producing a photoresist (160, 162) on the metal hard mask (150) obtained by physical or chemical vapor deposition; Structuring the photoresist (160, 162) and Structuring the metal hard mask (150) with the structured photoresist (160, 162); and Structuring the dielectric layer (140) with the structured metal hard mask (150) to produce a plurality of through-holes (146) in the dielectric layer (140); producing a plurality of conductive structural elements (170a, 170b) each in the through-holes (146).

Description

Background of the invention

[0001] Integrated circuit elements, such as transistors, are fabricated on semiconductor wafers. These components are interconnected via metal traces and vias to create functional circuits. During the fabrication of these traces and vias, a dielectric layer is etched to create the through-holes. A metal hard mask can be used for etching this dielectric layer. The metal hard mask can be used in the etching process to transfer structures onto the semiconductor wafers. The metal hard mask allows for a desired etch profile and the control of critical dimensions to reduce the size of geometries.

[0002] US 2012 / 0098073A1 describes a semiconductor device with a transistor and several contact elements. Publications CN103779268A and KR10200500064215A describe various structuring methods for fabricating metal hard masks. US 9184060B1 discusses the application of electroplating to fabricate a metal hard mask. US 2002 / 0055244A1 shows various contact structures in a transistor above a buried insulating layer. Brief description of the drawings

[0003] Aspects of the present invention are best understood with reference to the detailed description below in conjunction with the accompanying drawings. It should be noted that, in accordance with common industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of discussion, the dimensions of the various elements may be arbitrarily enlarged or reduced. The Fig. Figures 1A to 1F are sectional views of a method for producing a semiconductor structure according to various embodiments of the present invention. Fig. Figure 2 is a top view of a Cluster Plant 900 according to some embodiments. The Fig. Figures 3A to 3F are sectional views of a method for producing a semiconductor structure according to different embodiments of the present invention. Detailed description

[0004] The following description provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are in direct contact, and it may also include embodiments in which additional elements can be formed between the first and second elements such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present invention.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0005] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. These spatially relative terms are intended to encompass orientations of the component in use or operation beyond the orientation shown in the figures. The device can be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0006] Unless otherwise stated, all terms (including technical and scientific terms) used herein have the meanings generally known to those skilled in the art in the field to which this invention belongs. It should also be clear that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant field and the present invention, and should not be interpreted in an idealized or overly formal sense unless expressly stated herein.

[0007] The Fig. Figures 1A to 1F are sectional views of a method for producing a semiconductor structure according to various embodiments of the present invention. Let us now turn to… Fig. 1A. First, a substrate 110 is provided. In some embodiments, the substrate 110 comprises silicon. Alternatively, the substrate 110 may comprise germanium, silicon germanium, gallium arsenide, or other suitable semiconductor materials. Also alternatively, the substrate 110 may have an epitaxial layer. For example, the substrate 110 may have an epitaxial layer located over a bulk semiconductor. Furthermore, the substrate 110 may be strained to improve performance. The epitaxial layer may, for example, comprise a semiconductor material different from that of the bulk semiconductor, such as a layer of silicon germanium over bulk silicon or a layer of silicon over bulk silicon germanium. This strained substrate may be fabricated by selective epitaxial growth (SEG). In addition, the substrate 110 may have an SOI sensor (SOl: semiconductor on insulator).Alternatively, the substrate 110 can be a buried dielectric layer, such as a BOX layer (BOX: buried oxide), which can be produced, for example, using SIMOX technology (SIMOX: separation by implantation of oxygen), wafer bonding, SEG, or another suitable method. In some embodiments, the substrate 110 can have different doped regions depending on the design requirements (e.g., p-wells or n-wells). The doped regions can be doped with p-doped elements, such as boron or BF₂, n-doped elements, such as phosphorus or arsenic, or a combination thereof. The doped regions can be produced directly in the substrate 110, in a p-well structure, an n-well structure, a double-well structure, or a raised structure.

[0008] A conductive structure 120 is fabricated in, on, and / or above the substrate 110. The conductive structure 120 can be an electrical element fabricated in, on, and / or above the substrate 110. The electrical element can include CMOS transistors, diodes, resistors, capacitors, inductors (CMOS: complementary metal-oxide semiconductor), and other active and passive semiconductor devices. For clarity, in Fig. Figure 1A shows a single electrical element. However, in some other embodiments, several electrical elements of different types can be used.

[0009] In Fig. 1A is the first conductive structure 120, a transistor. The transistor has a gate structure 122, a plurality of source / drain structural elements (also called S / D structural elements) 124, a channel 126, and a plurality of gate spacers 128. The channel 126 is located between the source / drain structural elements 124, and the gate structure 122 is located on the channel 126. In some embodiments, the source / drain structural elements 124 can be doping regions. The source / drain structural elements 124 can be fabricated by an ion implantation process or a diffusion process. N-dopeds, such as phosphorus or arsenic, can be used to fabricate the S / D structural elements 124 for an n-field-effect transistor (NFET), and p-dopeds, such as boron, can be used to fabricate the S / D structural elements 124 for a PFET.The S / D structural elements 124 are each aligned with the outer boundaries of the gate spacers 128. It is clear that in some embodiments, LDD regions (LDD: lightly doped source / drain) can be fabricated in the substrate 110 before the gate spacers 128 are produced. For the sake of simplicity, the LDD regions are not shown in detail here.

[0010] In some further embodiments, the S / D structural elements 124 and the channel 126 consist of fin structures. In some further embodiments, the S / D structural elements 124 are epitaxial structures. The S / D structural elements 124 can comprise silicon (Si), silicon phosphorus (SiP), silicon carbide phosphorus (SiCP), gallium antimony (GaSb), or silicon germanium (SiGe) with a relatively low germanium concentration for an NFET. The S / D structural elements 124 can comprise germanium (Ge), germanium tin (GeSn), or silicon germanium (SiGe) with a relatively high germanium concentration for a PFET.

[0011] In some embodiments, the gate structure 122 can comprise one or more dielectric gate layers and a polysilicon gate. The polysilicon can be doped or undoped. Fig. Although doped polysilicon is used as the gate in 1A, other silicon-based materials from the group consisting of single-crystal silicon, polysilicon, doped silicon, doped polysilicon, amorphous silicon and / or silicon germanium can also be used.

[0012] In some embodiments, an RPG process scheme (RPG: replacement gate) is used. In some embodiments, an RPG process scheme involves first fabricating a polysilicon dummy gate, which is then replaced by a metal gate after high-heat-budget processes have been carried out. That is, the gate structure 122 is a metal gate. The metal gate may comprise one or more dielectric gate layers, capping layers, filler layers, and / or other suitable layers that are expedient in a metal gate stack. The metal gate may be deposited by ALD (atomic layer deposition), PVD (physical vapor deposition), CVD (chemical vapor deposition), or another suitable method.

[0013] In some embodiments, the transistor further features a plurality of silicide contacts 129, each located on the S / D structural elements 124. Silicides, which are compounds consisting of a metal and silicon, are used for contacts in semiconductor devices. The silicide contacts 129 are thermally stable, have a lower resistivity than polysilicon, and provide good ohmic contacts. The silicide contacts 129 are also reliable because the silicide formation reaction eliminates many defects at the interface between a contact and a device structure. One process used in the semiconductor manufacturing industry is the salicid process (salicide: self-aligned silicide). The salicid process can be used in the fabrication of high-speed CMOS devices.In the salicid process, the surface areas of the S / D structural elements 124 are converted into silicide contacts 129. The salicid process involves the deposition of a metal that undergoes a silicide formation reaction with silicon (Si). To create the silicide contacts 129 on the S / D structural elements 124, oxide spacers are fabricated directly adjacent to the gate structure 122. The metal material is then deposited as a protective layer on the transistor. The transistor is heated to a temperature at which the metal reacts with the silicon of the S / D structural elements 124, forming contacts. Subsequently, the unreacted metal is removed. Silicide contacts 129 remain over the S / D structural elements 124, while unreacted metal is removed from other areas.

[0014] A dielectric layer 140 is then fabricated on the substrate 110 and the conductive structure 120. The dielectric layer 140 can be an ILD layer (ILD: inter-layer dielectric; or inter-level dielectric). The dielectric layer 140 can be fabricated by chemical vapor deposition (CVD), high-density plasma deposition, spin deposition, sputtering, or other suitable methods. In some embodiments, the dielectric layer 140 comprises silicon dioxide. In some other embodiments, the dielectric layer 140 can comprise silicon dioxide nitride, silicon nitride, or a low-k material.

[0015] In some embodiments, the dielectric layer 140 can comprise several parts stacked on top of each other. For example, a dielectric material can be deposited on the substrate 110 and the conductive structure 120. A planarization process is then carried out to partially remove the dielectric protective material, forming a first part 142 of the dielectric layer 140 and exposing a top surface of the gate structure 122 of the transistor. The planarization process is, for example, a CMP process (CMP: chemical-mechanical polishing). In some embodiments, an RPG process can then be carried out, replacing a dummy gate of the transistor with a metal gate. After this, further dielectric material is formed on the first part 142 of the dielectric layer 140 to form a second part 144.The first part 142 and the second part 144 of the dielectric layer 140 can be made of the same material or of different materials.

[0016] Now let's move on to... Fig. 1B. A metal hard mask 150 is produced on the dielectric layer 140 without carrying out a degassing process. In particular, the structure of Fig. 1A The manufacturing process for the metal hard mask 150 is carried out after the dielectric layer 140 has been produced. No degassing process is carried out between the manufacturing process for the metal hard mask 150 and the manufacturing process for the dielectric layer 140. The degassing process is intended to maintain the structure of Fig. 1A needs to be heated to remove moisture. To remove the moisture, the structure of Fig. 1A is heated to a high temperature, such as approximately 150 °C to approximately 500 °C. However, when the metal hard mask 150 is manufactured, while the structure of Fig. If the temperature in 1A is high, there would be a risk that the metal hard mask 150 would have an unstable grain size and density. This unstable grain size and density would also affect the refractive index and extinction coefficient of the metal hard mask 150, thus reducing its quality. A low-quality metal hard mask 150 would impair the production of the through-holes (see Fig. 1D and Fig. 1E) impair, for which the metal hard mask 150 is used.

[0017] Fig. Figure 2 is a top view of a cluster plant 900 according to some embodiments. During the manufacture of the metal hard mask 150, the structure of Fig. 1A is loaded into the cluster system 900. The cluster system 900 comprises the following: at least one loading lock 910, at least one degassing chamber 920, at least one process chamber 930, at least one through-chamber 940, and at least one robot blade 950. The structure of Fig. Wafer 1A (referred to as the wafer) is placed from loading port 910 into cluster unit 900. Loading port 910 is then closed. Loading port 910 can create an atmosphere depending on the wafer's next destination. The gas content of loading port 910 can be changed by mechanisms such as supplying purified gases or creating a vacuum, along with other suitable means for adjusting the atmosphere of loading port 910. Once the desired atmosphere has been achieved, the corresponding door can be opened, and the wafer is accessible. Degassing chamber 920 is configured to degasse the wafer. Process chamber 930 can be a PVD chamber or a CVD chamber for producing the metal hard mask 150 (see Fig. 1B) on the wafer. The passage chamber 940 is a chamber for receiving the transported wafer. The robot blade 950 is configured to transport the wafer.

[0018] Now let's move on to the Fig. 1B and Fig. 2. Since in Fig. If the degassing process is omitted, a wafer entering the loading port 910 of the cluster unit 900 is transported to the process chamber 930 without passing through the degassing chamber 920. This means the wafer is only heated when it enters the process chamber 930. Alternatively, at least one further process can be performed on the wafer before it enters the process chamber 930. However, the wafer is not heated to as high a temperature as in the degassing process. In other words, the wafer's temperature is not high. For example, the initial temperature of the dielectric layer 140 of the wafer for the production of the metal hard mask 150 is approximately 15 °C to 30 °C. At this temperature, the quality of the metal hard mask 150 can be improved, and its refractive index and extinction coefficient can also be enhanced.

[0019] In some embodiments, the metal hard mask 150 can consist of titanium nitride, tantalum nitride, boron nitride, titanium, tantalum, or a combination thereof. The metal hard mask 150 can be produced by physical vapor deposition (PVD) or chemical vapor deposition (CVD). The CVD process can be plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or the like. In some embodiments, the precursors for the deposition of the metal hard mask 150 can be TiCl4, N2, Ar, H2, and the like.

[0020] Now let's move on to... Fig. 1C. Here, a photolithographic process is carried out that defines the metal hard mask 150. In some embodiments, a three-layer photoresist 160 can be used, comprising a PR layer 162 (PR: photoresist) as the top or uppermost part, a middle layer 164, and a bottom layer 166. The three-layer photoresist 160 is arranged on the metal hard mask 150. The three-layer photoresist 160 comprises: the PR layer 162; the middle layer 164, which may include antireflective or back-side antireflective coatings to aid exposure and focusing during PR processing; and the bottom layer 166, which may be a hard mask material, for example, a nitride.To structure the three-layer photoresist 160, the PR layer 162 is structured using a mask. This involves exposure to radiation, such as light or an excimer laser, followed by a curing step to harden the resist, and the use of a developer to remove either the exposed or unexposed parts of the resist (depending on whether a positive or negative resist is used) to create the structure of the mask in the PR layer 162. This structured PR layer 162 is then used to etch the underlying middle layer 164 and bottom layer 166 to create an etching mask for the target layer, in this case, the metal hard mask 150. In some further embodiments, the middle layer 164 and the bottom layer 166 can be omitted. That is, the photoresist 160 is then a single-layer photoresist.

[0021] Now let's move on to... Fig. 1D. Here, an etching process is carried out to produce a structured 150' metal hard mask. The PR layer 162 (see Fig. 1C) is structured and used as a mask during the etching process. During the etching process, the middle layer 164, the bottom layer 166, and the metal hard mask 150 (see Fig. 1C) can be etched using various methods, including dry etching, wet etching, or a combination of dry and wet etching. For the dry etching process, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6) or a chlorine-containing gas (e.g., Cl2, CHCl6, CCl4, and / or BCl) can be used. eA brominated gas (e.g., HBr and / or CHBr3), an oxygen-containing gas, an iodine-containing gas, other suitable gases and / or plasmas, or combinations thereof, may be used. The etching process may involve multi-step etching to achieve etch selectivity, flexibility, and a desired etch profile. After structuring the metal hard mask 150, the PR layer 162, the middle layer 164, and the bottom layer 166 are removed.

[0022] Now let's move on to... Fig. 1E. Using the structured metal hard mask 150' as a mask, the dielectric layer 140 is etched using various methods, such as dry etching, wet etching, or a combination of dry and wet etching, to create a multitude of through-holes 146. The through-holes 146 extend substantially vertically through the dielectric layer 140, exposing the gate structure 122 and the silicide layers 129, respectively. The number of through-holes 146 in Fig. 1E is an example. A specialist can choose a suitable number for the through-holes 146 according to the actual circumstances.

[0023] Now let's move on to... Fig. 1F. Here, a large number of conductive structural elements 170a and 170b are fabricated in the through-holes 146. The conductive structural elements 170a and 170b are in Fig. 1F Metal contacts. That is, the conductive structural elements 170a and 170b and the dielectric layer 140 form a metal-dielectric layer (MD layer). The conductive structural elements 170a are each connected to the silicide layers 129 to electrically connect them to the S / D structural elements 124 of the transistor, and the conductive structural element 170b is connected to the gate structure 122 of the transistor. In some embodiments, metal materials can be filled into the through-holes 146, and the excess parts of the metal materials are removed by performing a CMP process to produce the conductive structural elements 170a and 170b. The conductive structural elements 170a and 170b can be made of tungsten, aluminum, copper, or other suitable materials. The conductive structural elements 170a and 170b can also form composite structures, such as barrier and adhesive layers, e.g.made of titanium / titanium nitride or tantalum nitride, and include additional layers.

[0024] In Fig. In 1F, the conductive structural element 170a has a bottom surface 174a and at least one side wall 172a. The bottom surface 174a and the side wall 172a of the conductive structural element 170a intersect, forming an interior angle θa. The interior angle θa is approximately 92 degrees to approximately 98 degrees. The conductive structural element 170b has a bottom surface 174b and at least one side wall 172b. The bottom surface 174b and the side wall 172b of the conductive structural element 170b intersect, forming an interior angle θb. The interior angle θb is approximately 92 degrees to approximately 98 degrees. Furthermore, the interior angles θa and θb of any two adjacent conductive structural elements 170a and 170b differ by less than or approximately 3 degrees. This means that the profiles of the conductive structural elements 170a and 170b are essentially the same, and the manufacture of the conductive structural elements 170a and 170b (or the through-holes 146 of Fig. 1E) is stable. The term “essentially” used here can be used to modify a quantitative representation that could permissibly change without altering the basic function to which it refers.

[0025] Since at the Fig. When the metal hard mask is produced in processes 1A to 1F, if the initial temperature of the wafer's dielectric layer is approximately 15°C to 30°C, or if the metal hard mask is produced without a degassing process, the grain size and density of the metal hard mask are stable. Therefore, the quality of the metal hard mask can be improved, and its refractive index and extinction coefficient can also be enhanced. This improvement subsequently allows for the creation of good profiles of the conductive structural elements.

[0026] The Fig. Figures 3A to 3F are sectional views of a method for fabricating a semiconductor structure according to various embodiments of the present invention. First, a substrate 210 is provided. In some embodiments, the substrate 210 is a semiconductor substrate, such as a solid silicon substrate, a semiconductor wafer, an SOI substrate, or a silicon germanium substrate, but it can also comprise other semiconductor materials, such as elements of Group III, Group IV, and / or Group V.

[0027] A semiconductor structure 220 is fabricated on substrate 210. To fabricate the semiconductor structure 220, an electrical element is fabricated in, on, and / or above the substrate 210. The electrical element can include CMOS transistors, diodes, resistors, capacitors, inductors, and other active and passive semiconductor devices. For clarity, in Fig. Figure 3A shows a single electrical element 222. In some further embodiments, however, several electrical elements 222 of different types can be used. Subsequently, an interconnection structure 224 is fabricated on the electrical element 222. In some embodiments, the interconnection structure 224 covers the electrical element 222. The interconnection structure 224 is configured to connect the electrical elements 222 to one another. The interconnection structure 224 has a plurality of metallization layers comprising metal conductors and vias (not shown) in a plurality of dielectric layers. The metal conductors and vias can be made of copper or copper alloys and can be fabricated using known damascening techniques.The dielectric layers of the compound structure 224 can consist of a low-k dielectric material, an extremely low-k dielectric material, or silicon. The low-k dielectric material is a material with a lower dielectric constant than silicon dioxide, whose dielectric constant is approximately 3.9, and the extremely low-k dielectric material has a dielectric constant of less than approximately 2.5. In some further embodiments, the compound structure 224 can comprise well-known inter-layer dielectrics (ILDs) and inter-metal dielectrics (IMDs).

[0028] A conductive structure 230 is fabricated on the semiconductor structure 220. In other words, the interconnect structure 224 is fabricated between the electrical element 222 and the conductive structure 230. Fig. In embodiment 3A, the conductive structure 230 has a multitude of parts. For example, a conductive layer (not shown) and a photoresist (not shown) can be sequentially fabricated on the semiconductor structure 220. The photoresist is then exposed and developed to create a structured photoresist. Subsequently, the conductive layer is etched based on the structured photoresist to fabricate the multitude of parts. In some embodiments, the conductive structure 230 can include metal contact points, such as aluminum (Al), and can thus also be referred to as an aluminum contact point, but it can also consist of copper (Cu), silver (Ag), gold (Au), nickel (Ni), tungsten (W), alloys, or combinations thereof. In some further embodiments, the conductive structure 230 can consist of aluminum copper (AlCu). The conductive structure 230 can, for example,The electrical element 222 is connected via the connecting structure 224 located below.

[0029] A dielectric layer 240 is fabricated to cover the conductive structure 230. The dielectric layer 240 can be fabricated by chemical vapor deposition (CVD), high-density plasma deposition, spin deposition, sputtering, or other suitable methods. In some embodiments, the dielectric layer 240 comprises silicon dioxide. In other embodiments, the dielectric layer 240 can comprise silicon dioxide nitride, silicon nitride, or a low-k material.

[0030] Now let's move on to... Fig. 3B. A metal hard mask 250 is produced on the dielectric layer 240 without a degassing process. In particular, the structure of Fig. 3A The manufacturing process for the metal hard mask 250 is carried out after the dielectric layer 240 has been produced. No degassing process is carried out between the manufacturing process for the metal hard mask 250 and the manufacturing process for the dielectric layer 240.

[0031] Now let's move on to the Fig. 3B and Fig. 2. Since in Fig. 3B if no degassing process is carried out, the structure of Fig. 3A (referred to as a wafer), which enters the loading port 910 of the cluster unit 900, is transported to the process chamber 930 without entering the degassing chamber 920. This means the wafer is only heated when it enters the process chamber 930. Alternatively, at least one further process can be performed on the wafer before it enters the process chamber 930. However, the wafer is not heated to as high a temperature as in the degassing process. In other words, the wafer's temperature is not high. For example, the initial temperature of the dielectric layer 240 of the wafer for the production of the metal hard mask 250 is approximately 15 °C to 30 °C. At this temperature, the quality of the metal hard mask 250 can be improved, and its refractive index and extinction coefficient can also be enhanced.

[0032] In some embodiments, the metal hard mask 250 can consist of titanium nitride, tantalum nitride, boron nitride, titanium, tantalum, or a combination thereof. The metal hard mask 250 can be produced by physical vapor deposition (PVD) or continuous vapor deposition (CVD). The CVD process can be plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or the like. In some embodiments, the precursors for the deposition of the metal hard mask 250 can be TiCl4, N2, Ar, H2, and the like.

[0033] Now let's move on to... Fig. 3C. Here, a photolithographic process is carried out that defines the metal hard mask 250. In some embodiments, a three-layer photoresist 160 can be used, comprising a PR layer 162 as the top or uppermost part, a middle layer 164, and a bottom layer 166. The three-layer photoresist 160 is arranged on the metal hard mask 250. In some further embodiments, the middle layer 164 and the bottom layer 166 can be omitted. That is, the photoresist 160 is then a single-layer photoresist.

[0034] Now let's move on to... Fig. 3D. Here, an etching process is performed to produce a structured 250' metal hard mask. The PR layer 162 (see Fig. 3C) is structured and used as a mask during the etching process. During the etching process, the middle layer 164, the bottom layer 166, and the metal hard mask 250 (see Fig. 3C) can be etched using various methods, including dry etching, wet etching, or a combination of dry and wet etching. For the dry etching process, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., CI2, CHCl6, CCl4, and / or BCl6), a bromine-containing gas (e.g., HBr and / or CHBr3), an oxygen-containing gas, an iodine-containing gas, other suitable gases and / or plasmas, or combinations thereof can be used. The etching process may involve multi-step etching to achieve etch selectivity, flexibility, and a desired etch profile. After structuring the metal hard mask 250, the PR layer 162, the middle layer 164, and the bottom layer 166 are removed.

[0035] Now let's move on to... Fig. 3E. Using the structured metal hard mask 250' as a mask, the dielectric layer 240 is etched by various methods, such as dry etching, wet etching, or a combination of dry and wet etching, to create a multitude of through-holes 246. The through-holes 246 extend substantially vertically through the dielectric layer 240, exposing the conductive structure 230. The number of through-holes 246 in Fig. 3E is an example. A specialist can choose a suitable number for the through-holes 246 according to the actual circumstances.

[0036] Now let's move on to... Fig. 3F. Here, a large number of conductive structural elements 270 are manufactured in the through-holes 246. The conductive structural elements 270 are in Fig. 3F vias. In some embodiments, metallic materials can be filled into the via holes 246, and the excess parts of the metallic materials are removed by performing a CMP process to produce the conductive structural elements 270. The conductive structural elements 270 can be made of tungsten, aluminum, copper, or other suitable materials.

[0037] In Fig. 3F The conductive structural element 270 has a bottom surface 274 and at least one side wall 272. The bottom surface 274 and the side wall 272 of the conductive structural element 270 intersect, forming an internal angle θ. The internal angle θ is approximately 92 degrees to approximately 98 degrees. Furthermore, the internal angles θ of any two adjacent conductive structural elements 270 differ by less than or approximately 3 degrees. This means that the profiles of the conductive structural elements 270 are essentially uniform, and the fabrication of the conductive structural elements 270 (or the through-holes 246 of Fig. 3E) is stable. The term “essentially” used here can be used to modify a quantitative representation that could permissibly change without altering the basic function to which it refers.

[0038] Since at the Fig.In processes 3A to 3F, if the metal hard mask is produced when the initial temperature of the wafer's dielectric layer is approximately 15°C to 30°C, or if the metal hard mask is produced without a degassing process, the grain size and density of the metal hard mask are stable. Therefore, the quality of the metal hard mask can be improved, and its refractive index and extinction coefficient can also be enhanced. This improvement subsequently allows for the creation of good profiles of the conductive structural elements.

[0039] According to some embodiments, a semiconductor structure comprises a conductive structure, a dielectric layer, and a plurality of conductive structural elements. The dielectric layer is located on the conductive structure. A plurality of through-holes are formed in the dielectric layer, and at least one of the through-holes exposes the conductive structure. The conductive structural elements are located within the through-holes. At least one of the conductive structural elements has a bottom surface and at least one side surface. The bottom surface and the side surface of the conductive structural element intersect, forming an interior angle. The interior angles of any two adjacent conductive structural elements differ by less than or approximately equal to 3 degrees.

[0040] According to some embodiments, a method for producing a semiconductor structure involves producing a dielectric layer on a conductive structure. A hard mask is produced on the dielectric layer without performing a degassing process.

[0041] According to some embodiments, a method for fabricating a semiconductor structure includes the fabrication of a dielectric layer on a conductive structure. A metal hard mask is then fabricated on the dielectric layer. The initial temperature of the dielectric layer for fabricating the metal hard mask is approximately 15 °C to approximately 30 °C.

Claims

[1] Method for fabricating a semiconductor structure, comprising the following steps: Creating a dielectric layer (140) on a conductive structure (120) and Producing a metal hard mask (150) on the dielectric layer (140) by physical or chemical vapor deposition, wherein no degassing process is carried out between the production of the metal hard mask (150) and the production of the dielectric layer (140), and wherein an initial temperature of the dielectric layer (140) for producing the metal hard mask (150) is about 15 °C to about 30 °C; Structuring the metal hard mask, wherein structuring the metal hard mask (150) comprises the following steps: Producing a photoresist (160, 162) on the metal hard mask (150) obtained by physical or chemical vapor deposition; Structuring the photoresist (160, 162) and Structuring the metal hard mask (150) with the structured photoresist (160, 162); and Structuring the dielectric layer (140) with the structured metal hard mask (150) to produce a plurality of through-holes (146) in the dielectric layer (140); producing a plurality of conductive structural elements (170a, 170b) each in the through-holes (146). [2] Method according to claim 1, wherein at least one through-hole (146) exposes the conductive structure (120). [3] Method according to claim 1 or 2, wherein the structuring of the metal hard mask (150) further comprises the following step: Creating a lower layer (166) and a middle layer (164) between the photoresist (162) and the metal hard mask (150). [4] Method according to any one of claims 1 to 3, wherein the metal hard mask (150) consists of titanium nitride, tantalum nitride, boron nitride, titanium, tantalum or combinations thereof. [5] The method of claim 2, further comprising the following step: Producing at least one conductive structural element (170a, 170b) in the at least one through-hole (146) to connect it to the conductive structure (120). [6] Method according to any one of claims 1 to 5, wherein the conducting structure (120) is a transistor. [7] Method according to any one of claims 1 to 5, wherein the conducting structure (120) is a conducting intermediate layer conductor. [8] Method according to any one of claims 1 to 7, further comprising the following step: Removal of the metal hard mask (150).

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