SRAM structure with reduced capacity and reduced resistance

Abstract

Integrated circuit structure, comprising: an SRAM cell (10) (SRAM: static random access memory), comprising: a first pull-up MOS device (PU-1) (MOS: metal oxide semiconductor) and a second pull-up MOS device (PU-2), and a first pull-down MOS device (PD-1) and a second pull-down MOS device (PD-2), forming inverters cross-locked to the first pull-up MOS device (PU-1) and the second pull-up MOS device (PD-2); an elongated contact (54) located over and electrically connected to a source of the first pull-down MOS device (PD-1); a first metal layer (M1) containing a bit line and a CVdd line; a first CVss contact island (52B) overlapping the elongated contact (54) and is electrically connected to this, wherein the first CVss contact island (52B) has a part in the SRAM cell (10) which has a first length and a first width,which are smaller than a second length and a second width of the SRAM cell (10), wherein the SRAM cell (10) has a first boundary (10A) and a second boundary (10B) that are parallel to each other, and a third boundary (10C) and a fourth boundary (10D) that are parallel to each other, and the first CVss contact island (52B) overlaps the first boundary (10A) and the fourth boundary (10D) but does not extend beyond the second boundary (10B) and the third boundary (10C); a first word line (50) having a first longitudinal direction, wherein the first word line (50) extends from the third boundary (10C) to the fourth boundary (10D), wherein the first word line (50) and the first CVss contact island (52B) are located in a second metal layer (M2) above the first metal layer (M1), and wherein the first word line (50) forms a strip portion (50A) and has a protruding part (50B),which is connected to a part of a first side wall of the strip section (50A) in the first longitudinal direction and extends in a direction perpendicular to the first longitudinal direction, wherein the projecting part (50B) extends in the direction of the first boundary (10A) and is spaced from the first boundary (10A) and further extends from the third boundary (10C) in the direction of the fourth boundary (10D) and is spaced from the fourth boundary (10D), wherein the CVss contact island (52B) and the projecting part (50B) are spaced apart by a distance S1 so that they do not electrically short-circuit, wherein the word line has a width W1 and the projecting part (50B) has a width W2 and wherein 0.1 <= W2 / W1 <= 0.5,wherein the width of the first word line (50) is increased by the projecting part (50B) and thereby the resistance of the first word line (50) is reduced; and a first CVss line (58) in a third metal layer (M3) above the second metal layer (M2), wherein the first CVss line (58) is electrically connected to the first CVss contact island (52B) and has a second longitudinal direction that is perpendicular to the direction of the first longitudinal direction.

Description

Background of the invention Static random access memory (SRAM) is commonly used in integrated circuits. SRAM cells have the advantage of retaining data without requiring data refresh. With the ever-increasing demand for faster integrated circuits, the read and write speeds of SRAM cells are becoming increasingly important. However, with the further miniaturization of the already very small SRAM cells, it is difficult to meet this demand. For example, the layer resistance of the metal traces that form the word and bit lines of SRAM cells is constantly increasing, and therefore the RC delay of the word and bit lines of the SRAM cells is increasing, preventing improvements in read and write speeds. With the advent of the nanometer era, SRAM cells with split word lines became increasingly widespread due to the lithography-friendly layout of their active areas, polysilicon traces and metal layers, and their shorter bit lines, thus increasing speed. However, in the nanometer era, SRAM cells are also larger, leading to the following two problems. First, each bit line must be connected to multiple rows of SRAM cells, resulting in higher bit line-metal coupling capacitance and thus reducing the differential velocity of the different bit lines (bit line and bit line rail). Second, each word line must also be connected to multiple columns of SRAM cells, leading to longer word lines and therefore a less favorable resistance. Patent application US 2013 / 0258759 A1 discloses an SRAM cell structure in which the CVss, CVdd, and bit lines are arranged in a first metal layer, whereas the word lines are arranged in a second metal layer. Patent application DE 10 2013 105020 A1 discloses an SRAM cell structure in which the bit divisions and the CVss metal tracks are arranged in a first metal layer, while the CVdd metal tracks and the word lines are arranged in a second metal layer. Patent application DE 60 2005 002546 T2 discloses an SRAM cell structure in which bit divisions are arranged in a first metal layer, while the Vcc and Vss metal tracks are in a second metal layer and the word divisions are in a third metal layer. Brief description of the drawings Aspects of the present invention are best understood with reference to the detailed description below in conjunction with the accompanying drawings. It should be noted that, in accordance with common industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of discussion, the dimensions of the various elements may be arbitrarily enlarged or reduced. Figures 1 and 2 show circuit diagrams of an SRAM cell according to some embodiments. Figure 3 shows a sectional view of layers involved in an SRAM cell according to some embodiments. Figure 4 shows a layout of input elements of an SRAM cell according to some embodiments. Figure 5 shows a word line and CVss contact islands in an SRAM cell according to some embodiments. Figure 6 shows word lines and CVss contact islands in an SRAM cell according to some embodiments.Figure 7 shows a layout of an SRAM cell according to some embodiments. Figure 8 shows dual word lines and dual CVss lines according to some embodiments. Figure 9 shows the layout of an SRAM cell with dual word lines and dual CVss lines according to some embodiments. Figure 10 shows elements in metal layers M1 to M3 of an SRAM cell according to some embodiments. Figure 11 shows a sectional view of the elements in metal layers M1 to M3 of an SRAM cell according to some embodiments. Detailed description The following description provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present invention. These are, of course, merely examples and are not intended to be limiting. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are in direct contact, and it may also include embodiments in which additional elements can be formed between the first and second elements such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present invention.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed. Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. These spatially relative terms are intended to encompass orientations of the component in use or operation beyond the orientation shown in the figures. The device can be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly. According to various exemplary embodiments, an SRAM cell (SRAM: static random-access memory) and the corresponding SRAM array are provided. Furthermore, some variations of certain embodiments are discussed. In all views and explanatory embodiments, similar reference symbols are used to denote similar elements. Fig. 1 shows a circuit diagram of an SRAM cell 10 according to some embodiments. The SRAM cell 10 comprises pull-up transistors PU-1 and PU-2, which are PMOS transistors (PMOS: p-type metal-oxide semiconductor), and pull-down transistors PD-1 and PD-2 and pass-through gate transistors PG-1 and PG-2, which are NMOS transistors (NMOS: n-type metal-oxide semiconductor). The gates of the pass-through gate transistors PG-1 and PG-2 are controlled by a word line WL, which determines whether the SRAM cell 10 is selected or not. A latch consisting of the pull-up transistors PU-1 and PU-2 and the pull-down transistors PD-1 and PD-2 stores a bit, with the complementary values ​​of the bit being stored in an SD node (SD: storage data) 110 and an SD node 112.The stored bit can be written to or read from SRAM cell 10 via complementary bit lines comprising a bit line (BL) 114 and a bit line bar (BLB) 116. SRAM cell 10 is powered by a positive supply node Vdd, which has a positive supply voltage (also denoted Vdd). SRAM cell 10 is also connected to a supply voltage VSS (also denoted Vss), which can be an electrical ground. Transistors PU-1 and PU-2 form a first inverter. Transistors PD-1 and PD-2 form a second inverter. The input of the first inverter is connected to transistor PG-1 and the output of the second inverter. The output of the first inverter is connected to transistor PG-2 and the input of the second inverter. The sources of pull-up transistors PU-1 and PU-2 are connected to CVdd nodes 102 and 104, respectively, which are in turn connected to the supply voltage (and line) Vdd. The sources of pull-down transistors PD-1 and PD-2 are connected to CVss nodes 106 and 108, respectively, which are in turn connected to the supply voltage / line Vss. The gates of transistors PU-1 and PD-1 are connected to the drains of transistors PU-2 and PD-2, forming a connection node designated SD node 110. The gates of transistors PU-2 and PD-2 are connected to the drains of transistors PU-1 and PD-1, and this connection node is designated SD node 112. A source / drain region of the through-gate transistor PG-1 is connected to the bit line BL 114 at a BL node. A source / drain region of the through-gate transistor PG-2 is connected to the bit line BLB 116 at a BLB node. Fig. 2 shows an alternative circuit diagram of the SRAM cell 10, in which transistors PU-1 and PD-1 from Fig. 1 are represented as the first inverter, Inverter-1, and transistors PU-2 and PD-2 are represented as the second inverter, Inverter-2. The output of the first inverter, Inverter-1, is connected to transistor PG-1 and the input of the second inverter, Inverter-2. The output of the second inverter, Inverter-2, is connected to transistor PG-2 and the input of the second inverter, Inverter-2. Fig. 3 shows a schematic sectional view of a multitude of layers involved in an SRAM cell 10, fabricated on a semiconductor chip or wafer. It should be noted that Fig. 3 is a schematic representation to show various levels of interconnect structures and transistors and cannot depict the actual sectional view of the SRAM cell 10. The interconnect structure has a contact layer, an OD layer (where OD stands for 'active region'), via layers Via_0, Via_1, Via_2, and Via_3, and metal layer layers M1, M2, M3, and M4. Each of the depicted layers comprises one or more dielectric layers and the conductive structural elements fabricated therein.The conductive structural elements located in the same plane can have top surfaces and bottom surfaces that are essentially at the same level, and they can be manufactured simultaneously. The contact plane can include gate contacts (also called contact pins) for connecting the gate electrodes of transistors (such as the exemplary transistors PU-1 and PU-2 shown) to a plane above, such as the Via_0 plane, and source / drain contacts (referred to as "contacts") for connecting the source / drain regions of transistors to the plane above. Fig. 4 shows a layout of the input elements of the SRAM cell 10 according to some exemplary embodiments, wherein the input elements comprise the elements in the plane Via_0 (Fig. 1) and in the planes located below the plane Via_0. Outer boundaries 10A, 10B, 10C, and 10D of the SRAM cell 10 are represented by dashed lines marking a rectangular area. An n-well region N_well is located in the center of the SRAM cell 10, and two p-well regions P_well are located on opposite sides of the n-well region N_well. The CVdd node 102, the CVdd node 104, the CVss node 106, the CVss node 108, the bit line (BL) node, and the bit line rail (BLB) node shown in Fig. 1 are also shown in Fig. 4. A gate electrode 16 forms the pull-up transistor PU-1 with the active area (in the n-well area) 20 located below it, which can be fin-based and is therefore referred to below as fin 20.Gate electrode 16 forms the pull-down transistor PD-1 with active regions 14 located below it (in the first p-well region P_well on the left side of the n-well region N_well), which can also be fin-based. Gate electrode 18 forms the through-gate transistor PG-1 with region 14 located below it. Gate electrode 36 forms the pull-up transistor PU-2 with region 40 located below it (in the n-well region N_well). Gate electrode 36 also forms the pull-down transistor PD-2 with region 34 located below it (in the second p-well region P_well on the right side of the n-well region). Gate electrode 38 forms the through-gate transistor PG-2 with region 34 located below it.In some embodiments of the present invention, the pass-through gate transistors PG-1 and PG-2, the pull-up transistors PU-1 and PU-2, and the pull-down transistors PD-1 and PD-2 are fin field-effect transistors (FinFETs). In alternative embodiments of the present invention, the pass-through gate transistors PG-1 and PG-2, the pull-up transistors PU-1 and PU-2, and the pull-down transistors PD-1 and PD-2 are planar MOS devices. Fig. 4 shows two fins 14 (and two fins 34) according to some embodiments. In other embodiments, the number of fins can be one, two, or three, with one of the fins 14 (and one of the fins 34) shown with a dashed line to indicate additional fins that may or may not be present. As shown in Fig. 4, the SD node 110 comprises a source / drain contact pin 42 and a gate contact pin 44, which are the elements in the contact plane (Fig. 2). The contact pin 42 is elongated, and its longitudinal direction extends in the X-direction, which is parallel to the orientations of the gate electrodes 16 and 36. The gate contact pin 44 has a portion that is located above the gate electrode 36 and is electrically connected to it. In some embodiments of the present invention, the longitudinal direction of the gate contact pin 44 extends in the Y-direction, which is perpendicular to the X-direction. When fabricating the SRAM cell 10 on physical semiconductor wafers, the contact pins 42 and 44 can be manufactured as a single, continuous dome contact pin. The SD node 112 comprises a source / drain contact pin 46 and a gate contact pin 48. The gate contact pin 48 has a portion that overlaps the source / drain contact pin 46. Since the SD node 110 can be symmetrical to the SD node 112, the details of the gate contact pin 48 and the source / drain contact pin 46 are not repeated here and can be found by referring to the descriptions of the gate contact pin 44 and the source / drain contact pin 42, respectively. Fig. 4 also shows word line contacts (referred to as WL contacts) connected to gate electrodes 18 and 38. In addition, several vias, each represented by a circle containing an "X", are located above and in contact with the individual contact pins below. Elongated contact pins 54A and 54B connect the source regions of pull-down transistors PD-1 and PD-2, respectively, to CVss lines. The elongated contact pins 54A and 54B are part of the CVss nodes 106 and 108, respectively. The longitudinal direction of the elongated contact pins 54A and 54B is parallel to the X direction, and they can be designed to overlap the corners of the SRAM cell 10. Furthermore, the elongated contact pins 54A and 54B can extend further into adjacent SRAM cells that border SRAM cell 10. Fig. 5 shows the conducting elements in plane M2 (Fig. 1), where the conducting elements are those inside or adjacent to the SRAM cell 10. For clarity, the input elements shown in Fig. 4 are not shown in Fig. 5, but they are nevertheless present. The SRAM cell 10 has cell boundaries 10A and 10B, which are parallel to each other and extend in the X direction, and cell boundaries 10C and 10D, which are parallel to each other and extend in the Y direction. A word line 50 (comprising parts 50A and 50B) has a strip part 50A extending in the X direction. The strip part 50A extends the entire distance from boundary 10A to boundary 10B. The strip part 50A has a rectangular shape. The opposite edges of strip section 50A are parallel to each other and run in the X direction. In some embodiments of the present invention, the word line 50 further comprises a single projecting part 50B on only one side of the strip portion 50A. The production of the projecting part 50B leads to an advantageous increase in the width of the word line 50 and thus to a reduction in the resistance of the word line 50, thereby advantageously reducing the RC delay in the word line 50. The projecting strip portions 50B are indicated by dashed lines. CVss contact islands 52A and 52B, collectively referred to as CVss contact islands 52, are also fabricated in plane M2. Throughout this description, the term "contact islands" refers to conductive elements large enough to accommodate the vias located above them (in this case, the vias in plane Via_2). In some embodiments of the present invention, the CVss contact islands 52A and 52B are separate islands in the top view of the SRAM cell 10, and they may have rectangular shapes. The lengths of the CVss contact islands 52A and 52B are much shorter than the length of the word line 50. For example, the CVss contact islands 52A and 52B are so short that each CVss contact island 52A and 52B extends into and terminates in two adjacent columns of SRAM cells. As shown in Fig. 6, each of the CVss contact islands 52A and 52B extends into four adjacent SRAM cells.In contrast, the word line 50 can extend into 4, 8, 16, 32 or more columns of SRAM cells. In conventional SRAM structures, Vss lines are fabricated as long lines parallel to the word lines, and they can be the same length as the word lines. This results in high parasitic capacitance in the word lines. However, since in embodiments of the present invention the CVss contact islands 52 are much shorter than the adjacent word lines 50, the parasitic capacitance between the CVss contact islands 52 and the word line 50 is low. Furthermore, because the CVss contact islands 52 are short, protruding parts 50B can be fabricated using gaps that are free due to the shortening of the CVss lines / contact islands. In some exemplary embodiments of the present invention, the ratio of a width W2 of the protruding parts 50B to a width W1 of the strip part 50A can be greater than about 0.1. The W2 / W1 ratio can be in the range of about 0.1 to about 0.5. As shown in Fig. 5, a projecting part 50B1, which is one of the projecting parts 50B, extends towards the boundary 10A of the SRAM cell 10 and is still spaced apart from the boundary 10A. The projecting part 50B1 further extends from the boundary 10C towards the CVss contact island 52B. The CVss contact island 52B extends from the boundary 10D towards the projecting part 50B1. However, the CVss contact island 52B and the projecting part 50B1 are spaced apart by a distance S1 (in the X direction), so that sufficient process clearance remains to prevent the projecting part 50B1 and the CVss contact island 52B from electrically short-circuiting each other. Fig. 6 shows a portion of an SRAM cell array 12, where the depicted portion may be part of a larger array. The depicted portion of the SRAM array comprises 4 x 4 SRAM cells 10. As shown in Fig. 6, the projecting portion 50B has one end 50B' terminating in the SRAM cell 10 and another end 50B'' terminating in an adjacent SRAM cell 10. The stripe portions 50A of the word line 50, on the other hand, may be contiguous stripes extending into a plurality of SRAM cells 10 in the same row. In Fig. 6, letters F are used to represent the relative directions of the layouts of the SRAM cells 10, with each letter F representing a SRAM cell and its orientation. The letter F is unique because its elements point in four different directions (+X, -X, +Y, -Y) and can therefore be used to identify the orientation of the SRAM cells. As shown in Fig.As shown in Figure 6, adjacent SRAM columns can mirror each other, and likewise adjacent SRAM rows can mirror each other. Fig. 7 shows the layout of the SRAM cell 10 according to some embodiments of the present invention. The structure shown in Fig. 5 and the structure shown in Fig. 6 are combined to form Fig. 7. Thus, the relative positions of the elements shown in Fig. 5 and the elements shown in Fig. 6 can be found in Fig. 7. The vias are shown in Fig. 7, but are not individually labeled with reference symbols. The CVss node 106 includes the contact pin 54A in the contact plane (Fig. 1), wherein the contact pin 54A is electrically connected to the contact island 56A (in plane M1) via a via (in plane Via_0). The contact pin 54A is also electrically connected to the source region of the pull-down transistor PD-1. The contact island 56A in level M1 is also electrically connected (via a via in level Via_1) to the CVss contact island 52A in the level M2 above.The contact island 52A in layer M2 is also electrically connected (via a via in layer Via_2) to a CVss line 58A located in layer M3. The CVss line 58A extends in the Y direction and can reach into a multitude of SRAM cells in the same column. As further shown in Fig. 7, the word line 50, located in plane M2 (Fig. 1), is electrically connected via a via in plane Via_1 to a contact island 60A in plane M1. The contact island 60A is also electrically connected via a via in plane Via_0 to a gate contact pin 62A. Again, the vias in different planes are shown, but not individually labeled. The aforementioned connections are located on the left side of SRAM cell 10. Likewise, a multitude of connections, including contact islands, vias, and contact pins, are made on the right side of the SRAM cells. The connections on the right side may be similar to and symmetrical with those on the left side and are therefore not discussed in detail here. The connections on the right side have the same numbers as the corresponding connections on the left side, except that the reference symbols of the connections on the right side end with the letter B instead of the letter A. As shown in Fig. 7, a CVdd line 118, a bit line 114, and a bit line bus (BLB) 116 are arranged in the plane M1 (Fig. 1), and their longitudinal direction is parallel to the Y direction. Therefore, the CVdd line 118, the bit line 114, and the BLB 116 can each extend into and be connected to a plurality of SRAM cells in the same column. As further shown in Fig. 7, the word line 50, referred to as a first word line, is located in plane M2. To reduce the resistance of the word lines, a second word line 64, extending in the X direction, is arranged in plane M4, as shown in Fig. 8. Some elements shown in Fig. 7 are omitted from Fig. 8 for clarity, but these elements are nevertheless present. Fig. 8 shows the double word line and the double CVss line / contact according to some embodiments of the present invention. The word line 64 can also be made as a continuous metal conductor extending into a plurality of SRAM cells in the same row. The word line 64 can overlap a portion of the underlying word line 50, thus facilitating intermediate connections.For example, a contact island 66 in plane M3 is connected to the word line 64 above it via a via in plane Via_3 and to the word line 50 below it via a via in plane Via_2. Thus, word lines 50 and 64 are connected to each other to form a dual word line structure, thereby reducing the resistance of the resulting dual word line structure compared to a single word line structure. In some embodiments of the present invention, shown in Fig. 8, there is one (or more) dual word line connections (comprising the contact island 66 as well as a via above it and a via below it) per SRAM cell. In alternative embodiments, there is a single dual word line connection that is shared by a plurality of SRAM cells in the same row.A double word line connection can be made, for example, every four SRAM cells, every eight SRAM cells, etc. in the same row. Fig. 8 also shows a CVss line 70 in plane M4, where the CVss line 70 (referred to as a second CVss line) is parallel to the second word line 64. The CVss line 70 is made at the boundary of the SRAM cell 10 and can be shared by adjacent rows of SRAM cells. The longitudinal direction of the second CVss line 70 is parallel to the X direction. Furthermore, there are CVss lines 58 in plane M3 (comprising CVss lines 58A and 58B, referred to as first CVss lines) running in the Y direction. The CVss lines 58 and 70 are connected via the vias in plane Via_3 to form a double CVss line structure, thus reducing the resistance of the CVss lines. In the top view of the respective SRAM array, the CVss lines 58 and 70 form a mesh structure. The CVss mesh is connected to the CVss contact islands 52A and 52B. Fig. 9 shows a layout combining the input structure of Fig. 7 with the structure of Fig. 8. For clarity, the protruding word line parts are not shown in Fig. 8, regardless of whether they are manufactured or not. Furthermore, only one fin is shown for each transistor, although multi-fin transistors are also being considered. Fig. 10 shows some of the elements shown in Fig. 9. The elements shown include those in planes M1 and M3 and the elements between them, while other elements, including the input elements and vias in plane Via_0, are not shown for clarity. For example, the elements in planes M1, M2, and M3 are shown. The elements in plane M1 include CVdd line 118, bit line 114, and bit line bus 116. The elements in plane M2 include word line 50 [which includes stripe part 50A and protruding parts 50B (not shown)] and CVss contact islands 52A and 52B. The elements in plane M3 include CVss lines 58A and 58B. Fig. 11 shows a schematic sectional view of the structure of Fig. 10, the sectional view being created from the plane containing line 11-11 of Fig. 10. In some embodiments of the present invention, the metal structures in plane M1, such as a contact island 56B, each have a thickness T1, the metal structures in plane M2, such as the CVss contact island 52B and the word line 50, each have a thickness T2, and the metal structures in plane M3, such as the second CVss line 58B, each have a thickness T3. In some embodiments of the present invention, the thickness T2 is greater than the thicknesses T1 and T3. The thickness T2 can be, for example, 30 percent or approximately 30 percent to approximately 100 percent greater than the combined thicknesses T1 and T3. In other words, the ratios T2 / T1 and T2 / T3 can each be greater than about 1.3 or in the range of about 1.3 to about 2.0.In alternative embodiments, the thickness T2 is equal to or greater than the thickness T1, and the thickness T3 is equal to or greater than the thickness T2. Word lines 50 are long, especially in large SRAM arrays. Therefore, the resistance of the word lines 50 significantly impacts the performance of large SRAM cell arrays. Since the word lines 50 are located in layer M2, which is typically thin in conventional structures, their performance can become a bottleneck in improving the SRAM cell array's performance. Increasing the thickness of the word lines 50 can thus advantageously reduce their layer resistance. This, in turn, improves the speed of the resulting SRAM cells. Furthermore, the resistance of the bit lines can be reduced by placing them in layers M3 and M4, which are typically thick. The embodiments of the present invention have several advantages. By producing CVss contact islands 52A and 52B that are short and separated (instead of being long metal leads), the parasitic capacitance between the CVss contact islands and the word leads is reduced. Furthermore, by splitting the CVss leads in plane M2 into short contact islands, protruding word lead segments can be created, thereby reducing the resistance of the word leads. Since both the parasitic capacitance and the resistance are reduced, the RC delay of the word leads is also reduced, and the speed of the resulting SRAM cell is improved. The reduction in the resistance of the word leads can also be achieved by producing double word leads (in planes M2 and M4) and increasing the thickness of the elements in plane M2. The present invention is defined by the main claim and the dependent claims. Further embodiments of the invention are described by the dependent claims.

Claims

Integrated circuit structure, comprising: an SRAM cell (10) (SRAM: static random access memory), comprising: a first pull-up MOS device (PU-1) (MOS: metal oxide semiconductor) and a second pull-up MOS device (PU-2), and a first pull-down MOS device (PD-1) and a second pull-down MOS device (PD-2), forming inverters cross-locked to the first pull-up MOS device (PU-1) and the second pull-up MOS device (PD-2); an elongated contact (54) located over and electrically connected to a source of the first pull-down MOS device (PD-1); a first metal layer (M1) containing a bit line and a CVdd line; a first CVss contact island (52B) overlapping the elongated contact (54) and is electrically connected to this, wherein the first CVss contact island (52B) has a part in the SRAM cell (10) which has a first length and a first width,which are smaller than a second length and a second width of the SRAM cell (10), wherein the SRAM cell (10) has a first boundary (10A) and a second boundary (10B) that are parallel to each other, and a third boundary (10C) and a fourth boundary (10D) that are parallel to each other, and the first CVss contact island (52B) overlaps the first boundary (10A) and the fourth boundary (10D) but does not extend beyond the second boundary (10B) and the third boundary (10C); a first word line (50) having a first longitudinal direction, wherein the first word line (50) extends from the third boundary (10C) to the fourth boundary (10D), wherein the first word line (50) and the first CVss contact island (52B) are located in a second metal layer (M2) above the first metal layer (M1), and wherein the first word line (50) forms a strip portion (50A) and has a protruding part (50B),which is connected to a part of a first side wall of the strip section (50A) in the first longitudinal direction and extends in a direction perpendicular to the first longitudinal direction, wherein the projecting part (50B) extends in the direction of the first boundary (10A) and is spaced from the first boundary (10A) and further extends from the third boundary (10C) in the direction of the fourth boundary (10D) and is spaced from the fourth boundary (10D), wherein the CVss contact island (52B) and the projecting part (50B) are spaced apart by a distance S1 so that they do not electrically short-circuit, wherein the word line has a width W1 and the projecting part (50B) has a width W2 and wherein 0.1 <= W2 / W1 <= 0.5,wherein the width of the first word line (50) is increased by the projecting part (50B) and thereby the resistance of the first word line (50) is reduced; and a first CVss line (58) in a third metal layer (M3) above the second metal layer (M2), wherein the first CVss line (58) is electrically connected to the first CVss contact island (52B) and has a second longitudinal direction that is perpendicular to the direction of the first longitudinal direction. Integrated circuit structure according to claim 1, further comprising a second CVss contact island (52A) that overlaps the second boundary (10B) and the third boundary (10C) but does not extend beyond the first boundary (10A) and the fourth boundary (10D). Integrated circuit structure according to claim 1 or 2, wherein the projecting part (50B) extends further from the third boundary (10C) to the fourth boundary (10D) and is spaced apart from the fourth boundary (10D). Integrated circuit structure according to one of the preceding claims, further comprising a second word line (64) in a fourth metal layer (M4) above the third metal layer (M3), wherein the second word line (64) is parallel to the first word line (50) and has a part that overlaps a part of the first word line (50), and the first word line (50) is electrically connected to the second word line (64). Integrated circuit structure according to one of the preceding claims, further comprising a second CVss line (70) in a fourth metal layer (M4) above the third metal layer (M3), wherein the second CVss line (70) is perpendicular to the first CVss line (58) and has a portion that overlaps a portion of the first CVss line (58), and the first CVss line (58) is electrically connected to the second CVss line (70). Integrated circuit structure according to one of the preceding claims, wherein the second metal layer (M2) has a thickness greater than the thickness of the first metal layer (M1) and the thickness of the third metal layer (M3). Integrated circuit structure, comprising: an SRAM cell (10) (SRAM: static random access memory) having a first boundary (10A) and a second boundary (10B) parallel to each other, and a third boundary (10C) and a fourth boundary (10D) parallel to each other, the SRAM cell (10) comprising: a first pull-up MOS device (PU-1) and a second pull-up MOS device (PU-2), and a first pull-down MOS device (PD-1) and a second pull-down MOS device (PD-2) forming inverters cross-locked to the first pull-up MOS device (PU-1) and the second pull-up MOS device (PU-2); an elongated contact (54) located above and electrically connected to a source of the first pull-down MOS device (PD-1); a first metal layer (M1) above the elongated contact (54), wherein a bit line and a CVdd line are located in the first metal layer (M1); a CVss contact island (52B),which overlaps the elongated contact (54) and is electrically connected to it, a first word line (50) extending from the third boundary (10C) to the fourth boundary (10D), wherein the first word line (50) is located in a second metal layer (M2) above the first metal layer (M1) and comprises: a strip portion (50A) in the SRAM cell (10), wherein the strip portion has a rectangular shape in plan view, and a projecting portion (50B) connected to a first side wall of the strip portion (50A) and extending towards the first boundary (10A) and spaced from the first boundary (10A), and further extending from the third boundary (10C) towards the fourth boundary (10D) and spaced from the fourth boundary (10D), wherein the CVss contact island (52B) and the projecting portion (50B) are spaced apart by a distance S1, such that that they do not short-circuit electricallywherein the word line has a width W1 and the projecting part (50B) has a width W2 and wherein 0.1 <= W2 / W1 <= 0.5, wherein the width of the first word line (50) is increased by the projecting part (50B) and thereby the resistance of the first word line (50) is reduced; and a first CVss line (58) in a third metal layer (M3) above the second metal layer (M2). Integrated circuit structure according to claim 7, wherein the CVss contact island (52B) is formed in the second metal layer (M2), and wherein the CVss contact island (52B) overlaps the first boundary (10A) and the fourth boundary (10D) and extends from the first boundary (10A) towards the first word line (50). Integrated circuit structure according to claim 8, wherein the CVss contact island (52B) extends from the fourth boundary (10D) towards the projecting part (50B) and the projecting part (50B) extends from the third boundary (10C) towards the CVss contact island (52B), wherein a total length of a part of the CVss contact island (52B) and a part of the projecting part (50B) in the SRAM cell (10) is less than a distance between the third boundary (10C) and the fourth boundary (10D). Integrated circuit structure according to one of claims 7 to 9, further comprising a second word line (64) in a fourth metal layer (M4) above the third metal layer (M3), wherein the second word line (64) is parallel to the first word line (50) and has a part that overlaps a part of the first word line (50), and the first word line (50) is electrically connected to the second word line (64). Integrated circuit structure according to one of claims 7 to 10, further comprising a second CVss line (70) in a fourth metal layer (M4) above the third metal layer (M3), wherein the second CVss line (70) is perpendicular to the first CVss line (58) and has a part that overlaps a part of the first CVss line (58), and the first CVss line (58) is electrically connected to the second CVss line (70). Integrated circuit structure according to one of claims 7 to 11, wherein the second metal layer (M2) has a thickness greater than the thickness of the first metal layer (M1) and the thickness of the third metal layer (M3). Integrated circuit structure, comprising: an SRAM cell (10) (SRAM: static random access memory) having a first boundary (10A) and a second boundary (10B) parallel to each other, and a third boundary (10C) and a fourth boundary (10D) parallel to each other, the SRAM cell (10) comprising: a first pull-up MOS device (PU-1) (MOS: metal oxide semiconductor) and a second pull-up MOS device (PU-2), and a first pull-down MOS device (PD-1) and a second pull-down MOS device (PD-2) forming inverters cross-locked to the first pull-up MOS device and the second pull-up MOS device; an elongated contact (54) located above and electrically connected to a source of the first pull-down MOS device (PD-1); a CVss contact island (52B) that overlaps the elongated contact (54) and is electrically connected to it, a first metal layer (M1) over the elongated contact (54),wherein a bit line and a CVdd line are located in the first metal layer; a first word line (50) extending from the third boundary (10C) towards the fourth boundary (10D), wherein the first word line (50) is located in a second metal layer (M2) above the first metal layer (M1) and comprises: a strip portion (50A) in the SRAM cell (10), wherein the strip portion has a rectangular shape in plan view, and a projecting portion (50B) connected to a first side wall of the strip portion (50A) extending towards the first boundary (10A) and spaced from the first boundary, and further extending from the third boundary (10C) towards the fourth boundary (10D) and spaced from the fourth boundary (10D), wherein the width of the first word line (50) is increased by the projecting portion (50B) and thereby reduces the resistance of the first word line (50).wherein the CVss contact island (52B) and the projecting part (50B) are spaced apart by a distance S1 so that they do not electrically short-circuit, wherein the word line has a width W1 and the projecting part (50B) has a width W2 and wherein 0.1 ≤ W2 / W1 ≤ 0.5,; and a first CVss line (58) in a third metal layer (M3) above the second metal layer (M2), wherein the second metal layer (M2) has a thickness greater than the thickness of the first metal layer (M1) and the thickness of the third metal layer (M3). Integrated circuit structure according to claim 13, wherein the first CVss line (58) overlaps the first boundary (10A), the second boundary (10B) and the fourth boundary (10D). Integrated circuit structure according to claim 13 or 14, wherein the CVss contact island (52B) is formed in the second metal layer (M2), and wherein the CVss contact island (52B) extends from the first boundary (10A) in the direction of the first word line (50), overlaps the first boundary (10A) and the fourth boundary (10D) and is spaced apart from the third boundary (10C). Integrated circuit structure according to one of claims 13 to 15, further comprising a second word line (64) in a fourth metal layer (M4) above the third metal layer, wherein the second word line (64) is parallel to the first word line (50) and has a part that overlaps a part of the first word line (50), and the first word line (50) is electrically connected to the second word line (64). Integrated circuit structure according to one of claims 13 to 16, further comprising a second CVss line (70) in a fourth metal layer (M4) above the third metal layer (M3), wherein the second CVss line (70) is perpendicular to the first CVss line (58) and has a part that overlaps a part of the first CVss line (58), and the first CVss line (58) is electrically connected to the second CVss line (70).

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