METHOD FOR COMPONENT DIVISION ON SYSTEM-ON-CHIP AND DEVICE FOR THIS

Abstract

Method (100) for dividing a plurality of components of a system-on-chip, SOC (300, 400), comprising: Sorting the multitude of components into a multitude of sub-areas (A, B, C) according to a set of allocation criteria; Sorting the plurality of components of each sub-area into a first stack (A1) and a plurality of adjacent second stacks (A2, 311, 313, 315, 411, 413, 415) according to a set of stacking criteria, wherein the first stack comprises a plurality of higher-pitch metal layers (331, 333) and the second stacks comprise a plurality of lower-pitch metal layers, wherein the splitting criteria include component size, power, and speed, and the stacking criteria include a metal layer pitch (331, 333, 431, 433); Forming conductive means (340) between the components of each of the first stacks by an interposer (330, 430); Formation of conductive means (440) between the interposer (330, 440) and the components of the second stacks (311, 313, 315, 411, 413, 415).

Description

BACKGROUND

[0001] Improvements in integration density have resulted from repeated reductions in the minimum feature size, allowing more components to be integrated into a given area. In an effort to increase circuit density, three-dimensional (3D) integrated circuits (ICs) have been explored. In a typical manufacturing process for a 3D IC, two dies are bonded together, and electrical connections are made between each die and contact pads on a substrate. Interposer stacking is a part of 3D IC technology, whereby an interposer embedded by a through-silicon via (TSV) is connected to a device silicon with a microbump. 3D IC manufacturing process flows can be divided into two types. In a chip-on-chip-on-substrate (CoCos) process flow, a silicon interposer die is first attached to a packaging substrate, and then another device silicon die is attached to the interposer.In a chip-on-wafer-on-substrate (CoWoS) process, a device silicon chip is first attached to a silicon interposer wafer, which is then singulated. The resulting stacked silicon is then attached to a substrate.

[0002] However, when more devices are integrated into a chip, more complex designs are required. A system-on-chip (SOC) has multiple metal layers, and not all components on the SOC require a sophisticated process. The processing of each metal layer varies depending on numerous factors, such as pitch. Processing without differentiation for different metal layers will likely result in high production costs.

[0003] US 9 021 414 B1 relates to a method for designing a 3D integrated circuit comprising performing a partitioning into at least a first layer and a second layer and performing a first placement of the first layers using a 2D placer executed by a computer.

[0004] US 2015 / 0 235 949 A1 relates to a component package having a fan-out redistribution layer (RDL) and a component connected to the fan-out RDL, wherein the component comprises a first functional layer comprising an interconnect structure having an inter-tier via on a second substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of the present disclosure are best understood by reading the following detailed description in conjunction with the accompanying figures. It is noted that, as is common practice in the industry, various features are not drawn to scale. Indeed, the dimensions of the various features may be exaggerated or reduced as desired for clarity of explanation. Fig. 1 is a block diagram illustrating a method for component partitioning on a system-on-chip according to some embodiments of the present disclosure; Fig. 2 is a flowchart illustrating a method for component partitioning on a system-on-chip according to some embodiments of the present disclosure; Fig. 3 is a schematic diagram illustrating an architecture of a system-on-chip according to some embodiments of the present disclosure; Fig. 4 is a schematic diagram illustrating an architecture of a system-on-chip according to some embodiments of the present disclosure; Fig. 5 is a schematic diagram illustrating an architecture of a system-on-chip according to some embodiments of the present disclosure; Fig. 6 is a schematic diagram illustrating an architecture of a system-on-chip according to some embodiments of the present disclosure; and Fig. 7 is a schematic diagram illustrating an architecture of a system-on-chip according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0006] The invention results from the independent claims. The dependent claims relate to corresponding developments. The following disclosure provides many different embodiments or examples for realizing various features of the intended subject matter. To simplify the present disclosure, specific examples of components and arrangements are described below. These are, of course, only examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact.Furthermore, reference numbers and / or letters may be repeated throughout the various examples in the present disclosure. This repetition is for the purpose of simplicity and clarity and, as such, should not necessarily be construed as a connection between the various embodiments and / or configurations discussed.

[0007] A chip package structure can be used as a component in the fabrication of three-dimensional integrated circuits (ICs) and can be placed over a substrate, a board, a wafer, or other chips or chip packages. For example, the chip package can include a memory device or associated components, a processor, other chip logic, or a combination thereof. The chip package can include a second chip or die placed on a first chip or die using a CoWoS-like process flow. This process flow enables wafer-level packaging with specialized component separation.

[0008] With the continued development of 3D IC integration technology, multiple metal layers are stacked on top of each other on a single chip. This multi-layer architecture comprises metal layers with a wide variety of dimensions. It is not uncommon to find upper metal layers with a greater width and pitch than the lower metal layers. The upper metal layers occupy a larger area on the chip, and in general, the upper and lower metal layers cannot be reduced in size at the same rate due to their different dimensions. A SOC may comprise one or more stacked chips or chip logic, which may further comprise one or more stacked dielectric, conductive, and / or semiconductor layers. For example, the stacked chips or stacked chip logic may be one or more overlaid memory devices (e.g.,Flash memory and DRAM memory), one or more processors or processor cores (e.g., CPU cores), other digital logic, or a combination thereof. However, not all SoC components require advanced processing. Several process nodes share the same definition of a back-end-of-line (BEOL). Removing upper metal layers (e.g., metal layers 5-7) from advanced process chips and fabricating these metal layers with older process nodes incurs significant production costs.

[0009] In this document, embodiments are described with reference to a specific context, namely a chip package manufactured using a CoWoS-like process flow that includes system-on-chip (SoC) component partitioning and the formation of electrical connections of the upper metal layers. However, this disclosure may also be applied to other integrated circuits, electronic structures, and the like.

[0010] Now on Fig. Referring to Figure 1, an embodiment of a method 100 of dividing a plurality of components of an SOC is illustrated. Embodiments of the method 100 Fig. 1 are further shown in the schematic diagram of Fig. 2 and reference should be made to the figure as indicated in the text below.

[0011] As in process 110 from Fig. 1, a plurality of components of a SOC are sorted into a plurality of sub-areas according to a set of partitioning criteria. This is described in Fig. 2, which represents a schematic flow diagram of the partitioning process. The SOC comprises many components in different blocks, such as CPU, GPU, memory devices, or the like. These components are first divided into different sub-areas A, B, and C, which are Fig. 2. These components are sorted according to a set of partitioning criteria. The partitioning criteria include, but are not limited to, the process node (block size), power consumption, processing speed, block type, block cost, and the like. In particular, the feature size determines the area of ​​the subregion, and components that have a similar block size may be grouped together. For example, subregion A may have a feature size of 10 nm, subregion B may have a feature size of 16 nm, and subregion C may have a feature size of 28 nm. However, the present disclosure is not limited to this. Power consumption refers to real power, and leakage current should be considered. Processing speed is another factor that contributes to component partitioning.For example, components with higher processing speeds can be sorted into sub-area A, while components with lower processing speeds can be sorted into sub-area B, and components with slow processing speeds can be sorted into sub-area C. The block type is a less important partitioning criterion, which sometimes depends on the properties of the material provided by a third-party supplier. Production costs must of course be taken into account. This means that the components of the SOC are partitioned according to the minimum process requirements, which ultimately leads to minimal production costs. After the initial phase of sorting according to the partitioning criteria, the logic of the device can be created. It should be understood that sub-areas A, B and C, which are shown in . Fig. 2 are embodiments of the method and the number of sub-areas depends more or less on the requirements of the specific application.

[0012] As in Fig. As set forth in the process 120 illustrated in Figure 1, after the components have been divided according to division criteria, in each of sub-areas A, B, and C, components with similar properties are sorted into different stacks according to a set of stacking criteria. Take sub-area A, for example. The components are further sorted according to a set of stacking criteria. In particular, upper metal layers, which have a larger width and larger pitch routing, are sorted into a first stack A1. Lower metal layers are sorted into a second stack A2. For example, upper metal layers MY / MZ (BEOL), whose width / pitch is greater than 80 µm, are grouped in the first stack A1, while lower metal layers MX, whose pitch is less than 80 µm, and front-end (FE) are grouped in the second stack A2. This second-phase sorting process determines the layout in sub-area A.Analogously, the same process is applied in each of the other sub-areas, namely sub-areas B and C. Upper metal layers, for example, M5-7, are sorted into the first block B1 and C1. Lower metal layers, for example, M1-4, are sorted into the second block B2 and C2.

[0013] The first stack comprises upper metal layers that are similar in width and pitch and can be electrically connected by the most cost-effective process node via an interposer. Fig. 2, where the first stacks A1, B1, and C1 are arranged on the same plane for common routing. The conductive means between the first stacks, which comprise the upper metal layers, and the second stacks can be implemented by various means. The device architecture will be discussed in detail later.

[0014] In operation 130, the electrical connection is made according to the corresponding metal layer of the first and second stacks.

[0015] Now on Fig. 3, an embodiment of a SOC architecture fabricated according to the discussed partitioning method is illustrated. The components of the SOC 300 are arranged according to the partitioning criteria and the stacking criteria. The components in the first stacks comprise the upper metal layers, namely at least a second metal layer 331 and at least a third metal layer 333. These higher-pitch metal layers are electrically connected by an interposer 330. In other words, the higher-pitch metal layers of different components in the first stacks share the same routing. The external connectors and vias of the interposer 330 are not illustrated for clarity. In this embodiment, the interposer 330 provides electrical connection between the second and third metal layers 331, 333 and to a (front-side) redistribution layer (RDL) 335.The horizontal connection between the first stacks is formed by the interposer 330. A plurality of package pins 370 are arranged on the interposer, with the package connection being established via the pins 370. This side of the interposer is referred to as the backside. The first stacks may be collectively referred to as the interposer 330.

[0016] A substrate 320 is arranged on the front side of the interposer 330, opposite the package pins 370. The second stacks (or dies) 311, 313, and 315 comprise the bottom metal layer, namely at least one first metal layer 317a, 317b, and 317c in each of the second stacks. The dies 311, 313, and 315 are arranged on the substrate 320, which is located on the front side of the interposer 330. The conductive means between the first stacks / interposer 330 and the second stacks / dies 311, 313, and 315 is realized by through-substrate vias (TSVs) 340. One of the TSVs is arranged and aligned between the first metal layer 317a and the second metal layers 331. The remaining TSVs establish a connection between the first metal layers 317b and 317c using a similar configuration.TSVs 340 extend the length of substrate 320 and connect dies 311, 313, and 315 to the second metal layers of interposer 330. Chip-on-wafer technology is used to create an electrical path between interposer 330 and dies 311, 313, and 315, and the conductive path is connected by TSVs 340. The conductive path runs from the first metal layer 317a, 317b, and 317c to the redistribution layer 335 sequentially through the TSVs, the second metal layer 331, and the third metal layer 333, and the latter two are connected by interposer 330.

[0017] In the packaging industry, interposers are sometimes classified as "active," "passive," or "lightly active" ("active-lite"). A passive interposer can be an interposer that can make electrical connections primarily using passive wires, having a minimal number, such as zero, of active device elements (e.g., diodes, transistors, or the like). A "lightly active" interposer can be a cross between a true passive interposer and an active die. It can, for example, contain wires and a limited number of electronic elements. A "lightly active" interposer can have the cost advantage of a passive interposer and the advantage of requiring only a small investment to obtain some additional benefits without having to pay the price of a fully active die. The interposer 330 is a "lightly active" interposer, that is, an active interposer with limited functionality.The interposer 330 includes buffers 350 and wiring 360. The wiring 360 may be system-level electrostatic discharge (ESD) protection circuits.

[0018] It should be understood that the number of dies, metal layers and TSVs may be larger or smaller than those shown in Fig. 3 can be shown.

[0019] A concrete example is provided in connection with the previously discussed partitioning method. Components of an SOC are sorted into three sub-regions according to partitioning criteria, namely sub-region A (structure size: 10 nm), sub-region B (structure size: 16 nm), and sub-region C (structure size: 28 nm). Components of sub-region A are further sorted according to stacking criteria, with BEOL metal layers (e.g., first metal layer 317a) with a pitch smaller than 80 µm and FE being grouped together as a second stack A2. The remaining BEOL metal layers (e.g., second metal layer 331 and third metal layer 333) of sub-region A have a pitch larger than 80 µm and are arranged as a first stack A1. The same sorting process applies to sub-regions B and C, and the resulting groups are first stacks A1, B1, and C1 and second stacks A2, B2, and C2 (e.g., second stacks 311, 313, and 315).A horizontal electrical connection between the first stacks A1, B1, and C1 is achieved by means of the interposer (e.g., interposer 330) using the most cost-effective process node (e.g., feature size: 65 nm). The vertical electrical connection between the interposer and the second stacks (dies) is achieved by conductive means (e.g., TSVs 340) that establish connections between the metal layers.

[0020] Let us now turn Fig. 4. This discusses another embodiment of an SOC architecture fabricated according to the partitioning method. The components of the SOC 400 are arranged according to the partitioning criteria and the stacking criteria. The components in each of the first stacks are the upper metal layers, namely at least a second metal layer 431 and at least a third metal layer 433. These higher-pitch metal layers are electrically connected by an interposer 430. The interposer 430 provides electrical connection between the second and third metal layers 431, 433 and to a (front-side) redistribution layer (RDL) 435 using the most cost-effective process node. In other words, the common electrical connection between the first stacks is formed by the interposer 430.

[0021] A substrate 420 is arranged on the back side of the interposer 430, and a second (back) redistribution layer 425 is formed in the substrate 420. A plurality of package pins 470 are arranged on the substrate 420. The electrical connection between the first and second redistribution layers 435, 425 is formed by substrate vias (TSVs) 423. Signal transmission from the front to the back side of the interposer 430 proceeds via the first redistribution layer 435, the substrate vias 423, the second redistribution layer 425, and the package pins 470.

[0022] The second stacks (or dies) 411, 413, and 415 comprise the lower metal layers, namely at least one first metal layer 417a, 417b, and 417c, respectively, in each of the second stacks. The dies 411, 413, and 415 are arranged opposite the substrate 420, which is located at the back of the interposer 430. The conductive means between the first stacks / interposer 430 and the second stacks / dies 411, 413, and 415 is realized by inter-tier vias 440. One of the inter-level vias 440 is arranged and aligned between the first metal layer 417a and the second metal layers 431. The remaining inter-level vias 440 establish connections between the first metal layers 417b and 417c via similar paths.The interlevel vias 440 are smaller than the substrate vias because they run along a shorter distance, measured approximately through the thickness of the interposer 430 or, alternatively, between the first metal layer 417a and the second metal layer 431. The interlevel vias may also be referred to as microbumps (µ-bumps), which are used between the die and the interposer, transmitting signals between the layers and providing a shorter path. Compared to the metal lines within the interposer, the microbump has lower resistance and reduced wiring density, and therefore, signal integrity is improved due to less interference and crosstalk. The trace extends from the first metal layer 417a, 417b, and 417c through interlevel vias 423 to the second metal layers 431.Furthermore, the signal is routed along the path from the first redistribution layer 435 on the front side through the substrate vias 423 to the second redistribution layer 425. The interposer 430 is a "lightly active" interposer, i.e., an active interposer with limited functionality. The interposer 430 includes buffers 450 and interconnects 460. The interconnects 460 may be system-level electrostatic discharge (ESD) protection circuits.

[0023] Let us now turn Fig. 5. Yet another embodiment of an SOC architecture fabricated according to the partitioning method is discussed therein. The components of the SOC 500 are arranged according to the partitioning criteria and the stacking criteria. The components in each of the first stacks are the upper metal layers, namely at least one second metal layer 531 and at least one third metal layer 533. These higher-pitch metal layers are electrically connected by an interposer 530. The interposer 530 provides a common platform between the second and third metal layers 531, 533 of various components and to a first (front-side) redistribution layer (RDL) 535.

[0024] A substrate 520 is arranged on the back side of the interposer 530, and a second (back) redistribution layer 525 is formed in the substrate 520. A plurality of package pins 570 are arranged on the substrate 520. The electrical connection between the first and second redistribution layers 535, 525 is formed by substrate vias (TSVs) 523. Signal transmission from the front to the back side of the interposer 530 proceeds via the first redistribution layer 535, the substrate vias 523, the second redistribution layer 525, and the package pins 570.

[0025] The second stacks (or dies) 511, 513, and 515 comprise the lower metal layers, namely at least one first metal layer 517a, 517b, and 517c, respectively, in each of the second stacks 511, 513, and 515. The dies 511, 513, and 515 are arranged opposite the substrate 520, which is located on the backside of the interposer 530. The conductive means between the first stacks / interposer 530 and the second stacks / dies 511, 513, and 515 is realized by metal / oxide bonding. Specifically, a wafer-on-wafer technique is used in the SOC 500. As shown in Fig. As shown in Figure 5, a metal bond 540 is disposed between the first redistribution layer 535 and the first metal layer 517a. In other words, the interconnection between the die and the interposer extends from the first metal layer 517a through the metal bond 540 to the first redistribution layer 535. The bond may be a metal bond, a high-temperature oxide bond, or a metal-oxide hybrid bond. The first redistribution layer 535 is electrically connected in the substrate 520 to the second redistribution layer 525 through the substrate vias 523. The interposer 530 is a "lightly active" interposer and includes buffers 550 and interconnects 560. The interconnects 560 may be system-level electrostatic discharge (ESD) protection circuitry.

[0026] Let us now turn Fig. 6. Yet another embodiment of an SOC architecture fabricated according to the partitioning method is discussed therein. The components of the SOC 600 are arranged according to the partitioning criteria and the stacking criteria. The components in each of the first stacks are upper metal layers, including at least a second metal layer 631 and at least a third metal layer 633. These higher-pitch metal layers of different components are electrically connected by an interposer 630. The interposer 630 provides electrical connection between the second and third metal layers 631, 633 and to a first (front-side) redistribution layer (RDL) 635.

[0027] A substrate 620 is arranged on the back side of the interposer 630, and a plurality of package pins 670 are arranged on the front side of the interposer 630, opposite the substrate 620. This arrangement is feasible when the second stacks / dies are low-pin-count devices that require less space and therefore provide more space for the package pins on the front side of the interposer 630.

[0028] The second stacks (or dies) 611, 613, and 615 comprise the lower metal layers, namely at least one first metal layer 617a, 617b, and 617c, respectively. The conductive means between the first stacks / interposer 630 and the second stacks / dies 611, 613, and 615 is realized by metal / oxide bonding. As shown in Fig. As shown in Figure 6, a metal bond 640 is disposed between the first redistribution layer 635 and the first metal layer 617a. Signals from the dies 611, 613, and 615 travel through the first metal layer 617a and the metal bond 640 to the first redistribution layer 635 and via the common interposer 630 to the second and third metal layers 633, 631. The package terminal provides a path from the first redistribution layer 635 to the package pins 670 on the front side. In this embodiment, no substrate vias are present. The interposer 630 is a "lightly active" interposer and includes buffers 650 and interconnects 660. The interconnects 660 may be system-level electrostatic discharge (ESD) protection circuitry.

[0029] Let us now turn Fig.7. Yet another embodiment of an SOC architecture fabricated according to the partitioning method is discussed therein. The components of the SOC 700 are arranged according to the partitioning criteria and the stacking criteria. The components in each of the first stacks are upper metal layers, including at least a second metal layer 731 and at least a third metal layer 733. These higher-pitch metal layers of different components are electrically connected by an interposer 730. The interposer 730 provides electrical connection between the second and third metal layers 731, 733 and to a first (front-side) redistribution layer (RDL) 735.

[0030] A substrate 720 is arranged on the back side of the interposer 730, and a plurality of package pins 770 are arranged on the front side of the interposer 730, opposite the substrate 720. The second stacks (or dies) 711, 713, and 715 comprise the lower metal layers, namely at least one first metal layer 717a, 717b, and 717c, respectively. The conductive means between the first metal layers 717a, 717b, and 717c and the second metal layers 731 is realized by microbumps in the form of interlevel vias 740. The interlevel vias 740 extend through the thickness of the interposer 730, and an electrical connection can be established. Signals from 711, 713 and 715 travel through the first metal layers 717a, 717b and 717c, respectively, and the interlevel vias 740 to the second metal layer 731.The second metal layer 731 and the third metal layer 733 share an electrical connection through the interposer 730, and the package connection extends from the first redistribution layer 735 to the package pins 770 on the front of the interposer 730. The interposer 730 is a "lightly active" interposer and includes buffers 750 and wirings 760. The wirings 760 may be system-level electrostatic discharge (ESD) protection circuitry.

[0031] The zoning technique provides a cost-effective alternative to chips in advanced process nodes. Top metal layers, which have a larger pitch, do not scale well, and occupy a larger area, are sorted together. They share the interposer under the same process node. Temporarily removing the top metal layers from each sub-area alleviates routing congestion. Furthermore, similarly sized metal layers are grouped together, allowing the area layout to precisely match the components. Chip efficiency, performance, and utilization can be improved. Furthermore, because the top metal layers from different sub-areas are grouped and connected by an interposer, the number of required masks is reduced, thus also reducing overall costs.Blocks of diffused intellectual property (also called IP or macro-functional blocks) authorized to generate dated processes, for example, including processor cores, high-speed interfaces, and memory, can be configured and reused through the metal layers.

[0032] In one aspect of the present disclosure, a partitioning method includes sorting the plurality of components into a plurality of subregions according to a set of partitioning criteria and sorting the plurality of components of each subregion into a first stack and a second stack according to a set of stacking criteria, and the first stack includes a plurality of higher pitch metal layers.

[0033] In another aspect of the present disclosure, a method for manufacturing systems-on-chips (SOCs) having a plurality of components includes sorting the components into first stacks and second stacks according to a set of partitioning criteria and a set of stacking criteria. An interposer is formed for electrically connecting the first stacks. A redistribution layer is formed in the interposer. A conductive means is formed between the second stacks and the interposer. A substrate is applied to the interposer.

[0034] In yet another embodiment of the present disclosure, a system-on-chip having a plurality of components is provided. The system-on-chip comprises a plurality of sub-regions. Each of the sub-regions comprises a plurality of components sorted according to a set of partitioning criteria, and each of the sub-regions is sorted into a first stack and a second stack according to a set of stacking criteria. An interposer is arranged on the second stack, establishing an electrical connection between the components of the first stack. At least one conductive element is arranged between the interposer and the second stacks.

[0035] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the present disclosure. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same benefits of the embodiments presented herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions, and modifications thereto without departing from the spirit and scope of the present disclosure.

Claims

[1] A method (100) for dividing a plurality of components of a system-on-chip, SOC (300, 400), comprising: Sorting the plurality of components into a plurality of sub-areas (A, B, C) according to a set of partitioning criteria; Sorting the plurality of components of each sub-area into a first stack (A1) and a plurality of adjacent second stacks (A2, 311, 313, 315, 411, 413, 415) according to a set of stacking criteria, wherein the first stack comprises a plurality of higher pitch metal layers (331, 333) and the second stacks comprise a plurality of lower pitch metal layers, wherein the partitioning criteria comprise size, power and speed of the component and the stacking criteria comprise a pitch of a metal layer (331, 333, 431, 433); Forming conductive means (340) between the components of each of the first stacks by an interposer (330, 430); Forming conductive means (440) between the interposer (330, 440) and the components of the second stacks (311, 313, 315, 411, 413, 415). [2] The method of claim 1, further comprising: Forming a substrate (320) on the second stacks (311, 313, 315); Forming a plurality of metal layers (331, 333) and at least one redistribution layer (335) in the first stacks; Routing the metal layers (331, 333) and the redistribution layer (335) in the first stack by the interposer (330); and Forming a substrate via, TSV (340), between the interposer (330) and the second stacks (311, 313, 315). [3] The method of claim 1, wherein forming an electrical connection in each of the first stacks by the interposer (430) further comprises: Forming a plurality of metal layers (431, 433) and at least one first redistribution layer (435) in the first stacks; Routing the metal layers (431, 433) and the first redistribution layer (435) through the interposer (430); and forming a substrate (420) on the interposer (430). [4] The method of claim 3, further comprising: Forming a second redistribution layer (425) in the substrate (420); Forming at least one substrate via (423) connecting the first redistribution layers (435) in the interposer (430) and the second redistribution layer (425) in the substrate (420); Forming a plurality of inter-level vias (440) that establish electrical connections between the first and second stacks; and Forming package pins (470) on the substrate (420). [5] The method of claim 3 or 4, further comprising: Forming a second redistribution layer (425) in the substrate (420); Forming at least one substrate via (423) connecting the first and second redistribution layers (435, 425) in the interposer (430) and the substrate (420); Forming a plurality of metal interconnects (417a, 417b, 417c) that establish electrical connections between the first and second stacks; and Forming package pins (470) on the substrate (420). [6] The method of claim 3, further comprising: Forming metal connections (640) between the second stacks (611, 613, 615) and the first redistribution layer (635) in the interposer (630); and Forming package pins (670) on the interposer (630). [7] A method according to any one of claims 1 or 2, further comprising: Forming substrate vias (340) between the second stacks (311) and the metal layers (331, 333) in the first stack; and Forming package pins (370) on the interposer. [8] A method (100) for manufacturing a system-on-chip, SOC (300), having a plurality of components, comprising: Sorting the components according to a set of partitioning criteria and a set of stacking criteria into a plurality of first stacks and a plurality of adjacent second stacks (311, 313, 315); Forming an interposer (330) for electrically connecting the first stacks; Forming a redistribution layer (335) in the interposer (330); Forming conductive means (317a, 317b, 317c) between the second stacks (311, 313, 315) and the interposer (330); and Applying a substrate (320) on the interposer (330), wherein the second stacks (311, 313, 315) are arranged on the substrate (320). [9] The method of claim 7, wherein the partitioning criteria include size, power, and speed of the component and the stacking criteria include a pitch of a metal layer (331, 333). [10] The method of claim 7 or 8, wherein sorting the components according to a set of splitting criteria and a set of stacking criteria further comprises: Sorting the plurality of components into a plurality of sub-areas (A, B, C) according to the set of partitioning criteria; and Sorting the plurality of components of each sub-region into a first stack and a second stack according to the set of stacking criteria, wherein the first stack comprises a plurality of higher pitch metal layers (A1) (331, 333). [11] The method of claim 9, wherein the substrate (320) is disposed between the interposer (330) and the second stacks (311, 313, 315) and the conductive means is a substrate via (340). [12] System-on-chip (300) with a plurality of components, comprising: a plurality of sub-areas (A, B, C), each of the sub-areas comprising a plurality of components sorted according to a set of partitioning criteria, each of the sub-areas being sorted into a first stack and a plurality of adjacent second stacks (311, 313, 315) according to a set of stacking criteria; an interposer (330) arranged on the second stacks (311, 313, 315) and establishing an electrical connection between the components of the first stack; and at least one conductive element arranged between the interposer (330) and the second stacks (311), wherein the interposer (330) comprises a substrate (320) arranged between the interposer and the second stack (311), and the conductive elements are substrate vias (340) extending through the substrate. [13] The system-on-chip of claim 12, wherein the partitioning criteria include size, power consumption, and speed, and the stacking criteria include a pitch of a metal layer (331, 333).

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