Semiconductor device

Abstract

Semiconductor device comprising the following: a channel layer (CHL) provided on a substrate (100), wherein the channel layer (CHL) has a two-dimensional atomic layer made of a first material; and a source / drain layer (SDL) provided on the substrate (100), wherein the source / drain layer (SDL) comprises a second material, where the first material is one of phosphorus allotropes, the second material of one of carbon allotropes, and the channel layer (CHL) and the source / drain layer (SDL) are connected to each other by covalent bonds between the first and second materials, and wherein the channel layer (CHL) extends in one direction perpendicular to an upper surface of the substrate (100).

Description

BACKGROUND

[0001] The present disclosure relates to a field-effect transistor and a semiconductor device comprising the same, and in particular to a field-effect transistor in which a channel layer with a two-dimensional atomic layer is provided, and a semiconductor device comprising the same.

[0002] Due to their small size, multifunctionality, and / or low cost, semiconductor devices are used throughout the electronics industry. Semiconductor devices can be classified into storage devices for storing data, logic devices for processing data, and hybrid devices that incorporate both storage and logic elements. To meet the increasing demand for electronic devices with high speed and / or low power consumption, it is advantageous to develop semiconductor devices with high reliability, high performance, and / or multiple functions. To achieve this, the complexity and / or integration density of semiconductor devices is increased.

[0003] The paper “Phosphorene FETs - Promising Transistors based on a few Layers of Phosphorus Atoms” by Xiong, K. et al., published in the 2015 IEEE MTT-S International Microwave Workshop Series on Advanced Materials and Processes for RF and THz Applications (IMWS-AMP), July 1-3, 2015, provides an overview of the development and progress of phosphorene FETs and their advantageous properties. However, the paper also indicates that further improvements are needed for high-speed and high-frequency applications.

[0004] Document US 2015 / 0303299A1 relates to a semiconductor device with an ultrathin body and a method for fabricating such a device. A dielectric layer is formed on a substrate. A three-dimensional structure in the form of a trench is formed within the dielectric layer. A two-dimensional layer of graphene, transition metal dichalcogenides (TMDs), or boron nitride (BN) is formed over the sidewalls of the structure. A gate dielectric layer is formed over the two-dimensional layer, and a gate electrode is formed over the gate dielectric layer. Source / drain contacts are electrically connected to the two-dimensional layer on opposite sides of the gate electrode. SUMMARY

[0005] One objective of the invention is to provide semiconductor devices with improved electrical characteristics.

[0006] This problem is solved by semiconductor devices according to claim 1. Advantageous further developments are the subject of the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Exemplary embodiments will be more clearly understood from the following brief description together with the accompanying drawings, in which: Fig. 1A is a perspective view illustrating a semiconductor device; Fig. 2B an enlarged view of section “M” of the Fig. 1A is; Fig. 2 is a perspective view illustrating a semiconductor device; Fig. 3 is a sectional view, taken along a line II' of the Fig. 2; Fig. 4 is a perspective view illustrating a semiconductor device; Fig. 5 is a sectional view, taken along a line II' of the Fig. 4; Fig. 6A is a perspective view illustrating a semiconductor device; Fig. 6B an enlarged view of section “N” of the Fig. 6A is; Fig. 7 is a sectional view illustrating a semiconductor device; Fig. 8 is a sectional view illustrating a semiconductor device; Fig. 9 is a top view illustrating a semiconductor device; Fig. 10 is a sectional view, taken along a line II' of the Fig. 9; Fig. 11 is a perspective view illustrating a semiconductor device according to some exemplary embodiments; Fig. 12 is a top view illustrating a semiconductor device according to some exemplary embodiments; Fig. 13A, Fig. 13B and Fig. 13C Sectional views are taken along lines I-I', II-II' and III-III' of each of the Fig. 12; Fig. 14 is a top view illustrating a semiconductor device according to some exemplary embodiments; Fig. 15A and Fig. 15B Sectional views are taken along lines II' and II-II' of the Fig. 14; Fig. 16 is a perspective view illustrating a semiconductor device according to some exemplary embodiments; Fig. 17 is a top view illustrating a semiconductor device according to some exemplary embodiments; Fig. 18A and Fig. 18B Sectional views are taken along II' and II-II' of each of the Fig. 17; Fig. 19 is a perspective view illustrating a semiconductor device according to some exemplary embodiments; Fig. 20 is a perspective view illustrating a semiconductor device according to some exemplary embodiments; Fig. 21 is a perspective view illustrating a semiconductor device according to some exemplary embodiments; Fig. Sectional views 22A to 22F illustrate a method for manufacturing a semiconductor device according to some exemplary embodiments; Fig. 23 is a top view illustrating a light-sensing device; and Fig. 24 is a sectional view, taken along a line II' of the Fig. 23.

[0008] Fig. Figures 1 to 10, 23 and 24 are examples to illustrate various aspects of the invention, which, however, do not exhibit all features of an embodiment according to the invention. DETAILED DESCRIPTION

[0009] Fig. Figure 1A is a perspective view illustrating a semiconductor device. Fig. 1B is an enlarged view of section “M” of the Fig. 1A.

[0010] Referring to the Fig. 1A and Fig. 1B A field-effect transistor, comprising an active layer AL and a gate electrode GE, can be provided on a substrate 100. The substrate 100 can be an insulating substrate containing an insulating material. As an example, the substrate 100 can be formed from, or comprise at least one of, glass, sapphire, quartz, organic polymers, silicon dioxide, and silicon nitride.

[0011] The active layer AL can comprise source / drain layers SDL and a channel layer CHL, which is arranged between the source / drain layers SDL. The channel layer CHL has a two-dimensional atomic layer made of a first material, and each of the source / drain layers SDL can have a two-dimensional atomic layer made of a second material. In some exemplary embodiments, the channel layer CHL can consist of the first material, and each of the source / drain layers SDL can consist of the second material. In embodiments, the first and second materials are different materials or contain different atoms.

[0012] The two-dimensional atomic layer can be a single atomic layer in which atoms are connected to each other by covalent bonds. Within this single atomic layer, the atoms can be arranged to form an essentially two-dimensional configuration. Both the first and second materials can have a single atomic layer or multiple layered atomic layers. In other words, both the first and second materials can be configured to have a single-layer or a multi-layer structure. In the case of a multi-layer structure, the structure can contain from two to approximately 100 layered atomic layers. These layered atomic layers can be coupled to each other by van der Waals forces.As one example, each of the channel layer CHL and the source / drain layer SDL can be a single atomic layer. As another example, each of the channel layer CHL and the source / drain layer SDL can be composed of multiple atomic layers.

[0013] Each of the first and second materials can be electrically conductive. This means that an electron mobility and a hole mobility can be defined for each of the first and second materials.

[0014] The first material can be phosphorus. In some exemplary embodiments, the first material can be phosphorus, which is a semiconductor material. In embodiments, the first material is or comprises allotropes of phosphorus (P), which are provided in the form of two-dimensional atomic layers. The phosphorus can have a similar or higher electron and / or hole mobility than silicon, and a leakage current that is lower than that of silicon, and therefore the phosphorus can be used as a channel layer of the field-effect transistor.

[0015] The phosphorus atoms in the phosphorus can be arranged in various configurations within the two-dimensional atomic layer. For example, the phosphorus can be arranged in an armchair structure, a diagonal structure, a zigzag structure, or any combination thereof. The energy bandgap of the phosphorus can be modified depending on its atomic arrangement. Phosphorus in a diagonal structure can have a larger energy bandgap than phosphorus in an armchair structure, and phosphorus in a zigzag structure can have a larger energy bandgap than phosphorus in a diagonal structure. Consequently, by changing the structure of the phosphorus in the channel layer CHL, it is possible to modify the threshold voltage of the field-effect transistor.As an example, for a field-effect transistor with a low threshold voltage, the phosphorene of the channel layer can be formed to create an armchair structure. In contrast, for a field-effect transistor with a high threshold voltage, the phosphorene of the channel layer can be formed as CHL to create a zigzag structure.

[0016] The threshold voltage of the field-effect transistor can be changed by other methods. For example, the threshold voltage of the field-effect transistor can be changed by adjusting the number of phosphorus atom layers that form the first material.

[0017] The second material can be graphene. In some exemplary embodiments, the second material can be graphene, which is one of the metal-like materials with high electrical conductivity. In other embodiments, the second material is or comprises allotropes of carbon (C), provided in the form of a two-dimensional atomic layer. Since the energy bandgap of graphene is essentially zero, in some cases graphene may not be suitable for the channel layer of the field-effect transistor. However, since graphene has very high electron and / or hole mobility, it may be more suitable for the source / drain regions of the field-effect transistor. The graphene can be used to compensate for the relatively low electron mobility of the phosphor for the channel layer.

[0018] The first and second materials can be coupled to each other by covalent bonds or by van der Waals forces. Accordingly, the channel layer (CHL) can be directly connected to the source / drain layers (SDL). In the case where the first and second materials are coupled to each other by covalent bonds, the electrical conductivity of the resulting structure can be high compared to that resulting from van der Waals forces. This high electrical conductivity from the covalent bonds can make it possible to realize the field-effect transistor with improved electrical characteristics.

[0019] Referring back to Fig. 1B In the case where the first and second materials are each made of phosphorus and graphene, the first and second materials can be coupled to each other by covalent bonds 103. Phosphorus atoms 101 of the phosphorus can be coupled to each other by covalent bonds 103, carbon atoms 105 of the graphene can be coupled to each other by covalent bonds 103, and therefore covalent bonds 103 can be formed between the phosphorus atoms 101 and carbon atoms 105 at an interface between the phosphorus and the graphene.

[0020] Referring back to Fig. 1A The gate electrode GE can be arranged on the channel layer CHL. A dielectric gate layer GI can be arranged between the gate electrode GE and the channel layer CHL. The gate electrode GE can comprise at least one conductive material. For example, the gate electrode GE can be formed from or comprise at least one or more doped semiconductors (e.g., doped silicon, doped silicon-germanium, doped germanium, etc.), metals (e.g., titanium, tantalum, tungsten, aluminum, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), or metal-semiconductor compounds (e.g., tungsten silicide, cobalt silicide, nickel silicide, titanium silicide, etc.). The dielectric gate layer GI can comprise at least one dielectric material with a high k-value.As an example, the dielectric gate layer GI can be formed from or comprise at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc cniobate.

[0021] Fig. Figure 2 is a perspective view illustrating a semiconductor device. Fig. 3 is a sectional view, taken along line II' of the Fig. 2. In the following description, an element that was previously referred to with reference to the Fig. 1A and Fig. 1B is described by a similar or identical reference symbol without repeating an overlapping description of it.

[0022] Referring to the Fig. 2 and Fig. 3. A semiconductor device which includes the field-effect transistor of the Fig. 1A is provided. In some exemplary embodiments, the semiconductor device may include logic cells configured to process data, and the field-effect transistor may be used to implement the logic cells.

[0023] In detail, active layers AL can be provided on a substrate 100. For example, it shows Fig. Two active layers AL are arranged side-by-side on substrate 100. This is just one example, and any number of active layers AL can be provided. The active layers AL can be arranged in a first direction D1, which is parallel to an upper surface of substrate 100. Each of the active layers AL can have source / drain layers SDL and a channel layer CHL in between.

[0024] A gate electrode GE can be provided to cross a plurality of the active layers AL. In some exemplary embodiments, the gate electrode GE can be provided to cross a plurality of the channel layers CHL. The dielectric gate layer GI can be positioned between the gate electrode GE and the channel layers CHL. The gate electrode GE and the dielectric gate layer GI can extend in the first direction.

[0025] Contact points 111 can be provided on both sides of the gate electrode GE, as shown in Fig. Figure 2 shows that each of the contact points 111 can be provided to cross at least one of the source / drain layers SDL on the side where the contact point 111 is provided. Each of the contact points 111 can be electrically connected to the at least one of the source / drain layers SDL. As an example, each of the contact points 111 can extend in the first direction D1 and can jointly cross a plurality of the source / drain layers SDL. For example, the contact point 111 on the right side of the gate electrode GE crosses Fig. 2 three source-drain layers SDL, and the contact point 111 on the left side of the gate electrode GE in Fig. 2 crosses three source / drain layers SDL. The majority of the source / drain layers SDL can be electrically connected to each other by a corresponding contact point 111. In certain exemplary embodiments, each of the contact points 111 can be provided on a corresponding source / drain layer SDL, as shown in Fig. 4 is shown.

[0026] Contacts 113 can be arranged on the contact points 111. An intermediate insulating layer 110 can be provided to cover the active layers AL, the gate electrode GE, the contact points 111 and the contacts 113, as shown in Fig. Figure 3 shows that the contacts 113 can be provided to have upper surfaces that are essentially coplanar with an upper surface of the intermediate insulating layer 110. Interconnecting lines 121 can be provided on the intermediate insulating layer 110 and can each be electrically connected to the contacts 113. In other words, the connecting lines 121 can be provided to allow electrical signals to be applied to the source / drain layers (SDL).

[0027] The contact points 111, the contacts 113, and the connecting leads 121 can each comprise at least one conductive material (for example, doped semiconductors, metals, conductive metal nitrides, or metal-semiconductor compounds). The intermediate insulating layer 110 can be formed from, or comprise at least one silicon oxide layer, one silicon nitride layer, and one silicon oxynitride layer.

[0028] Fig. Figure 4 is a perspective view illustrating a semiconductor connection. Fig. 5 is a sectional view, taken along line II' of the Fig. 4. In the following description, an element that was previously referred to with reference to the Fig. 1A, Fig. 1B, Fig. 2 and Fig. 3, can be identified by a similar or identical reference symbol without repeating an overlapping description of it.

[0029] Referring to the Fig. 4 and Fig. 5 can be a semiconductor device which includes the field-effect transistor of the Fig. 1A is provided. In some exemplary embodiments, the semiconductor device may include memory cells configured to store data, and the field-effect transistor may be used to implement the memory cells.

[0030] In detail, active layers AL can be provided on a substrate 100. The active layers AL can be arranged in a first direction D1, and each of the active layers AL can have a plurality of source / drain layers SDL and a plurality of channel layers CHL. For example, illustrated Fig. 4 three active AL layers. However, this is just an example and any number of active AL layers can be provided.

[0031] Gate electrodes GE can be arranged to cross the active layers AL. Each of the gate electrodes GE can be provided to cross a plurality of the channel layers CHL, which are arranged in the first direction D1. The electrical gate layers GI can be positioned between the gate electrodes GE and the channel layers CHL.

[0032] A source line SL can be provided on the source / drain layer SDL, which is located between a pair of channel layers CHL. The source line SL can extend in the first direction D1 and can cross a plurality of the source / drain layers SDL that are arranged in the first direction D1. The source line SL can connect to a source contact point 131, which is in direct contact with the source / drain layers SDL, and to a conductive line 133 (see Fig. 5) which is provided at the source contact point 131. The source contact point 131 and the conductive conductor 133 can be formed from or comprise at least one conductive material (for example, doped semiconductors, metals, conductive metal nitrides, or metal-semiconductor compounds). An intermediate insulating layer 110 can be provided on the substrate 100 and can be formed from or comprise at least one silicon oxide layer, one silicon nitride layer, and one silicon oxynitride layer.

[0033] Contact points 111 can each be located on the source / drain layers SDL, which are provided on opposite sides of each of the active layers AL, as shown in Fig. As shown in Figure 4, contacts 113 can each be provided on the contact points 111. Data storage elements DS can be provided on the intermediate insulating layers 110 and can each be electrically connected to the contacts 113. The data storage elements DS can be storage elements, each of which is configured to store data. Here, field-effect transistors having active layers AL and gate electrodes GE can be used as switching elements. In some exemplary embodiments, each of the data storage elements DS can be a capacitor, a magnetic tunnel contact structure, a phase-changing material, and a storage element with a variable resistance material.

[0034] Fig. Figure 6A is a perspective view illustrating a semiconductor device. Fig. 6B is an enlarged view of section “N” of the Fig. 6A. In the following description, an element that was previously referred to with reference to the Fig. 1A and Fig. 1B is described by a similar or identical reference symbol without repeating an overlapping description thereof.

[0035] Referring to the Fig. 6A and Fig. 6B can be a field-effect transistor comprising an active layer AL and a gate electrode GE on a substrate 100. The active layer AL can have source / drain layers SDL, each of which has a planar section P1 and a columnar section P2. The planar section P1 can have a two-dimensional structure which may include a second material. The columnar sections P2 can each be arranged on the planar sections P1 and can have a longitudinal axis parallel to a third direction D3. The third direction D3 can be perpendicular to an upper surface of the substrate 100. The columnar section P2 can be referred to as the junction 111 and the contact 113, which, with reference to the Fig. 2 and Fig. 3 are described, function.

[0036] Each of the column sections P2 can have a three-dimensional atomic layer, which may be formed from a third material. The third material can be a metal-like material, a semiconductor material with a finite energy bandgap, etc. The third and second materials can be the same material or different materials. As an example, the third material can have at least one carbon nanotube. In some exemplary embodiments, the third material can have at least one metallic carbon nanotube.

[0037] The second and third materials can be coupled to each other by covalent bonds. Consequently, each planar section P1 and corresponding column section P2 can be directly connected, thus serving as a source / drain region of the field-effect transistor. Because the second and third materials are coupled to each other by covalent bonds, the resulting structure can have high electrical and thermal conductivity. For example, compared to the case where contact point 111 and contact 113, which are connected with reference to the Fig. 2 and Fig. As described in section 3, it is possible to use the electrical and thermal characteristics (e.g., resistance and heat dissipation) of the field-effect transistor to improve them. Referring back to Fig. 6B, the planar section P1 (for example made of the second material such as graphene) and the column section P2 (for example made of the third material such as carbon nanotubes) can be coupled to each other by covalent bonds.

[0038] Fig. Figure 7 is a sectional view illustrating a semiconductor device. In the following description, an element previously referred to in the Fig. 2, Fig. 3, Fig. 6A and Fig. 6B is described by a similar or identical reference symbol without repeating an overlapping description of it.

[0039] Referring to Fig. 7 can be a semiconductor device which includes the field-effect transistor of the Fig. 6A is provided. In some exemplary embodiments, the semiconductor device may include logic cells configured to process data, and the field-effect transistor may be used to implement the logic cells.

[0040] An intermediate insulating layer 110 can be provided on a substrate 100 to cover an active layer AL and a gate electrode GE. The upper surfaces of column sections P2 of the source / drain layers SDL can be essentially coplanar with the upper surface of the intermediate insulating layer 110. Interconnect lines 121 can be provided on the intermediate insulating layer 110 and can each be electrically connected to the column sections P2. In other words, the interconnect lines 121 can be provided to allow electrical signals to be applied to the source / drain layers SDL.

[0041] Fig. Figure 8 is a sectional view illustrating a semiconductor device. In the following description, an element referred to above can be described as follows: Fig. 4, Fig. 5, Fig. 6A and Fig. 6B is described by a similar or identical reference symbol without repeating an overlapping description of it.

[0042] Referring to Fig. 8 can be a semiconductor device which includes the field-effect transistor of the Fig. 6A is provided. In some exemplary embodiments, the semiconductor device may include memory cells configured to store data, and the field-effect transistor may be used to implement the memory cells.

[0043] An intermediate insulating layer 110 can be provided on a substrate 100 to cover an active layer AL, a source conductor SL, and a gate electrode GE. Each of the source / drain layers SDL, which are provided at opposite ends of the active layer AL, can have a column section P2. The column sections P2 can be provided to have top surfaces that are substantially coplanar with those of the intermediate insulating layer 110. Data storage elements DS can be provided on the intermediate insulating layer 110 and can each be electrically connected to the column sections P2.

[0044] Although not shown, the source / drain layer SDL, which is placed between a pair of channel layers CHL, can be provided to include the column section P2. In this case, the source line SL can be omitted. A source intermediate line can be provided on the intermediate insulating layer 110 and can be electrically connected to the column section P2.

[0045] Fig. Figure 9 is a top view showing a semiconductor device according to some exemplary embodiments. Fig. 10 is a sectional view, taken along a line II' of the Fig. 9. In the following description, an element that was previously referred to with reference to the Fig. 6A and Fig. 6B is described by a similar or identical reference symbol without repeating an overlapping description of it.

[0046] Referring to the Fig. 9 and Fig. 10 can be a semiconductor device which includes the field-effect transistor of the Fig. 6A is provided. In some exemplary embodiments, the semiconductor device may be a FLASH memory device.

[0047] A stack of vertically stacked field-effect transistors (SS) can be provided on a substrate 100. In some exemplary embodiments, a plurality of SS stacks, spaced apart from one another in a first direction D1, can be provided on the substrate 100. For the sake of simplicity, however, the following description will refer to an example in which the SS stack is provided individually.

[0048] As in Fig. As shown in Figure 10, the SS stack can have active layers AL, which are stacked on substrate 100 and vertically spaced apart. The active layers AL can be used as the active regions of the field-effect transistors that form the SS stack. Each of the active layers AL can have source / drain layers SDL and a channel layer CHL in between.

[0049] The first to fourth intermediate insulating layers 110, 120, 130, and 140 can be stacked or layered vertically on the substrate 100. The lowest of the active layers AL can be positioned between the substrate 100 and the first intermediate insulating layer 110. Each of the remaining active layers AL can be positioned between a corresponding pair of the first to fourth intermediate insulating layers 110, 120, 130, and 140.

[0050] Each of the source / drain layers (SDL) can have a planar section P1 for each of the active layers AL and a columnar section P2. Each columnar section P2 of the source / drain layers (SDL) can be provided in one of the first to fourth intermediate insulating layers 110, 120, 130, and 140, respectively. Each of the source / drain layers (SDL) can be provided such that the columnar section P2 is directly connected to another source / drain layer (SDL) positioned adjacent to it in a vertical direction. The columnar section P2 and the other source / drain layer (SDL) can be coupled to each other by covalent bonds. In other words, the source / drain layers (SDL) that are stacked vertically on one side of the stack (SS) can be electrically connected to each other by their columnar sections P2.

[0051] The SS stack can include floating gates FG, which are vertically stacked and spaced apart, and gate electrodes GE, which are also vertically stacked and spaced apart. Each floating gate FG can be provided in one of the first four intermediate insulating layers 110, 120, 130, and 140, respectively, and each gate electrode GE can be provided in one of the first four intermediate insulating layers 110, 120, 130, and 140, respectively. The floating gate FG and the gate electrode GE can be positioned on one of the channel layers CHL, respectively. The floating gates FG can be configured to store electrical charges. For example, the floating gates FG can be made of or comprise a doped semiconductor material (e.g., doped silicon, doped silicon-germanium, doped germanium, etc.).The gate electrodes GE can serve as word lines WL of a FLASH storage device.

[0052] A plurality of Floating Gates FG can be provided in each of the first through fourth intermediate insulation layers 110, 120, 130, and 140. Viewed from a top view, the Floating Gates FG can be arranged on the same plane to overlap with the channel layers CHL on the same plane. In other words, the Floating Gates FG can be arranged on the same plane along the channel layers CHL or in the first direction D1. The Floating Gates FG on the same plane can be laterally spaced from each other.

[0053] In contrast, each of the gate electrodes GE can extend in the first direction D1. For example, in each of the first to fourth intermediate insulating layers 110, 120, 130 and 140, each of the gate electrodes GE can be provided to cross the channel layers CHL and the floating gates FG on the same plane.

[0054] First dielectric gate layers GI1 can each be arranged between the channel layers CHL and the floating gates FG. Second dielectric gate layers GI2 can each be arranged between the floating gates FG and the gate electrodes GE. Each of the first dielectric gate layers GI1 can have a tunnel insulating layer (for example, a silicon oxide layer). Each of the second dielectric gate layers GI2 can have a barrier insulating layer. For example, the barrier insulating layer can be formed from materials whose dielectric constants are higher than those of the tunnel insulating layer. In some exemplary embodiments, the barrier insulating layer can have at least one ONO layer and a dielectric layer with a high k (for example, an aluminum oxide layer, a hafnium oxide layer, a hafnium aluminum oxide layer, or a zirconium oxide layer).Here, the ONO layer can refer to a stack of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer.

[0055] A first to fourth insulating layer 115, 125, 135, 145 can be provided on each of the gate electrodes GE. Each of the first to fourth insulating layers 115, 125, 135, and 145 can be configured to allow the underlying gate electrode to be electrically isolated from the active layer AL on top of it. Each of the first to fourth intermediate insulating layers 110, 120, 130, and 140, and of the first to fourth insulating layers 115, 125, 135, 145, can be formed from, or comprise at least one of, a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0056] A source line SL and a bit line BL can be provided on the fourth insulating layer 145. The source line SL can be electrically connected to the source / drain layers SDL on one side of the stack SS. The bit line BL can be electrically connected to the source / drain layers SDL on the opposite side of the stack SS. In other words, the source line SL can serve as a common source for the field-effect transistors of the stack SS, and the bit line BL can serve as a common drain for the field-effect transistors of the stack SS.

[0057] In the semiconductor device according to the present embodiment, the active layer AL, which has a substantially two-dimensional or planar structure, can be used as an active region of a FET. This makes it possible to provide an additional active layer AL on the intermediate insulating layer 110, which covers the FET, and consequently, to easily implement an additional FET on top of the existing FET. In contrast, for a conventional silicon-based semiconductor device, a silicon layer or silicon structure with a relatively large thickness can be used as an active region, and therefore it is difficult to implement a multilayer FET structure.In other words, according to some exemplary embodiments, it is possible to more easily realize the multilayer FET structure, which has a plurality of vertically stacked FETs, and therefore the semiconductor device can be manufactured to have an increased integration density.

[0058] Fig. Figure 11 is a perspective view illustrating a semiconductor device according to some exemplary embodiments. In the following description of the present embodiment, an element previously described with reference to the Fig. 1A and Fig. 1B is described by a similar or identical reference symbol without repeating an overlapping description of it.

[0059] Referring to Fig. 11. A field-effect transistor, comprising an active layer AL and a gate electrode GE, can be provided on a substrate 100. The active layer AL can be provided such that one of its normal directions is perpendicular to an upper surface of the substrate 100 (i.e., in a third direction D3). In other words, the active layer can be a fin-shaped structure projecting perpendicularly from the substrate 100. Here, a channel layer CHL can have surfaces opposite the active layer AL, which are exposed above the substrate 100.

[0060] The gate electrode GE can be positioned to extend in a first direction D1 and to cross the channel layer CHL. In some exemplary embodiments, the gate electrode GE can be positioned to face both opposite surfaces of the channel layer CHL. In other words, this structure can make it possible to realize a double-gate effect, which is equivalent to providing two gate electrodes on and below a channel region.

[0061] For a FinFET with a conventional silicon fin channel structure, the top surface of the channel structure is a two-dimensional surface that can serve as a path for leakage current. However, for the semiconductor device according to the present exemplary embodiment, the top surface of the channel layer CHL is shaped like a one-dimensional line and not like a two-dimensional surface, thus preventing the leakage current that can occur in the conventional silicon FinFET.

[0062] Fig. Figure 12 is a top view illustrating a semiconductor device according to some exemplary embodiments. Fig. 13A, Fig. 13B and Fig. 13C are sectional views, taken along lines I-I', II-II' and III-III' of each of the Fig. 12. In the following description, an element that was previously referred to with reference to the Fig. 2, Fig. 3 and Fig. 11, can be identified by a similar or identical reference symbol without repeating an overlapping description of it.

[0063] Referring to the Fig. 12 and 13A to 13C can be a semiconductor device which uses the field-effect transistor of the Fig. 11A is provided. In some exemplary embodiments, the semiconductor device may include logic cells configured to process data, and the field-effect transistor may be used to implement the logic cells.

[0064] Fin-shaped active layers AL can be provided on a substrate 100 to extend orthogonally to the substrate 100 in a third direction D3, and to be arranged on the substrate 100 in a first direction D1. Referring to Fig. 12. The active layers AL can be provided to be spaced apart from each other by at least two different distances in the first direction D1. For example, in the exemplary embodiment described in Fig. Figure 12 shows three groups of three active layers AL. The three active layers AL of each group are spaced apart by a distance d1, and the groups of active layers AL are spaced apart by a distance d2. The distance d2 can be larger than the distance d1. However, this is only an example, and there can be more or fewer than three active layers AL per group, and there can be more or fewer than three groups. Similarly, the example of Fig. 12. Three active layers AL in each group, uniformly spaced by the distance d1. However, this is only an example, and the active layers AL can be spaced by different distances. Similarly, the groups of active layers AL, which are in Fig. Figure 12 shows the layers uniformly spaced by the distance d2. However, the group of active layers AL can be spaced by different distances. The active layers AL can extend in a second direction D2, which intersects the first direction D1, and be parallel to each other.

[0065] Gate electrodes GE can be provided to jointly cross channel layers CHL of the active layers AL. The gate electrodes GE can extend in the first direction D1 and can be parallel to each other. The gate electrodes GE can be spaced apart from each other in the second direction D2.

[0066] Contact points 111 can be provided to cover source / drain layers (SDL) of the active layers (AL). Each contact point 111 can be provided to jointly cover the source / drain layers (SDL) that are adjacent to each other in the first direction (D1). Contacts 113 can be provided at each contact point 111.

[0067] Intermediate connecting lines 121 (see Fig. 13A) can be provided on an intermediate insulating layer 110 on the substrate. The intermediate connecting lines 121 can each be electrically connected to the contacts 113. In other words, the intermediate connecting lines 121 can be provided to allow electrical signals to be applied to the source / drain layers SDL.

[0068] Fig. Figure 14 is a top view illustrating a semiconductor device according to some exemplary embodiments. Fig. 15A and Fig. 15B are sectional views taken along lines II' and II-II' of the Fig. 14 each. In the following description, an element which is referred to above with reference to the Fig. 4, Fig. 5 and Fig. 11, can be identified by a similar or identical reference symbol without repeating an overlapping description thereof.

[0069] Referring to the Fig. 14, Fig. 15A and Fig. 15B can be a semiconductor device which includes the field-effect transistor of the Fig. 11. In some exemplary embodiments, the semiconductor device may include memory cells configured to store data, and the field-effect transistor may be used to implement the memory cells.

[0070] Fin-shaped active layers AL can be provided on a substrate 100 to extend orthogonally to the substrate 100 in a third direction D3 and to be arranged on the substrate 100 in a first direction D1. The active layers AL can extend in a second direction D2, which intersects the first direction D1, and can be parallel to each other.

[0071] Gate electrodes GE can be provided to jointly cross channel layers CHL of the active layers AL. The gate electrodes GE can extend in the first direction D1 and can be parallel to each other. A source conductor SL can be provided between a pair of gate electrodes GE to extend in the first direction D1 and to jointly cross source / drain layers SDL of the active layers AL. The source conductor SL can be provided to directly cover the source / drain layers SDL and can be electrically connected to the source / drain layers SDL.

[0072] Contact points 111 can be provided to cover the source / drain layers SDL, which are positioned at opposite ends of each of the active layers AL. Contacts 113 can be provided on each of the pads 111.

[0073] Data storage elements DS can be provided on an intermediate insulating layer 110 on the substrate 100, and the data storage elements DS can each be electrically connected to the contacts 113.

[0074] Fig. Figure 16 is a perspective view illustrating a semiconductor device according to some exemplary embodiments. In the following description, an element previously referred to in Fig. 11, can be identified by a similar or identical reference symbol without repeating an overlapping description of it.

[0075] Referring to Fig. 16. A plurality of active layers AL can be provided on a substrate 100 and can be arranged in a first direction D1. Each of the active layers AL can have a fin-shaped channel layer CHL, which extends orthogonally to the substrate 100 in a third direction D3, and source / drain layers SDL on both sides of the channel layer CHL.

[0076] Each of the source / drain layers (SDL) can be configured to have essentially the same characteristics as the column section P2, which was described above with reference to the Fig. 6A and Fig. 6B is described. In other words, the planar sections P1 in the source / drain layer SDL may be omitted, which are described above with reference to the Fig. 6A and Fig. As described in Figure 6B, the source / drain layer (SDL) can be directly connected to the active layer (AL) via covalent bonds. For example, the source / drain layer (SDL) can be a carbon nanotube.

[0077] A gate electrode GE can be provided to extend on substrate 100 in the first direction D1 and along the channel layers DHL. The gate electrode GE can have sections positioned between the channel layers CHL. For example, the sections of the gate electrode GE can be provided to face opposite surfaces of the channel layer CHL.

[0078] Fig. Figure 17 is a top view illustrating a semiconductor device according to some exemplary embodiments. Fig. 18A and Fig. 18B are sectional views taken along lines II' and II-II' of the Fig. 17 each. In the following description, an element that was previously referred to with reference to the Fig. Items described in sections 13A to 13C and 16 can be identified by a similar or identical reference numeral without repeating an overlapping description thereof.

[0079] Referring to the Fig. 17, Fig. 18A and Fig. 18B can be a semiconductor device which includes the field-effect transistor of the Fig. 16. In some exemplary embodiments, the semiconductor device may include logic cells configured to process data, and the field-effect transistor may be used to implement the logic cells.

[0080] A plurality of the active layers AL can be arranged in a first direction D1 on a substrate 100. Each of the active layers AL can have channel layers CHL, which are arranged in a second direction D2, and source / drain layers SDL, which are provided between the channel layers CHL. Here, the source / drain layers SDL can be configured to have essentially the same characteristics as the column section P2, which was previously described with reference to the Fig. 6A and Fig. 6B is described. Each of the source / drain layers SDL can be referred to as contact point 111 and contact 113, which were previously described with reference to the Fig. They function as described in sections 12 and 13A to 13C.

[0081] Intermediate connecting lines 121 (see Fig. 18A and Fig. 18B), can be provided on an intermediate insulating layer 110 on the substrate 100. The intermediate connecting lines 121 can be electrically connected to the source / drain layers SDL.

[0082] Fig. Figure 19 is a perspective view illustrating a semiconductor device according to some exemplary embodiments. In the following description, an element referred to above in the Fig. 16, can be identified by a similar or identical reference symbol without repeating an overlapping description of it.

[0083] Referring to Fig. 19 A gate electrode GE can be provided to extend on substrate 100 in a first direction D1 and to cross channel layers CHL. Unlike that of the Fig. 16. The gate electrode GE can have at least one section 101 positioned between a pair of channel layers CHL. In other words, such a section 101 of the gate electrode GE can be provided to be adjacent to one of the opposite surfaces of each channel layer CHL. The other of the opposite surfaces of each channel layer CHL can be not adjacent to the gate electrode GE. The modification in the structure of the gate electrode GE can make it possible to control a saturation current (Idsat) value of a field-effect transistor. For example, the field-effect transistor according to the exemplary embodiment described in Fig. As shown in Figure 19, they have a saturation current (Idsat) value which is smaller than that of the field-effect transistor, which was previously described with reference to Fig. 16 is described.

[0084] Fig. Figure 20 is a perspective view illustrating a semiconductor device according to some exemplary embodiments. In the following description, an element referred to above may be Fig. 16, can be identified by a similar or identical reference symbol without repeating an overlapping description of it.

[0085] Referring to Fig. 20. A channel layer CHL can have one or more sections extending on the substrate 100 in a first direction D1. The channel layer CHL can have first sections CHLa, second sections CHLb, and a third section CHLc. Each of the first sections CHLa can have a fin-shaped structure extending orthogonally from the substrate 100 and parallel to a third direction D3. The second sections CHLb and the third section CHLc can be positioned to have a surface parallel to an upper surface of the substrate 100. The second sections CHLb can be positioned adjacent to the bottoms of the first sections CHLa, and the third section CHLc can be positioned adjacent to the tops of the first sections CHLa. In other words, the second sections CHLb can be positioned at a level lower than that of the third section CHLc.

[0086] The first sections CHLa, the second sections CHLb, and the third section CHLc can be connected to form a single body. The second section CHLb can be located between one pair of the first sections CHLa, and the third section CHLc can be located between another pair of the first sections CHLa. In other words, when viewed in a vertical section taken along the first direction D1, the channel layer CHL can have a zigzag shape.

[0087] One source / drain layer (SDL) can be electrically connected to one end section of the channel layer (CHL), and another source / drain layer (SDL) can be electrically connected to the opposite end section of the channel layer (CHL), as shown in Fig. Figure 20 shows that each of the source / drain layers (SDL) can be configured to have essentially the same characteristics as column section P2, which is described above with reference to the Fig. 6A and Fig. 6B is described. As an example, the source / drain layer (SDL) can be provided in the form of a carbon nanotube.

[0088] For example, the source / drain layer SDL can be used as a source electrode of a field-effect transistor, and the other source / drain layer SDL can be used as a drain electrode of the field-effect transistor. The channel layer CHL between the source / drain layers SDL can be used as a channel region of the field-effect transistor. In certain exemplary embodiments, unlike that of the Fig. 16, one or more sections of the channel layer CHL can extend in the first direction and can be used as a single channel region of a single field-effect transistor. In other words, the field-effect transistor according to the exemplary embodiment shown in Fig. Figure 20 shows that they have a long channel compared to the field-effect transistor, which is shown in Fig. Figure 16 shows that since the channel layer CHL has the first sections of CHLa, it is possible to achieve the double-gate effect described above.

[0089] Although not shown, a gate electrode GE can be provided to extend on substrate 100 in the first direction D1 or along the channel layer CHL. For example, the gate electrode GE can be configured to have similar technical characteristics to those of the gate electrode GE described above with reference to Fig. 19 is described. In certain exemplary embodiments, the gate electrode GE can be provided to have a section which is positioned below the third section CHLc, and this makes it possible to achieve the double-gate effect.

[0090] Fig. Figure 21 is a perspective view illustrating a semiconductor device according to some exemplary embodiments. In the following description, an element referred to above may be Fig. 16, can be identified by a similar or identical reference symbol without repeating an overlapping description of it.

[0091] Referring to Fig. 21 A plurality of active layers AL can be arranged in a first direction D1 on a substrate 100. Each of the channel layers CHL can have a pair of first sections CHLa and a second section CHLb, which is arranged interposed between the pair of first sections CHLa. Each of the first sections CHLa can have a fin-shaped structure extending orthogonally to the substrate 100 and parallel to a third direction D3. The second section CHLb can be provided to have a surface parallel to an upper surface of the substrate 100. The second section CHLb can be provided adjacent to the bases of the first sections CHLa.

[0092] The first sections CHLa and the second section CHLb can be joined together to form a single body (i.e., the canal layer CHL). When viewed in a vertical section taken along the first direction D1, the canal layer CHL can be shaped like the letter "U".

[0093] Source / drain layers (SDL) can be electrically connected to any of the channel layers (CHL). Each of the source / drain layers (SDL) can be configured to have essentially the same characteristics as the column section (P2), which was described above with reference to the Fig. 6A and Fig. 6B is described. As an example, the source / drain layer SDL can be provided in the form of a carbon nanotube. The first section CHLa between a pair of source / drain layers SDL can be used as a channel region of the field-effect transistor. In such a case, the second section CHLb does not have a function other than that of the channel region.

[0094] A gate electrode GE can be provided to extend on the substrate 100 in the first direction D1 and along the channel layers CHL.

[0095] The Fig. Figures 22A to 22F are sectional views illustrating a method for manufacturing a semiconductor device according to some exemplary embodiments. For example, a method described in the Fig. 22A to 22F is illustrated, and can be used to design the semiconductor device of the Fig. to produce 21. That means that the Fig. 22A to 22F are sectional views, which are along a line II' of the Fig. 21 have been recorded.

[0096] Referring to the Fig. 21 and Fig. 22A First conductive structures 150 can be formed on a substrate 100 and can be arranged in a first direction D1. For example, the first conductive structures 150 can be formed from or have at least one of conductive materials (for example, doped semiconductors, metals, conductive metal nitrides, or metal-semiconductor compounds).

[0097] Referring to the Fig. 21 and Fig. In 22B, a first dielectric layer 51, a preliminary channel layer 53, and a second dielectric layer 155 can be formed successively to cover the first conductive structures 150. The first dielectric layer 151, the preliminary channel layer 153, and the second dielectric layer 155 can be formed to extend in the first direction D1 or along the first conductive structures 150. Subsequently, a plurality of source / drain layers (SDL) can be formed to be electrically connected to the preliminary channel layer 153. As another example, the source / drain layers (SDL) can be formed after a subsequent process to form a gate electrode (GE); however, the inventive concept is not limited to this.

[0098] The first and second dielectric layers 151 and 155 can be formed from a high k-dielectric material, and a channel layer CHL can be formed to have a two-dimensional atomic layer made from a first material. Each of the source / drain layers SDL can have two-dimensional atomic layers and can be formed from a second material and / or a third material.

[0099] Referring to the Fig. 21 and Fig. 22C, a second conductive structure 160 can be formed on the second dielectric layer 155. The second conductive structure 160 can be formed to extend in the first direction D1 or along the second dielectric layer 155. For example, the second conductive structure 160 can be formed from or comprise at least one of conductive materials (for example, doped semiconductors, metals, conductive metal nitrides, or metal-semiconductor compounds).

[0100] Referring to the Fig. 21 and Fig. 22D, the second conductive structure 160 can be planarized to expose the upper surfaces of the first conductive structures 150 and to form third conductive structures 165. Upper sections of the first and second dielectric layers 151 and 155 and the preliminary channel layer 153 can be removed during the planarization process of the second conductive structure 160. As a result, the first and second dielectric layers 151 and 155 can be structured to form dielectric gate layers GI, and the preliminary channel layer 153 can be structured to form the channel layer CHL.

[0101] Each of the channel layers CHL can be positioned between a pair of the first conductive structures 150 and the third conductive structure 165. Each of the channel layers CHL can have a pair of the first sections CHLa and a second section CHLb positioned between the pair of first sections CHLa. In other words, each of the channel layers CHL can be shaped like the letter "U". Each of the dielectric gate layers GI can be positioned between the third conductive structure 165 and the first conductive structure 150. Each of the dielectric gate layers GI can be shaped like the letter "U".

[0102] Referring to the Fig. 21 and Fig. Insulating structures IP can be formed on the channel layers CHL. For example, an etching process can be performed to remove vertically exposed upper surfaces of the channel layers CHL between the first and third conductive structures 150 and 165. Similarly, upper sections of the dielectric gate layers GI can be removed during the etching process of removing the channel layers CHL. The insulating structures IP can be formed to fill the removed areas. In some exemplary embodiments, the insulating structures IP can be formed from, or comprise, at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0103] Referring to the Fig. 21 and Fig. 22 A fourth conductive structure 170 can be formed on the first conductive structures 150 and the third conductive structures 165. The fourth conductive structure 170 can be formed to extend in the first direction D1 or along the first and third conductive structures 150 and 165. The first, third, and fourth conductive structures 150, 165, and 170 can form a gate electrode GE extending in the first direction D1. For example, the fourth conductive structure 170 can be formed from or comprise at least one of conductive materials (for example, doped semiconductors, metals, conductive metal nitrides, or metal-semiconductor compounds).

[0104] Fig. Figure 23 is a top view illustrating a light detection device. Fig. 24 is a sectional view, taken along a line II' of the Fig. 23.

[0105] Referring to the Fig. 23 and Fig. 24. A first source / drain layer SDL(S), a channel layer CHL, and a second source / drain layer SDL(D) can be layered sequentially on a substrate 100. The first source / drain layer SDL(S), the channel layer CHL, and the second source / drain layer SDL(D) can partially overlap when viewed from a top view. For example, the overlapping sections can form a detection area ECA. As an example, the first source / drain layer SDL(S) can be used as a source area S of the light detection device, and the second source / drain layer SDL(D) can be used as a drain area D of the light detection device. However, this is only an example.

[0106] The channel layer CHL can have a two-dimensional atomic layer made of a first material, and each of the first and second source / drain layers SDL(S) and SDL(D) can have a two-dimensional atomic layer made of a second material. For example, the channel layer CHL can be made of phosphors, and the first and second source / drain layers SDL(S) and SDL(D) can be made of graphene. Since phosphors are generally black and therefore have a high light absorption efficiency, they can be effectively used to generate photoelectrons, thus serving as a channel region of a light-sensing device.

[0107] Sections of the first source / drain layer SDL(S), the channel layer CHL, and the second source / drain layer SDL(D) can be electrically and vertically connected. For example, the sections of the first source / drain layer SDL(S), the channel layer CHL, and the second source / drain layer SDL(D) can be connected by covalent bonds between the first and second materials or by van der Waals forces. Van der Waals forces can be advantageous for achieving an effective connection between the first and second materials within the two-dimensional structure.

[0108] For example, if the graphene is coupled to a different material by a van der Waals force, the charge carrier mobility may be degraded. However, if the graphene is coupled to the phosphorene by a van der Waals force, it is possible to suppress or prevent any degradation of the charge carrier mobility. Furthermore, the first and second materials can be configured to have essentially the same characteristics as those described in the... Fig. are described in 1A.

[0109] Each of the first and second source / drain layers SDL(S) and SDL(D) can have a planar section P1 and a column section P2. For example, column section P2 can be positioned on areas of planar section P1 of the first and second source / drain layers SDL(S) and SDL(D) that do not overlap with or are spaced from the channel layer CHL. A channel column CHP can be provided on areas of channel layer CHL that do not overlap with or are spaced from the first and second source / drain layers SDL(S) and SDL(D). As another example, the channel column CHP can be omitted.

[0110] The column sections P2 and the channel column CHP can be configured to have a longitudinal axis perpendicular to an upper surface of substrate 100 or parallel to a third direction D3. Accordingly, the column sections P2 and the channel column CHP can be used as contacts connected to the planar sections P1 and the channel layer CHL. Each of the column sections P2 and the channel column CHP can have a three-dimensional atomic layer formed from a third material (for example, carbon nanotubes). The channel column CHP and the channel layer CHL can be electrically connected to each other by covalent bonds between the first and third materials. In addition, the column sections P2 can be configured to have essentially the same features as those of the Fig. 6A and Fig. 6B.

[0111] Furthermore, although not shown, connecting lines can be provided and electrically connected to the column sections P2 and the channel column CHP. If a voltage is applied between the column sections P2 via these connecting lines, the second source / drain layer SDL(D), to which a relatively high voltage is applied, can have an elevated Fermi level, and the first source / drain layer SDL(S), to which a relatively low voltage is applied, can have a decreased Fermi level. When photons enter the detection area ECA, charge carriers (e.g., electrons) can be generated in the channel layer CHL of the detection area ECA. The generated electrons can accumulate in the second source / drain layer SDL(D) with the elevated Fermi level.An increase in the intensity of the incident light can lead to an increase in the number of electrons generated in the channel layer CHL, and this can lead to an increase in the amount of electric current flowing between the first and second source / drain layers SDL(S) and SDL(D). The incident photons can be detected by measuring the magnitude of the electric current.

[0112] According to some exemplary embodiments, a semiconductor device can have a channel layer with a two-dimensional atomic layer, and this may necessitate the implementation of a field-effect transistor with high charge carrier mobility and low leakage current. Furthermore, according to some exemplary embodiments, the channel layer and the source / drain layer can have a very small thickness (for example, on the order of one atomic diameter), and this may necessitate the implementation of a highly integrated semiconductor device.

Claims

[1] Semiconductor device comprising: a channel layer (CHL) provided on a substrate (100), wherein the channel layer (CHL) has a two-dimensional atomic layer made of a first material; and a source / drain layer (SDL) provided on the substrate (100), wherein the source / drain layer (SDL) comprises a second material, where the first material is one of phosphorus allotropes, the second material of one of carbon allotropes, and the channel layer (CHL) and the source / drain layer (SDL) are connected to each other by covalent bonds between the first and second materials, and wherein the channel layer (CHL) extends in one direction perpendicular to an upper surface of the substrate (100). [2] Device according to claim 1, wherein the first material is phosphorus. [3] Device according to claim 2, wherein the phosphor has an armchair structure, a diagonal structure, a zigzag structure or any combination thereof, and the channel layer (CHL) and the source / drain layer (SDL) form a field-effect transistor whose threshold voltage depends on a structure of the phosphor. [4] Device according to claim 1, wherein the first material has a single atomic layer or a plurality of vertically stacked atomic layers, and the channel layer (CHL) and the source / drain layer (SDL) form a field-effect transistor whose threshold voltage depends on the number of atomic layers of the first material. [5] Device according to claim 1, wherein the second material is at least one of graphene and carbon nanotubes. [6] Device according to claim 1, further comprising a gate electrode (GE) which is provided on the substrate (100) such that it crosses the channel layer (CHL). [7] Device according to claim 1, wherein the channel layer (CHL) and the source / drain layer (SDL) form an active layer (AL), and a plurality of active layers (AL) are provided, and the active layers (AL) are provided on the substrate (100) such that they are arranged in a direction parallel to an upper surface of the substrate (100). [8] Device according to claim 7, further comprising a gate electrode (GE) which extends in the direction and jointly crosses the channel layers (CHL) of the active layers (AL). [9] Device according to claim 1, wherein the second material comprises a carbon nanotube whose longitudinal axis is perpendicular to an upper surface of the substrate (100) and the carbon nanotube is directly connected to the channel layer (CHL). [10] Device according to claim 1, wherein the substrate (100) comprises an insulating material. [11] Device according to claim 1, further comprising: a gate electrode (GE) which is provided adjacent to at least one of the surfaces of the channel layer (CHL), wherein the source / drain layer (SDL) is arranged on one side of the channel layer (CHL) and is electrically connected to the channel layer (CHL), where the first material is phosphorus, and where the second material is graphene or carbon nanotubes. [12] Device according to claim 11, wherein the source / drain layer (SDL) comprises a carbon nanotube whose longitudinal axis is perpendicular to an upper surface of the substrate (100), and the carbon nanotube is directly connected to the channel layer (CHL). [13] Device according to claim 11, wherein the channel layer (CHL) comprises: a first section extending in one direction perpendicular to an upper surface of the substrate (100); and a second section which extends from the first section to be parallel to an upper surface of the substrate (100). [14] Device according to claim 11, wherein the channel layer (CHL) has a plurality of first sections and a plurality of second sections which are connected to each other in a zigzag shape, and the source / drain layer (SDL) has a first source / drain layer (SDL(S)) and a second source / drain layer (SDL(D)) which are each connected to two opposite end sections of the channel layer (CHL). [15] Device according to claim 11, further comprising: an insulating layer (115, 125, 135, 145) covering the channel layer (CHL), the source / drain layer (SDL), and the gate electrode (GE); and an intermediate connecting line (121) which is provided on the insulating layer (115, 125, 135, 145) and is electrically connected to the source / drain layer (SDL). [16] Device according to claim 11, further comprising: an insulating layer (115, 125, 135, 145) which covers the channel layer (CHL), the source / drain layer (SDL) and the gate electrode (GE) and a data storage element which is provided on the insulating layer (115, 125, 135, 145) and is electrically connected to the source / drain layer (SDL). [17] Device according to claim 11, wherein the channel layer (CHL) and the source / drain layer (SDL) form an active layer (AL), and a plurality of active layers (AL) are provided, the active layers (AL) on the substrate (100) are arranged in a direction parallel to an upper surface of the substrate (100), and The gate electrode (GE) is provided to jointly cross the channel layers (CHL) of the active layers (AL). [18] Device according to any one of claims 1 to 17, wherein the device is a field-effect transistor.

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