Flying and twisted bitline architecture for a static dual-port random access memory (DP-SRAM)

Abstract

Semiconductor storage device (102), comprising: an array (104) of memory cells (106) arranged in rows (N) and columns (X), wherein the array (104) comprises a first subarray (110) of memory cells (106) and a second subarray (108) of memory cells (106), a first pair of CBLs (120, 120b) extending along a column of the array (104), from a first side of the array (104), and terminating between the first and second subarray (108), wherein the first pair of CBLs (120, 120b) is electrically coupled to memory cells (106) of the first subarray (110) in the column, a second pair of CBLs (118, 118b) extending from the first side of the array (104), along the column, to a second side of the array (104), wherein the second pair of CBLs (118, 118b) is electrically coupled to memory cells (106) of the second subarray (108) in the column, and wherein the CBLs of the second pair of CBLs (118, 118b) have stepped profiles between the first and the second subarray (110, 108), a third pair of CBLs (120, 120a) and a fourth pair of CBLs (118, 118a) extending along the column, wherein the third and fourth pairs of CBLs (120, 120a, 118, 118a) are each electrically coupled to the memory cells (106) of the first subarray (110) in the column and the memory cells (106) of the second subarray (108) in the column, a set of word lines (112), a port AI / O array (130a) on the second or first side of the array (104) of memory cells (106), designed to use the fourth pair of CBLs (118, 118a) and the third pair of CBLs (120, 120a) to read from and / or write to memory cells (106) accessed by the word lines (112), and a port BI / O array (130b) on the first or second side of the array (104) of memory cells (106), designed to use the second pair of CBLs (118, 118b) and the first pair of CBLs (120, 120b) to read from and / or write to memory cells (106) accessed by the word lines (112).

Description

CROSS-REFERENCE TO RELATED REGISTRATION

[0001] This application claims priority over preliminary US patent application No. 62 / 272,170, which was filed on December 29, 2015. STATE OF THE ART

[0002] A semiconductor memory is an electronic data storage device implemented on a semiconductor-based integrated circuit. Semiconductor memories come in many different types and offer faster access times than other data storage technologies. For example, a byte of data can often be written to or read from a semiconductor memory within a few nanoseconds, whereas access times for rotating storage, such as hard drives, are in the range of milliseconds. For these reasons, among others, semiconductor memories are used as a primary storage mechanism for computers to retain data that computers are currently working on. One semiconductor device is known from US patent 5,696,727. Other semiconductor devices are also known from DE 101 24 752 B4 and US patent 6,498,758 B1. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of this disclosure are best understood from the detailed description below, when read together with the accompanying figures. It should be noted that, in accordance with industry standard practice, various features are not drawn to scale. Rather, the dimensions of the various features may have been enlarged or reduced as appropriate for clarity of discussion. Fig. Figure 1 shows a block diagram of some embodiments of a static dual-port direct access memory device (DP-SRAM device) with jump cells. Fig. Figure 2A shows a layout view of some embodiments of bit lines within a column of the DP-SRAM device of Fig. 1. Fig. Figure 2B shows a cross-sectional view of some embodiments of jump cells within the column of Fig. 2A. Fig. Figure 3A shows a schematic view of some embodiments of a memory cell within the DP-SRAM device of Fig. 1. Fig. Figure 3B shows a schematic view of some more detailed embodiments of the memory cell of Fig. 3A. Fig. Figure 4 shows a block diagram of some other embodiments of the DP-SRAM device. Fig. 1 with twisting cells. Fig. Figure 5A shows a layout view of some embodiments of bit lines within a column of the DP-SRAM device of Fig. 4. Fig. Figure 5B shows a cross-sectional view of some embodiments of jump cells within the column of Fig. 5A. Fig. Figure 5C shows a cross-sectional view of some embodiments of a twisting cell within the column of Fig. 5A. Fig. Figure 5D shows another cross-sectional view of some embodiments of a twisting cell within the column of Fig. 5A. Fig. Figure 6 shows a block diagram of some other embodiments of the DP-SRAM device. Fig. 1, in which the input / output (I / O) is distributed between opposite sides of the DP-SRAM device. Fig. Figure 7A shows a layout view of some embodiments of bit lines within a column of the DP-SRAM device of Fig. 6. Fig. Figure 7B shows a cross-sectional view of some embodiments of jump cells within the column of Fig. 7A. Fig. Figure 8 shows a block diagram of some other embodiments of the DP-SRAM device. Fig. 6 with twisting cells. Fig. Figure 9A shows a layout view of some embodiments of bit lines within a column of the DP-SRAM device of Fig. 8. Fig. Figure 9B shows a cross-sectional view of some embodiments of jump cells within the column of Fig. 9A. Fig. Figure 9C shows a cross-sectional view of some embodiments of a twisting cell within the column of Fig. 9A. Fig. Figure 9D shows another cross-sectional view of some embodiments of a twisting cell within the column of Fig. 9A. Fig. Figure 10A shows a block diagram of some embodiments of a multi-bank DP-SRAM device. Fig. Figure 10B shows a block diagram of some other embodiments of the multi-bank DP-SRAM device by Fig. 10A, in which input / output (I / O) is distributed between opposite sides of the multi-bank DP-SRAM device. Fig. Figure 11 shows a flowchart of some embodiments of a method for reading and / or writing data using a flying and / or twisted bitline architecture. DETAILED DESCRIPTION

[0004] The present disclosure provides many different embodiments, or examples, for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, forming a first feature over or on top of a second feature in the description below may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features can be formed between the first and second features, so that the first and second features may not be in direct contact. Furthermore, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition is done for the sake of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0005] Furthermore, terms relating to spatial relativity, such as "below," "under," "lower," "above," "upper," and the like, may be used herein for the convenience of discussion to describe the relationship of one element or feature to another element or feature (or other elements or features), as illustrated in the figures. The terms relating to spatial relativity are intended to encompass various orientations of the apparatus or device used or operated, in addition to the orientation illustrated in the figures. The apparatus or device may be oriented in a different way (rotated by 90 degrees or otherwise), and the terms relating to spatial relativity used herein may likewise be interpreted accordingly.Furthermore, the terms "first," "second," "third," "fourth," and the like are merely general designations and can therefore be interchanged in different embodiments. While an element (e.g., a pair of bit lines) may be referred to as a "first" element in some embodiments, the same element may be referred to as a "second" element in other embodiments.

[0006] One type of semiconductor memory is static dual-port random-access memory (DP-SRAM). A DP-SRAM device allows two memory accesses to occur simultaneously, or nearly simultaneously, each via two "ports." The DP-SRAM device comprises one or more banks of memory cells, with each bank containing multiple memory cells arranged in rows and columns. Two word lines correspond to the two ports and extend along each row, electrically coupled to each memory cell in the row. Two pairs of complementary bit lines (CBLs) correspond to the two ports and extend along each column, electrically coupled to each memory cell in the column.The word lines of each port allow access to the memory cells on a row-by-row basis, and the CBLs of each port allow data states to be written to or read from access memory cells on a column-by-column basis.

[0007] A bank of memory cells typically has between 128 and 512 rows. However, this results in long bit lines and therefore high loads on the bit lines. These high loads can, in turn, lead to high minimum read and write voltages. Read and write voltages below these high minimum voltages cause instability when reading from and writing to the memory cells. Furthermore, these high minimum read and write voltages can lead to high dynamic power consumption. One solution to mitigate the effects of long bit lines is to use smaller banks of memory cells. For example, a large bank of 128 rows can be replaced by two smaller banks of 64 rows each.However, increasing the number of banks increases the area used by the storage cells, which can lead to higher costs.

[0008] Furthermore, bit lines often run parallel to each other and are separated by only a small distance. With technological improvements and reductions in feature sizes, the distances between adjacent bit lines will become even smaller. However, this close spacing leads to a significant amount of capacitive coupling, especially for long bit lines that extend continuously along an entire column of a bank. Capacitive coupling can, in turn, lead to slow read and write times and can also degrade signal-to-noise ratios.

[0009] In light of the foregoing, the present application relates to a flying and / or twisted bitline architecture for a DP-SRAM. In some embodiments, a DP-SRAM device comprises an array of memory cells arranged in rows and columns, the array comprising a first subarray of memory cells and a second subarray of memory cells. A first pair of CBLs extends along a column of the array, from a first side of the array, and terminates between the first and second subarrays. Furthermore, the first pair of CBLs is electrically coupled to memory cells of the first subarray in the column. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The second pair of CBLs is electrically coupled to memory cells of the second subarray in the column.Furthermore, in some embodiments, the CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The third and fourth pairs of CBLs are electrically coupled to the memory cells of the first subarray and the memory cells of the second subarray, respectively. Additionally, in some embodiments, the CBLs of the third or fourth pair of CBLs have stepped profiles between the first and second subarrays.

[0010] Advantageously, the stepped profiles of the second pair of CBLs allow the CBLs of the second pair to "fly" above the first subarray and then descend to the second subarray for electrical coupling with the memory cells of the second subarray. Similarly, the stepped profiles of the third and fourth pairs of CBLs allow the third and fourth pairs to "fly" above one subarray of the first and second subarrays to the other subarray of the first and second subarrays for electrical coupling with memory cells in the other subarray of the first and second subarrays. Furthermore, dividing the array into multiple sections, each with individual pairs of CBLs, advantageously facilitates low loads on the CBLs, as each pair of CBLs carries a portion of the total load for a corresponding column. These low loads, in turn, can lead to low minimum read and write voltages on the CBLs.The low minimum read and write voltages can, in turn, lead to low dynamic power consumption. Furthermore, these low loads can allow the DP-SRAM device to use a small area for a given memory size, since individual memory banks can be large.

[0011] In some embodiments, the DP-SRAM device further comprises a pair of twisting cells configured to twist a first pair of adjacent bit lines and a second pair of adjacent bit lines. The adjacent bit lines of the first pair each originate from two pairs of CBLs extending along the column, and the adjacent bit lines of the second pair each originate from two pairs of CBLs. Furthermore, the two pairs of CBLs correspond to two of the first, second, third, and fourth pairs of CBLs. For example, the two pairs of CBLs can correspond to the first and third pairs of CBLs. As another example, the two pairs of CBLs can correspond to the second and fourth pairs of CBLs.Advantageously, twisted cells facilitate low capacitive coupling between adjacent bit lines, as they break up parallel planes of the neighboring bit lines. This low capacitive coupling can, in turn, lead to high capacitive matching between pairs of CBLs, resulting in fast read and / or write times and good signal-to-noise ratios.

[0012] With reference to Fig. Figure 1 shows a block diagram 100 of some embodiments of a DP-SRAM device 102. The DP-SRAM device 102 comprises a memory cell array 104. The memory cell array 104 comprises several memory cells 106 arranged in X columns and N rows, where X and N are greater than zero integers and can be equal or different. For clarity, the memory cells 106 are shown individually as MC. <spalte>< / spalte> , <zeile>< / zeile> in Fig. 1. Furthermore, the memory cell array 104 comprises an upper memory cell subarray 108, which holds memory cells in rows 1 to M, and it further comprises a lower memory cell subarray 110, which holds cells in rows M+1 to N, where M is an integer greater than zero and less than N. In some embodiments, M is half of N. For example, M may be 256 and N may be 512.

[0013] The memory cells 106 are arranged at the intersections of their respective columns and rows and each has internal data states. For example, each of the memory cells 106 can have an internal data state representing a single bit of data. In addition, in some embodiments, the internal data states are defined by bistable interlocking circuits. As will be discussed in more detail below, when the DP-SRAM device 102 is in operation, the memory cells 106 can be accessed on a row-by-row basis to read data from and / or write data to the internal data states of the access memory cells. Furthermore, two memory accesses can be performed simultaneously, or nearly simultaneously, each via two “ports” of the DP-SRAM device 102. For clarity, the ports are designated by subscripts “A” and “B” in Fig. 1 displayed.

[0014] A set of word lines 112 facilitates access to the memory cells 106 on a line-by-line basis. The word lines 112 comprise a pair of word lines for each line, where the pair includes a first word line for Port A (i.e., a Port A word line) and a second word line for Port B (i.e., a Port B word line). For example, the word lines 112 can be word lines WL 1,A and WL 1,B for line 1. Furthermore, the word lines 112 extend laterally from a line decoder 114 along the respective lines to be electrically coupled to memory cells in the corresponding lines. For clarity, the word lines 112 are individually designated as WL. <zeile> , <port>< / port> < / zeile> in Fig. 1 marked.

[0015] The line decoder 114 is designed to selectively activate the word lines 112 for each port based on address signals 116. For clarity, the address signals 116 are denoted as ADDR. <port>< / port>The address signals 116 carry respective Y-bit addresses, where Y is an integer greater than zero. A Y-bit address for a port indicates a row of the memory cell array 104 and Z columns of the memory cell array 104, thus determining Z memory cells at the intersection of the row and Z columns. For example, a specified number of the most or least significant bits in the Y-bit address can indicate the row of the memory cell array 104, while the remaining bits in the Y-bit address can indicate the Z columns of the memory cell array 104. Z is an integer greater than zero, such as 1, 8, 16, 32, 64, 128, or X. Furthermore, the Z memory cells can, for example, define a unit of data, such as a word.

[0016] A set of upper bit lines 118 for the upper memory cell subarray 108 and a set of lower bit lines 120 for the lower memory cell subarray 110 facilitate reading from and / or writing to access memory cells. The upper bit lines 118 comprise two pairs of complementary bit lines (CBLs) for each column, with the two pairs comprising a first pair of CBLs for port A (i.e., an upper port A pair of CBLs) and a second pair of CBLs for port B (i.e., an upper port B pair of CBLs). For example, the upper bit lines 118 can be bit lines BL 2,TP,A and BL' 2,TP,A as well as BL bit lines 2,TP,B and BL' 2,TP,B for column 2. Likewise, the lower bit lines 120 comprise two pairs of CBLs for each column, with the two pairs including a third pair of CBLs for port A (i.e., a lower port A pair of CBLs) and a fourth pair of CBLs for port B (i.e., a lower port B pair of CBLs). For example, the lower bit lines 120 can be bit lines BL1,BT,A and BL' 1,BT,A as well as BL bit lines 1,BT,B and BL' 1,BT,B for column 1. Two bit lines of a pair of CBLs (e.g. BL) X,TP,A / BL' X,TP,A The two bit lines are complementary in that, in operation of the DP-SRAM device 102, one of the two bit lines is biased to carry a first voltage level corresponding to a logical "1", while the other of the two bit lines is biased to carry a second voltage level corresponding to a logical "0". For clarity, the two bit lines of each pair of CBLs are each designated as BL. <zeile> , <subarray> , <port>< / port> < / subarray> < / zeile> and BL' <zeile> , <subarray> , <port>< / port> < / subarray> < / zeile> in Fig. 1 marked.

[0017] Using separate bit lines for the upper memory cell subarray 108 and the lower memory cell subarray 110 advantageously results in low loads on the upper and lower bit lines 118 and 120. For example, if M is half of N, the upper and lower bit lines 118 and 120 will have loads that are approximately half the total loads for their respective columns. The low loads on the upper and lower bit lines 118 and 120 can, in turn, lead to low minimum read and write voltages on these lines. Furthermore, the low minimum read and write voltages can also result in low dynamic power consumption.Furthermore, the use of separate bit lines for the upper memory cell subarray 108 and the lower memory cell subarray 110 advantageously allows the DP-SRAM device 102 to use a small area for a given memory size, since individual memory banks (discussed below) can be large.

[0018] The upper bit lines 118 extend laterally along respective columns from a first side of the memory cell array 104 to a second side of the memory cell array 104 opposite the first side. The upper bit lines 118 are also connected to the memory cells of the upper memory cell subarray 108 (e.g., MC). 1,1 to MC 1,MThe access memory cells in column 1), located in their respective columns, are electrically coupled to allow each port to read from and / or write to access memory cells of the upper memory cell subarray 108 on a column-by-column basis. The upper bit lines 118 each comprise a flying bit line segment 122, a local bit line segment 124, and a jump cell 126.

[0019] The flying bitline segments 122 of the upper bitlines 118 extend along respective columns of the memory cell array 104, from the first side of the memory cell array 104, and terminate between the upper and lower memory cell subarrays 108, 110. The local bitline segments 124 of the upper bitlines 118 extend from the space between the upper and lower memory cell subarrays 108, 110, along respective columns, to the second side of the memory cell array 104. In some embodiments, the local bitline segments 124 are spaced laterally from the flying bitline segments 122 in a direction that is substantially parallel to the rows.

[0020] Although not in Fig. As shown in Figure 1, in some embodiments the local bitline segments 124 are spaced above or below the flying bitline segments 122 in a direction substantially perpendicular to the rows and columns, such that the upper bitlines 118 have a step down or a step up at the transition from the flying bitline segments 122 to the local bitline segments 124. For example, the flying bitline segments 122 may be located in a metal 2 layer of a back-end-of-line (BEOL) interconnect structure, and the local bitline segments 124 may be located in a metal 0 layer of the BEOL interconnect structure. Alternatively, the flying bitline segments 122 may be located in a metal 0 layer of a BEOL interconnect structure, and the local bitline segments 124 may be located in a metal 2 layer of the BEOL interconnect structure.As another example, the flying bit line segments 122 and the local bit line segments 124 can be located in different metal layers of a BEOL interconnect structure. Alternatively, in other embodiments, the flying bit line segments 122 and the local bit line segments 124 are located in the same metal layer of a BEOL interconnect structure.

[0021] The jump cells 126 of the upper bit lines 118 are located between the upper and lower memory cell subarrays 108, 110 and electrically couple the flying bit line segments 122 to the local bit line segments 124. The jump cells 126 extend laterally at an angle to the columns (e.g., substantially perpendicular to the columns) from the ends of the flying bit line segments 122 to the ends of the local bit line segments 124. Furthermore, the jump cells 126 extend perpendicular to the rows and columns (e.g., vertically) from the ends of the flying bit line segments 122 to the ends of the local bit line segments 124.

[0022] The lower bit lines 120 extend laterally along their respective columns from the first side of the memory cell array 104 and terminate between row M+1 and the jump cells 126. Unlike the upper bit lines 118, the lower bit lines 120 do not have any floating bit segments. Furthermore, the lower bit lines 120 are connected to the memory cells of the lower memory cell subarray 110 (e.g., MC). 2,M+1 to MC 2,N in column 2), which are located in the respective columns, are electrically coupled to allow each data port to read from and / or write to access memory cells of the lower memory cell subarray 110 on a column-by-column basis. In some embodiments, the lower bit lines 120 are laterally spaced from the flying bit line segments 122 in a direction substantially parallel to the rows and / or are aligned with the local bit line segments 124.

[0023] Although not in Fig. As shown in Figure 1, in some embodiments the lower bit lines 120 are spaced above or below the flying bit line segments 122 in a direction substantially perpendicular to the rows and columns. Such a spacing may, for example, be the same or a different value than the spacing between the local bit line segments 124 and the flying bit line segments 122 in a direction substantially perpendicular to the rows and columns. For example, the lower bit lines 120 and the local bit line segments 124 may be located in a metal 0 layer of a BEOL interconnect structure, while the flying bit line segments 122 may be located in a metal 2 layer of the BEOL interconnect structure.As another example, the lower bit lines 120 and the local bit line segments 124 can be located in a metal 2 layer of a BEOL interconnect structure, while the flying bit line segments 122 can be located in a metal 0 layer of the BEOL interconnect structure. As yet another example, the lower bit lines 120 can be located in a metal 1 layer of a BEOL interconnect structure, the local bit line segments 124 can be located in a metal 0 layer of the BEOL interconnect structure, and the flying bit line segments 122 can be located in a metal 2 layer of the BEOL interconnect structure. Alternatively, in other embodiments, the lower bit lines 120 and the flying bit line segments 122 are located in the same metal layer of a BEOL interconnect structure.

[0024] As noted above, the loads on the upper and lower bit lines 118, 120 are advantageously low. In some embodiments, the loads on the upper bit lines 118 are approximately equal to the intrinsic loads of the upper bit lines 118 (e.g., due to internal resistances) plus the loads imposed by the memory cells of the upper memory cell subarray 108. For example, bit line BL 1,TP,A exhibit a load approximately equal to the intrinsic load of the BL bit line 1,TP,A plus the load of memory cells MC 1,1 up to the memory cell MC 1,M in column 1. Similarly, in some embodiments, the loads on the lower bit lines 120 are approximately equal to the intrinsic loads of the lower bit lines 120 plus the loads imposed by the memory cells of the lower memory cell subarray 110. For example, the bit line BL 2,BT,Bexhibit a load approximately equal to the intrinsic load of the BL bit line 2,BT,B plus the load of memory cells MC 2,M+1 up to the memory cell MC 2,N in column 2. If M is half of N, then accordingly the upper and lower bit lines 118, 120 have approximately the same loads, but the upper bit lines 118 have slightly higher loads due to the flying bit line sections 122.

[0025] An input / output array (I / O array) 130 is configured to use the upper and / or lower bit lines 118, 120 to read from and / or write to memory cells accessed by the word lines 112 and the line decoder 114. Furthermore, in some embodiments, the I / O array 130 is configured to output data read from the access memory cells to data signals 132 for the respective ports and / or to write data input on the data signals 132 to the access memory cells. The data signals 132 carry Z bit data values ​​and are designated as DATA. <port>< / port> The I / O array 130 is controlled by a controller 134 using control signals 136 and comprises several I / O cells 138. The I / O cells 138 correspond to the columns of the memory cell array 104 and are designated as I / O <spalte>< / spalte>marked. Furthermore, the I / O cells 138 are electrically coupled to the upper and lower bit lines of the corresponding columns. For example, I / O1 can be connected to BL. 1,TP,B , BL 1,TP,A , BL' 1,TP,B and BL' 1,TP,A as well as BL 1,BT,B , BL 1,BT,A , BL' 1,BT,B and BL' 1,BT,A They are electrically coupled. The I / O cells 138 each comprise a selection circuit 140 and a read / write circuit (R / W circuit) 142.

[0026] The selection circuits 140 are designed to select pairs of CBLs corresponding to the Y-bit addresses on the address signals 116. For example, if a Y-bit address is on the port A address signal (i.e., ADDR) A ) Displaying row 1 and column 1, selects a selection circuit 140a for column 1 bit lines BL. 1,TP,A / BL' 1,TP,AThis is because this pair of CBLs corresponds to the Y-bit address. Furthermore, the selection circuits 140 are designed to select the pairs of CBLs based on the control signals 136 from the controller 134. For example, the controller 134 can be designed to decode the Y-bit addresses and generate the control signals 136, so that the selection circuits 140 select the pairs of CBLs that correspond to the Y-bit addresses.

[0027] In some embodiments, the selection circuits 140 each comprise a pair of subarray multiplexers 144 and a port multiplexer 146. The subarray multiplexers 144 are configured to select between respective upper bit lines (i.e., bit lines of the upper memory cell subarray 108) and respective lower bit lines (i.e., bit lines of the lower memory cell subarray 110). For example, a first subarray multiplexer 144a for column X may be configured to select either BL X,BT,Band BL X,BT,A or BL X,TP,B and BL X,TP,A selects, while a second subarray multiplexer 144b for column X can be designed such that it either BL' X,BT,B and BL' X,BT,A or BL' X,TP,B , and BL' X,TP,A selects. The port multiplexers 146 are designed to select between the respective bit lines for port A and the respective bit lines for port B. For example, a port multiplexer 146a for column X can be designed to select BL X,BT,B and BL' X,BT,B or BL X,BT,A and BL' X,BT,AIn some embodiments, the port multiplexers 146 are electrically coupled to the subarray multiplexers 144, so that the port multiplexers 146 select from bit lines selected by the subarray multiplexers 144. Furthermore, in some embodiments, the subarray multiplexers 144 and the port multiplexers 146 are controlled by the control signals 136. For example, the control signals 136 can include individual selection signals for the subarray multiplexers 144 and the port multiplexers 146.

[0028] The R / W circuits 142 are designed such that they are based on R / W signals 148 from access memory cells that correspond to the selected pairs of CBLs (e.g. BL). 2,TP,B / BL' 2,TP,B ) correspond to, read from, and / or write to the ports. The R / W signals 148 correspond to the ports and indicate whether a read or write operation is to be performed on the corresponding ports. For clarity, the R / W signals 148 are also referred to as R / W <port>< / port>characterized. In some embodiments, the R / W circuits 142 are further configured to output data read from the access memory cells to the data signals 132 and / or to write data input on the data signals 132 to the access memory cells. The R / W circuits 142 are controlled by the controller 134 and each comprises circuits for reading from and writing to the selected pairs of CBLs. The controller 134 can, for example, be configured to generate the control signals 136 to control the R / W circuits 142 based on the R / W signals 148.

[0029] To read data from the selected pairs of CBLs, in some embodiments the R / W circuits 142 include respective sampling amplifiers (not shown). The sampling amplifiers are designed to detect differential bias voltages applied to the selected pairs of CBLs through memory cells accessed by the word lines 112. The differential bias voltages represent the internal data states of the memory cells (e.g., MC). 1,M and MC 2,M ), which are accessed through the word lines 112 (e.g. WL) M,A) is accessed. For example, a first differential bias can correspond to a logical "1", while a second differential bias can correspond to a logical "0". Furthermore, the sampling amplifiers are designed to lock or otherwise store data values ​​of the differential biases. To write data to the selected pairs of CBLs, in some embodiments the R / W circuits 142 include respective differential drivers (not shown). The differential drivers are designed to apply differential biases to the selected pairs of CBLs. The differential biases represent data states to be stored in memory cells accessed by the word lines 112 and overwrite the internal data states in the memory cells. The differential biases can, for example, correspond to bits of the data signals 132.

[0030] In some embodiments, the data signals 132 to the I / O array 130 are routed via a column decoder 150. For example, if Z (i.e., the number of bits carried on each of the data signals 132) is less than X (i.e., the number of columns of the memory cell array 104), the data signals 132 to the I / O array 130 can be routed via the column decoder 150. The column decoder 150 is designed to electrically couple the data signals 132 to the I / O cells 138 corresponding to the Y-bit addresses on the address signals 116. Furthermore, the column decoder 150 is designed to electrically couple the data signals 132 of the I / O cells 138, so that bits of the data signals 132 are mapped to the I / O cells 138 with a one-to-one mapping. For example, if a Y-bit address is on the address signal for port A (e.g., ADDR) A Column 1 to X indicates the data signal for port A (e.g., DATA). A) X bits, each corresponding to the I / O cells in columns 1 to X (e.g., I / O1 to I / O x ) are depicted.

[0031] The controller 134 is designed to control the I / O array 130 and, in some embodiments, the row decoder 114 and / or the column decoder 150 to perform read and / or write operations on the two ports. Furthermore, as mentioned above, two read and / or write operations can be performed simultaneously or nearly simultaneously using the two ports. For example, a first row of memory cells (e.g., memory cells MC) can be read. 1,1 to M x,1 ) via a Port A word line (e.g. WL) 1,A ) are accessed while accessing an (M+1)th row of the memory cells (e.g., memory cells MC). 1,M+1 to MC x,M+1 ) simultaneously via a Port B word line (e.g. WL) M+1,B) can be accessed. During access to the memory cells of the first row, the upper bit lines of Port A (e.g., BL) can then be accessed. 1,TP,A / BL' 1,TP,A to BL X,TP,A / BL' X,TP,A ) are used to read from or write to the first row of access memory cells. During access to the memory cells of the (M+1)th row, lower bit lines of Port B (e.g., BL) can be used equally. 1,BT,B / BL' 1,BT,B to BL X,BT,B / BL' X,BT,B ) can be used to simultaneously read from or write to the (M+1)th row of access memory cells.

[0032] As a more detailed example, suppose that a write operation is performed via port A into a first row of memory cells, and further suppose that a read operation is performed via port B into an (M+1)th row of the memory cells simultaneously with the write operation. To write data via port A into the first row of memory cells (e.g., memory cells MC), 1,1 to M X,1 ) to write the R / W signal for port A (e.g., R / W) A ) is delivered to the DP-SRAM device 102 in an initial state (e.g., a logical "0"), indicating that a write operation is about to take place. Additionally, a data signal for port A (e.g., DATA) is provided. A ) to the DP-SRAM device 102 with a first Z-bit data value, and an address signal for port A (e.g. ADDR A ) is provided to the DP-SRAM device 102 with a first Y-bit address indicating Z consecutive memory cells in the first row.

[0033] Upon receiving the Port A signals, the line decoder 114 activates a Port A word line (e.g. WL). 1,A ), which corresponds to the first Y-bit address, and the column decoder 150 electrically couples the data signal for Port A to one or more I / O cells (e.g. I / O1 to I / O X ), corresponding to the first Y-bit address. Furthermore, controller 134 controls the I / O array 130 to select one or more Port A pairs CBLs (e.g., BL). 1,TP,1 / BL' 1,TP,A to BL X,TP,A / BL' X,TP,A ) , corresponding to the first Y-bit address, and activates write circuits in the I / O array 130. This in turn applies differential biases to each of the Port A pair(s) CBLs to write the first Z-bit data value to the Z consecutive memory cells in the first row.

[0034] Simultaneously with writing the data to the first row via port A, data can be written to an (M+1)th row of memory cells (e.g., memory cells MC). 1,M+1 to MC X,M+1 ) can be read. The R / W signal for port B (e.g., R / W B The data is provided to the DP-SRAM device 102 in a second state (e.g., a logical "1"), indicating that a read operation is to take place. Additionally, an address signal for Port B (e.g., ADDR) is provided. B ) is provided to the DP-SRAM device 102 with a second Y-bit address, indicating Z consecutive memory cells in the (M+1)th row. Based on the Port B signals, the column decoder 150 electrically couples the data signal for Port B (e.g., DATA). B ) with one or more I / O cells (e.g. I / O1 to I / O X), which correspond to the second Y-bit address. Furthermore, controller 134 controls the I / O array 130 to select one or more Port B pairs CBLs (e.g., BL). 1,BT,B / BL' 1,BT,B to BL x,BT,B / BL' X,BT,B ) , corresponding to the second Y-bit address, and activates write circuits in the I / O array 130. The controller 134 can even, for example, control the I / O array 130 to float the Port B pair(s) CBLs and preload the Port B pair(s) CBLs to a voltage level between a logical "0" and a logical "1".

[0035] The line decoder 114 and the control unit 134 then activate a Port B word line (e.g. WL). M+1,B ), which corresponds to the second Y-bit address. This in turn prompts the access memory cells (e.g., memory cells MC) to be accessed. 1,M+1 to MC X,M+1) to apply differential biases to each of the Port B pair(s) CBL(s), where the differential biases represent internal data states of the access memory cells. For example, if memory cell MC 1,M+1 stores a logical "1", and MC X,M+1 Storing a logical "0" represents a first differential bias on BL. 1,2,B / BL' 1,2,B a logical "1" and a second, different differential bias on BL X,2,B / BL' X,2,B represents a logical "0". Furthermore, the sampling amplifiers of the respective I / O cells 138 then store the corresponding data states on the Port B pair(s) CBL(s), and the data states for the Z consecutive memory cells in the (M+1)th row are passed as a second Z-bit data value to the data signal for Port B (e.g., DATA). B ) issued.

[0036] Although the foregoing focused on a DP-SRAM, it is understood that other types of dual-port semiconductor memories are possible. While the foregoing focused on one I / O configuration, other I / O configurations are also possible. For example, the I / O array 130 may have a different configuration, such as separate read / write circuits for Port A and Port B. As another example, the relationship between the row decoder 114, the column decoder 150, the I / O array 130, and the controller 134 may differ. While the upper and lower memory cell subarrays 108 and 110 have been described as "upper" and "lower," they can alternatively be referred to as a first memory cell subarray and a second memory cell subarray.

[0037] With reference to Fig. 2A is a layout view 200A of some embodiments of bit lines 118', 120' within a column of the DP-SRAM device 102 of Fig. 1 provided. The bit lines 118', 120' represent bit lines within each column of the DP-SRAM device 102 of Fig. 1, and in accordance with the notation described above, the column is indicated by a subscript index “x”, which is an integer value greater than or equal to 1 and less than or equal to X. Furthermore, for clarity, a key to symbols is provided at the bottom of Layout View 200A to indicate BEOL metal layers within which various sections of the 118' and 120' bit lines may be arranged.

[0038] As shown in layout view 200A, the bit lines 118', 120' include upper bit lines 118' (e.g. BL). X,TP,A / BL' X,TP,A and BL x,TP,B / BL' x,TP,B ) and lower bit lines 120' (e.g. BL) x,BT,A / BL' x,BT,Aand BL x,BT,B / BL' x,BT,B The upper bit lines 118' each extend from subarray multiplexers 144a', 144b' at a first end of the column, laterally along the column, to a second end of the column opposite the first end. In some embodiments, the subarray multiplexers 144a', 144b' comprise two subarray multiplexers (e.g., TP / BT MUX B and TP / BT MUX B') for each port. Furthermore, the upper bit lines 118' each comprise a flying bit line segment 122', a local bit line segment 124', and a jump cell 126'.

[0039] The flying bitline segments 122' of the upper bitlines 118' extend along the column from the subarray multiplexers 144a' and 144b', respectively, and terminate between an upper memory cell subarray 108 and a lower memory cell subarray 110. Furthermore, the flying bitline segments 122' are electrically coupled to the subarray multiplexers 144a' and 144b' via first vias 202. The local bitline segments 124' of the upper bitlines 118' extend from the space between the upper and lower memory cell subarrays 108 and 110 along the column to the second end of the column. Furthermore, the local bitline segments 124' are connected to memory cells 106a' of the upper memory cell subarray 108 (e.g., MC). x,1 to MC x,M ) , which are located in the column, are electrically coupled.

[0040] In some embodiments, the flying bitline segments 122' and the local bitline segments 124' extend along the gap in the same metal layer of a BEOL interconnect structure. In alternative embodiments, the flying bitline segments 122' and the local bitline segments 124' extend along the gap in different metal layers of a BEOL interconnect structure. For example, the flying bitline segments 122' can extend along the gap in a Metal 2 layer of a BEOL interconnect structure, while the local bitline segments 124' can extend along the gap in a Metal 0 layer of the BEOL interconnect structure.As another example, the flying bit line segments 122' can extend along the column in a metal 0 layer of a BEOL interconnect structure, while the local bit line segments 124' can extend along the column in a metal 2 layer of the BEOL interconnect structure.

[0041] The jump cells 126' of the upper bit lines 118' are located between the upper and lower memory cell subarrays 108, 110 and electrically couple the flying bit line segments 122' to the local bit line segments 124'. Each jump cell 126' comprises a transition bit line segment 203 and secondary vias 204. The transition bit line segments 203 extend laterally at an angle to the column (e.g., substantially perpendicular to the column) from the ends of the flying bit line segments 122' to the ends of the local bit line segments 124'. Furthermore, the transition bit line segments 203 are electrically coupled to the flying bit line segments 122' and the local bit line segments 124' via the secondary vias 204.In some embodiments, the transition bit-line segments 203 are vertically spaced between a first metal layer of a BEOL interconnect structure, which accommodates the flying bit-line segments 122', and a second metal layer of the BEOL interconnect structure, which accommodates the local bit-line segments 124'. For example, the transition bit-line segments 203 can be located in a metal-1 layer of a BEOL interconnect structure if the flying bit-line segments 122' are located in a metal-2 layer of the BEOL interconnect structure and the local bit-line segments 124' are located in a metal-0 layer of the BEOL interconnect structure.

[0042] The lower bit lines 120' extend laterally along the column, each from the subarray multiplexers 144a', 144b', and terminate between the upper and lower memory cell subarrays 108, 110. Furthermore, the lower bit lines 120' are electrically coupled to the subarray multiplexers 144a', 144b' via the first vias 202 and are connected to memory cells 106b' of the lower memory cell subarray 110 located in the column (e.g., MC). x,M+1 and MC x,N) , electrically coupled. In some embodiments, the lower bit lines 120' also extend laterally in the same or a different metal layer of a BEOL interconnect structure as the local bit line segments 124'. For example, the lower bit lines 120' and the local bit line segments 124' can extend laterally in a metal 0 layer of a BEOL interconnect structure. As another example, the lower bit lines 120' can extend laterally in a metal 2 layer of a BEOL interconnect structure, while the local bit line segments 124' can extend laterally in a metal 0 layer of a BEOL interconnect structure.

[0043] As also shown in layout view 200A, one or more voltage source lines (Vss lines) 206 extend laterally from the first end of the column to the second end of the column and are connected to the memory cells 106a', 106b' of the column (e.g. MC).x,1 to MC x,N ) electrically coupled. In some embodiments, the Vss line(s) 206 extends laterally in a metal O-layer of a BEOL interconnect structure and / or are connected by flying bit line segments (e.g., the flying bit line segments of BL). x,TP,A and BL' x,TP,A ) overlaps. Alternatively, in other embodiments, the Vss line(s) 206 extends laterally in a metal-2 layer of a BEOL interconnect structure and / or overlaps flying bit line segments (e.g., the flying bit line segments of BL). x,TP,A and BL' x,TP,A ). In some other embodiments, the Vss line(s) 206 are generally supply and / or ground lines.

[0044] With reference to Fig. 2B is a cross-sectional view 200B of some embodiments of jump cells 126'' within the column of Fig. 2A provided. The cross-sectional view 200B can be seen, for example, along line AA' in Fig. 2A is drawn, and the jump cells 126'' represent the jump cells 126' within the column of Fig. 2A. As shown, a semiconductor substrate 208 carries a BEOL interconnect structure 210 and the memory cells 106a', 106b' of Fig. 2A (not shown). The semiconductor substrate 208 can be, for example, a bulk semiconductor substrate (e.g., a bulk silicon substrate) or an SOI substrate (silicon on an insulator). The BEOL interconnect structure 210 comprises a first dielectric layer 212 within which several metal layers M0, M1, M2 are stacked alternately with several via layers V1, V2. In some embodiments, the BEOL interconnect structure 210 also comprises a second dielectric layer 214, which separates a metal O layer (e.g., M0) from the semiconductor substrate 208.

[0045] The metal layers M0, M1, M2 and the via layers V1, V2 define a set of upper bit lines 118'' (e.g. BL) x,TP,A and BL x,TP,B in Fig. 2A) for Port A and Port B respectively. The upper bit lines 118'' each comprise a flying bit line segment 122'', a transition bit line segment 203', and a local bit line segment 124''. The flying bit line segment 122'' and the local bit line segment 124'' are located in different metal layers, and the transition bit line segment 203' is located in a metal layer between these different metal layers. For example, the flying bit line segment 122'' may be located in a Metal 2 layer (i.e., M2), the transition bit line segment 203' may be located in a Metal 1 layer (i.e., M1), and the local bit line segment 124'' may be located in a Metal 0 layer (i.e., M0).As another example, the flying bitline segment 122'' can be located in the metal 2 layer, the transition bitline segment 203' can be located in the metal 1 layer, and the local bitline segment 124'' can be located in the metal 0 layer. Furthermore, the upper bitlines 118'' each include a first via 204a'' and a second via 204b''. The first via 204a'' electrically couples the local bitline segment 124'' to the transition bitline segment 203', for example, in a via 1 layer (i.e., V1). The second via 204b' electrically couples the transition bitline segment 203' to the bitline segment 122', for example, in a via 2 layer (i.e., V2). In some embodiments, the metal layers further define a Vss line 206' which crosses under one of the transition bit line sections 203', for example in the metal 0 layer.

[0046] With reference to Fig. Figure 3A is a schematic view of some embodiments of a memory cell 106'' within the DP-SRAM device 102 of Fig. 1 provided. Memory cell 106'' represents each memory cell within the DP-SRAM device 102 of Fig. 1 and, in accordance with the notation described above, a column of memory cell 106'' and a row of memory cell 106'' are each indicated by a subscript "x" and a subscript "n". "x" is an integer value greater than or equal to 1 and less than or equal to X, and "n" is an integer value greater than or equal to 1 and less than or equal to N. Furthermore, the subscript " <tp bt>"whether memory cell 106" is located in the upper or lower memory cell subarray 108, 110 of Fig. 1 is located.

[0047] As shown, the memory cell 106'' comprises a data storage element 302, which consists of a first inverter 304 and a second inverter 306. The first and second inverters 304, 306 are cross-coupled to form a first data storage node 308a (SN) and a second data storage node 308b (SN'). The first and second data storage nodes 308a, 308b are complementary. One data storage node is biased to carry a first voltage corresponding to a logical "1", while the other data storage node is biased to carry a second voltage corresponding to a logical "0". Therefore, the first and second inverters 304, 306 store one bit of data in a mutually reinforcing manner.

[0048] Some access transistors 310, 312, 314, 316 selectively couple the first and second data storage nodes 308a, 308b each to bit lines 318 (e.g. BL). x, <tp bt> ,A < / tp> and BL' x, <tp bt> ,A < / tp> ) based on whether word lines 112' (e.g. WL n,A and WL n,B ) are activated, which allows data to be selectively read from and / or written to data storage element 302. Depending on where memory cell 106'' is located within DP-SRAM device 102 of Fig. If the bit lines are arranged in 1, the bit lines 318 can be connected to the upper bit lines 118 from Fig. 1 or the lower bit lines 120 of Fig. 1 corresponds.

[0049] With respect to Port A, a first access transistor 310 (AT1) is electrically coupled to the first data storage node 308a, and a second access transistor 312 (AT2) is electrically coupled to the second data storage node 308b. The first access transistor 310 selectively couples the first data storage node 308a via bit line BL. x, <tp bt> ,A < / tp> based on a tension of the word line WL n,A , while the second access transistor 312 selectively connects the second data storage node 308b with bit line BL' x, <tp bt> ,A < / tp> based on the tension of the word line WL n,A electrically couples. Bit lines BL x, <tp bt> ,A < / tp> and BL' x, <tp bt> ,A < / tp> They are complementary and therefore form a CBL pair. With respect to Port B, a third access transistor 314 (AT3) is electrically coupled to the first data storage node 308a, and a fourth access transistor 316 (AT4) is electrically coupled to the second data storage node 308b. The third access transistor 314 selectively couples the first data storage node 308a to bit line BL. x, <tp bt> ,B < / tp> based on a tension of the word line WL n,B , while the fourth access transistor 316 selectively connects the second data storage node 308b with bit line BL' x, <tp bt> ,B < / tp> based on the tension of the word line WL n,B electrically couples. Bit lines BL x, <tp bt> ,B < / tp> , BL' x, <tp bt> , B < / tp> are complementary and therefore form a CBL pair.

[0050] With reference to Fig. Figure 3B is a schematic view of some more detailed embodiments of the 106'' memory cell. Figure 300B is a schematic view of some more detailed embodiments of the 106'' memory cell. Fig. 3A is provided. As shown, the first inverter 304 includes a first pull-up transistor 320 (PU1) and a first pull-down transistor 322 (PD1). Furthermore, the second inverter 306 includes a second pull-up transistor 324 (PU2) and a second pull-down transistor 326 (PD2).

[0051] With reference to Fig. Figure 4 is a block diagram of some other embodiments of the DP-SRAM device 102. Fig. 1 provided. As shown, the upper bit lines 118 each comprise upper twist cells 402, 403 in the upper memory cell subarray 108 between row 1 and row M, and the lower bit lines 120 each comprise lower twist cells 404, 405 in the lower memory cell subarray 110 between row M+1 and row N. For example, the upper twist cells 402, 403 may be located midway between row 1 and row M, and / or the lower twist cells 404, 405 may be located midway between row M+1 and row N. The upper and lower twist cells 402, 403, 404, 405 are each configured to twist a pair of adjacent bit lines and are each formed from a pair of cross sections 406, which are discussed and illustrated in detail below.

[0052] Twisting a pair of adjacent bit lines (e.g. BL') 1,TP,A and BL' 1,TP,B ) includes crossing a first bit line of the pair (e.g. BL') 1,TP,B ) over a second bit line of the pair (e.g. BL') 1,TP,A Although not in Fig. As shown in Figure 4, the first bit line crosses the second bit line at a distance from the second bit line in a direction that is essentially perpendicular to the rows and columns, so that it does not contact the second bit line. For example, the first bit line may be located in a metal-2 layer of a BEOL interconnect structure, and the second bit line may be located in a metal-0 layer of the BEOL interconnect structure, while the first and second bit lines cross. Furthermore, in some embodiments, twisting a pair of adjacent bit lines (e.g., BL) involves 1,BT,A and BL 1,BT,B ) a swapping of axes along which the bit lines extend. Suppose that, for example, a first bit line (e.g., BL) is located before a twist cell (e.g., a twist cell 408). 1,BT,A ) of the pair extends laterally along a first axis, and a second bit line (e.g. BL) 1,BT,B ) of the pair extends laterally along a second axis that is parallel to the first axis. After the twisting cell, the first bit line (e.g., BL) can 1,BT,A ) extend laterally along the second axis, and the second bit line (e.g. BL) 1,BT,B ) can extend laterally along the first axis.

[0053] Advantageously, the upper and lower twisted cells 402, 403, 404, 405 facilitate low capacitive coupling between the upper and lower bit lines 118, 120, since the upper and lower twisted cells 402, 403, 404, 405 break parallel surfaces of the upper and lower bit lines 118, 120. This, in turn, leads to high capacitive matching between pairs of CBLs (e.g., BL). 1,TP,A / BL' 1,TP,A ) as well as high read and write times and good signal-to-noise ratios.

[0054] The upper twisting cells 402, 403 comprise left upper twisting cells 402 on the left sides of respective columns and right upper twisting cells 403 on the right sides of respective columns. In some embodiments, the upper twisting cells 402, 403 comprise a pair of upper twisting cells 402a, 403a for each column, the pair comprising a left upper twisting cell 402a and a right upper twisting cell 403a. Similarly, the lower twisting cells 404, 405 comprise left lower twisting cells 404 on the left sides of respective columns and right lower twisting cells 405 on the right sides of respective columns. In some embodiments, the lower twisting cells 404, 405 comprise a pair of lower twisting cells 404a, 405a for each column, wherein the pair comprises a left lower twisting cell 404a and a right lower twisting cell 405a.

[0055] In some embodiments, a left twist cell 410 of a twist cell pair (e.g. 402a / 403a or 404a / 405a) twists Port A and Port B bit lines (e.g. BL). 1,TP,A and BL 1,TP,B ), which are adjacent on the left side of a column. The Port A and Port B lines that are adjacent on the left side of the column correspond to the upper bit lines 118 for the upper twist cells 402, 403 and correspond to the lower bit lines 120 for the lower twist cells 404, 405. A right twist cell 412 of the twist cell pair twists Port A and Port B bit lines (e.g. BL' 1,TP,A and BL' 1,TP,B ), which are adjacent on the right side of the column, and which are complementary to the Port A and Port B bit lines which are adjacent on the left side of the column. Similar to the left twisted cells 410, the Port A and Port B lines which are adjacent on the right side of the column correspond to the upper bit lines 118 for the upper twisted cells 402, 403 and correspond to the lower bit lines 120 for the lower twisted cells 404, 405.

[0056] A flying bit line section 414 is located laterally between the adjacent bit lines (e.g. BL'). 1,BT,A and BL' 1,BT,B ) each of the lower twisted cells is spaced 404, 405 apart. Assume, for example, that a first bit line (e.g. BL) 1,BT,A ) of a twisted cell (e.g., a twisted cell 408) extends laterally along a first axis, and a second bit line (e.g., BL) 1,BT,B ) of the twisting cell extends laterally along a second axis parallel to the first axis. In this example, the flying bit line segment 414 can extend laterally along a third axis parallel to the first and second axes and spaced laterally between the first and second axes. Although not in Fig. As can be seen in Figure 4, in some embodiments the flying bit line section 414 is further spaced from the lower twisted cells 404, 405 in a direction that is essentially perpendicular to the rows and columns of the memory cell array 104, so that the flying bit line section 414 “flies” over the lower twisted cells 404, 405.

[0057] With reference to Fig. 5A is a layout view 500A of some embodiments of bit lines 118', 120' within a column of the DP-SRAM device 102 of Fig. 4 provided. As shown, Fig. 5A a variation of Fig. 2A, in which upper bit lines 118' comprise upper twisted cells 402', 403' over an upper memory cell subarray 108, and in which lower bit lines 120' comprise lower twisted cells 404', 405' over a lower memory cell subarray 110. The upper and lower twisted cells 402', 403', 404', 405' are each configured such that they comprise a pair of adjacent bit lines (e.g. BL). x,TP,A and BL xTP,B ), which comprises a Port A bit line and a Port B bit line adjacent to the Port A bit line, are twisted. Furthermore, the upper and lower twisting cells 402', 403', 404', 405' are each formed from a cross-under section 406a' and a cross-above section 406b'. The cross-under section 406a' is a section of a first bit line (e.g., BL'). x,BT,B ) in the pair of adjacent bit lines, which is under a second bit line (e.g. BL') x,BT,A ) in the pair of adjacent bit lines, and the cross-over section 406b' is a section of the second bit line that crosses over the first bit line.

[0058] In some embodiments, each pair of adjacent bit lines extends (e.g. BL') x,BT,A and BL' x,BT,B ), which are twisted by the upper and lower twist cells 402', 403', 404', 405', laterally in a metal O layer of a BEOL interconnect structure to form a corresponding twist cell (e.g., a twist cell 501). At the twist cell, the adjacent bit lines cross each other by means of a cross-below section (e.g., a cross-below section 502) and a cross-above section (e.g., a cross-above section 503).

[0059] For example, the adjacent bit lines (e.g. BL') increase x,BT,A and BL' x,BT,B ) upwards from the metal 0 layer to a metal 2 layer of the BEOL interconnect structure via first vias 504 and extend laterally along the gap in the metal 2 layer. A first bit line (e.g. BL') x,BT,A ) of the adjacent bit lines extends over a second bit line (e.g. BL') x,BT,B ) of the adjacent bit lines in the metal 2 layer, and the adjacent bit lines then descend to a metal 1 layer of the BEOL interconnect structure via two vias 506. Within the metal 1 layer, the first bit line (e.g. BL') extends x,BT,A ) laterally towards the second bit line and vice versa. After extending towards the first bit line, the second bit line rises (e.g. BL'). x,BT,B ) down to the metal 0 layer via a third via 508 and extends along the gap in the metal 0 layer. On the other hand, the first bit line (e.g. BL') rises. x,BT,A ) up to the metal 2 layer via a fourth via 510 after extending to the second bit line. The first bit line also extends laterally along the gap in the metal 2 layer. Subsequently, the first bit line descends to the metal 0 layer via a fifth via 512 and extends along the gap in the metal 0 layer.

[0060] Although the preceding example describes a specific embodiment of the upper and lower twisted cells 402', 403', 404', 405', it is understood that other embodiments of the upper and lower twisted cells 402', 403', 404', 405' are possible. For example, while the adjacent bit lines cross in the metal 0 layer and the metal 2 layer in the preceding example, the adjacent bit lines may cross in other metal layers.

[0061] Furthermore, in some embodiments, each of the lower twisting cells 404', 405' has one of the flying bit line sections 122' (e.g., the flying bit line section of BL'). x,TP,B ) on, which is laterally between the adjacent bit lines (e.g. BL' x,BT,A and BL' x,BT,B ) of the lower twisted cell, and / or each of the upper and lower twisted cells 402', 403', 404', 405' has one of the Vss line(s) 206, which is laterally between the adjacent bit lines (e.g. BL) x,TP,A and BL x,TP,B ) of the twisting cell. In some embodiments, the flying bit line segments 122' extend laterally in a metal 2 layer of a BEOL interconnect structure, such that the flying bit line segments 122' "fly" over the lower twisting cells 404', 405'. Furthermore, in some embodiments, the Vss line(s) 206 extends laterally in a metal 0 layer of a BEOL interconnect structure, such that the Vss line(s) 206 lies under the upper and lower twisting cells 402', 403', 404', 405' and / or under the flying bit line segments 122'. Alternatively, in other embodiments the flying bit line sections 122' are located in the metal 0 layer and the Vss line(s) 206 are located in the metal 2 layer, so that the Vss line(s) 206 lies over the flying bit line sections 122'.

[0062] With reference to Fig. 5B is a cross-sectional view 500B of some embodiments of jump cells 126' within the column of Fig. 5A provided. The cross-sectional view 500B can be seen, for example, along line AA' in Fig. 5A is drawn, and the jump cells 126'' represent the jump cells 126' within the column of Fig. 5A. As shown, is Fig. 5B a variation of Fig. 2B, in which the jump cells 126'' are designed such that they are connected to the upper and lower twisting cells 402', 403', 404', 405' of Fig. 5A can be integrated.

[0063] With reference to Fig. 5C is a cross-sectional view 500C of some embodiments of a lower twisting cell 405'' within the column of Fig. 5A provided. The lower twist cell 405'' represents each of the lower twist cells 404', 405' within the column of Fig. 5A and each of the upper twisting cells 402', 403' within the column of Fig. 5A by omitting flying bit line sections 122'''. Furthermore, the cross-sectional view 500C can be, for example, along line BB' in Fig. 5A is drawn, extending along a cross-under section 406a'' of the lower twist cell 405''. As shown, metal layers M0, M1, M2 and via layers V1, V2 of a BEOL interconnect structure 210 are stacked to define the lower twist cell 405''. The lower twist cell 405'' comprises the cross-under section 406a'' and a cross-over section 406b''.

[0064] The cross-subsection 406a'' is part of a first bit line 514 (e.g. BL') x,BT,B from Fig. 5A) and the cross-above section 406b'' is part of a second bit line 516 (e.g. BL' x'BT,A from Fig. 5A). Furthermore, the cross-under section 406a'' and the cross-over section 406b'' are formed from several metal conductors 518 and vias 520. The cross-under section 406a'' crosses under the second bit line 516, and the cross-over section 406b'' crosses over the first bit line 514 to intersect the first and second bit lines 514, 516. In some embodiments, the cross-under section 406a'' also crosses over a Vss line 206'' and / or under one of the flying bit line sections 122'''.

[0065] In some embodiments, the cross-under section 406a'' ascends from a metal 0 layer (i.e., M0) to a metal 2 layer (i.e., M2) via a first via 504a' traversing a via 1 layer (i.e., V1) and a via 2 layer (i.e., V2), and then descends to a metal 1 layer (i.e., M1) via a second via 506a' in the via 2 layer. At the metal 1 layer, the cross-under section 406a'' crosses over the Vss line 206'' and / or under one of the flying bit line sections 122''' before descending again to the metal 0 layer via a third via 508' in the via 1 layer. After descending back to the metal 0 layer, the cross-lower section 406a'' runs below the cross-upper section 406b''.Furthermore, in some embodiments, the cross-top section 406b'' descends from the metal 2 layer to the metal 1 layer via a fourth via 506b' in the via 2 layer.

[0066] With reference to Fig. 5D is another cross-sectional view 500D of some embodiments of a lower twisting cell 404'' within the column of Fig. 5A provided. The lower twist cell 404'' represents each of the lower twist cells 404', 405' within the column of Fig. 5A and each of the upper twisting cells 402', 403' within the column of Fig. 5A by omitting flying bit line sections 122''. Furthermore, the other cross-sectional view 500D can, for example, be along line CC' in Fig. 5A is drawn, extending along a cross-above section 406b''' of the lower twist cell 404''. As shown, metal layers M0, M1, M2 and via layers V1, V2 of a BEOL interconnect structure 210 are stacked to define the lower twist cell 404''. The lower twist cell 404'' comprises a cross-below section 406a''' and the cross-above section 406b'''.

[0067] The cross-subsection 406a''' is part of a first bit line 514' (e.g. BL) x,BT,B from Fig. 5A) and the cross-above section 406b''' is part of a second bit line 516' (e.g. BL) x,BT,A from Fig. 5A). Furthermore, the cross-below section 406a''' and the cross-above section 406b''' are formed from several metal conductors 518' and vias 520'. The cross-below section 406a''' crosses under the second bit line 516', and the cross-above section 406b''' crosses over the first bit line 514' to cross the first and second bit lines 514', 516'. In some embodiments, the cross-above section 406a''' also crosses over a Vss line 206' and / or under one of the flying bit line sections 122''.

[0068] In some embodiments, the cross-above section 406b''' ascends from a metal 0 layer (i.e., M0) to a metal 2 layer (i.e., M2) via a first via 504b'' that extends through a via 1 layer (i.e., V1) and a via 2 layer (i.e., V2), and then crosses over the cross-below section 406a'''. After crossing over the cross-below section 406a''', the cross-above section 406b''' descends to a metal 1 layer (i.e., M1) via a second via 506b'' in the via 2 layer. At the metal-1 layer, the cross-above section 406b''' crosses over the Vss line 206' and / or under one of the flying bit line sections 122'', before rising again to the metal-2 layer via a third via 510' in the via-2 layer.After ascending back to the metal-2 layer, the cross-top section 406b''' descends from the metal-2 layer to the metal-0 layer via a fourth via 512', which extends through the via-1 layer and the via-2 layer. Furthermore, in some embodiments, the cross-bottom section 406a''' descends from the metal-1 layer to the metal-0 layer via a fifth via 508'' in the via-1 layer.

[0069] With reference to Fig. Figure 6 is a block diagram of some other embodiments of the DP-SRAM device 102. Fig. 1 is provided, in which the input / output (I / O) is distributed between opposite sides of the DP-SRAM device 102. As shown, the DP-SRAM device 102 comprises a set of upper Port A bit lines 118a, a set of upper Port B bit lines 118b, a set of lower Port A bit lines 120a, and a set of lower Port B bit lines 120b. The upper Port A bit lines 118a comprise a pair of CBLs (e.g., BL). X,TP,A / BL' X,TP,A ) for each column, and the upper Port B bit lines 118b comprise a pair of CBLs (e.g. BL) x,TP,B / BL' X,TP,B ) for each column. Similarly, the lower Port A bit lines 120a comprise a pair of CBLs (e.g., BL). X,BT,A / BL' X,BT,A ) for each column, and the lower Port B bit lines 120b comprise a pair of CBLs (e.g. BL) x,BT,B / BL' X,BT,B ) for each column.

[0070] The lower Port A bit lines 120a are connected to memory cells (e.g., MC). 2,M+1 or MC x,N The lower memory cell subarray 110, located in the respective columns, are electrically coupled. Furthermore, each lower Port A bit line 120a comprises a flying Port A bit line segment 122a, a local Port A bit line segment 124a, and a Port A jump cell 126a. The flying Port A bit line segments 122a extend along the respective columns from a first side of the memory cell array 104 and terminate between the upper and lower memory cell subarrays 108, 110. The local Port A bit line segments 124a extend from the space between the upper and lower memory cell subarrays 108, 110 along the respective columns to a second side of the memory cell array 104, opposite the first side.The Port A jump cells 126a are located between the upper and lower memory cell subarray 108, 110 and electrically couple the flying Port A bit line sections 122a to the local Port A bit line sections 124a.

[0071] The upper Port B bit lines 118a are connected to memory cells (e.g., MC). 2,1 or MC X,M The upper memory cell subarray 108, located in the respective columns, are electrically coupled. Furthermore, the upper Port B bit lines 118a each comprise a flying Port B bit line segment 122b, a local Port B bit line segment 124b, and a Port B jump cell 126b. The flying Port B bit link segments 122b extend along respective columns from the second side of the memory cell array 104 and terminate between the upper and lower memory cell subarrays 108, 110. The local Port B bit link segments 124b extend from the space between the upper and lower memory cell subarrays 108, 110 along the respective columns to the second side of the memory cell array 104. The Port B jump cells 126b are located between the upper and lower memory cell subarrays 108, 110 and electrically couple the flying Port B bit link segments 122b to the local Port B bit link segments 124b.

[0072] The upper Port A bit lines 118a extend laterally along their respective columns from the first side of the memory cell array 104 and terminate between row M and the Port A jump cells 126a. Similarly, the lower Port B bit lines 120b extend laterally along their respective columns from the second side of the memory cell array 104 and terminate between row M+1 and the Port B jump cells 126b. The upper Port A bit lines 118a are connected to memory cells (e.g., MC). x,1 or MC 2,M ) of the upper memory cell subarray 108, which are located in the respective columns, are electrically coupled, and the lower Port B bit lines 120b are connected to memory cells (e.g. MC) X,N or MC 1,M+1 ) of the lower memory cell subarray 110, which are located in the respective columns, are electrically coupled.

[0073] A Port AI / O array 130a is located on the first side of the memory cell array 104 and is configured to use the upper Port A bit lines 118a and the lower Port A bit lines 120a to read from and / or write to memory cells accessed by the word lines 112. In some embodiments, the Port AI / O array 130a is configured to output read data to a Port A data signal 132a on the first side of the memory cell array 104 and / or write data from the Port A data signal 132a. The Port AI / O array 130a is controlled by a controller 134 via Port A control signals 136a and comprises multiple Port AI / O cells 138.

[0074] A port BI / O array 130b is located on the second side of the memory cell array 104 and is configured to use the upper port B bit lines 118b and the lower port B bit lines 120b to read from and / or write to memory cells accessed by the word lines 112. In some embodiments, the port BI / O array 130b is configured to output read data to a port B data signal 132b on the second side of the memory cell array 104 and / or write data from the port B data signal 132b. The port BI / O array 130b is controlled by a controller 134 via port B control signals 136b and comprises multiple port BI / O cells 138b.

[0075] The Port A and Port BI / O cells 138a, 138b correspond to the columns of the memory cell array 104 and are configured as I / O <spalte> , <port>< / port> < / spalte> marked. Furthermore, the Port A and Port BI / O cells 138a, 138b are electrically coupled to the upper and lower bit lines of the corresponding columns. For example, the Port AI / O cells 138a are coupled to the upper Port A bit lines 118a (e.g., BL'). X,TP,A ) and the lower Port A bit lines 120a (e.g. BL) 1,BT,A ) electrically coupled, while the Port BI / O cells 138b are connected to the upper Port B bit lines 118b (e.g. BL' 2,TP,B ) and the lower Port B bit lines 120b (e.g. BL' X,BT,B ) are electrically coupled. The Port A and Port BI / O cells 138a, 138b each comprise a selection circuit 140 and a read / write circuit (R / W circuit) 142.

[0076] The selection circuits 140 are designed to form pairs of CBLs (e.g. BL) 1,TP,A / BL' 1,TP,A ), which correspond to the Y-bit addresses on the address signals 116. In some embodiments, the selection circuits 140 each comprise a pair of subarray multiplexers 144 configured to select between respective upper bit lines (i.e., bit lines of the upper memory cell subarray 108) and respective lower bit lines (i.e., bit lines of the lower memory cell subarray 110). In contrast to the embodiments of Fig. 1 and Fig. 4. Port multiplexers (e.g., the port multiplexer 146 from Fig. 1 and Fig. 4) are advantageously omitted since each port has an I / O array. The R / W circuits 142 are configured to read from and / or write to access memory cells corresponding to the selected pairs of CBLs, based on R / W signals 148 for each port. In some embodiments, the R / W circuits 142 are also configured to output data read from the access memory cells to the Port A and Port B data signals 132a, 132b, and / or to write data input on the Port A and Port B data signals 132a, 132b to the access memory cells.

[0077] In some embodiments, the Port A data signals 132a are routed to the Port AI / O arrays 130a via a Port A column decoder 150a, and the Port B data signals 132b are routed to the Port BI / O arrays 130b via a Port B column decoder 150b. The Port A and Port B column decoders 150a, 150b are configured to electrically couple the Port A and Port B data signals 132a, 132b, respectively, to the Port A and Port BI / O cells 138a, 138b corresponding to the Y-bit addresses. For example, if a Y-bit address is on the Port A address signal (i.e., ADDR) A ) If memory cells in columns 1 to X are displayed, the Port A column decoder 150a can display bits 1 to X on the Port A data signal 132a (i.e., DATA). A ) each to the port AI / O cells (e.g. I / O 1,A to I / O X,A ) for columns 1 to X.

[0078] With reference to Fig. 7A is a layout view 700A of some embodiments of bit lines 118a', 118b', 120a', 120b' within a column of the DP-SRAM device 102 of Fig. 6 provided. As shown, Fig. 7A a variation of Fig. 2A, in which I / O is distributed between opposite ends of the column. For example, Port-AI / O is located at one end of the column, and Port-BI / O is located at the other end of the column, opposite the first end.

[0079] Lower Port A bit lines 120a' (e.g. BL) x,BT,A / BL' x,BT,A The lower Port A bit lines 120a' extend from Port A subarray multiplexers 144a' at the first end of the column, laterally along the column, to the second end of the column. Furthermore, each lower Port A bit line 120a' comprises a flying Port A bit line segment 122a', a local Port A bit line segment 124a', and a Port A jump cell 126a'. The flying Port A bit line segments 122a' extend over an upper memory cell subarray 108, and the local Port A bit line segments 124a' extend over a lower memory cell subarray 110 to be electrically coupled to memory cells in the lower memory cell subarray 110.

[0080] Similarly, upper Port B bit lines extend 118b' (e.g. BL). x,TP,B / BL' x,TP,B ) of Port B subarray multiplexers 144b' at the second end of the column laterally along the column to the first end. Furthermore, the upper Port B bit lines 118b' each comprise a flying Port B bit line segment 122b', a local Port B bit line segment 124b', and a Port B jump cell 126b'. The flying Port B bit line segments 122b' extend over the lower memory cell subarray 110, and the local Port B bit line segments 124b' extend over the upper memory cell subarray 108 to be electrically coupled to memory cells in the upper memory cell subarray 108.

[0081] In some embodiments, the flying Port A and Port B bit line segments 122a', 122b' are located in the same metal layer of a BEOL interconnect structure as the local Port A and Port B bit line segments 124a', 124b'. For example, the flying Port A and Port B bit line segments 122a', 122b' and the local Port A and Port B bit line segments 124a', 124b' may be located in a single Metal 2 layer. Alternatively, in other embodiments, the flying Port A and Port B bit line segments 122a', 122b' are located in a different metal layer of a BEOL interconnect structure than the local Port A and Port B bit line segments 124a', 124b'. For example, the flying Port A and Port B bit line sections 122a', 122b' can be located in a Metal 2 layer, and the local Port A and Port B bit line sections 124a', 124b' can be located in a Metal 0 layer.

[0082] The Port A jump cells 126a' are located between the upper and lower memory cell subarrays 108, 110 and electrically couple the flying Port A bit line segments 122a' to the local Port A bit line segments 124a'. Similarly, the Port B jump cells 126b' are located between the upper and lower memory cell subarrays 108, 110 and electrically couple the flying Port B bit line segments 122b' to the local Port A bit line segments 124b'. Furthermore, each Port A jump cell 126a' includes a Port A transition bit line segment 203a', and each Port B jump cell 126b' includes a Port B transition bit line segment 203b'. The Port A and Port B transition bit line sections 203a', 203b' are electrically coupled to the flying Port A and Port B bit line sections 122a', 122b' and the local Port A and Port B bit line sections 124a', 124b' via second vias 204.In some embodiments, the flying Port A and Port B bit line sections 122a', 122b' are located in a first metal layer (e.g., a Metal 2 layer), the local Port A and Port B bit line sections 124a', 124b' are located in a second metal layer (e.g., a Metal 0-Metal layer), and the Port A and Port B transition bit line sections 203a', 203b' are located in a third metal layer (e.g., a Metal 1 layer) between the first and second metal layers.

[0083] Upper port A bit lines 118a' (e.g. BL x,TP,A / BL' x,TP,A ) extend laterally along the column, each from the Port A subarray multiplexers 144a', and terminate between the upper and lower memory cell subarrays 108, 110. Furthermore, the upper Port A bit lines 118a' are electrically coupled to the memory cells 106a' in the upper memory cell subarray 108. Similarly, lower Port B bit lines 120b' (e.g., BL) extend x,BT,B / BL' x,BT,B ) laterally along the column, each from the Port B subarray multiplexers 144b', and terminate between the upper and lower memory cell subarrays 108, 110. In addition, the lower Port B bit lines 120b' are electrically coupled to the memory cells 106b' in the lower memory cell subarray 110.

[0084] In some embodiments, the upper Port A bit lines 118a' and the lower Port B bit lines 120b' extend along the same metal layer of a BEOL interconnect structure as the local Port A and Port B bit line segments 124a', 124b'. In some embodiments, the upper Port A bit lines 118a' and the lower Port B bit lines 120b' also extend along the same metal layer of the BEOL interconnect structure as the flying Port A and Port B bit line segments 122a', 122b'. In some embodiments, the upper Port A bit lines 118a' and the lower Port B bit lines 120b' also extend along a different metal layer of the BEOL interconnect structure than the flying Port A and Port B bit line sections 122a', 122b' and / or than the local Port AB and Port B bit line sections 124a', 124b'.For example, the upper Port A bit lines 118a' and the lower Port B bit lines 120b' can extend along a Metal 0 layer with the local Port A and Port B bit line sections 124a', 124b', and the flying Port A and Port B bit line sections 122a', 122b' can extend along a Metal 2 layer.

[0085] As also shown in layout view 700A, one or more Vss lines 206 extend laterally from the first end of the column to the second end of the column and are connected to the memory cells 106a', 106b' of the column (e.g. MC). x,1 to MC x,N ) electrically coupled. In some embodiments, the Vss line(s) 206 extends laterally in the metal O layer and / or are coupled by flying Port A bit line segments (e.g., the flying bit line segments of BL). x,BT,A and BL' x,BT,A ) overlaps. Alternatively, in some embodiments, the Vss line(s) 206 extends laterally in the metal 2 layer and / or overlaps flying Port A bit line segments (e.g., the flying bit line segments of BL). x,BT,A and BL' x,BT,A ).

[0086] With reference to Fig. 7B is a cross-sectional view 700B of some embodiments of jump cells 126a'', 126b'' within the column of Fig. 7A provided. The cross-sectional view 700B can be seen, for example, along line AA' in Fig. 7A is drawn, and the jump cells 126a'', 126b'' represent the jump cells 126a', 126b' within the column of Fig. 7A.

[0087] As shown, metal layers M0, M1, M2 and via layers V1, V2 define a lower Port A bit line 120a'' and an upper Port B bit line 118b''. The lower Port A bit line 120a'' and the upper Port B bit line 118b'' each comprise a flying bit line segment 122a'', 122b'', a transition bit line segment 203a', 203b', and a local bit line segment 124a'', 124b''. The flying bit line segment 122a'', 122b'' is located in a different metal layer than the local bit line segment 124a'', 124b'', and the transition bit line segment 203a', 203b' is located in a metal layer between the different metal layers. For example, the flying bit line section 122a'', 122b'' can be located in a metal 2 layer (i.e., M2), the transition bit line section 203a', 203b' can be located in a metal 1 layer (i.e.,The local bit line segment 124a'', 124b'' is located in a metal 0 layer (i.e., M0). Furthermore, the lower Port A bit line 120a'' and the upper Port B bit line 118b'' each include a first via 204a' and a second via 204b'. The first via 204a' electrically couples the local bit line segment 124a'', 124b'' to the transition bit line segment 203a', 203b', for example, in a via-1 layer (i.e., V1). The second via 204b' electrically couples the transition bit line segment 203a', 203b' to the flying bit line segment 122a'', 122b'', for example, in a via-2 layer (i.e., V2).

[0088] With reference to Fig. Figure 8 is a block diagram of some other embodiments of the DP-SRAM device 102. Fig. 6 provided. As shown, I / O for Port A and Port B is compared to Fig. 6 conversely. Furthermore, upper bit lines 118a, 118b each comprise upper twist cells 402, 403 between row 1 and row M, and lower bit lines 120a, 120b each comprise lower twist cells 404, 405 between row M+1 and row N. The upper and lower twist cells 402, 403, 404, 405 are each configured to twist a pair of adjacent bit lines, and each is formed from a pair of cross segments 406. Furthermore, the upper and lower twist cells 402, 403, 404, 405 are configured as described with reference to Fig. 4 described. In some embodiments, each of the upper twisting cells 402, 403 has one of the flying Port B bit line segments 122b (e.g. the flying bit line segment of BL'). X,BT,B ) which is spaced laterally between the adjacent bit lines of the upper twisted cell, and / or each of the lower twisted cells 404, 405 has one of the flying Port A bit line sections 122a (e.g. the flying bit line section of BL) 1,BT,A ) which is spaced laterally between the adjacent bit lines of the lower twisted cell.

[0089] With reference to Fig. 9A is a layout view 900A of some embodiments of bit lines 118a', 118b', 120a', 120b' within a column of the DP-SRAM device 102 of Fig. 8 provided. As shown, Fig. 9A a variation of Fig. 7A, in which the I / O for Port A and Port B is reversed. Furthermore, upper bit lines 118a', 118b' comprise upper twist cells 402', 403' over an upper memory cell subarray 108, and lower bit lines 120a', 120b' comprise lower twist cells 404', 405' over a lower memory cell subarray 110. The upper and lower twist cells 402', 403', 404', 405' are each configured to twist a respective pair of adjacent bit lines and are each formed from a cross-below section 406a' and a cross-above section 406b'. Furthermore, the upper and lower twisting cells 402', 403', 404', 405' are designed as described with reference to Fig. 5A described.

[0090] In some embodiments, each of the upper twisting cells 402', 403' has one of the flying Port B bit line segments 122b' (e.g., the flying bit line segment of BL'). x,BT,B ) on, which is laterally between the adjacent bit lines (e.g. BL' x,TP,A / BL' x,TP,B ) of the upper twist cell, and / or each of the lower twist cells 404', 405' has one of the flying Port A bit line segments 122a' (e.g. the flying bit line segment of BL' x,TP,A ) on, which is laterally between the adjacent bit lines (e.g. BL' x,BT,A and BL' x,BT,B ) of the lower twisting cell. In addition, in some embodiments, each of the upper and lower twisting cells 402', 403', 404', 405' has one of the Vss line(s) 206, which is spaced laterally between the adjacent bit lines (e.g. BL'). x,BT,A and BL' x,BT,B ) the twisting cell is (are).

[0091] With reference to Fig. 9B is a cross-sectional view 900B of some embodiments of jump cells 126a'', 126b'' within the column of Fig. 9A provided. The cross-sectional view 900B can be seen, for example, along line AA' in Fig. 9A is drawn, and the jump cells 126a'', 126b'' represent the jump cells 126a', 126b' within the column of Fig. 9A. As shown, is Fig. 9B a variation of Fig. 7B, in which a Port-A jump cell 126a'' is arranged along an upper Port-A bit line 118a'', and in which a Port-B jump cell 126b'' is arranged along a lower Port-B bit line 120b'', such that it is connected to the upper and lower twist cells 402', 403', 404', 405' of Fig. 9A will be integrated.

[0092] With reference to Fig. 9C is a cross-sectional view 900C of some embodiments of a lower twisting cell 405'' within the column of Fig. 9A provided. The lower twist cell 405'' represents each of the lower twist cells 404', 405' within the column of Fig. 9A and each of the upper twisting cells 402', 403' within the column of Fig. 9A. Furthermore, the cross-sectional view 900C can be, for example, along line BB' in Fig. 9A is drawn, extending along a cross-under section 406a'' of the lower twisting cell 404''. As shown, Fig. 9C a variation of Fig. 5C, in which the lower twisting cell 405'' was modified to accommodate Port-A and Port-BI / O on opposite sides of the column. In contrast to the embodiments of Fig. 5C show the embodiments of Fig. 9C a single flying bit line section 122a'''.

[0093] With reference to Fig. 9D is another cross-sectional view 900D of some embodiments of a lower twisting cell 404'' within the column of Fig. 9A provided. The lower twist cell 404'' represents each of the lower twist cells 404', 405' within the column of Fig. 9A and each of the upper twisting cells 402', 403' within the column of Fig. 9A. Furthermore, the cross-sectional view 900D can, for example, be displayed along line CC' in Fig. 9A is drawn, extending along a cross-upper section 406b'' of the lower twisting cell 404''. As shown, Fig. 9D is a variation of Fig. 5D, in which the lower twisting cell 404'' was modified to accommodate Port-A and Port-BI / O on opposite sides of the column. In contrast to the embodiments of Fig. 5D show the embodiments of Fig. 9D a single flying bit line section 122a''.

[0094] With reference to Fig. Figure 10A provides a block diagram 1000A of some embodiments of a multi-bank DP-SRAM device 1002. As shown, the multi-bank DP-SRAM device 1002 comprises L memory banks 1004, where L is an integer greater than 0. The L memory banks 1004 are memory cell arrays, each of which has N rows of memory cells and X columns of memory cells. N and X are integers greater than zero and can, for example, be the same across the L memory banks 1004. Furthermore, each of the L memory banks 1004 has the same configuration of memory cells and bit lines as the memory cell array 104 of Fig. 1 or Fig. 4.

[0095] The L memory banks 1004 each comprise an upper memory cell subarray 1006, a lower memory cell subarray 1008, and jump cells 1010. In some embodiments, the L memory banks 1004 also each comprise upper twist cells 1012 and lower twist cells 1014. The upper and lower memory cell subarrays 1006 and 1008 are configured in the same way as the upper and lower memory cell subarrays 108 and 110 in [reference missing]. Fig. 1 or Fig. 4. Therefore, the upper memory cell subarrays 1006 hold memory cells in rows 1 to M of the L memory banks 1004, and the lower memory cell subarrays 1006 hold memory cells in rows M+1 to N of the L memory banks 1004, where M is an integer greater than zero and less than N.

[0096] The jump cells 1010 are located between the upper and lower memory cell subarrays 1006 and 1008 and can, for example, be designed in the same way as the jump cells 126. Fig. 1 or Fig. 4. The upper twisting cells 1012 are located in the upper memory cell subarrays 1006 and can, for example, be designed in the same way as the upper twisting cells 402, 403 of Fig. 4. The lower twist cells 1014 are located in the lower memory cell subarrays 1008 and can, for example, be designed in the same way as the lower twist cells 404, 405 of Fig. 4.

[0097] Since the L memory banks 1004 each have the same configuration of memory cells and bit lines as the memory cell array 104 of Fig. 1 or Fig. 4. Advantageously, the multi-bank DP-SRAM device 1002 uses separate bit lines for the upper memory cell subarrays 1006 and the lower memory cell subarrays 1008. This results in low loads on the bit lines, allowing the L memory banks 1004 to be large. Furthermore, the large memory banks enable the multi-bank DP-SRAM device 1002 to have a small footprint (e.g., a small footprint). For a given memory size, a few large memory banks use less space than many small memory banks.

[0098] A set of word lines 1016 is shared by the L memory banks 1004 and facilitates access to memory cells of the L memory banks 1004 on a line-by-line basis. The word lines 1016 include a Port A word line (e.g., WL). 1,A ) for each line and one Port B word line (e.g. WL) 1,B ) for each line. Furthermore, the word lines 1016 extend laterally from a line decoder 1018 along the respective lines to be electrically coupled to memory cells in the corresponding lines for each of the L memory banks 1004. The line decoder 1018 is designed to selectively activate the word lines 1016 for Port A and Port B based on address signals 1020. The address signals 116 carry respective Y-bit addresses, where Y is an integer greater than zero.

[0099] Several I / O arrays 1022, corresponding to the L memory banks 1004, are configured to use the bit lines of the L memory banks 1004 to read from and / or write to memory cells accessed by the word lines 1016 and the line decoder 1018. Furthermore, the I / O arrays 1022 are configured to output data read from the access memory cells to data signals 1024 for Port A and Port B, respectively, and / or to write data input on the data signals 1024 to the access memory cells. The data signals 1024 carry Z bit data values, where Z is an integer greater than zero. The I / O arrays 1022 are formed from I / O cells (not shown) and are each configured like the I / O array 130 of Fig. 1 or Fig. 4.

[0100] In some embodiments, the data signals 1024 are routed to the I / O arrays 1022 via a column decoder 1026. The column decoder 1026 is designed to electrically couple the data signals 1024 to I / O cells corresponding to the Y-bit addresses. For example, a Y-bit address (e.g., on ADDR) A The column decoder 1026 electrically couples bits 1 to Z of a data signal (e.g., DATA) to Z memory cells distributed across a series of Z memory banks (e.g., memory banks 1 to Z). A ) for the port with the I / O cells for the Z memory cells.

[0101] A controller 1028 is designed to control the I / O arrays 1022 and, in some embodiments, the row decoder 1018 and / or the column decoder 1026 to perform read and / or write operations on Port A and Port B. Such control is based on R / W signals 1030 for Port A and Port B, respectively, and the address signals 1020. For example, memory cells corresponding to a Port AY bit address can be accessed via a Port A word line (e.g., WL) M,A ) can be accessed. Afterwards, Port A bit lines (not shown) corresponding to the Port AY bit address can be selected, and a read or write operation can be performed on the selected bit lines. Such a read or write operation can vary depending on whether a Port AR / W signal (e.g., R / W) is present. A ) indicates a read operation or a write operation.

[0102] With reference to Fig. 10B is a block diagram 1000B of some other embodiments of the multi-bank DP-SRAM device 1002 by Fig. 10A provided. As shown, I / O is distributed between opposite sides of the multi-bank DP-SRAM device 1002, such that the L memory banks 1004 each have the same configuration of memory cells (not shown) and bit lines (not shown) as the memory cell array 104 of Fig. 6 or Fig. 8. Furthermore, for example, the jump cells 1010 can be used like the jump cells 126a, 126b of Fig. 6 or Fig. 8. Furthermore, in embodiments with the upper and lower twisting cells 1012, 1014, the upper twisting cells 1012 can, for example, be designed like the upper twisting cells 402, 403 of Fig. 8 be designed, and the lower twisting cells 1014 can, for example, be like the lower twisting cells 404, 405 of Fig. It should be designed for 8.

[0103] Several Port AI / O arrays 1022a are arranged on a first side of the multi-bank DP-SRAM device 1002, and several Port BI / O arrays 1022b are arranged on a second side of the multi-bank DP-SRAM device 1002 opposite the first side. In some embodiments, the Port AI / O arrays 1022a are adjacent to the upper memory cell subarrays 1006, and the Port BI / O arrays 1022b are adjacent to the lower memory cell subarrays 1008. In other embodiments, the Port AI / O arrays 1022a are adjacent to the lower memory cell subarrays 1008, and the Port BI / O arrays 1022b are adjacent to the upper memory cell subarrays 1006. The Port A and Port BI / O arrays 1022a, 1022b have the same configuration as the I / O arrays 130a, 130b of Fig. 6 or Fig. 8. Furthermore, in some embodiments, a Port-A column decoder 1026a is designed to electrically couple a Port-A data signal 1024a with the Port-AI / O arrays 1022a, and / or a Port-B column decoder 1026b is designed to electrically couple a Port-B data signal 1024b with the Port-BI / O arrays 1022b.

[0104] With reference to Fig. Figure 11 provides a flowchart of some embodiments of a method for reading and / or writing data using a flying and / or twisted bitline architecture.

[0105] At 1102, a storage device is provided. The storage device has a memory cell array that is subdivided into an upper memory cell subarray and a lower memory cell subarray. The storage device also has a first set of bit lines for the upper memory cell subarray and a second set of bit lines for the lower memory cell. The first set of bit lines includes a Port A pair of CBLs for each column of the memory cell array and a Port B pair of CBLs for each column of the memory cell array. Similarly, the second set of bit lines includes a Port A pair of CBLs for each column of the memory cell array and a Port B pair of CBLs for each column of the memory cell array.

[0106] In the 1104, an address signal and a read / write signal are provided on port A or B. The address signal carries an address that indicates a memory cell of the storage device. In some embodiments, the address also indicates one or more other memory cells of the storage device. The read / write signal indicates whether a read or write operation is to be performed.

[0107] At 1106, a determination is made based on the address as to whether the memory cell is located in the upper or lower memory cell subarray. If the memory cell is in the upper memory cell subarray, a corresponding pair of CBLs is selected from the first set of bit lines at 1108. If the memory cell is in the lower memory cell subarray, a corresponding pair of CBLs is selected from the lower memory cell subarray at 1110. In each case, the selection also takes into account the port on which the address is provided. Therefore, the selected pair of CBLs is a Port A pair if the address is provided on Port A, and a Port B pair if the address is provided on Port B.

[0108] At 1112, a word line of the storage device is activated to access a row of the memory cell array corresponding to the memory cell. The word line is a Port A word line if the address is provided on Port A, and a Port B word line if the address is provided on Port B.

[0109] At 1114, a determination is made whether to read from or write to the memory cell. This determination is based on the read / write signal. If a read determination is made, at 1116 a differential bias generated by the memory cell on the selected pair of CBLs is sampled to read data from the memory cell. If a write determination is made, at 1118 a differential bias is applied to the selected bit lines to write data to the memory cell.

[0110] Although flowchart 1100 is illustrated and described here as a series of processes or events, it is understood that the depicted sequence of such processes or events should not be interpreted restrictively. In addition to those shown and / or described here, some processes may, for example, occur in different sequences and / or simultaneously with other processes or events. Furthermore, processes not shown may be required to implement one or more aspects or embodiments of the description, and one or more of the processes shown here may be executed in one or more separate processes and / or phases.

[0111] In light of the foregoing, some embodiments of the present application provide a semiconductor memory device. An array of memory cells is arranged in rows and columns. The array comprises a first subarray of memory cells and a second subarray of memory cells. A first pair of CBLs extends along a column of the array from a first side of the array and terminates between the first and second subarrays. The first pair of CBLs is electrically coupled to memory cells of the first subarray in the column. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The second pair of CBLs is electrically coupled to memory cells of the second subarray in the column. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column.The third and fourth pairs of CBLs are each electrically coupled to the memory cells of the first subarray in the column and the memory cells of the second subarray in the column.

[0112] Furthermore, other embodiments of the present application provide a different semiconductor memory device. An array of memory cells is arranged in rows and columns. The array comprises a first subarray of memory cells and a second subarray of memory cells. A first pair of CBLs extends along a column of the array from a first side of the array and terminates between the first and second subarrays. The first pair of CBLs is electrically coupled to memory cells of the first subarray in the column. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The second pair of CBLs is electrically coupled to memory cells of the second subarray in the column. A third pair of CBLs and a fourth pair of CBLs extend along the column.The third and fourth pairs of CBLs are electrically coupled to the memory cells of the first subarray in the column and the memory cells of the second subarray in the column, respectively. A twist cell is designed to twist one pair of adjacent bit lines from each pair of CBLs extending along the column. These two pairs of CBLs correspond to two of the first, second, third, and fourth pairs of CBLs.

[0113] Furthermore, other embodiments of the present application provide yet another semiconductor memory device. An array of memory cells is arranged in rows and columns. The array comprises a first subarray of memory cells and a second subarray of memory cells. A first pair of CBLs extends along a column of the array from a first side of the array and terminates between the first and second subarrays. The first pair of CBLs is electrically coupled to memory cells of the first subarray in the column. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The second pair of CBLs is electrically coupled to memory cells of the second subarray in the column. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column.The third and fourth pairs of CBLs are electrically coupled to the memory cells of the first subarray and the memory cells of the second subarray, respectively. The CBLs of the third and fourth pairs of CBLs have stepped profiles between those of the first and second subarrays. A twist cell is designed such that one pair of adjacent bit lines is twisted. The adjacent bit lines each originate from two pairs of CBLs extending along the column, and these two pairs of CBLs correspond to two pairs from the first, second, third, and fourth pairs of CBLs.

[0114] The foregoing outlines features of several embodiments so that a person skilled in the art can better understand the aspects of the present disclosure. A person skilled in the art should recognize that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to accomplish the same tasks and / or achieve the same advantages as the embodiments presented herein. A person skilled in the art should also understand that such equivalent embodiments do not deviate from the inventive concept and scope of the present disclosure, and that they can make various changes, substitutions, and modifications here without deviating from the inventive concept and scope of the present disclosure.< / tp>

Claims

[1] Semiconductor storage device (102), comprising: an array (104) of memory cells (106) arranged in rows (N) and columns (X), wherein the array (104) comprises a first subarray (110) of memory cells (106) and a second subarray (108) of memory cells (106), a first pair of CBLs (120, 120b) extending along a column of the array (104), from a first side of the array (104), and terminating between the first and second subarray (108), wherein the first pair of CBLs (120, 120b) is electrically coupled to memory cells (106) of the first subarray (110) in the column, a second pair of CBLs (118, 118b) extending from the first side of the array (104), along the column, to a second side of the array (104), wherein the second pair of CBLs (118, 118b) is electrically coupled to memory cells (106) of the second subarray (108) in the column, and wherein the CBLs of the second pair of CBLs (118, 118b) have stepped profiles between the first and the second subarray (110, 108), a third pair of CBLs (120, 120a) and a fourth pair of CBLs (118, 118a) extending along the column, wherein the third and fourth pairs of CBLs (120, 120a, 118, 118a) are each electrically coupled to the memory cells (106) of the first subarray (110) in the column and the memory cells (106) of the second subarray (108) in the column, a set of word lines (112), a port AI / O array (130a) on the second or first side of the array (104) of memory cells (106), designed to use the fourth pair of CBLs (118, 118a) and the third pair of CBLs (120, 120a) to read from and / or write to memory cells (106) accessed by the word lines (112), and a port BI / O array (130b) on the first or second side of the array (104) of memory cells (106), designed to use the second pair of CBLs (118, 118b) and the first pair of CBLs (120, 120b) to read from and / or write to memory cells (106) accessed by the word lines (112). [2] Semiconductor storage device (102) according to claim 1, wherein the third pair of CBLs (120) extends along the column from the first side of the array (104) and terminates between the first and second subarray (108), and wherein the fourth pair of CBLs (118) extends from the first side of the array (104) along the column to the second side of the array (104), and wherein the CBLs of the fourth pair of CBLs (118) have stepped profiles between the first and second subarray (108). [3] Semiconductor storage device (102) according to claim 1, wherein the third pair of CBLs (120) extends from the second side of the array (104), along the column, to the first side of the array (104), and wherein the CBLs of the third pair of CBLs (120) have stepped profiles between the first and the second subarray (108), and wherein the fourth pair of CBLs (118) extends along the column, from the second side of the array (104), and terminates between the first and the second subarray (108). [4] Semiconductor storage device (102) according to claim 3, further comprising: a first multiplexer (144) on the first side of the array (104) and designed to choose between the first pair of CBLs (120) and the second pair of CBLs (118), and a second multiplexer (144) on the second side of the array (104) and designed to choose between the third pair of CBLs (120) and the second pair of CBLs (118). [5] Semiconductor storage device (102) according to claim 1, wherein a CBL of the second pair of CBLs (118) comprises: a flying bit line segment (122, 122a, 122b) extending laterally along the column from the first side of the array (104) and terminating between the first and second subarray (108), a local bit line section (124, 124a, 124b) extending from the space between the first and second subarray (108), laterally along the column, to the second side of the array (104), wherein the local bit line section (124, 124a, 124b) is spaced below the flying bit line section (122, 122a, 122b) in a direction perpendicular to the rows (N) and columns (X), and a jump cell (126, 126a, 126b) between the first and the second subarray (108), wherein the jump cell (126, 126a, 126b) electrically couples the flying bit line segment (122, 122a, 122b) with the local bit line segment (124, 124a, 124b). [6] Semiconductor storage device (102) according to claim 5, wherein the flying bit line section (122, 122a, 122b) and the local bit line section (124, 124a, 124b) are spaced apart laterally in a direction perpendicular to the lines (N). [7] Semiconductor storage device (102) according to claim 1, further comprising: a twisting cell (402, 402a, 403, 403a, 404, 404a, 405, 405a, 410, 412, 501) designed to twist adjacent bit lines of two pairs of CBLs extending along the column, the two pairs of CBLs corresponding to two of the first, second, third and fourth pair of CBLs (118). [8] Semiconductor storage device (102) according to claim 7, wherein the adjacent bit lines comprise a first bit line extending to the twist cell (402, 402a, 403, 403a, 404, 404a, 405, 405a, 410, 412, 501) along a first axis, and further comprise a second bit line extending to the twist cell (402, 402a, 403, 403a, 404, 404a, 405, 405a, 410, 412, 501) along a second axis parallel to the first axis and the column, wherein the first bit line extends from the twist cell (402, 402a, 403, 403a, 404, 404a, 405, 405a, 410, 412, 501) extends along the second axis, and the second bit line extends from the twisting cell (402, 402a, 403, 403a, 404, 404a, 405, 405a, 410, 412, 501) along the first axis. [9] Semiconductor memory device (102) according to claim 8, wherein the twist cell (402, 402a, 403, 403a, 404, 404a, 405, 405a, 410, 412, 501) is spaced apart in the column between the memory cells (106) of the first subarray (110), wherein the two pairs of CBLs correspond to the first and third pair of CBLs (120), and wherein the second or fourth pair of CBLs (118) comprises a bit line extending along a third axis parallel to the first and second axes and located between the first and second axes, and wherein the bit line is located above the twist cell (402, 402a, 403, 403a, 404, 404a, 405, 405a, 410, 412, 501) extends along the third axis. [10] Semiconductor memory device (102) according to claim 8, wherein the twist cell (402, 402a, 403, 403a, 404, 404a, 405, 405a, 410, 412, 501) is spaced apart in the column between the memory cells (106) of the second subarray (108), wherein the two pairs of CBLs correspond to the second and fourth pairs of CBLs (118), and wherein the third pair of CBLs (120) comprises a bit line extending along a third axis parallel to the first and second axes and located between the first and second axes, and wherein the bit line extends over the twist cell (402, 402a, 403, 403a, 404, 404a, 405, 405a, 410, 412, 501) extends along the third axis. [11] Semiconductor memory device (102) according to claim 1, wherein a first memory cell in the first subarray (110) and a second memory cell in the second subarray are DP-SRAM cells, wherein dual ports of the first memory cell are each electrically coupled to the first pair of CBLs (120) and the third pair of CBLs (120), and wherein dual ports of the second memory cell are each electrically coupled to the second pair of CBLs (118) and the fourth pair of CBLs (118). [12] Semiconductor storage device (102), comprising: an array (104) of memory cells (106) arranged in rows (N) and columns (X), wherein the array (104) comprises a first subarray (110) of memory cells (106) and a second subarray (108) of memory cells (106), a first pair of CBLs (120, 120b) extending along a column of the array (104), from a first side of the array (104), and terminating between the first and second subarray (108), wherein the first pair of CBLs (120, 120b) is electrically coupled to memory cells (106) of the first subarray (110) in the column, a second pair of CBLs (118, 118b) extending from the first side of the array (104), along the column, to a second side of the array (104), wherein the second pair of CBLs (118, 118b) is electrically coupled to memory cells (106) of the second subarray (108) in the column, a third pair of CBLs (120, 120a) and a fourth pair of CBLs (118, 118a) extending along the column, wherein the third and fourth pairs of CBLs (120, 120a, 118, 118a) are each electrically coupled to the memory cells (106) of the first subarray (110) in the column and the memory cells (106) of the second subarray (108) in the column, a set of word lines (112), a port AI / O array (130a) on the second or first side of the array (104) of memory cells (106), designed to use the fourth pair of CBLs (118, 118a) and the third pair of CBLs (120, 120a) to read from and / or write to memory cells (106) accessed by the word lines (112), and a port BI / O array (130b) on the first or second side of the array (104) of memory cells (106), designed to use the second pair of CBLs (118, 118b) and the first pair of CBLs (120, 120b) to read from and / or write to memory cells (106) accessed by the word lines (112), and a twisting cell (402, 402a, 403, 403a, 404, 404a, 405, 405a, 410, 412, 501) designed to twist a pair of adjacent bit lines each of two pairs of CBLs extending along the column, the two pairs of CBLs corresponding to two of the first, second, third and fourth pairs of CBLs (118, 120). [13] Semiconductor storage device (102) according to claim 12, further comprising: a second twisting cell designed to twist another pair of adjacent bit lines from each of the two pairs of CBLs, wherein the adjacent bit lines of the other pair are complementary to the adjacent bit lines of the pair adjacent to the other pair. [14] Semiconductor storage device (102) according to claim 12, wherein the adjacent bit lines comprise a first bit line extending to the twist cell (402, 402a, 403, 403a, 404, 404a, 405, 405a, 410, 412, 501) along a first axis, and further comprise a second bit line extending to the twist cell (402, 402a, 403, 403a, 404, 404a, 405, 405a, 410, 412, 501) along a second axis parallel to the first axis and the column, wherein the first bit line extends from the twist cell (402, 402a, 403, 403a, 404, 404a, 405, 405a, 410, 412, 501) extends along the second axis, and the second bit line extends from the twisting cell (402, 402a, 403, 403a, 404, 404a, 405, 405a, 410, 412, 501) along the first axis. [15] Semiconductor storage device (102) according to claim 12, wherein the adjacent bit lines comprise a first bit line and a second bit line, the first bit line crossing the second bit line at the twisting cell (402, 402a, 403, 403a, 404, 404a, 405, 405a, 410, 412, 501) and over the second bit line in a direction perpendicular to the rows (N) and columns (X). [16] Semiconductor memory device (102) according to claim 12, wherein the twist cell (402, 402a, 403, 403a, 404, 404a, 405, 405a, 410, 412, 501) is spaced apart in the column between the memory cells (106) of the first subarray (110), wherein the two pairs of CBLs correspond to the first and third pair of CBLs (120), and wherein the second or fourth pair of CBLs (118) comprises a bit line extending along the column and directly above the twist cell (402, 402a, 403, 403a, 404, 404a, 405, 405a, 410, 412, 501) between the adjacent bit lines. [17] Semiconductor storage device (102) according to claim 12, wherein the twisting cell (402, 402a, 403, 403a, 404, 404a, 405, 405a, 410, 412, 501) is spaced apart in the column between the memory cells (106) of the second subarray (108), and wherein the two pairs of CBLs correspond to the second and fourth pairs of CBLs (118). [18] Semiconductor storage device (102) according to claim 12, further comprising: a BEOL interconnect structure (210) comprising a dielectric layer (212), several metal layers (M0, M1, M2) and several via layers (V1, V2), wherein the metal layers (M0, M1, M2) are stacked alternately with the via layers (V1, V2) in the dielectric layer (212), and wherein the metal layers (M0, M1, M2) and the via layers (V1, V2) define the first, second, third and fourth pair of complementary bit lines (118, 120). [19] Semiconductor storage device (102) according to claim 18, wherein the BEOL interconnect structure (210) comprises a metal 0 layer (M0), a metal 1 layer (M1) spaced above the metal 0 layer (M0) in a direction perpendicular to the rows (N) and columns (X), and a metal 2 layer (M2) spaced above the metal 1 layer (M1) in the direction wherein the first pair of CBLs (120) extends along the column in the metal 0 layer (M0), and wherein the second pair of CBLs (118) extends along the column in the metal 2 layer (M2), while located above the first subarray (110), descends to the metal 0 layer (M0) between the first and second subarray (110, 108), and extends along the column in the metal 0 layer (M0), while it is located above the second sub-array (108). [20] Semiconductor storage device (102), comprising: an array (104) of memory cells (106) arranged in rows (N) and columns (X), wherein the array (104) comprises a first subarray (110) of memory cells (106) and a second subarray (108) of memory cells (106), a first pair of CBLs (120, 120b) extending along a column of the array (104), from a first side of the array (104), and terminating between the first and second subarray (220, 108), wherein the first pair of CBLs (120, 120b) is electrically coupled to memory cells (106) of the first subarray (110) in the column, a second pair of CBLs (118, 118b) extending from the first side of the array (104), along the column, to a second side of the array (104), wherein the second pair of CBLs (118, 118b) is electrically coupled to memory cells (106) of the second subarray (108) in the column, and wherein the CBLs of the second pair of CBLs (118, 118b) have stepped profiles between the first and second subarray (108), a third pair of CBLs (120, 120a) and a fourth pair of CBLs (118, 118a) extending along the column, wherein the third and fourth pairs of CBLs (120, 120a, 118, 118a) are each electrically coupled to the memory cells (106) of the first subarray (110) and the memory cells (106) of the second subarray (108) are electrically coupled, and wherein the CBLs of the third or fourth pair of CBLs (120, 118) have stepped profiles between the first and the second subarray (108), a set of word lines (112), a port AI / O array (130a) on the second or first side of the array (104) of memory cells (106), designed to use the fourth pair of CBLs (118, 118a) and the third pair of CBLs (120, 120a) to read from and / or write to memory cells (106) accessed by the word lines (112), and a port BI / O array (130b) on the first or second side of the array (104) of memory cells (106), designed to use the second pair of CBLs (118, 118b) and the first pair of CBLs (120, 120b) to read from and / or write to memory cells (106) accessed by the word lines (112), and a twisting cell (402, 402a, 403, 403a, 404, 404a, 405, 405a, 410, 412, 501) designed to twist one pair of adjacent bit lines each, wherein the adjacent bit lines each originate from two pairs of CBLs extending along the column, and wherein the two pairs of CBLs correspond to two of the first, second, third and fourth pair of CBLs (118, 120).

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