Storage array structure and methods for its fabrication

Abstract

Storage device, comprising: an array of memory cells (108); a first bit line (110) coupled to memory cells (108) of a first column of the array of memory cells (108), wherein the first bit line (110) is arranged on a first metal layer; a second bit line (112) coupled to the first bit line (110), wherein the second bit line (112) is arranged on a second metal layer and coupled to the first bit line (110) via at least one via (114); and a word line (116) that is coupled to a row of the array of memory cells (108), wherein the at least one via (114) is arranged on a first edge cell region of the array and wherein a further via (114) coupling the first and second bit lines (110, 112) is arranged on a second edge cell region of the array, the second edge cell region being on a side of the array opposite the first edge cell region.

Description

BACKGROUND

[0001] The present application relates generally to the field of semiconductor devices and in particular to integrated circuits and methods for manufacturing the integrated circuits.

[0002] Memory circuits are used in various applications. Traditionally, memory circuits can include DRAM, SRAM, or non-volatile memory such as ROM. Memory circuits typically comprise a plurality of memory cells arranged in arrays. The memory cells are typically addressed by a bit line (BL) (connected to a column of the array) and a word line (WL) (connected to a row of the array). The memory cell at the intersection of the specified BL and WL is the addressed cell. An example of an SRAM memory cell is a 6-transistor (6-T) SRAM cell. The 6-T SRAM memory cell is connected to other cells in the array and peripheral circuitry by a bit line (BL), a complement bit line (BLB), and a word line (WL). Four of the six transistors form two cross-coupled inverters for storing a data point representing "0" or "1".The remaining two transistors serve as access transistors to control access to the data in the memory cell. Various other memory cell designs are also used in different applications.

[0003] US 2003 / 0117827A1 discloses a device and a method for enabling a programmable semiconductor memory device to provide a block selection transistor of a high-voltage-resistance type to prevent voltage degradation at the time of programming, to prevent readout current degradation, and to provide a constant total resistance of the electrically conductive regions, regardless of the memory cell positions. In a pair of two electrically conductive regions arranged to extend parallel and separate from each other on a substrate surface, one longitudinal end of one of the electrically conductive regions is diagonally connected to the other longitudinal end of the other electrically conductive region by wiring to form a set of subbit lines.Selection transistors are provided at both ends of the memory cell array for connecting the subbit lines and main bit lines. A plurality of sets of subbit lines, connected to the selection transistors at both ends of the memory cell array, are arranged such that in a region between paired electrically conductive regions (a, a) forming a set of subbit lines, there is one (b, e) of two paired electrically conductive regions forming two sets of subbit lines connected to two main bit lines on either side of a given main bit line, and one (c, d) of two paired electrically conductive regions forming two sets of subbit lines connected to the opposing selection transistors at the longitudinal ends. The selection transistors are insulated from each other by a field oxide film.

[0004] US 5,708,621 A discloses a semiconductor memory consisting of a word line layer of high-impedance signal lines connected in parallel by low-impedance signal lines in a separate layer. Each high-impedance signal line is divided into segments separated by gaps. Connections between the high- and low-impedance signal lines in each word line are aligned with the gaps in the high-impedance signal lines in the adjacent word lines.

[0005] US 7,812,407 B2 discloses a memory array with an array of interconnect cells. According to embodiments of the disclosure, interconnect cells are positioned between two rows of a memory array. The interconnect cells provide a positive positive (P+) connection between the positive positive (N+) active regions of two memory cells in a column of the memory array. The interconnect cells provide an insulating structure between the two rows of the memory array and ensure more consistent operation of the memory cells, regardless of their positions within the memory array. In one embodiment, a dummy N-well can be formed along the outer edge of the memory array in a direction perpendicular to the array of interconnect cells.Furthermore, transistors can be formed in the interconnected cells to provide additional insulation between the connected memory cells.

[0006] The invention is defined in the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, in accordance with standard industry practice, various elements are not drawn to scale. In fact, the dimensions of the various features may be enlarged or reduced as desired for the clarity of the discussion. Fig. Figure 1 shows a top view of a layout of an array of semiconductor memory cells according to an embodiment of the present disclosure. Fig. Figure 2 shows a top view of a layout of an array of semiconductor memory cells according to an embodiment of the present disclosure. Fig. Figure 3 shows an exemplary cross-sectional view according to one embodiment of the Fig. 1 and Fig. 2. Fig. 4A and Fig. Figure 4B shows a layout view and a cross-sectional view according to various aspects of the present disclosure in an embodiment of the device of Fig. 2. Fig. Figure 5 shows a top view of a layout of an array of semiconductor memory cells according to an embodiment of the present disclosure. Fig. Figure 6 shows an exemplary cross-sectional view according to one embodiment of the Fig. 5. Fig. Figure 7 shows a top view of a layout of an array of semiconductor memory cells according to an embodiment of the present disclosure. Fig. Figure 8 shows an exemplary cross-sectional view according to one embodiment of the Fig. 7. Fig. 9A and Fig. Figure 9B shows a layout view and a cross-sectional view according to various aspects of the present disclosure and an example of an embodiment of Fig. 7. Fig. 10A and Fig. Figure 10B shows a layout view and a cross-sectional view according to various aspects of the present disclosure and the embodiment of Fig. 7. Fig. Figure 11 shows a top view of a layout of an array of semiconductor memory cells according to an embodiment of the present disclosure, which has a double word line configuration. Fig. Figure 12 shows an exemplary cross-sectional view according to one embodiment of the Fig. 11. Fig. Figure 13 shows an exemplary cross-sectional view according to one embodiment of the Fig. 11. Fig. 14A and Fig. Figure 14B shows a layout view and a cross-sectional view according to various aspects of the present disclosure and an embodiment of the device of Fig. 11. Fig. Figure 15 shows a top view of a layout of a storage device having a plurality of subarrays of memory cells, according to an embodiment of the present disclosure. Fig. Figure 16 shows a flowchart that provides an exemplary method for manufacturing devices according to one or more aspects of the present disclosure. Fig. 17, Fig. 18 and Fig. Figure 19 shows exemplary schematic views of memory cells that can be constructed according to the various aspects of the present disclosure. Fig. Figure 20 shows a cross-sectional view of an exemplary stack of metal arranged on a substrate, as an example in a storage device constructed according to various aspects of the present disclosure. DETAILED DESCRIPTION

[0008] It is understood that the following disclosure provides for many different embodiments or examples to implement various features of different embodiments. Specific examples of components and arrangements are described below to simplify the present disclosure. In addition, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition serves the purpose of simplicity and clarity and does not in itself imply any relationship between the various described embodiments and / or configurations.

[0009] While certain embodiments are provided herein that describe the provision of an interconnection architecture using a given metal layer (e.g., Metal-1 (M1), Metal-2 (M2), Metal-3 (M3)) of a multilayer interconnect (MLI), a person skilled in the art will recognize that other metal layers can be used to implement the interconnection architecture of the present disclosure. For example, the embodiments described herein can be implemented using a multilayer interconnect (MLI) such as that described in Fig. Figure 20 shows, for example, via 1, Metal-2 (M1), via 2, Metal-2 (M2), via 3, Metal-3 (M3), via 4, and Metal-4 (M4). The MLI comprises a densely layered structure of conductive traces (extending, for example, along a length parallel to an upper surface of the substrate) connecting vertically extending vias located between insulating films, providing electrical connections (and the associated insulation) to and between various devices on a substrate. While three or four metal layers are shown in some embodiments, any number of metal layers can be provided and used to implement the present disclosure.An MLI structure can also be described as back-end metallization, which features many stacked metal layers extending horizontally and vertically extending vias or contacts that provide connections between and to the stacked metal layers. The MLI can be arranged above the substrate and above the contact plane (e.g., above the gate contact, the source / drain contact, etc.), see [reference]. Fig. 20.

[0010] In general, relative terms such as "first metal layer" and "second metal layer" are used to simplify identification and do not require that the device be formed on a specific metal layer, e.g., M1 and M2, unless expressly stated. The present disclosure describes a metal layer as the nearest adjacent metal layer of two metal layers in a stack, between which a dielectric and / or a via is located, but without another metal layer providing routing in a substantially horizontal direction—for example, M2 is the nearest adjacent metal layer to M1, M5 and M3 are the nearest adjacent metal layers to M4, and so on.

[0011] With reference to Fig. Figure 1 shows a storage device 100 comprising a plurality of cells 102, 104, 106, 108 arranged in an array. The storage device 100 of Fig. 1 can be a ROM device, a DRAM device, and / or another suitable storage device technology. Cells 102 can be dummy corner cell(s). Cells 104 can be edge cells. Cells 106 can be edge cells. Certain cells 102, 104, and 106 need not be used to store data but provide other functionality to the device; for example, cells 104 can provide a basin contact and / or stripe functionality (see, for example, U.S. Patent No. 7,812,407, incorporated herein by reference). Memory cells 108 can be functional memory cells of the array, with each memory cell 108 capable of storing data (e.g., a stored bit). For example, each of the memory cells 108 can be an addressed memory cell, accessed by "switching on" the associated WL / BL to memory cell 108.

[0012] Note that storage device 100 is an example of a storage array having 4 columns and 8 rows of memory cells 108 providing storage. This array configuration and size are only exemplary and serve descriptive purposes; they are not intended to limit array size or configuration.

[0013] The memory device 100 can be arranged on a semiconductor substrate. In one embodiment, the semiconductor substrate comprises silicon. Other example compositions include, without limitation, silicon-germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon-germanium carbide, gallium arsenide-phosphide, gallium-indium phosphide, germanium, and / or other suitable materials. The memory cells 108 formed on the semiconductor substrate can have any suitable memory cell design, including, for example, those designed with respect to Fig. 17, Fig. 18 and / or 19 are defined and described below.

[0014] A bit line (BL) 110 is allocated to each column of the storage device 100 (referred to as associated). A word line (WL) 116 is allocated to each row of the array of the storage device 100 (referred to as associated). The BL / WL is a connecting line that is linked to an associated column / row of the array, as it is a line that carries a signal (for example, voltage) used to read / write an addressed cell of that column / row. The intersection of the specified row-column pair, defined by the respective BL / WL that are "switched on," is referred to as the addressed element or addressed memory cell 108.

[0015] In addition to the single BL 110 and single WL 116, the storage device 100 exhibits a dual-line configuration for bit lines of the device 100. The storage device 100 comprises the first bit line (1st BL) 110, described above, and additionally a second bit line (2nd BL) 112, which belongs to each column of the array of storage devices 108. The 1st BL 110 is coupled to each addressable memory cell (bit) 108 in the given column and serves to access the addressed cell. For example, the 1st BL 110 can be coupled to an element of the memory cell 108, such as the source / drain of the transistor (see, e.g., the Fig. 18, Fig. 19). The storage device 100 also includes the 2nd BL 112, which belongs to the same column as a 1st BL 110. In some embodiments, the 2nd BL 112 runs parallel to the 1st BL 110 on a different (e.g., higher) metal layer arranged above the storage cells 108. The 2nd BL 112 belonging to the column is coupled to the 1st BL 110 for the given column at one or more points. In the embodiment shown in Fig. In the embodiment shown in Figure 1, the second BL112 is coupled to the first BL110 at two locations, shown as vias 114. While the vias are shown above the associated edge cell 104, in other embodiments the connection between the first BL110 and the second BL112 can be configured over other sections of the device 100. In some embodiments, the second bit line 112 for a given column is coupled to the first BL110 for that column at more than two locations, including within the array of memory cells 108 (e.g., at the periphery of one of the addressable memory cells 108).

[0016] The second BL line 112 can be coupled to the memory cell element 108 (e.g., including its transistor) via its connection to the first BL line 110. In other words, an electrical path between the second BL line 112 and an addressed memory cell 108 runs via the first BL line 110. For example, the circuitry of cell 108 can drive the first BL line 110 via a connection (e.g., a via / contact) from the first BL line to the transistor / capacitor / etc. of the addressed memory cell 108. The second BL line 112, belonging to the column, is coupled to the first BL line 110 and is therefore provided in the same state. For example, in one embodiment of a read access to a memory device 100 (e.g., DRAM), the first BL 110 is connected to the storage capacitors of the memory cell 108, and charge sharing causes the first BL 110 to pivot up or down. The second BL 112 maintains this state via its connection to the first BL 110. Either the firstBL 110 or BL 112 extends to the peripheral circuits to provide the state of the addressed cell. Thus, the state of BL 110 and BL 112 is linked (i.e., identical) and can be determined by the storage device 100 by coupling either BL 110 or BL 112 to memory cell 108 and either BL 110 or BL 112 to the peripheral control circuit.

[0017] In some embodiments, only one of the first BL 110 and the second BL 112 is connected to the peripheral control circuit (not shown) of the storage device 100. For example, one of the first BL 110 and the second BL 112 may extend to circuits such as column address circuits, decoders, read amplifiers, drivers, preload circuits, Vdd, and / or other suitable peripheral circuit functionality. In another embodiment, the other of the first BL 110 and the second BL 112 terminates without a spatial connection to the control circuit. For example, in one embodiment, the second BL 112, while extending beyond the connection point with the first BL 110 (via 114), terminates at a point before the connection to the control circuit of the storage device 100, while the first BL 110 extends to the peripheral circuits. In another embodiment, the 2nd BL 112 extends to the peripheral circuit and the 1stBL 110 terminates at a point before the connection to the array control circuitry and after the connection (e.g., via 114) to the second BL 112. Thus, the state of the first BL 110 and the second BL 112 is linked, and this state can be determined by coupling either the first BL 110 or the second BL 112 to the peripheral circuitry. For example, in some embodiments, the first BL 110 is coupled to a peripheral device (e.g., a read amplifier), and the second BL 112 is coupled to the peripheral device (e.g., the read amplifier) ​​only via the first BL 110.

[0018] The first BL 110 and the second BL 112 are horizontally extending conductive traces, referred to as metal layers (e.g., M1, M2, etc., above the substrate) of an MLI. The metal layers forming the first BL 110 and / or the second BL 112 consist of conductive materials, including, for example, aluminum, aluminum alloy (e.g., aluminum / silicon / copper), copper, copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, silicide, polysilicon, and / or other suitable conductive materials. In one example, a Damascene and / or dual-Damascene process is used to form the metal layers. The first BL 110 and the second BL 112 are coupled by the via 114. The via 114 may include copper, tungsten, and / or other suitable conductive materials. Apart from the one or more vias 114, the 1st BL 110 and the 2ndBL 112 should be insulated from each other by a suitable dielectric material of the MLI structure, for example, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon dioxide such as boron phosphosilicate glass (BPSG), molten quartz glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. Note that the different widths of BL 110 and 112 are shown in the representation of . Fig. 1 (as with the other figures shown here) serve the purpose of simplicity of representation and are not intended to be restrictive for any relative width.

[0019] Similarly, the WL 116 can consist of conductive materials, including, for example, aluminium, aluminium alloy (e.g. aluminium / silicon / copper), copper, copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, silicide, polysilicon and / or other suitable conductive materials.

[0020] In one embodiment, the first BL 110 is located on the metal layer Mn and the second BL 112 is located on the metal layer Mn + x, where x is greater than or equal to 1. In another embodiment, n is equal to 1 (for example, the first BL is located on Metal-1 (M1)) and x is equal to 1, defining the next adjacent metal layer (for example, the second BL 112 is located on Metal-Metal-32 (M2)). In such an embodiment, the via 114 connecting the first BL 110 and the second BL 112 is a via that is interposed and adjacent to both adjacent metal layers—for example, Metal-1 and Metal-2—and is designated via 2 of the MLI. In another embodiment, the WL 116 can be located on the next adjacent metal layer above the second BL 112, for example, Metal-3 (M3). In another embodiment, n equals 1 (for example, the 1st BL is arranged on Metal-1 (M1)) and x equals 2 (for example, the 2nd BL is arranged on Metal-1 (M1)).BL 112 arranged on Metal-3 (M3). In such an embodiment, the via 114 connecting the 1st BL 110 to the 2nd BL 112 comprises vias of multiple layers and / or contact surfaces located between Metal-1 (M1) and Metal-3 (M3), as described with reference to . Fig. 7 is described further. In another embodiment, the WL 116 lies on Metal-2, the nearest adjacent metal layer to that of the 1st BL 110. In other embodiments, the 1st BL 110, the 2nd BL 112, and the WL 116 lie on several different metal conductors.

[0021] The use of the dual bitline structure and the 1st BL 110 and the 2nd BL 112 for each column of the array of memory device 100 can offer an advantage by reducing the addressing resistance of the memory element 108. The lower bitline resistance can allow less bitline IR drop during addressing of memory cell 108 (e.g., during a write cycle), thereby improving the quality of the memory device 100 (e.g., improving the write area). In other words, errors caused by a voltage drop across the resistance of a source path to the device's ground when current flows can be reduced. In some embodiments, the lower bitline resistance allows for a reduction in the bitline resistance capacitance (RC) delay.

[0022] Providing an additional metal conductor as a second bit line for each column can offer an advantage over, for example, reducing the width of a single metal conductor when forming a single bit line in a storage device. Reducing the width would necessitate reducing the thickness to avoid an aspect ratio that cannot be reliably achieved using certain manufacturing techniques (e.g., Damascene processes).

[0023] Referring to Fig. Figure 2 shows an embodiment of a storage device 200. In one embodiment, the storage device 200 is a static random access memory (SRAM) device. Fig. Figure 2 is an example of a memory array comprising 4 columns and 8 rows of 108 memory cells. Again, this array configuration and size are merely exemplary and serve descriptive purposes; they are not intended to limit array size or configuration. The memory device 200 may be substantially similar to the memory device 100 described above. Fig. as described in Figure 1, except that the storage device 200 comprises a complementary bit line (also called a bit line bar or BL_bar) belonging to each column of the array of memory cells 108. The storage device 200 comprises the 1st BL 110 and the 2nd BL 112 for each column of the memory cells 108, analogous to the above with reference to Fig. The storage device 200 is described in section 1. Additionally, the storage device 200 includes a first complementary bit line (1st BL_bar) 202 and a second complementary bit line (2nd BL_bar) 204 for each column of the memory cells 108. The 1st BL_bar 202 is a complementary bit line to the 1st BL 110. The 2nd BL_bar 204 is coupled to the 1st BL_bar 202 essentially analogously to the 2nd BL 112 in relation to the 1st BL 110 described above. A via 206 establishes the connection to the 2nd BL_bar 204, which is connected to the 1st BL_bar 202. The via 206 is essentially similar to the via 114 described above.

[0024] As described above, the first BL 110 is connected to each addressable memory cell 108 in the given column; similarly, the first BL_bar 202 is also connected to each memory cell 108 in the given column. For example, the second BL 112 can be coupled to the memory cell element 108 (e.g., including its transistor) only via the connection to the first BL 110. In other words, an electrical path between the second BL 112 and the given addressed memory cell 108 runs through the first BL 110. The device 200 also includes complementary bit lines (BL_bar) suitable for certain types of memory devices (e.g., SRAM). The second BL_bar 204 can be connected to the memory cell element 108 (e.g., including its transistor) only via the connection to the first BL_bar 202. In other words, an electrical path between the 2nd BL_bar 204 and the given addressed memory cell 108 runs via the 1st BL_bar 202. The 1stBL_bar and the 2nd BL_bar can be coupled to memory cell 108 in essentially the same way as with reference to . Fig. 17 is shown.

[0025] As shown in device 200, the second BL 112 belonging to the column is coupled to the first BL 110 for the given column at two locations, shown as vias 114. In other embodiments, the second BL 112 is coupled to the first BL 110 at one or more locations for a given column, where the coupling can be provided at one or more different locations, including over a boundary cell 104, over the array of memory cells 108 (for example, at an outer edge of one or more addressable cells 108). As shown in device 200, the second BL 204 belonging to the column is coupled to the first BL 202 for the given column at two locations, the vias 206. In other embodiments, the second BL 204 is coupled to the first BL 110 at one or more locations, including over a boundary cell 104, over the array of memory cells 108 (for example, at an outer edge of one or more addressable cells 108).BL_bar 202 coupled at one or more locations for a given column, where coupling can be provided at one or more of different locations, including over a boundary cell 104, over the array of memory cells 108 (for example, at an outer boundary of one or more addressable cells 108).

[0026] In one embodiment, the vias 114 represent one or more vias or contact pads extending from the second BL 112 to the first BL 110, wherein the first BL 110 is located on the metal layer Mp and the second BL 112 is located on the metal layer Mp + y, where y is greater than or equal to 1. In another embodiment, the vias 206 represent one or more vias or contact pads extending from the second BL 204 to the first BL 202, wherein the first BL 202 is located on the metal layer Mp and the second BL 204 is located on the metal layer Mp + y, where y is greater than or equal to 1. While not required, the first BL and the first BL 204 are located on the same metal layer (e.g., "p").

[0027] In another embodiment, p equals 1 (for example, the first BL and / or BL_bar 202 is arranged on Metal-1 (M1)) and y equals 1 (for example, the second BL 112 and / or BL_bar 204 is arranged on the next adjacent, overlying metal layer, Metal-2 (M2)). In such an embodiment, the via 206 connecting the first BL_bar and the second BL_bar is the via located between Metal-1 and Metal-2, for example, via 2 of the MLI, which is adjacent to and connects M1 and M2. In a further embodiment, the WL 116 can be located on Metal-3 (M3).

[0028] In another embodiment, p equals 1 (for example, the first BL and / or the first BL_bar 202 is arranged on Metal-1) and y equals 2 (for example, the second BL 112 and / or the second BL_bar 204 is arranged on Metal-3). In such an embodiment, the via 206 connecting the first BL_bar 202 to the second BL_bar 206 comprises vias and / or contact surfaces located between Metal-1 (M1) and the overlying, non-adjacent Metal-3 (M3) (e.g., via 2, via 3, contact surface on M2). In a further embodiment, the WL 116 is located on Metal-2 (e.g., between the first BL_bar 202 and the second BL_bar 204). In other embodiments, both the 1st BL_bar 202 and the 2nd BL_bar 204, as well as the WL 116, are located on different metal conduits of different configurations. Exemplary embodiments of this are shown in the following. Fig. 3-10B shown, which also refers to device 200 of Fig. 2 are applied.

[0029] As described above with reference to device 100, and which also applies to device 200, in some embodiments only one of the 1. BL 110 and the 2. BL 112 are connected to the peripheral control circuit (not shown) of the storage device 100. Similarly, only one of the 1. BL_bar 202 and the 2. BL_bar 204 may be connected to the peripheral control circuit. For example, a group of the 1. BL 110 / 1. BL_bar 202 and the 2. BL 112 / 2. BL_bar 204 may extend to circuits such as column address circuits, decoders, read amplifiers, drivers, preload circuits, Vdd, and / or other suitable peripheral circuit functionality. In another embodiment, the other group of the 1. BL 110 / 1. BL_bar 202 and the 2. BL 112 / 2. BL_bar 204 terminates. BL_bar 204 without a spatial connection to the control circuit. For example, in one embodiment, the second BL_bar 204 terminates while extending via the connection point with the first.BL_bar 202 extends beyond the via 116 at a point before the connection to the array control circuit, while BL_bar 202 extends to the peripheral circuit. In another embodiment, BL_bar 204 extends to the peripheral circuit, and BL_bar 204 terminates at a point before the connection to the array control circuit, after the connection (e.g., via 206) with BL_bar 204. Thus, the state of BL_bar 202 and BL_bar 204 is linked (i.e., identical), and this state can be determined by connecting either BL_bar 202 or BL_bar 204 to the peripheral circuit.

[0030] Similar to the double bit lines of BL 110 and BL 112, the complementary double bit lines of BL 1 and BL 204 are conductive traces referred to as metal layers of an MLI (e.g., M1, M2, etc.) above the substrate. The metal layers forming BL 1 and / or BL 204 consist of conductive materials, including, for example, aluminum, aluminum alloy (e.g., aluminum / silicon / copper), copper, copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, silicide, polysilicon, and / or other suitable conductive materials. In one example, a Damascene and / or dual-Damascene process is used to form the metal layers. The via 206 may include copper, tungsten, and / or other suitable conductive materials. Apart from the via 206, the 1st BL_bar 202 and the 2ndBL_bar 204 be insulated from each other by suitable dielectric material, for example tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass or doped silicon oxide such as boron phosphosilicate glass (BPSG), molten quartz glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG) and / or other suitable dielectric materials.

[0031] Fig. Figure 3 shows an embodiment of a cross-sectional view of section AA' of the device 200 of Fig. 2. Fig. Figure 3 is an example of an embodiment of a cross-sectional view through the BL_bar area. A substantially similar cross-sectional view can also represent a parallel section through a BL of the device 200. Fig. Figure 3 shows a plurality of metal layers and vias that are part of a multilayer conductive interlayer (MLI) arranged on a substrate and interrupted by interlayer dielectric (ILD) layer(s) 302. For example, the ILD layer 302 can comprise materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon dioxide such as boron phosphosilicate glass (BPSG), molten quartz glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. The ILD layer 302 can be deposited by a subatmospheric continuous vapor deposition (SACVD) process, a flowable CVD process, or another suitable deposition technique.

[0032] Fig. Figure 3 shows the first BL_bar 202, which is formed on a first metal layer (e.g., M1), the second BL_bar 204, which is formed on a second, higher metal layer (e.g., M2), and the word line (WL) 116, which is formed on a third adjacent, higher metal layer (e.g., M3). The via 206 connects the first BL_bar 202 and the second BL_bar 204. The first BL_bar 202 is coupled to an element located on the substrate (e.g., a contact with a transistor area), for example, via a via (not shown) that extends from and below the first metal layer.

[0033] The Fig. 4A and Fig. Figure 4B shows a layout view or a cross-sectional view of section 402 of a storage device. In one embodiment, section 402 is an embodiment of the memory cell 108 of the storage device 200, which is described above with reference to the Fig. 2 and Fig. Section 402 can include memory cell 108 as an SRAM memory cell. Layout section 402 includes the 1st BL 110, the 2nd BL 112, the 1st BL_bar 202, the 2nd BL_bar 204, and the WL 116. Layout section 402 further includes Vdd lines 404 and Vss lines 406.

[0034] In the embodiment shown, the first BL 110, the first BL_bar 202, the first Vdd line 402, and the Vss lines 404 are each formed on a first metal layer (e.g., M1). The second BL 112 and the second BL_bar 204 are formed on a second metal layer (e.g., M2) above the first metal layer. The WL 116 is arranged on a third metal layer (e.g., M3) above the second metal layer. The Vss lines 406 can be arranged on the first and second metal layers (e.g., M1 and M2). A plurality of vias are shown (circles enclosing an "x") to indicate connections between the elements. The via 410 shows a connection between the first BL_bar 202 and an underlying element of the memory cell 108. The via 206 provides a connection between the first BL_bar 202 and the second BL_bar 204 above it. In one embodiment, the via 410 connects the firstBL_bar with the source / drain of a transistor of memory cell 108 (e.g. a drain node of a pass-gate device in cell 108 as an SRAM device, see e.g. . Fig. 17).

[0035] Fig. 4B shows a related cross-sectional view along section BB' of layout section 402 of Fig. 4A, comprising the 1st BL_bar 202, the 2nd BL_bar 204 and the WL 116 on successive metal layers, wherein the via 206 connects the 1st BL_bar 202 to the 2nd BL_bar and the via 410 provides a connection to the underlying element of the memory cell 108 (e.g. a transistor).

[0036] Fig. Figure 5 shows another embodiment of the storage device 200, which is referred to as storage device 200'. In one embodiment, the device 200' is an SRAM device. The device 200' is essentially similar to the device 200 described above with reference to the Fig. 2, Fig. 3, Fig. 4A and Fig. 4B is described. Additionally, the device 200' shows a further plurality of connections (couplings) between the 1st BL 110 and the 2nd BL 112 and a further plurality of connections (couplings) between the 1st BL 202 and the 2nd BL 204. The six (6) connections 502 are only exemplary and are not intended to be limiting in number or position. In one embodiment, one or more of the plurality of connections 502 are arranged over the cells 104 that provide the trough or stripe area. These connections 502 may be substantially similar to the connections 206 and 114 described above. In one embodiment, one or more of the plurality of connections are arranged at a cell edge or peripheral area of ​​the memory cell 108. The connections 502 comprise one or more vias or conductive contact pads extending between the dual bit lines / complementary dual bit lines.

[0037] As described above, the first BL 110 is coupled to each cell 108 in the corresponding column. The second BL 112 is coupled to the first BL multiple times in the corresponding column via the connections 502. The first BL_bar 202 is coupled to each addressable cell 108 in the corresponding column (e.g., via the via / contact with the transistor element), and the second BL_bar 204 is coupled to the first BL_bar multiple times for the corresponding column via the connections 502. Note that the embodiment of Fig. Figure 1, which shows the device 100, may also include the plurality of connections shown as 502; in other words, in some embodiments, a plurality of connections (vias) between the 1st BL and the 2nd BL in a given column, including those connections 502 in the array, may be used in other types of memory arrays, including those that do not have a complementary bit line.

[0038] In some embodiments, the connections 502 are each a via (see, for example, Fig. 6), extending from one metal layer to an underlying metal layer. In some embodiments, the connections 502 comprise a plurality of vias and / or contact pads to provide a connection between a metal layer and a non-adjacent, underlying metal layer. The connections 502 may comprise a suitable conductive material, such as aluminum, aluminum alloy (e.g., aluminum / silicon / copper), copper, copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, silicide, polysilicon, and / or other suitable conductive materials.

[0039] Fig. Figure 6 shows a cross-sectional view of an embodiment of the device along the C-C' section line. Fig. 5. Fig. Figure 6 shows an embodiment of the device 200', comprising the first BL_bar 202 on a first metal layer (e.g., M1), the second BL_bar 204 on a second, overlying metal layer (e.g., M2), and the word line (WL) 116 on a third, overlying metal layer (e.g., M3). Note that in this embodiment, the second metal layer (including the second BL_bar 204) is the next adjacent overlying metal layer to the first metal layer (which includes the first BL_bar 202).

[0040] Fig. Figure 7 shows another embodiment of a storage device, designated as storage device 200". In one embodiment, device 200 is an SRAM device. Device 200 is essentially similar to device 200 described above with reference to the Fig. 2, Fig. 3, Fig. 4A and Fig. 4B is described. The storage device 200" is an example of a further embodiment of the storage device in which the 1st BL 110 and the 2nd BL 112 are not arranged on adjacent metal layers and thus a contact surface 702 together with vias 704 provides a vertical connection between the 1st BL 110 and the 2nd BL 112. Similarly, the storage device 200" is an example of an embodiment of the device 200 in which the 1st BL 202 and the 2nd BL 204 are not arranged on adjacent metal layers and thus contact surfaces 702 together with vias 704 provide a vertical connection between the 1st BL 202 and the 2nd BL 204.

[0041] As described above, the first BL 110 is coupled to each cell 108 in the corresponding column. The second BL 112 is coupled to the first BL one or more times in the corresponding column via connections 702 and 704. The first BL_bar 202 is coupled to each addressable cell 108 in the corresponding column (e.g., via vias / contacts with the transistor element), and the second BL_bar 204 is coupled to the first BL_bar one or more times for the corresponding column via connections 702 and 702. Note that the embodiment of Fig. 1, which shows the device 100, may also include the vias 702 and / or contact pads 704 shown in an embodiment of a storage device which need not require the complementary bit lines.

[0042] The connections 702 and 704 can comprise a suitable conductive material, such as aluminum, aluminum alloy (e.g., aluminum / silicon / copper), copper, copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, silicide, polysilicon, and / or other suitable conductive materials. The contact surfaces 704 can be formed simultaneously with the metal conductors of the associated metal layer (e.g., the metal layer located between the first BL 110 and the second BL 112).

[0043] Fig. Figure 8 shows a cross-sectional view of an embodiment of the device 200'' along the D-D' section line of Fig. 7. Fig. Figure 8 shows an embodiment of the device 200'' comprising the first BL_bar 202 on a first metal layer (e.g., M1), the WL 116 on a second, adjacent and overlying metal layer (e.g., M2), and the second BL_bar 204 on a third metal layer that is adjacent to and overlying the second metal layer (e.g., M3). Note that in this embodiment, the second metal layer (including the WL 116) is the next adjacent overlying metal layer to the first metal layer (which includes the first BL_bar 202) and is located between the first metal layer and the metal layer that includes the second BL_bar 204. The contact surface 702 is coplanar with the second metal layer.

[0044] Fig. 9A and Fig. Figure 9B shows a layout view or a cross-sectional view of section 902 of a storage device. In one embodiment, section 902 is an embodiment of the memory cell 108 of the storage device 200'', which is described above with reference to the Fig. 7 and Fig. Section 902 can include memory cell 108 as an SRAM memory cell. Layout section 902 includes the 1st BL 110, the 2nd BL 112, the 1st BL_bar 202, the 2nd BL_bar 204, and the WL 116. Layout section 902 further includes various Vdd lines (e.g., Metal-1) 904 and various Vss lines (e.g., Metal-2) 906.

[0045] In the Fig. 9A and Fig. In the embodiment shown in Figure 9B, the first BL 110 and the first BL_bar 202 are each formed on a first metal layer (e.g., M1). The WL 116 is formed on a second metal layer (e.g., M2) above them, which is the next adjacent metal layer to the first. The second BL 112 and the second BL_bar 204 are formed on a third metal layer (e.g., M3) above the first and second metal layers, respectively, with the third metal layer being the next adjacent metal layer above the second. The Vss line 906 can be arranged on the second metal layer (e.g., M2). A plurality of vias are shown (circles enclosing an "x") to indicate connections between the elements. A via 410 shows a connection between the 1st BL_bar 202 and an underlying element of the memory cell 108. In one embodiment, the via 410 connects the 1stBL_bar with the source / drain of a transistor of memory cell 108 (e.g., a drain node of a pass-gate device in cell 108 as an SRAM device). Note that the connection of BL_bar 110 and BL_bar 212 is not shown in section 902, but should be present elsewhere in the array that includes section 902 (see above). Note that the connection of BL_bar 102 and BL_bar 204 is not shown in section 902, but should be present elsewhere in the array that includes section 902 (see above). For example, these connections would include the features Via 2, Metal-2, the contact pad, and Via 3.

[0046] Fig. Figure 9B shows an associated cross-sectional view along section EE' of layout section 902 of Fig. 9A, which has the 1st BL_bar 202, the WL 116 and the 2nd BL_bar 204 on successive metal layers, wherein the via 410 provides a connection with the underlying element of the memory cell 108 (e.g. a transistor that is electrically connected, for example, to a drain node of a pass-gate device of an SRAM). A Vss line 906 is also shown, which is arranged on a second metal layer.

[0047] Fig. 10A and Fig. Figure 10B shows a layout view or a cross-sectional view of section 1002 of a storage device. In one embodiment, section 1002 is an embodiment of the memory cell 108 of the storage device 200'', which is described above with reference to the Fig. 7 and Fig. Section 1002 can include memory cell 108 as an SRAM memory cell. Layout section 1002 includes the 1st BL 110, the 2nd BL 112, the 1st BL_bar 202, the 2nd BL_bar 204, and the WL 116. Layout section 1002 further includes various Vdd lines (e.g., Metal-1) 1004 and various Vss lines (e.g., Metal-3) 1006 and Vss contact pads (e.g., Metal-1) 1008.

[0048] In the Fig. 10A and Fig. In the embodiment shown in Figure 10B, the first BL 110 and the first BL_bar 202 are each formed on a first metal layer (e.g., M1). The WL 116 is arranged on a second metal layer (e.g., M2) above them, which is the next adjacent metal layer to the first. The second BL 112 and the second BL_bar 204 are formed on a third metal layer (e.g., M3) above the first and second metal layers, respectively, with the third metal layer being the next adjacent metal layer above the second. A plurality of vias are shown (circles enclosing an "x") to indicate connections between the elements. A via 410 shows a connection between the first BL_bar 202 and an underlying element of the memory cell 108. In one embodiment, the via 410 connects the first BL_bar to the source / drain of a transistor of the memory cell 108 (e.g.a drain node of a pass-gate device in cell 108 as an SRAM device). Note that the connection of the 1st BL 110 and the 2nd BL 112 is not shown in section 1002, but should be present elsewhere in the array that includes section 1002 (see above). Note that the connection of the 1st BL_bar 202 and the 2nd BL_bar 204 is not shown in section 1002, but should be present elsewhere in the array that includes section 1002 (see above). For example, these connections would include the devices Via 2, Metal-2 (contact surface), and Via 3.

[0049] Fig. Figure 10B shows a corresponding cross-sectional view along section FF' of layout section 1002 of Fig. 10A, which has the 1st BL_bar 202, the WL 116 and the 2nd BL_bar 204 on successive metal layers, wherein the via 410 provides a connection with the underlying element of the memory cell 108 (e.g. a transistor which is electrically connected to, for example, a drain node of a pass-gate device of an SRAM).

[0050] Fig. Figure 11 shows a top view of an embodiment of the storage device 200, which is designated as storage device 200'''. The storage device 200''' can be substantially similar to the embodiments described above, with the addition of a word line (dual-word-line configuration) in the device, as detailed below. Note that the device 200''' is Fig. 11 comprises the 1st BL 110 and the 2nd BL 112, the 1st BL_bar 202 and the 2nd BL_bar 204. In other embodiments, the storage device 200''' need not have complement bit lines. In the embodiment of the device 200''', as in Fig. Figure 11 shows the second BL 112 coupled to the first BL 110 using the via 114 over the edge cell 104 (as in the coupling with the first and second complement bit lines). In other embodiments, the connection can be arranged over other areas of the device 200''', including as shown above in the Fig. 5 and Fig. 7 is shown. See also Fig. 12 and Fig. 13.

[0051] The device 200''' comprises the 1st WL 116, which may be substantially similar to that described above, and additionally a 2nd WL 1102. The 1st WL and the 2nd WL each belong to a single line of the storage device. In some embodiments, the dual-word-line configuration of the 1st WL 116 and the 2nd WL 1102 may offer advantages such as a reduction in resistance for a given line. The 1st WL 116 and the 2nd WL 1102 are coupled to each other by connections 1104. The connections 1104 comprise suitable vias and / or conductive contact surfaces that establish an electrical connection between the 1st WL 116 and the 2nd WL 1102 above it. The first WL 116 can be provided at Mz and the second WL 1102 at Mz+b, where b is greater than or equal to 1. In one embodiment, z equals 3 and b equals 1. In another embodiment, z equals 2 and b equals 2. In other words, in one embodiment, the first WL 1102 can be provided at Mz+b.WL 116 is planned for M2 and the second WL 1102 for M4.

[0052] In some embodiments, the first WL 116 is coupled to the second WL 1102 at one location in the device 200''' (for example, a connection 1104). In some embodiments, the first WL 116 and the second WL 1102 are coupled at least two locations for the row of cells 108, see connections 1104. In the embodiment shown, Fig. 11 is the connection between the 1st WL 116 and the 2nd WL 1102 for a given row above the border cell region 106 at the edge of the array. In other embodiments, other locations of these connections may be provided. For example, in other embodiments, the 1st WL 116 and the 2nd WL 1102 are coupled at several locations in the array of cells 108, including those substantially similar to those described above with reference to Fig. 5 and the connections of the dual-bit-line configuration are described. In one embodiment, the first WL 116 is coupled to each individual addressable cell 108 in the row (for example, to the pass-gate transistor of cell 108) via suitable via configurations. See, for example, the connections shown with the exemplary memory cells of Fig. 17, Fig. 18 and Fig. 19 are defined below. In another embodiment, the 2nd WL 1102 is connected to the addressable cell 108 (for example, the pass-gate transistor) only via the 1st WL 116.

[0053] In one embodiment, either the 1st WL 116 or the 2nd WL 1102 extends to the control circuit for the array of memory cells 108. In another embodiment, the other of the 1st WL 116 and the 2nd WL 1102 terminates without a direct connection to the control circuit. For example, in one embodiment, the 2nd WL 1102 terminates after connection 1104, but at a point before the connection to the control circuit for the array. In another embodiment, the 2nd WL 1102 extends to the control circuit, and the 1st WL 116 terminates after connection 1104, but at a point before the connection to the control circuit for the array. In other words, in one embodiment, the control circuit activates one of the 1st WL 116 and the 2nd WL 1102 (where the other word line is not connected to the control circuit). Nevertheless, due to their connection, both the WL 116 and the 2nd WL 1102 are provided in the same condition.(Note that, as with the bit lines shown, the difference in width between the first WL 116 and the second WL 1102 is for ease of reference and is not intended to enforce such a configuration.) For example, the voltage at the first WL 116 can be raised or lowered by a driver element. In one embodiment, the first WL 116 is directly coupled to the driver element, while the second WL 1102 is coupled to the first WL 116 and receives its state (e.g., voltage) only via the first WL 116.

[0054] The 1st WL 116 and the 2nd WL 1102 may consist of conductive materials, including, for example, aluminium, aluminium alloy (e.g. aluminium / silicon / copper), copper, copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, silicide, polysilicon and / or other suitable conductive materials.

[0055] The Fig. 12 and Fig. Figure 13 shows cross-sectional views of two different embodiments of the device 200'''. Fig. 11. Fig. Figure 12 shows that the first BL 110 is arranged on the first metal conductor (for example, M1) and the second BL 112 is arranged on a second metal conductor (for example, M2). The second metal conductor can be the next adjacent metal conductor above the first metal conductor. Thus, in one embodiment, the first BL 110 and the second BL 112 are coupled by the through-hole 114 (e.g., via 1), which extends from the first metal layer to the second metal layer. In the embodiment shown in Fig. In the embodiment shown in Figure 12, the first WL 116 is arranged on a third metal conductor and the second WL 1102 is arranged on a fourth metal conductor. The fourth metal conductor can be the next adjacent metal conductor above the third metal conductor. Thus, in one embodiment, the first WL 116 and the second WL 1102 can be coupled by a via (not shown) extending from the third metal conductor to the fourth metal conductor (e.g., via 4).

[0056] Fig. Figure 13 shows that the first BL 110 is arranged on the first metal conductor (e.g., M1) and the second BL 112 is arranged on a third metal conductor (e.g., M3). The first WL 116 is arranged on the intermediate metal conductor (e.g., M2). The second WL 1102 is arranged on the fourth metal conductor (e.g., M4). Thus, in one embodiment, the first BL 110 and the second BL 112 are coupled by vias 702 and a contact surface 704 (e.g., via 2, metal-3 contact surface, and via 3) extending from the first metal layer to the third metal layer. In an embodiment of Fig. In Figure 13, the first WL 116 is arranged on a second metal conductor and the second WL 1102 on a fourth metal conductor, with the second BL 112 located on the intervening third metal conductor. Thus, in one embodiment, the first WL 116 and the second WL 1102 can be coupled by vias and contact surfaces extending from the second metal conductor to the fourth metal conductor (e.g., Via 3, contact surface at Metal-3, Via 4).

[0057] Fig. 14A and Fig. Figure 14B shows a layout view or a cross-sectional view of section 1402 of a storage device. In one embodiment, section 1402 is an embodiment of the memory cell 108 of the storage device 200''', which is described above with reference to the Fig. 12 and Fig. Section 1402 can include memory cell 108 as an SRAM memory cell. Layout section 1402 includes the 1st BL 110, the 2nd BL 112, the 1st BL_bar 202, the 2nd BL_bar 204, the 1st WL 116, and the 2nd WL 1102. Layout section 1402 further includes various Vdd lines (e.g., Metal-1) and various Vss lines (e.g., Metal-1) 1404 and word line contact pads (e.g., Metal-1, Metal-2) 1406.

[0058] In the Fig. 14A and Fig. In the embodiment shown in Figure 14B, the first BL 110 and the first BL_bar 202 are each formed on a first metal layer (e.g., M1). The second BL 112 and the second BL_bar 204 are formed on a second metal layer (e.g., M2), which is the next adjacent metal layer above the first metal layer. Thus, the via 206 extends from the first BL 110 to the second BL 112 and connects the bit lines. The first WL 116 is arranged on a third metal layer (e.g., M3) above, which is the next adjacent metal layer to the first metal layer. The second WL 1102 is arranged on a fourth metal layer (e.g., M4) above, which is the next adjacent metal layer to the third metal layer. A via (not shown) connects the first WL 116 and the second WL 1102.

[0059] A via 410 shows a connection between the 1st BL_bar 202 and an underlying element of the memory cell 108, including, for example, one that is located in the Fig. 17, Fig. 18 and Fig. Figure 19 shows that in one embodiment, the via 410 connects the first BL_bar to the source / drain of a transistor of the memory cell 108 (e.g., a drain node of a pass-gate device in the cell 108 as an SRAM device). Fig. Figure 14B shows a corresponding cross-sectional view along section HH' of layout section 1402 of Fig. 14A, which has the 1st BL_bar 202, the 2nd BL_bar 204, the 1st WL 116 and the 2nd WL 1102 on successive metal layers, wherein the via 410 provides a connection with the underlying element of the memory cell 108 (e.g. a transistor which is electrically connected to, for example, a drain node of a pass-gate device of an SRAM).

[0060] Fig. Figure 15 shows a storage device 200'''' having memory cells 108 configured and operated as a plurality of subarrays 1502. Some embodiments of the storage device 200'''' having a plurality of subarrays may provide improvements such as increased storage speed, since accessing smaller subarrays may be faster than accessing a single large array. Aspects of one or more of the embodiments of the storage device 200 described above may be applied to the configuration of the storage device 200'''' (e.g., an additional WL, additional connections between the first BL 110 and the second BL 112, additional connections between the first BL_bar 110 and the second BL_bar 112, connections between BLs on non-adjacent metal layers with contact surfaces, and / or other features described above). Fig. Reference 15 provides an exemplary embodiment of a storage device 200'''' comprising two subarrays; however, any number of subarrays and subarrays of any size are possible. In one embodiment, the storage device 200'''' is a multi-array SRAM.

[0061] Fig. Figure 16 shows a method 1600 for manufacturing a storage device, which can be used to manufacture one or more of the storage devices referred to above. Fig. The method 1600 begins at block 1602, in which a substrate is provided with a plurality of elements defined thereon, comprising memory cells configured in an array. The memory cells can be SRAM, DRAM, ROM, and / or other suitable memory types. In one embodiment, the memory cells can be substantially similar to those described above with reference to memory cells 108.

[0062] Procedure 1600 then continues with block 1604, which provides a layout for a multilayer interconnect (MLI) that has a dual- or two-connection structure for at least one bit line, complementary bit line, or word line. The dual- or two-connection structure may be substantially similar to that described above with reference to the Fig. as described in Figures 1-15. In one embodiment, the double interconnection structure comprises a first bit line located on a first metal layer and belonging to a column of a memory array, and further comprises a second bit line located on a higher metal layer than the first bit line, coupled to the first bit line, and also belonging to the same column of the memory array. In another embodiment, the double interconnection structure comprises a first complementary bit line located on a first metal layer and belonging to a column of a memory array, and further comprises a second complementary bit line located on a higher metal layer than the first complementary bit line, coupled to the first complementary bit line, and also belonging to the same column of the memory array.In one embodiment, the dual interconnect structure comprises a first word line located on a metal layer and belonging to a row of a memory array, and further comprises a second complementary bit line located on a higher metal layer than the first word line, coupled to the first word line, and also belonging to the same row of the memory array. Block 1604 may include providing a layout substantially similar to any of the layouts described above, including those of the . Fig. 1, Fig. 2, Fig. 4A, Fig. 5, Fig. 7, Fig. 9A, Fig. 10A, Fig. 11, Fig. 14A and / or 15.

[0063] Method 1600 then proceeds to Block 1606, in which a first interconnect is provided on a metallization layer belonging to a given row (or column) of the array, and the interconnect is coupled to an element (for example, a transistor) of the cell of the memory array in the given row / column. The first interconnect is formed according to the layout provided in Block 1604. The interconnect can be formed from Cu, Co, Ni, Ru, W, Al, conductive alloys, and combinations thereof. The interconnect can be formed by depositing conductive material into structured openings in a dielectric. In some embodiments, the deposition of the conductive material is followed by suitable back-etching or chemical-mechanical polishing processes.In some embodiments, adjacent vias can be formed simultaneously with the formation of the first connecting line (e.g., by Damascene processes).

[0064] Method 1600 then proceeds to block 1608, in which a second interconnect is formed on a further metallization level and coupled to the first interconnect, the second interconnect belonging to the given row / column. A via connecting the interconnect of block 1606 and the second interconnect of block 1608 can be formed with the second interconnect. The interconnect can be formed from Cu, Co, Ni, Ru, W, Al, conductive alloys, and combinations thereof. The interconnect can be formed by depositing conductive material into structured openings in a dielectric. In some embodiments, the deposition of the conductive material is followed by suitable back-etching or chemical-mechanical polishing processes.In some embodiments, adjacent vias can be formed simultaneously with the formation of the first connecting line (e.g., by Damascene processes).

[0065] Method 1600 further comprises a layout and / or deposition method by which the first interconnect of block 1606 and the second interconnect 1608 are connected to peripheral circuits of the storage device, as shown in block 1610. Thus, when performing a read or write operation on the memory cells, the first interconnect and the second interconnect (e.g., in the array or the addressable cell) are provided in the same state.

[0066] Fig. 17, Fig. 18 and Fig. Figure 19 shows various schematic representations of memory cells that can be implemented using aspects of the present disclosure described above. One or more of the memory cells described above 108 can be represented by the schematic representation (e.g., of the transistors, capacitors) of the Fig. 17, Fig. 18 and / or 19 are shown. Furthermore, the bit lines (BL), complementary bit lines (BLB), and word lines (WL) shown in the schematic diagram can be implemented as described above with reference to the 1st BL 110, the 1st BL_bar 202, and the WL116. For example, the track BL in the schematic diagrams can be constructed as a 1st BL 110 and a 2nd BL 112, where the 1st BL 110 provides the connection as shown in the schematic diagram, and the 2nd BL 112 is analogously connected to the cell via the 1st BL. As another example, the complementary bit line BLB can be constructed with a single track as a complementary double bit line structure, for example like the 1st BL and the 2nd BL_bar above, where the 1st BL_bar 202 provides the connection as shown by the schematic representation, and the 2nd BL_bar 204 is analogously connected to the cell via the 1st BL_bar 202. Fig. Figure 17 shows exemplary single-port SRAM cell circuits. Fig. Figure 18 shows an example ROM cell. Fig. Figure 19 shows an example DRAM cell. These schematic representations are only examples; for instance, a 6T transistor SRAM cell is shown in Fig. 17 shown, however other configurations are also possible, including dual-port SRAM cells.

[0067] Fig. Figure 20 shows a substrate 2001 comprising a plurality of gates 2002 and overlying multilayer interconnects 2004, which include a plurality of metal layers and intervening vias (via 1, M1, via 2, M2, via 3, M3, via 4, M4). The exemplary MLI 2004 can be used to implement any of the embodiments described above for a storage device.

[0068] The gates, for example gate 2002, can be used to control a transistor or part of it (including those located in the Fig. 17, Fig. 18 and Fig.(as shown in Figure 19) of the memory cell, for example, the memory cell 108 described above. The gate 2002 can have a gate electrode and an underlying gate dielectric. A source / drain region 2004 is adjacent to the gate 2002, thereby forming the transistor. In one embodiment, one or more gate transistors of the memory cell 108 are formed, and the source / drain 2004 is electrically connected to the first BL (e.g., BL 110) or the first BL bar (e.g., BL bar 202), which are formed in Metal-1 (M1). This connection is provided by a via (e.g., via 1 extending beneath Metal-1), substantially similar to the via 410, and an underlying contact element. The contact element can be made of tungsten, silicide, or another suitable conductive material.

[0069] This disclosure provides an interconnection architecture for memory cells of an array that can reduce resistance by improving the interconnection paths between points in the storage device (e.g., the arrays and / or peripheral devices). The improved interconnection paths include providing one or more additional bit lines, additional complementary bit lines (bit line bars), additional word lines, and / or other configurations described herein. The improved interconnection paths can be described as a double-line or stripe structure. The improved interconnection provides an additional conductor between two or more points, provided by a given metal conductor (e.g., BL) on the first metal layer, by also providing the path / connection, or parts thereof, on a second metal layer.In some embodiments, a dual bit-line structure is provided. In one embodiment, a dual bit-line bar (or complement of the bit line) structure is provided. In another embodiment, a dual word-line structure is provided. One or more of these embodiments can be used simultaneously in a storage device.

[0070] In one embodiment, a storage device is provided that has an array of memory cells arranged in columns and rows. Any number of rows or columns can be provided. The storage device includes a first bit line coupled to memory cells in a first column of the array. A second bit line is coupled to the first bit line and thus also to the memory cells in the first column of the array. The second bit line can be arranged on a different metal layer (for example, the MLI) than the first bit line. In one embodiment, the second bit line is coupled to the first bit line at least twice.For example, the lines can be coupled by a first via extending between the first and second bit lines, and a second via at a distance from the first via, also extending between the first and second bit lines. In one embodiment of the configuration, a single word line is coupled to memory cells of the first row of the array. In other embodiments, a dual-word-line configuration is provided, as described below. Both the first and second bit lines and the word line can be formed on different metallization layers, for example, different layers of the MLI.

[0071] Thus, in one embodiment, a memory array is provided that has a plurality of cells, wherein a first bit line is coupled to a first column of the array and a first word line is coupled to a first row of the array. The embodiment can further include a second bit line that is coupled to the first bit line at least twice for the first column of the array. The embodiment can further include a second word line that is coupled to the first word line at least twice for the first row of the array. The first and second bit lines are formed on different metallization layers but belong to the same column. The first and second word lines are formed on different metallization layers but belong to the same row.

Claims

[1] Storage device comprising: an array of memory cells (108); a first bit line (110) coupled to memory cells (108) of a first column of the array of memory cells (108), wherein the first bit line (110) is arranged on a first metal layer; a second bit line (112) coupled to the first bit line (110), wherein the second bit line (112) is arranged on a second metal layer and coupled to the first bit line (110) via at least one via (114); and a word line (116) that is coupled to a row of the array of memory cells (108), wherein the at least one via (114) is arranged on a first edge cell region of the array and wherein a further via (114) coupling the first and second bit lines (110, 112) is arranged on a second edge cell region of the array, the second edge cell region being on a side of the array opposite the first edge cell region. [2] Storage device according to claim 1, wherein the at least one via (114) extends from the first metal layer to the second metal layer. [3] Storage device according to one of the preceding claims, wherein the at least one via (114) is arranged at a cell edge between cells of the array. [4] Storage device according to any one of the preceding claims, further comprising: a first complement bit line (202) coupled to memory cells of the first column of the array of memory cells, wherein the first complement bit line (202) is arranged on the first metal layer; a second complement bit line (204) coupled to the first complement bit line, wherein the second complement bit line (204) is coupled to the first complement bit line (202) at least two points, wherein the second complement bit line (204) is arranged on the second metal layer. [5] Storage device according to any one of the preceding claims, further comprising: a second word line (1102) which is coupled with the word line (116) and is assigned to the row of the array. [6] Storage device according to one of the preceding claims, wherein the second metal layer is located above the first metal layer and wherein the word line (116) is arranged on a third metal layer above the second metal layer, wherein the second metal layer is a nearest adjacent metal layer to the first metal layer. [7] Storage device according to any one of claims 1 to 5, wherein the first metal layer and the second metal layer are part of a multilayer intermediate, wherein the first metal layer is Metal-1 (M1) and the second metal layer is Metal-3 (M3) and wherein the word line is part of the MLI and is arranged on Metal-2 (M2), wherein M2 lies over M1 and M3 lies over M2. [8] Storage device according to one of the preceding claims, wherein the first bit line (110) is connected to a transistor of the memory cell via a second via which extends under the first metal layer. [9] Storage device according to one of the preceding claims, wherein the row and column are located in a first array of memory cells (108) and wherein the storage device further comprises: a second array of memory cells (108) that are spaced a distance from the first array of memory cells; a third bit line coupled to memory cells (108) of a first column of the second array of memory cells, wherein the third bit line is arranged on the first metal layer; a fourth bit line coupled to the third bit line, the fourth being located on the second metal layer; and another word line that is coupled to a row of the second array of memory cells. [10] Storage device according to one of the preceding claims, wherein the memory cells (108) are of one of DRAM, SRAM, ROM. [11] Storage device comprising: an array of memory cells (108); a first bit line (110) coupled to memory cells of a first column of the array of memory cells, wherein the first bit line (110) is arranged on a first metal layer; a second bit line (112) coupled to the first bit line (110), wherein the second bit line (112) is arranged on a second metal layer above the first metal layer; a first complement bit line (202) coupled to memory cells (108) of the first column of the array of memory cells (108), wherein the first complement bit line (202) is arranged on the first metal layer; a second complement bit line (204) coupled to the first complement bit line (202), wherein the second complement bit line (204) is arranged on the second metal layer; a word line (116) that is coupled to a row of the array of memory cells (108). [12] Storage device according to claim 11, wherein the first metal layer is the Metal-1 (M1) layer of a multilayer intermediate and the second metal layer is the Metal-2 (M2) layer of the multilayer intermediate. [13] Storage device according to claim 11 or 12, wherein the word line (116) lies on metal 3 (M3) of the multilayer intermediate. [14] Storage device according to claim 11, wherein the first metal layer is the layer Metal-1 (M1) of a multilayer intermediate and the second metal layer is the layer Metal-3 (M3) of the multilayer intermediate and the word line (116) lies on Metal-2 (M2) of the multilayer intermediate. [15] Storage device comprising: an array of cells, where one cell (108) is from the array: a pass-gate transistor; a first bit line (110) connected to a drain node of the pass-gate transistor; and a second bit line (112) which is connected to the first bit line (110) via a via (114), wherein either the first or the second bit line (110, 112) extends to a control circuit for the storage device, wherein the first bit line (110) is arranged on a first metal layer and the second bit line (112) is arranged on a second metal layer; wherein the via (114) is arranged on a first edge cell region of the array and wherein a further via (114) coupling the first and second bit lines (110, 112) is arranged on a second edge cell region of the array, the second edge cell region being on an opposite side of the array from the first edge cell region. [16] Storage device according to claim 15, further comprising: a first word line (116) which is connected to a gate of the pass-gate transistor; a second word line (1102) connected to the first word line, with either the first or the second word line (116, 1102) extending to the control circuit for the storage device. [17] Storage device according to claim 15 or 16, wherein the second bit line (112) is connected to the first bit line (110) via the via (114) which is arranged at an edge of the cell (108). [18] Storage device according to claim 15 or 16, wherein the second bit line (112) is connected to the first bit line (110) via the via (114) which is arranged outside the edge of the cell. [19] Storage device according to any one of the preceding claims 15 to 18, wherein the via (114) extends from a first metal conductor to a second metal conductor, wherein the first bit line (110) is arranged on the first metal conductor and the second bit line (112) is arranged on the second metal conductor.

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