Method for estimating a temperature of a transistor

Abstract

A method for estimating a junction temperature or chip temperature of a transistor (61, 62, 63, 64, 65, 66, 700), the method comprising: Measuring a voltage change (dv ce / dt) when turning off with respect to the change in a time between a collector (41, 51) and an emitter (43, 53) of a transistor (61, 62, 63, 64, 65, 66, 700) in a phase of an inverter (50); Measuring a peak voltage (v cepeak ) of the transistor (61, 62, 63, 64, 65, 66, 700) between the collector (41, 51) and the emitter (43, 53); Determining a breaking current (i ceturnoff ), an inrush current (i ceturnon ) and a forward voltage drop (v ceon ) based on the turn-off voltage change (dv ce / dt) and the peak voltage (v cepeak ) as intermediate parameters; Determining an energy loss for a switching cycle of the transistor (61, 62, 63, 64, 65, 66, 700) based on the turn-off current (i ceturnoff ), the inrush current (i ceturnon ) and the forward voltage drop (v ceon ) between the collector (41, 51) and the emitter (43, 53) of the transistor (61, 62, 63, 64, 65, 66, 700); and Estimating a corresponding average junction or chip temperature of the transistor (61, 62, 63, 64, 65, 66, 700) over the switching cycle based on the determined energy loss, an observed inverter system temperature, and a temperature characteristic of an inverter system.

Description

[0001] This disclosure relates to a method for estimating a temperature of a transistor; in particular, for estimating a junction or chip temperature of a transistor. background

[0002] In semiconductor devices, certain prior art temperature sensing systems utilize a thermally sensitive resistor spaced from the semiconductor die to ensure adequate electrical isolation and reduce noise associated with semiconductor switching devices. In the steady-state mode of a transistor using a thermally sensitive resistor (such as a thermistor with a negative temperature coefficient), the estimated junction temperature of the transistor is more accurate than in transient mode, but is still not sufficiently accurate for some control applications for inverters driving electric motors. Thus, there is a need for an improved method for estimating the junction or die temperature of a transistor in real time, allowing for improved accuracy.

[0003] Regarding the state of the art, reference is also made to documents US 2013 / 0 177 041 A1 and CN 1 04 090 224 A. Brief description

[0004] A method is presented for estimating the junction temperature (of a bipolar transistor), channel temperature (of a field effect transistor) or generally the chip temperature of a semiconductor switching device, which determines the turn-off voltage change (e.g., a rate of voltage rise (dv ce / dt)) with respect to the change over time between a collector and emitter (or drain or source, respectively) of a transistor in one phase of an inverter. A detector measures the peak voltage (e.g., v cepeak ) of the transistor between the collector and the emitter (or drain or source).

[0005] An electronic data processing device determines as an intermediate parameter the breaking current (e.g. i ceturnoff ), the inrush current (e.g. i ceturnon) and the forward voltage drop (e.g. v ceon ), based on the turn-off voltage change (e.g. dv ce / dt) and the peak voltage (e.g. v cepeak ). The data processing device determines the energy loss for one switching cycle of the transistor based on the off current (e.g., i ceturnoff ), the inrush current (e.g. i ceturnon ) and the forward voltage drop (e.g. v ceon) between the collector and emitter (or drain or source, respectively) of the transistor. The data processing device estimates a corresponding average junction or chip temperature for the transistor over the switching cycle based on the determined power loss, the observed inverter system temperature (e.g., coolant temperature of a coolant in a coolant system) for cooling the inverter, and the thermal characteristics of an inverter system (e.g., thermal resistance of a liquid-cooled system) for the inverter. Short description of the drawings Fig. Figure 1 is a schematic diagram of a system for estimating the junction temperature or chip temperature of a transistor. Fig. Figure 2 is a schematic diagram of a system for processing forward power dissipation and measuring transistor voltages during an on-state. Fig. Figure 3 is a diagram of the waveforms encountered by transistors in an inverter, illustrating a complete switching cycle. Fig. 4 is a flowchart of one embodiment of a method for estimating the junction temperature or chip temperature of a transistor. Fig. 5 is a flowchart of another embodiment of a method for estimating the junction temperature or chip temperature of a transistor. Fig. 6 is a flowchart of yet another embodiment of a method for estimating the junction temperature or chip temperature of a transistor. Fig. Figure 7 is a schematic of a system for detecting a mirror current through a transistor. Fig. Figure 8 is a graph of the number of power cycles remaining for an inverter versus the change in temperature of its transistors. Detailed description

[0006] The junction temperature applies to the junction of a bipolar transistor (61, 62, 63, 64, 65, 66). The chip temperature means the junction temperature of a bipolar transistor (61, 62, 63, 64, 65, 66) or the channel temperature of the depletion or enhancement mode channel of a field-effect transistor or the chip temperature of any other transistor or any other semiconductor device. The junction temperature or chip temperature can be measured over the entire switching cycle or at any instantaneous time during the switching cycle. The chip temperature can vary over time during the switching cycle, with the variation being reduced during steady-state conditions, for example, with fixed electrical loads (e.g., inverter load from operating an electric motor at a range-bound or constant speed and torque) and static ambient temperature.

[0007] The following terminology is used in this document: Transistor voltages: (1) v ceon means forward voltage drop or potential (e.g. on-state, steady-state voltage drop) between the collector (41, 51) and the emitter (43, 53) (or drain or source respectively), (2) v ce_turnon means the voltage potential across the transistor (61, 62, 63, 64, 65, 66) during switching on, therefore means the voltage drop between the collector (41, 51) and emitter (43, 53) (or drain or source respectively) when switching on and v ce_turon (t) shows the voltage drop waveform with respect to time; (3) v cepeak means a peak voltage of the transistor (61, 62, 63, 64, 65, 66) between the collector (41, 51) and the emitter (43, 53) (or drain or source respectively), (4) dv ce / dt means the change in voltage with respect to time between a collector (41, 51) and an emitter (43, 53) (or drain or source, respectively) of a transistor in one phase of an inverter 50; and (5) v ge means the voltage potential between the gate and the emitter (43, 53) or between the base and the emitter (43, 53).

[0008] Transistor currents: (1) i ceturnoff or i igbt_turnoff means breaking current; (2) i ceturnon or i igbt_turnon denotes the inrush current of a transistor (61, 62, 63, 64, 65, 66); similarly, and (3) T joff or T j_tumoff means junction or chip temperature at turn-off, and (4) i a is a first phase current (i a ) or, more generally, the current (i a , i b , i c) from a phase (e.g. first phase 90, second phase 92 or third phase 94) of an inverter 50, which flows via the collector-emitter path or drain-source path of the transistor (61, 62, 63, 64, 65, 66).

[0009] Fig. Figure 1 is a schematic diagram of a system for estimating the junction temperature or chip temperature of a transistor (61, 62, 63, 64, 65, 66). The temperature estimation system of the Fig. 1 can be applied in the same way to a bipolar transistor or a field-effect transistor. Furthermore, the estimation system can be applied to an inverter 50 using one or more transistors (61, 62, 63, 64, 65, 66) in conjunction with a liquid-cooled cooling system (e.g., pump and heat sink) or an air-cooled system.

[0010] In Fig. 1, the system comprises a driver module 18. In one embodiment, the driver module 18 comprises one or more gate driver stages 20 or base drivers to drive respective input terminals (e.g., at the gate or base 70) of each phase (e.g., first phase 90, second phase 92, and third phase 94) of an inverter 50. An illustrative example of a gate driver stage 20 is shown for the first high-side transistor 61 (S1) in Fig. 1. The gate driver stage 20 includes a group of resistors (24, 26, 28) connected to a driver output node (e.g., at the base or gate 70). In turn, the output node is connected to the gate or base 70 of the first high-side transistor 61 (S1). With respect to the gate driver module 18, other gate driver stages, similar to the gate driver stage 20, may be connected in a similar manner to the corresponding transistors (62, 63, 64, 65, 66) within the inverter 50.

[0011] Even if the inverter 50 of Fig. 1 has three phases (90, 92, 94), it is understood that the inverter 50 can be used and configured for a single phase or multiple phases in other embodiments that fall within the scope of the appended claims. Each phase of the inverter 50 includes a pair of transistors, which may be referred to as a low-side transistor (62, 64, 66) and a high-side transistor (61, 63, 65). The high-side transistor (61, 63, 65) has a collector 51 or drain connected to the high side or positive DC bus terminal 67 (V DC). The low-side transistor (62, 64, 66) has an emitter 43 or source coupled to the low side or negative DC bus terminal (e.g., ground 30). Each phase (90, 92, 94) has a low-side input terminal (72) which is the base or gate of the low-side transistor (62, 64, 66), which is fed and controlled by a gate driver module 18. The output signals of the gate module 18 may use one or more resistors to limit the drive current or to match the impedance to the power transistors (61, 62, 63, 64, 65, 66) of the inverter 50. Each phase (90, 92, 94) has a high-side input terminal which is the base or gate of the high-side transistor (61, 63, 65) powered and controlled by the gate driver module 18.Each phase (90, 92, 94) has an output node (80, 82, 84) formed at the junction or coupling of the emitter 53 of one transistor and the collector 41 of the other transistor of the single-phase pair. In an exemplary embodiment, an optional protection diode 68 may be connected between the collector (41, 51) and emitter (43, 53) of each transistor or between the drain and source of any field-effect transistor.

[0012] In Fig. 1, there is a low-side transistor inductance (21, 23, 35), a high-side transistor inductance (31, 33, 35), and an output reactance (13, 15, 17) associated with each phase (90, 92, 94) of the inverter 50. In one embodiment, the output reactance (13, 15, 17) comprises an output cable resistance and an output cable inductance. The low-side transistor inductance (21, 23, 35), the high-side transistor inductance (31, 33, 35), and the output reactance (13, 15, 17) represent modeled values ​​(or mathematical representations) for modeling the electric machine 52 (e.g., a motor) and the electrical conductor (e.g., a cable) connecting the inverter 50 and the electric machine 52. Accordingly, in Fig. 1, the modeled values ​​and their corresponding electrical symbols for the low-side transistor inductance (21, 23, 35), the high-side transistor inductance (31, 33, 35), and the output reactance (13, 15, 17) are not physically present as inductors, resistors, or other electrical components in functional embodiments of the system, and therefore, such respective electrical symbols may be deleted from certain illustrations of this embodiment or other embodiments of the system and method for estimating a junction temperature or chip temperature of a transistor. Herein, the electrical symbols and blocks for the modeled values ​​are for illustrative purposes only, where their physical realizations (to the extent present) are inherent features or characteristics of the transistors and cables between the output phase terminals and the electric machine 52.

[0013] As illustrated, the electric machine 52 may include a motor or a generator with multiple phases. The output node (80, 82, 84) of each phase is connected to the corresponding terminals of the electric machine 52. The electric machine 52 may include an electric motor or a generator. For example, the electric machine 52 may include a permanent magnet motor or an induction motor. The electric machine 52 may be capable of operating in a motoring mode, a power generation mode, or both. In a motoring mode, the electric machine 52 provides control signals, such as pulse-width modulated or other AC signals, to control the torque, rotor speed, and acceleration of a motor. In a power generation mode, the inverter 50 converts generated AC power to DC power.

[0014] The motor or electric machine 52 may be connected to a rotor position sensor 54 or encoder for detecting a position of a rotor of the electric machine 52 or rotor. The rotor position sensor 54 provides rotor position data to a control unit 10 for processing.

[0015] In one embodiment, the control unit 10 may include one or more data processing devices 12, a data bus 14, a data storage device 16, and one or more data ports 207. A data processing device 12 may include a microcontroller, a microprocessor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a programmable logic device (PLA), a programmable gate array (PGA), or other electronic data processing device. The data processing device 12 is capable of executing software instructions or software stored in or retrieved from the data storage device 16 to estimate the junction temperature or chip temperature of a transistor in accordance with the method and system described in this disclosure.The data storage device 16 may comprise a memory, a random access electronic memory, a non-volatile electronic memory, a magnetic storage device, an optical storage device, or other electronic data storage device.

[0016] The data storage device 16 may be used to store software, software instructions, measurement data, or other data, such as thermal characteristics 205 for the inverter 50 system (e.g., the liquid or air-cooled system thereof) and any equations or lookup table references in this document.

[0017] In one embodiment, an inverter system temperature sensor 209 may provide temperature data or sensor data to the control unit 10 via a data interface. For example, the temperature sensor 209 may include a thermistor or other temperature sensor that provides the coolant temperature of a liquid-cooled cooling system for the inverter or the enclosure temperature of an air-cooled system for the inverter.

[0018] At a data port 207, the control unit 10 also receives peak voltage measurement data and voltage rise data via a detector 47 coupled (directly or indirectly) to at least one of the inverter phases (90, 92, 94). Although a detector 47 is shown as connected to a high-side transistor 61 (S1) at a collector 51 or drain, it should be understood that each phase or transistor may be associated with (or multiplexed to share a single detector) a corresponding detector for estimating the temperature of the respective transistor (61, 62, 63, 64, 65, 66) associated with such phase.

[0019] In an alternative embodiment, the control unit 10 may further include an optional counter 77, which is shown in dashed lines to indicate that this is optional and may be omitted in certain configurations. The optional counter 77 may be used to count the number of complete power cycles, pulses, or periods (316) of the respective waveforms 300 (in Fig. 3) counting the one or more outputs of the driver module 18 which drive the transistors (61, 62, 63, 64, 65, 66).

[0020] The detector 47 is associated with a detection circuit 60. In one embodiment of the detection circuit 60, a blocking diode 32 (D BLK ) to the high-side input (e.g. at the gate 70) of the high-side transistor 61 in series with a clamping resistor 34 (R CLAMP). A group of avalanche diodes, Zener diodes, or other multimode diodes (36, 38, 40, 42) are cascaded in series. For example, a multimode diode can include Zener diodes or transient voltage suppression (TVS) diodes.

[0021] A unidirectional TVS diode is an avalanche diode or multimode diode that: (a) operates in a conventional rectifier mode when forward biased, (b) operates in a DC blocking mode when reverse biased below the breakdown voltage, and (c) operates in a voltage clamp mode capable of holding the voltage at a substantially fixed voltage when reverse biased and above the breakdown voltage, with the diode connected in parallel and capable of withstanding very large peak or transient currents without damage in voltage clamp mode. A Zener diode is a diode that can exhibit both Zener breakdown and avalanche breakdown, but does not provide the same level of current transient overvoltage protection as a TVS diode.A Zener diode or a multimode diode operates: (a) in a conventional current blocking mode when forward biased, (b) in a DC blocking mode when reverse biased and below breakdown voltage, and (c) in a clamping mode that holds the voltage at a substantially fixed voltage when reverse biased and above breakdown voltage.

[0022] Here, using an insulated gate bipolar transistor (IGBT) (e.g., a PNPN configuration, as illustrated for illustrative purposes without limiting the transistor polarity for general applications of the system), the cathode of the first multimode diode 36 is connected to the collector 51 or drain. In other embodiments, the transistor (61, 62, 63, 64, 65, 66) may comprise a metal-oxide-semiconductor field-effect transistor (MOSFET), a transistor, or other semiconductor, instead of an IGBT. The last multimode diode 42 in the series is connected to the clamping resistor 34. The clamping resistor 34 is, in turn, coupled to a voltage divider resistor network (44, 46) that feeds the detector 47. A Zener diode 48 is connected in parallel with a grounded resistor of the resistor network (44, 46).

[0023] In one embodiment, a blocking diode 32 is connected between the driver module 18 and the clamping resistor 34 or the resistor network (44, 46). When a high logic level is applied to the blocking diode 32 from the driver module 18, the blocking diode 32 is reverse biased and prevents the development of a voltage potential across the sense resistor 46 (R2) or the resistive voltage divider. However, once the resistor network (44, 46) is at or near peak voltage and the driver module 18 output is at a low logic level, the blocking diode 32 can be forward biased to discharge the sensed voltage through the sense resistor R2 to the low logic signal or ground 30.The TVS diodes (36, 38, 40, 42), the clamping resistor (34), and the blocking diode (32) work together to charge the gate-to-source capacitance of transistor 61 when there is excessive voltage across terminals 51 and 53 of transistor 61. As a result of charging the gate-to-source capacitance, the voltage across terminals 51 and 53 is contained (meaning that the voltage does not exceed the rated voltage value). Accordingly, the circuit of the TVS diodes (36, 38, 40, 42), the clamping resistor (34), and the blocking diode (32) functions as an active clamping circuit.

[0024] In one embodiment, the detector (47) measures the off-change (or off-change rate or voltage rise) voltage (dv ce / dt) with respect to the change over time due to a drop in the applied voltage from the driver module 18 at the gate (e.g. 70) or due to a drop in the transistor gate voltage (v ge) is triggered to turn off an active transistor (e.g. 61). In case of a drop in the applied voltage from the driver module 18 at the gate (70, 72) or a drop in the transistor gate voltage (v ge To turn off an active transistor (e.g., 61), detector 47 measures a collector voltage of the transistor (e.g., 61) across a series of cascaded multimode diodes (36, 38, 40, 42) that feed a resistive voltage divider (44, 46), including sense resistor 46 (R2). Sensing resistor 46 is connected in series with Zener diode 48 to limit the voltage magnitude in sense resistor 46.

[0025] Similarly, in one configuration, the measurement of the peak voltage (v cepeak ) of the transistor (61, 62, 63, 64, 65, 66) by a drop in the applied voltage from the driver module 18 at the gate (70, 72) or by a drop in the transistor gate voltage (v ge) is triggered by the driver module 18 to turn off an active transistor (e.g. 61). In case of a drop in the applied voltage from the driver module 18 at the gate (70, 72) or in case of a drop in the transistor gate voltage (v ge ) to turn off an active transistor (e.g., 61), the detector 47 measures a change (e.g., a pulse or transient spike) in a collector voltage of the transistor (e.g., 61) across a series of cascaded multimode diodes (36, 38, 40, 42) feeding a resistive voltage divider (44, 46), including the sense resistor 46 (R2).

[0026] In an alternative embodiment, the detector may be coupled to the driver module 18 output to trigger the detection of the change in the measured voltage or pulse.

[0027] As in Fig. 1, the rate of voltage change across resistor 46 (R2) represents the rate of rise of the transistor turn-off voltage during transistor turn-off (e.g., the change in transistor turn-off voltage or dv ce / dt) or a first transistor parameter. The peak value of the voltage across resistor 46 (R2) represents the peak value of the transient voltage spike or voltage pulse that develops across the transistor (e.g., 61) during the turn-off event (e.g., v cepeak ) or a second transistor parameter. In one configuration, the transistor (e.g. 61) is for dv ce / dt rates with respect to a transistor junction temperature of minus 40°C to plus 175°C and a turn-off time (t off ) in relation to each dv ce / dt rate and a transistor junction temperature during turn-off (T joff ) marked; such dv ce / dt rates and corresponding temperatures are stored in lookup tables, files, inverted files, databases, or records in any suitable data structure (e.g., in the data storage device 16 for reference or retrieval by the processor 12).

[0028] Fig. Figure 2 is a schematic diagram of a system 201 for calculating forward power dissipation and measuring transistor voltages during an on-state. The forward power dissipation circuit of Fig. 2 can be used in conjunction with any of the transistors (for example, low-side transistors (62, 64, 66)) of the inverter 50 in Fig. 1 can be used to measure the voltage drop between the collector 41 and the emitter 43 (v ceon ) or between a drain and source when the transistor is turned on, in accordance with the voltage drop of the transistor gate voltage (v ge) between the gate 72 or the base and the emitter 43. An optional protection diode 68 is connected to the transistor. The same reference numerals in Fig. 1 and Fig. 2 denote identical elements.

[0029] A collector terminal of the transistor is connected to the diode 202. For example, the collector terminal or drain of the transistor (62, 64, 66) is connected to the cathode of the diode 202 and the anode of the diode 202 is connected in series with a resistor (R3) 204. A voltage source (V CC ) is connected in series with a resistor 208 (R4) and the capacitor 206 (C1). The node 218 between the resistor 208 (R4) and the capacitor 206 (C1) is connected to the resistor (R3) to measure the forward voltage drop (v ceon ) of the data processing device 12 via the optional signal converter 200 and the data connections 207. In Fig. 2, when the transistor (62, 64, 66) is turned on, the voltage across the capacitor 206 (C1) represents the forward voltage drop across the transistor, as v ceon The parameter of the transistor gate voltage (v ge ) is measured at the base or gate72 terminal of the transistor (62, 64, 66).

[0030] In one embodiment, an optional signal conditioner 200 is arranged between the output of the forward loss circuit and the input to the data terminals 207, which are in communication with the data processing device 12. The optional signal conditioner 200 is indicated as optional because it is shown with dashed lines and can be omitted in certain embodiments. The optional signal conditioner 200 can comprise a filter (e.g., a low-pass filter), a register, a flip-flop, a latch, or a memory device. The signal conditioner 200 can filter noise or fluctuations in the measured signals and / or (in a latch, flip-flop, or memory device) the voltage parameters (e.g., the forward voltage drop (v ceon ) and the transistor gate voltage (v ge)) provided by the forward loss circuit for further processing by the data processing device 12.

[0031] The data processing device 12 from Fig. 1 can determine certain voltage parameters (e.g. the forward voltage drop (v ceon ), the transistor gate voltage (v ge ), voltage in off state (v DC )) at one or more data ports 207 of the control unit 10; the data processing device 12 may receive other current parameters (e.g. i igbt_turnoff , i igbt_turnon ) as described in this document. The data processing device 12 can determine or calculate the above-mentioned voltage parameters (e.g., the forward voltage drop (v ceon ) and the transistor gate voltage (v ge )) to estimate the forward power / energy loss for a corresponding transistor (62, 64, 66).

[0032] Different waveforms are used in Fig. 3 for a switching period (T) 316 of a transistor (e.g., low-side or high-side transistor (61, 63, 65)), where the vertical axis represents the amplitude of each waveform and the horizontal axis represents time. As shown, the waveforms are synchronized or aligned with each other along the time axis to show the relative relationship of the waveforms over time.

[0033] A first waveform 300 represents a transistor base or gate voltage (v ge ) with an active interval of 314 (T ON ) and an inactive interval 312 (T OFF ) over an entire cycle or period T. For an NPN or PNPN transistor in an illustrative example, the transistor is off in the inactive interval and on in the active interval.

[0034] A second waveform 302 represents a transistor current (iigbt ) through the emitter (43, 53) and the collector (41, 51) or source and drain with a first magnitude 318 at a switch-on event (i igbt_turnon ) and a second magnitude of 320 in the case of a switch-off event (i igbt_turnoff ). The second waveform 302 has inflection points at the following times: t0, t1 and t2.

[0035] A third waveform 304 represents the voltage across the transistor (61, 62, 63, 64, 65, 66) with an off-state voltage (v DC ) and a voltage in the switched-on state (v ceon ). A fourth waveform 308 shows the voltage across the resistor (R2) in Fig. 1 (and can be used as v R2 A fifth waveform 310 illustrates the turn-on time (t on ) and the switch-off time (t off ) for the transistor. The turn-on time (t on ) and the switch-off (t off ) Runtimes are consistent with the other waveforms of Fig. 3 and are merely representative of possible waveforms of the transistors in accordance with this disclosure.

[0036] In accordance with one embodiment, Fig. 4 a flowchart of an embodiment of a method for estimating junction temperature or chip temperature of a transistor (61, 62, 63, 64, 65, 66).

[0037] In step S100, a detector 47, alone or in conjunction with the detection circuit 60, measures the turn-off voltage change (dv ce / dt) with respect to change over time between a collector (41, 51) and an emitter (43, 53) (or between drain and source) of the transistor (61, 62, 63, 64, 65, 66) in a phase (90, 92, 94) of an inverter 50. The turn-off voltage change may also be referred to as the voltage rise rate between a collector (41, 51) and emitter (43, 53) (or between drain and source) of a transistor in a phase of an inverter 50. In one embodiment, in response to the gate drive signal from the driver module 18, a change or drop in the transistor gate voltage (v ge ) to turn off an active transistor (61, 62, 63, 64, 65, 66), the detector 47 to measure the turn-off voltage change (or the rate or voltage rise of a pulse or the transient peak) (dv ce / dt) with respect to the change over time; and triggers the detector 47 to measure a voltage potential (v ce) between the collector (41, 51) and the emitter (43, 53) or between the drain and source of the transistor via a series of cascaded multimode diodes (36, 38, 40, 42) and a resistive voltage divider (44, 46). For example, the detector 47 can measure the turn-off voltage change (the rate or voltage rise of a pulse or the transient peak) (dv ce / dt) with respect to the change over time at or across the measuring resistor 46.

[0038] In step S102, a detector 47, alone or in conjunction with the detection circuit 60, measures the peak voltage (v cepeak ) of the transistor between the collector (41, 51) and the emitter (43, 53) or between the source and drain. For example, in response to the gate drive signal from the driver module 18, a change or drop in the transistor gate voltage (v ge) to turn off an active transistor (61, 62, 63, 64, 65, 66), the detector 47 to measure the peak voltage (v cepeak ) of a pulse or a transient spike of the transistor via a series of cascaded multimode diodes (36, 38, 40, 42) and a resistive voltage divider (44, 46). For example, the detector 47 can measure the turn-off voltage change in the peak voltage (v cepeak ) a transient spike or pulse at or across the measuring resistor 46.

[0039] In step S111, an electronic data processing device 12 determines as an intermediate parameter the breaking current (i ceturnoff ), the inrush current (i ceturnon ) and the forward voltage drop (v ceon ) based on the turn-off voltage change (dv ce / dt) and the peak voltage (v cepeak ) to allow estimation of the average energy loss for one cycle.

[0040] In step S112, the data processing device 12 determines the energy loss for one switching cycle of the transistor (61, 62, 63, 64, 65, 66) based on the turn-off current (i ceturnoff ), the inrush current (i ceturnon ) and the forward voltage drop (v ceon ) between the collector (41, 51) and the emitter (43, 53) or between the drain and source of the transistor.

[0041] In step S114, the computing device 12 estimates a corresponding average junction or average chip temperature for the transistor (61, 62, 63, 64, 65, 66) over the switching cycle (e.g., period 316) based on the determined energy loss, an observed inverter system temperature (e.g., coolant temperature of a coolant in a coolant system) for cooling the inverter 50, and a thermal characteristic of an inverter system (e.g., thermal resistance of a liquid-cooled system) for the inverter 50. An average junction or chip temperature may represent a mean junction or chip temperature, a median junction or chip temperature, or a mode junction or chip temperature.The temperature estimation method may be applied to an inverter 50 using one or more transistors (61, 62, 63, 64, 65, 66) in conjunction with a liquid-cooled coolant system (e.g., pump and heat sink) or an air-cooled system. For a liquid-cooled system, temperature sensor 209 provides a coolant temperature, while for an air-cooled system, temperature sensor 209 provides a case temperature of inverter 50. The liquid-cooled system may be associated with a first set of thermal characteristics 205 (e.g., first thermal resistance), while the air-cooled system may be associated with a second set of thermal characteristics 205 (e.g., second thermal resistance), wherein the first set is different from the second set.The thermal characteristics 205 are stored in the data storage device 16 for retrieval and processing by the data processing device 12.

[0042] In accordance with one embodiment, Fig. 5 shows a flowchart of another embodiment of a method for estimating the junction temperature or chip temperature of a transistor (61, 62, 63, 64, 65, 66). The method of Fig. 5 is similar to the procedure of Fig. 4, except that the procedure of Fig. 5 Step S111 of Fig. 4 is replaced with steps S104, S106, S108, and S110. Like reference numbers indicate like steps or operations.

[0043] In step S100, a detector 47, alone or in combination with the detection circuit 60, measures the turn-off voltage change (or voltage rise rate) (dv ce / dt) with respect to change over time between a collector (41, 51) and an emitter (43, 53) or between drain and source of a transistor (61, 62, 63, 64, 65, 66) in a phase (90, 92, 94) of an inverter 50.

[0044] In step S102, a detector 47, alone or in conjunction with the detection circuit 60, measures peak voltage (v cepeak ) of the transistor between the collector (41, 51) and the emitter (43, 53).

[0045] In step S104, the data processing device 12 estimates the junction or chip temperature at power-off (T joff or T j_turnoff ) of the transistor (61, 62, 63, 64, 65, 66) of step S100 on the basis of the measured turn-off change in the voltage (dv ce / dt). The transistor junction temperature is calculated as given in Equation 1: Tj_turnoff=fn(dvcedt)

[0046] In one configuration, the transistor (61, 62, 63, 64, 65, 66) is for dv ce / dt rates over transistor junction temperature or chip temperature over an operating range (e.g., from about minus 40°C to about plus 175°C). For example, before executing step S104 or before executing the method of Fig. 5, the transistor (61, 62, 63, 64, 65, 66) is characterized by one or more of the following features: (1) a respective turn-off time (t off ) in relation to each dv ce / dt rate or (2) a corresponding transistor junction temperature or chip temperature during turn-off (T joff ) in relation to each dv ce / dt rate. The dv ce / dt rates, a respective switch-off time (t off ) and chip temperature (T joff) may be stored in lookup tables, files, inverted files, databases, or records in any suitable data structure in the data storage device 16 for retrieval to perform Equation 1.

[0047] In step S106, the data processing device 12 determines the switch-off time (t off ) of the transistor (61, 62, 63, 64, 65, 66) on the basis of the turn-off voltage change with respect to change over time (dv ce / dt) and based on the estimated junction temperature during turn-off (T joff ). The turn-off time of the transistor (61, 62, 63, 64, 65, 66), which depends on the junction temperature, is given in equation 2: toff=fn(dvcedt and Tj_turnoff)

[0048] Step S106 may be performed according to various techniques, which may be applied separately and cumulatively. Under a first technique, the above function in Equation 2 is a polynomial equation based on the offline characterization of the transistor. For example, offline characterization means obtaining or collecting characteristic data or characterization (e.g., in factory, laboratory, or electronics test facilities, or by the transistor manufacturer) before the commercial installation of the transistor (61, 62, 63, 64, 65, 66) in the inverter 50 or before operation of the transistor by an end user. The characterization data or characterization may be stored in the data storage device 16 for retrieval and processing by the data processing device 12.

[0049] Under a second technique, the above function in equation 2 is determined as follows. For example, before executing step S106 or before executing the method of Fig. 5 the transistor is characterized for one or more of the following features: (1) a respective turn-off time (t off ) in relation to each dv ce / dt rate or (2) a corresponding transistor junction temperature at turn-off (T joff ) in relation to each dv ce / dt rate. The dv ce / dt rates, a respective switch-off time (t off ) and the chip temperature (T joff ) may be stored in lookup tables, files, inverted files, databases, or records in any suitable data structure in the data storage device 16 for retrieval and processing by the data processing device 12 to perform Equation 2.

[0050] In step S108, the data processing device 12 determines the off-current (i ceturnoff ) based on the switch-off time (t off ) and the peak voltage (v cepeak ). As soon as the switch-off time (t off ) is determined using the dv / dt rate and the junction temperature at the turn-off event, the transistor current at the turn-off event is determined by Equation 3: iigbt_turnoff=∫0toff(vcepeak−vDCLsIGBT)dt

[0051] In equation 3, v cepeak the peak voltage across the transistor (61, 62, 63, 64, 65, 66) when switched off, v DC is the direct current (DC) bus voltage of the inverter 50 and L dIGBT is the inductance associated with the transistor (e.g., leakage inductance, which takes into account the circuit path comprising the inverter direct current (DC) bus and the internal busbar in the transistor to the collector (41, 51) terminal or drain terminal).

[0052] In step S110, the data processing device 12 determines the inrush current (i ceturnon ) based on the breaking current (i ceturnoff ), inverter50 parameters, motor parameters, and motor voltage. To calculate the transistor current during a switch-on event, equations 11 and 12 can be used. Equations 11 and 12 assume that the phase A high-side transistor (61, 63, 65), for example, transistor S1 in Fig. 1, turns off at approximately time t2 and turns on at approximately time t1, consistent with waveforms 300 and 302 in Fig. 3. In the execution of step S110, equation (10) for i a be solved as follows: vDC=RSia+LSddtia+ωeΨm sin(θe)=RSia+LSddtia+ωe Ψm sin(ωet) ia=∫t1t2(vDC−RSia−ωe Ψm sin(ωet)LS)dt ia(t)at t2=iigbt_turnoff

[0053] For the purpose of background illumination, it should be noted that equations 10 to 12 that can be used in step S110 are derived based on the following equations 4 to 9, which do not need to be used again after their derivation: vDC=Ria+Lddtia+Ea

[0054] In equation (4) i a a phase-A current through the transistor (S1 or S4), E a is a phase-A back EMF (electromotive force) and R and L are derived from electrical cable and machine winding parameters as shown below: R=Rcab+RS L=Lcab+LS where R cab the cable resistance between the phase output terminal and the electrical machine 52 and L cab the cable inductance between the phase output terminal and the electrical machine 52 is R s is the resistance of the transistor at the collector (41, 51) terminal and L sis the inductance of the transistor at the collector (41, 51) terminal.

[0055] Since the electrical cable parameters are much smaller than the parameters of the electrical machine, R≅RS and L≅LS

[0056] It is assumed that the electric machine 52 is a PMSM (permanent magnet sinusoidal machine). The back EMF for phases a, b, and c (E a , E b or E c ) is defined in equation 8. [EaEbEc]=ωe Ψm[ sin(θe)sin(θe−2π3)sin(θe+2π3)]

[0057] In equation 8, ω e the electrical speed of the rotor in rad / second, Ψ m is the amplitude of the magnetic flux and this parameter is known to the motor control system over a range of rotor temperatures and θ eis the electrical position of the electric machine rotor of the electric machine 52. θ e is the rotor position, which is determined using a sensor as in Fig. 1 shown, is made available. ω e is expressed by equation 9. ωe=ddtθe

[0058] Using equations 5 - 9, equation 4 is modified as shown in equation 10.

[0059] In the execution of step S110, equation 10 for i a be solved: vDC=RSia+LSddtia+ωeΨm sin(θe)=RSia+LSddtia+ωe Ψm sin(ωet) ia=∫t1t2(vDC−RSia−ωe Ψm sin(ωet)LS)dt ia(t)at t2=iigbt_turnoffia(t)at t1=iigbt_turnon

[0060] Using equations 11 and 12, i a (t) at time t1 and that would be the transistor current during the turn-on event (i igbt_turnon ) in one switching cycle of the transistor.

[0061] In step S112, the data processing device 12 determines the energy loss for one switching cycle of the transistor (61, 62, 63, 64, 65, 66) based on the turn-off current (i ceturnoff ), the inrush current (i ceturnon ) and the forward voltage drop (v ceon ) between the collector (41, 51) and the emitter (43, 53) of the transistor or between the drain and source of the transistor. Once the transistor turn-on current is determined, the transistor turn-on time is calculated using a polynomial, which is based on the turn-on junction temperature as a function of previously characterizing data of the transistor. ton=fn(iigbt_turnon and Tj(n−1))

[0062] It must be noted that the voltage across the transistor (61, 62, 63, 64, 65, 66) falls at a rate which is determined by the turn-on time of the transistor, e.g. t on, is determined. Therefore, the rate of decay of the voltage across the transistor during turn-on is defined as follows: vce_turnon(t)=vDCton(t) Determination of energy loss in the transistor

[0063] Transistor energy losses during turn-on, turn-off, and on-state events are expressed by equations 15, 16, and 17, respectively.

[0064] Switch-on energy loss (E on ): E on is expressed by equation (15): Eon=vDC×iigbt_turnon×ton

[0065] Breaking energy loss (E off ): E off is expressed by equation (16): Eoff=vDC×Iigbt_turnoff×toff

[0066] Over a switching period, the transistor current varies as expressed by the simplified waveform shown in Fig. 3 is shown.

[0067] Energy loss when switched on (Eon_state ): E on_state is expressed by equation (17) as follows: Eon_state=vceon×(0.5×iigbt_turnoff+0.5×iigbt_turnoff)×TON

[0068] It must be noted that the average of the switch-on (i igbt_turnon ) and off-(i igbt_turnoff ) currents are considered crucial for determining the on-state energy loss in the transistor.

[0069] The total energy loss during one switching period of the transistor (61, 62, 63, 64, 65, 66) is the sum of the turn-on switching energy, the turn-off switching energy and the energy loss in the on state. ELoss=k1(vDC×Iigbt_turnon×ton)+k2(vDC×Iigbt_turnon×toff)+0.5k3×vceon×(iigbt_turnoff+iigbt_turnoff)×TON

[0070] In equation (18), the constants k1, k2 and k3 are determined by the designation of the usable transistor (61, 62, 63, 64, 65, 66) in an inverter 50 or in an inverter-driven electrical machine system.

[0071] The average power loss in the transistor (61, 62, 63, 64, 65, 66) during a switching interval is expressed as follows: PLoss=ELoss / T

[0072] Before calculating the switching loss, it is important to describe the switching waveforms over one switching period of the transistor.

[0073] In step S114, the data processing device 12 estimates a corresponding average junction or average chip temperature of the transistor (61, 62, 63, 64, 65, 66) over the switching cycle based on the determined energy loss, an observed inverter system temperature (e.g., coolant temperature of a coolant in a coolant system) for cooling the inverter 50, and a thermal characteristic of an inverter system (e.g., thermal resistance of a liquid-cooled system) for the inverter 50. An average junction or chip temperature may represent a mean junction or chip temperature, a median junction or chip temperature, or a mode junction or chip temperature.The method or temperature estimation may be applied to an inverter 50 employing one or more transistors (61, 62, 63, 64, 65, 66) in conjunction with a liquid-cooled coolant system (e.g., pump and heat sink) or with an air-cooled system. For a liquid-cooled system, temperature sensor 209 provides a coolant temperature, while for an air-cooled system, temperature sensor 209 provides a case temperature of inverter 50. The liquid-cooled system may be associated with a first set of thermal characteristics 205 (e.g., first thermal resistance), while the air-cooled system may be associated with a second set of thermal characteristics 205 (e.g., second thermal resistance), the first set being different from the second set.

[0074] In one embodiment, the heat resistance (R jc) of transistor thermal management is assumed to be X°C / Watt. For liquid-cooled power electronics systems, X could vary in the range of 0.1 to 0.3. Average junction temperature of the transistor (61, 62, 63, 64, 65, 66) over one switching period is as given below; Tj=Tcoolant+PLossRjc

[0075] The coolant temperature is provided by temperature sensor 209, or by an inverter control system, or by a vehicle control unit where inverter 50 is used to control vehicle propulsion or traction systems. When the vehicle control unit or engine controller 10 provides the coolant temperature, it can be communicated to the control unit 10 via a vehicle data bus 14 (e.g., the Controller Area Network (CAN) data bus, Ethernet, or another data bus).

[0076] Fig. 6 shows in its parts Fig. 6a and Fig. 6b is a flowchart of yet another embodiment of a method for estimating junction temperature or chip temperature of a transistor. The method is similar to the method of Fig. 5, except that some additional details are presented. The flowchart of Fig. 6a and Fig. Figure 6b shows an algorithm used to determine parameters and quantities needed for transistor energy loss estimation.

[0077] In step S600, the data processing device 12 starts the routine for parameter estimation for system variables required to estimate the transistor junction temperature.

[0078] In step S602, when the transistor gate voltage (v ge ) changes from high (H) logic level to low (L) logic level, the following parameters are read: the rotor position (θ e ) from the rotor position sensor 54, the direct current (VDC ) bus voltage from a voltage measuring circuit (e.g. comparator) and the voltage (V R2 ) via the resistor (R2) in Fig. 1.

[0079] In step S604, the detector 47 measures or determines dv ce / dt and v cepeak For example, the detector 47, alone or in conjunction with the detection circuit, measures or determines dv ce / dt according to step S100 and v cepeak according to step S102.

[0080] In step S606, the data processing device 12 uses a first lookup table, a first file, or a first data structure to determine the transistor junction temperature (T joff ) based on the specific dv ce / dt, where the lookup table defines the relationship between dv ce / dt and the junction temperature during a turn-off event (T joff). The first lookup table, the first file or the first data structure may be stored in the data storage device 16 and may be determined in advance or based on the properties of the transistor (61, 62, 63, 64, 65, 66) prior to execution of the method of Fig. 6 can be determined.

[0081] In step S608, the data processing device 12 determines the transistor turn-off time (t off ), based on dv ce / dt, and the transistor junction temperature T joff .

[0082] In step S610, the data processing device 12 solves an equation (e.g., equation 3) for i ight_turnoff For example, the equation for i ight_turnoff on the following integral, where the integral over the time period from t equal to 0 to t equal to t off from step S608. iigbt_turnoff=∫0toff(vcepeak−vDCLsIGBT)dt

[0083] In step S612, the data processing device 12 switches to the load or electrical machine 52, which is driven by the inverter 50, which includes two transistors (61, 62, 63, 64, 65, 66) per phase of the inverter 50. For example, the electrical machine 52 can be expressed by the following equation (e.g., Equation 10): vDC=RSia+LSddtia+ωeΨmsin(θe)=RSia+LSddtia+ωeΨmsin(ωet)

[0084] In step S614, the data processing device 12 determines the current of a phase at a transistor off time (t2) and the current of a phase A transistor on time (t1) in accordance with the following equations (e.g., equations 11 and 12). ia=∫t1t2(vDC−RSia−ωe Ψm sin(ωet)LS)dt ia(t)at t2=iigbt_turnoff ia(t)at t1=iigbt_turnon

[0085] In step S616, the data processing device 12 uses a polynomial function based on a second lookup table, a second file, or a second data structure to determine a power-on time (t on ) of the transistor as a function: t on = fn (i igbt_turnon , T j(n-1) ). The second lookup table, the second file or the second data structure may be stored in the data storage device 16 and may be determined or fixed in advance based on the properties of the transistor (61, 62, 63, 64, 65, 66) prior to execution of the method of Fig. 6.

[0086] In step S618, the data processing device 12 outputs the parameters or quantities t on , t off , i igbt_turnon and i igbt_turnoffto determine the transistor energy loss during a cycle. The quantities from step S618 can be used in steps S112 and S114 to estimate a corresponding average junction or chip temperature over a switching cycle of the transistor.

[0087] Fig. Figure 7 is a diagram of a system for detecting an image current (i igbt_sense ) by a transistor 700, wherein the transistor 700 can be replaced, for example, by each transistor (61, 62, 63, 64, 65, 66) in Fig. 1 can be substituted. The current mirror circuit with the elements 702, 704, 706 of the Fig. 7 facilitates cross-checking the value of the i igbt_turnoff and i igbt_turnon Currents which are produced in accordance with the procedures Fig. 4, Fig. 5 or Fig. 6. The current mirror circuit of Fig. 7 requires a transistor 700, which is constructed with a current mirror connected to the collector-emitter path or drain-source path. The current mirror generates a mirror current or secondary current (i igbt_sense ) which represents a small fraction (e.g. less than one percent) of the main stream (i igbt_main ) flowing through the transistor 700 between the collector 41 and the emitter 43. A current mirror can be implemented as a current source 704, where the value of the current supplied by this current source 704 is proportional to the main current (i igbt_main ) flowing through transistor 700. The mirror current associated with current source 704 can be accessed via an additional terminal 702 on transistor 700.

[0088] The mirror current flows through a resistor 706 (R shunt) of the correct size (ohm value and wattage). The voltage across the resistor R shunt is measured (for example at terminal 710) and is proportional to the mirror current (e.g. i igbt_sense ). The image current i ight_sense during IGBT turn-off is proportional to the main turn-off current, i igbr_turnoff , and during IGBT turn-on, the mirror current is proportional to the main turn-on current, i igbt_turnon . The data processing device 12 may receive the observed mirror current (or the corresponding voltage across resistor 706) via one or more data terminals 207 or a signal conditioner coupled to a data terminal 207. In one embodiment, the data processing device 12 uses the observed mirror current of a transistor 700 to determine the correctness and accuracy of the estimated i igbt_turnoff and i igbt_turnonin accordance with any method, step, or process disclosed herein. For example, the data processing device 12 may determine the cross-correlation (or the deviation of each proportionality constant) between the corresponding image current values ​​and the estimated i igbt_turnoff and i igbt_turnon according to any method, step, or operation disclosed in this document.

[0089] In one embodiment, the data processing device 12 measures the turn-on and turn-off mirror currents to ensure the correctness and accuracy of the determined turn-on current (i ceturnon ) based on the breaking current (i ceturnoff) by cross-correlation (between the respective mirror currents and corresponding determined turn-on and turn-off currents), such as from step S111 or the combination of S108 and S110, or by the degree of deviation (e.g., average, mean, mode, or median deviation) of any proportionality constant (between the respective mirror currents and corresponding determined turn-on and turn-off currents).

[0090] Fig. Figure 8 discloses a diagram of a number of power cycles 801 for an inverter (complete on and off cycles for the switching transistors (61, 62, 63, 64, 65)) on the vertical axis versus the total temperature change (ΔT j ) 802 of its transistors. The number of duty cycles 801 may be proportional to the duration of operation of the inverter 50. The duty cycle curve 803 of the Fig. 8 associated power cycle data can be calculated as a data file, a lookup table, a quadratic equation, or as a graph. The power cycle data includes the cumulative number of duty cycles versus the cumulative change in temperature (ΔT j ) as input to a transistor longevity estimator, which is stored in the data storage device 16 and executed by the data processing device 12. The power cycles 801 may be counted by a counter 77, a timer, or a data processing device 12 associated with the gate driver 18 or the control unit 10; the cumulative change in temperature (ΔT j ) is determined in accordance with any method, step, or process disclosed in this document.

[0091] Once the transistor die temperature or transistor junction temperature is determined, the data processing device 12 can use the die temperature for a real-time estimation of the damage in each transistor for each increase in the cumulative Delta Temp (ΔT j ). The power cycle data of Fig. 8 can be estimated by or fed to the data processing device to predict the remaining service life or lifetime of a transistor or inverter. The predicted remaining service life or lifetime of the inverter can be used, for example, for planning maintenance of the inverter or an electric powertrain in a vehicle.

[0092] In one embodiment, an optional counter 77 counts a number of power cycles of the transistor (61, 62, 63, 64, 65, 66) or a group of transistors in an inverter 50. The data processing device 12 determines a cumulative change in temperature for the transistor for the power cycles or for a group of transistors in the inverter 50. The data processing device 12 predicts a remaining lifetime of the transistor or an associated inverter based on the counted number of duty cycles and the determined cumulative change in temperature with reference to a lookup table, database, file, or other records stored in the data storage device 16.

[0093] The method and system of the present disclosure are well-suited for fast, accurate estimates of transistor temperature under steady-state and non-steady-state operating conditions of the inverter-fed electric motor / generator. Because the method and system of the disclosure does not require a conventional current sensor for current measurements, any error caused by the current sensor is eliminated. Typical errors of current sensors, such as Hall-effect sensors, can include any temperature-related deviation in the current measurement.

[0094] The method and system of the present disclosure can operate over a wide operating temperature range (e.g., -40°C to 175°C) of the transistor junction; which may be a wider operating range than available from a thermally sensitive resistor or thermistor. For example, due to the limitations of a thermally sensitive resistor, a sensed temperature below 0°C may be reported as cold, and a sensed temperature above 95°C may be declared hot due to the lack of any resolution at values ​​below 0°C and above 95°C. Accordingly, the method and system are well suited for operation with silicon carbide (SiC) power semiconductor devices or other wide bandgap semiconductor material, where they are expected to operate up to 200°C junction temperature.In certain applications, a conventional temperature sensor (e.g., thermistor) would not be able to maintain accuracy and linearity over the range of -40°C to 200°C. In such cases, the method and system of the present disclosure may enable maintenance of the linear range with an acceptable degree of accuracy in temperature sensing of wide bandgap semiconductor junctions.

[0095] The method and system has low or minimal switching losses, since only a first current, which is determined by R CLAMP in Fig.1 is required to implement the temperature sensing system, wherein the first current is substantially less than the current at the output of the transistor. The sensing circuit 60 facilitates the avoidance or dissipation of the transistor overvoltage during turn-off events. For example, in accordance with the sensing circuit, the overvoltage across the transistor is typically less than 200 nanoseconds, however, dv / dt across the transistor with a duration of approximately 200 nanoseconds is sufficient to determine the junction temperature during the turn-off event (T joffThe temperature estimation system and method does not require the placement of the temperature sensor (thermistor or negative temperature coefficient device) closer to the junction or channel of the transistor, which could otherwise lead to a reduction in electrical insulation / isolation and, consequently, a reduction in the reliability of the semiconductor device or inverter. Accordingly, the temperature estimation system and method is well suited to promote the guided thermal performance, dense power delivery, and safety of the semiconductor device and inverter.

Claims

[1] A method for estimating a junction temperature or chip temperature of a transistor (61, 62, 63, 64, 65, 66, 700), the method comprising: Measuring a voltage change (dv ce / dt) when turning off with respect to the change in a time between a collector (41, 51) and an emitter (43, 53) of a transistor (61, 62, 63, 64, 65, 66, 700) in a phase of an inverter (50); Measuring a peak voltage (v cepeak ) of the transistor (61, 62, 63, 64, 65, 66, 700) between the collector (41, 51) and the emitter (43, 53); Determining a breaking current (i ceturnoff ), an inrush current (i ceturnon ) and a forward voltage drop (v ceon ) based on the turn-off voltage change (dv ce / dt) and the peak voltage (v cepeak ) as intermediate parameters; Determining an energy loss for a switching cycle of the transistor (61, 62, 63, 64, 65, 66, 700) based on the turn-off current (i ceturnoff ), the inrush current (i ceturnon ) and the forward voltage drop (v ceon ) between the collector (41, 51) and the emitter (43, 53) of the transistor (61, 62, 63, 64, 65, 66, 700); and Estimating a corresponding average junction or chip temperature of the transistor (61, 62, 63, 64, 65, 66, 700) over the switching cycle based on the determined energy loss, an observed inverter system temperature, and a temperature characteristic of an inverter system. [2] A method for estimating the junction temperature according to claim 1, wherein determining the intermediate parameters further comprises: Estimating the junction or chip temperature when turning off the transistor (61, 62, 63, 64, 65, 66, 700) based on the measured turn-off voltage change (dv ce / dt); Determining a switch-off time (t off ) based on the turn-off voltage change (dv ce / dt) in terms of the change over time and based on the estimated junction temperature at turn-off; Determining the breaking current (i ceturnoff ) based on the switch-off time (t off ) and the peak voltage; and Determining the inrush current (i ceturnon ) based on the breaking current (i ceturnoff ), inverter parameters, motor parameters and a motor voltage. [3] The method of claim 1, wherein measuring the turn-off voltage change (dv ce / dt) or a rate or voltage rise with respect to the change over time by a drop in a voltage applied to a base or gate (70, 72) of the transistor (61, 62, 63, 64, 65, 66, 700) in an active state; and wherein, upon triggering, a transient spike in a collector voltage of the transistor (61, 62, 63, 64, 65, 66, 700) is measured via a series of cascaded multimode diodes (36, 38, 40, 42) and a resistive voltage divider (44, 46). [4] The method of claim 1, wherein measuring the peak voltage of the transistor (61, 62, 63, 64, 65, 66, 700) between switched terminals is triggered by a drop in a voltage applied to the base or gate (70, 72) of the transistor (61, 62, 63, 64, 65, 66, 700) in an active state; and wherein, upon triggering, a transient spike in a collector voltage of the transistor (61, 62, 63, 64, 65, 66, 700) is measured across a series of cascaded multimode diodes (36, 38, 40, 42) and a resistive voltage divider (44, 46). [5] The method of claim 1, wherein the inverter system temperature comprises a coolant temperature and wherein a thermal characteristic comprises a thermal resistance associated with the inverter system. [6] The method of claim 1, wherein the inverter system temperature comprises a case temperature of an inverter case, and wherein a thermal characteristic comprises a thermal resistance associated with the inverter system. [7] The method of claim 1, wherein determining the intermediate parameters further comprises: Sensing or measuring a voltage between a collector (41, 51) and emitter (43, 53) of the transistor (61, 62, 63, 64, 65, 66, 700) on a capacitor (206) coupled to the collector (41, 51) via a resistor (204) and a diode (202); and Providing the sampled or measured voltages to a data processing device (12) via one or more data terminals to enable an estimation of a forward power dissipation of the transistor (61, 62, 63, 64, 65, 66, 700). [8] The method of claim 7, further comprising: Sampling or measuring a voltage at a base or a gate (70, 72) of the transistor (61, 62, 63, 64, 65, 66, 700) to enable estimation of a forward power dissipation of the transistor (61, 62, 63, 64, 65, 66, 700). [9] The method of claim 1, further comprising: Measuring an observed mirror current of a transistor (61, 62, 63, 64, 65, 66, 700) in order to ensure accuracy and freedom from errors of the determined transistor turn-off current and the determined transistor turn-on current by cross-correlating the respective mirror currents with the corresponding determined turn-on and turn-off currents (i ceurnon, i ceturnoff ) or by a degree of deviation from a constant of proportionality. [10] The method of claim 1, further comprising: Counting a number of power cycles of the transistor (61, 62, 63, 64, 65, 66, 700); Determining a cumulative temperature change for the transistor for the power cycles; Predicting a remaining lifetime or longevity of the transistor (61, 62, 63, 64, 65, 66, 700) or an associated inverter based on the counted number of power cycles and the determined cumulative change in temperature. [11] A method for estimating a junction temperature or chip temperature of a transistor (61, 62, 63, 64, 65, 66, 700), the method comprising: Measuring a turn-off voltage change (dv ce / dt) with respect to change over time between a collector (41, 51) and an emitter (43, 53) of a transistor (61, 62, 63, 64, 65, 66, 700) in a phase of an inverter; Measuring a peak voltage (v cepeak ) of the transistor (61, 62, 63, 64, 65, 66, 700) between the collector (41, 51) and the emitter (43, 53); Determining a breaking current (i ceturnoff), an inrush current (i ceturnon ) and a forward voltage drop (v ceon ) based on the turn-off voltage change (dv ce / dt) and the peak voltage (v cepeak ) as intermediate parameters; Determining an energy loss for a switching cycle of the transistor (61, 62, 63, 64, 65, 66, 700) based on the turn-off current (i ceturnoff ), the inrush current (i ceturnon ) and the forward voltage drop (v ceon ) between the collector (41, 51) and the emitter (43, 53) of the transistor (61, 62, 63, 64, 65, 66, 700); and Estimating a corresponding average junction or chip temperature of the transistor (61, 62, 63, 64, 65, 66, 700) over the switching cycle based on the determined energy loss, an observed inverter system temperature, and a temperature characteristic of an inverter system. [12] A method for estimating the junction temperature according to claim 11, wherein determining the intermediate parameters further comprises: Estimating the junction or chip temperature at turn-off (T joff ) of the transistor (61, 62, 63, 64, 65, 66, 700) based on the measured turn-off voltage change (dv ce / dt); Determining a switch-off time (t off ) based on the turn-off voltage change with respect to the change over time (dv ce / dt) and based on the estimated turn-off junction temperature (T joff ); Determining the breaking current (i ceturnoff ) based on the switch-off time (t off ) and the peak voltage (V cepeak ); and Determining the inrush current (i ceturnon ) based on the breaking current (i ceturnoff ), inverter parameters, motor parameters and a motor voltage. [13] The method of claim 11, wherein measuring the turn-off voltage change or a rate or voltage rise (dv ce / dt) in relation to the change over time by a voltage (v ge ) applied to a base or a gate of the transistor (61, 62, 63, 64, 65, 66, 700) into an active state, or the fall thereof; and wherein, upon triggering, a transient spike in a collector voltage of the transistor (61, 62, 63, 64, 65, 66, 700) is measured via a series of cascaded multimode diodes (36, 38, 40, 42) and a resistive voltage divider (44, 46). [14] A method according to claim 11, wherein measuring the peak voltage (v cepeak ) of the transistor (61, 62, 63, 64, 65, 66, 700) by a voltage (v ge) applied to the base or gate of the transistor (61, 62, 63, 64, 65, 66, 700) in an active state, or the fall of which is triggered; and wherein, upon triggering, a transient spike in a collector voltage of the transistor (61, 62, 63, 64, 65, 66, 700) is measured via a series of cascaded multimode diodes (36, 38, 40, 42) and a resistive voltage divider (44, 46).

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