Parallelization compilation method, parallelization compiler and vehicle device

Abstract

A parallelization compilation method implemented by a multi-core processor (21) that simultaneously achieves an increase in processing speed and a reduction in energy consumption by integrating several processor cores, each having a low operating frequency, on a single chip, wherein the parallelization compilation method generates several segmented programs executable by the processor cores of the multi-core processor (21) from a sequential program executable by a single-core processor by subdividing the sequential program into the segmented programs, wherein the parallelization compilation method comprises: Assigning one or more macro tasks included in the sequential program to the processor cores included in the multi-core processor (21) in order to generate the segmented programs to be executed by the respective processor cores; Adding a new macro task to the sequential program or deleting one or more macro tasks from the sequential program; and Compiling the sequential program into the segmented programs in response to the addition of the new macro task, provided that the one or more macro tasks assigned to the respective processor cores and the execution order of the one or more macro tasks in the respective processor cores are not changed compared to the segmented programs before the addition; or compiling the sequential program into the segmented programs in response to the deletion of one or more macro tasks, provided that the remaining one or more macro tasks assigned to the respective processor cores and the execution order of the one or more macro tasks in the respective processor cores are not changed compared to the segmented programs before the deletion.

Description

TECHNICAL AREA

[0001] The present invention relates to a parallelization compilation method, a parallelization compiler and a vehicle device, each of which generates a segmented parallelized program for a multi-core processor from a sequential program prepared for a single-core processor. BACKGROUND

[0002] To technically refine and integrate a vehicle's control and information systems, it is essential to obtain higher processor capacity for implementing these refinements and integrations. For example, technically refining an engine control system, which plays a crucial role in developing a safe, comfortable, and fuel-efficient vehicle, requires an increase in computational load, such as refining a control algorithm or implementing a new control function. To address this challenge, increasing the processing speed of a process to achieve real-time control is indispensable.

[0003] However, improving a processor's operating frequency using conventional methods is difficult because energy consumption increases proportionally to the cube of the frequency. Therefore, multiple processor cores with low operating frequencies are integrated onto a single chip, and those cores with reduced frequency and voltage to lower energy consumption are operated in parallel. This results in a multi-core processor that can simultaneously achieve increased processing speed and reduced energy consumption at a rapid pace.

[0004] For a multi-core processor to execute processing at a higher speed than a single-core processor, the processing of a sequential program for a single-core processor must be divided into subprocesses, and these subprocesses must be assigned to corresponding processing cores, thus minimizing communication between the respective processing cores. Currently, the work of parallelizing the sequential program, as described above, must be performed manually. However, such work is very difficult and time-consuming, and suffers from many problems, such as increased development effort and reduced reliability of the parallelized program.

[0005] JP 2015 - 1 807 A (equivalent to US 2014 / 0 372 995 A1) proposes a parallelization compilation method that can create a parallelized program for an in-vehicle device system that is highly reliable and can perform high-speed processing while keeping development time and effort low.

[0006] US Patent 2015 / 0074257A1 discloses a computer-implemented method for parallelizing a computer program on a plurality of processing cores. This method includes receiving a computer program containing a plurality of instructions, which comprises: decomposing the plurality of instructions into a plurality of node networks, wherein each node network corresponds to one instruction in the plurality of instructions and includes one or more nodes corresponding to the execution dependencies of the instruction; mapping the plurality of node networks to a plurality of systolic arrays, wherein each systolic array comprises a plurality of cells and each non-data node in each node network is mapped to a cell in the plurality of cells; and mapping each cell in each systolic array to a processing core in the plurality of processing cores.

[0007] In the prior art, if a sequential program prepared for a single-core processor is parallelized once, and a macro task is subsequently added to or removed from the sequential program, the parallelization process is executed again. Therefore, a macro task assigned to a first core in an initial parallelization process can be assigned to a second core in a subsequent parallelization process. That is, the macro task, which undergoes no modification compared to its state when included in the initial sequential program—that is, the macro task for which no addition or removal occurs—can move between cores. Moving macro tasks between cores can cause a significant change to the overall program and increase testing time after parallelization. OVERVIEW OF THE INVENTION

[0008] With regard to the foregoing problems, it is an object of the present invention to provide a parallelization compilation method, a parallelization compiler, and a vehicle device which, when a program change such as adding or deleting is performed for a macro task included in the sequential program, can suppress any adverse effect caused by the program change on the execution of another macro task that does not contain any change when the sequential program is compiled into a segmented program. This object is achieved by the features of the independent claims. The dependent claims are directed to advantageous embodiments of the invention.

[0009] According to the parallelization method, the parallelization compiler, and the vehicle device according to the invention, if a macro task is deleted from or added to the sequential program, the sequential program can be compiled into the segmented program without affecting the macro tasks that do not involve a program change. Here, a program change includes adding or deleting a program. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The foregoing and further tasks, features and advantages of the present invention will become apparent from the following detailed description in conjunction with the drawings.

[0011] They show: Fig. 1 a block diagram illustrating a parallelization compiler according to an embodiment of the present invention; Fig. 2 a block diagram illustrating a vehicle device according to an embodiment of the present invention; Fig. 3A and Fig. 3B Diagrams illustrating a parallelization compilation method according to an embodiment of the present invention; Fig. 4A and Fig. 4B Diagrams illustrating the parallelization compilation method according to an embodiment of the present invention; Fig. 5A and Fig. 5B Diagrams illustrating the parallelization compilation method according to an embodiment of the present invention; Fig. 6A and Fig. 6B Diagrams illustrating the parallelization compilation method according to an embodiment of the present invention; Fig. 7A and Fig. 7B Diagrams illustrating the parallelization compilation method according to an embodiment of the present invention; and Fig. 8A and Fig. 8B Diagrams illustrating the parallelization compilation method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0012] An embodiment of the present invention is explained below with reference to the drawings. For ease of understanding, identical or equivalent components in the respective drawings are identified by identical reference numerals, and redundant descriptions are omitted.

[0013] An automatic parallelization compiler according to a first embodiment, a second embodiment, and a third embodiment of the present invention has a function for generating a parallelized program (segmented program) for a multi-core processor system of an embedded system. The parallelized program is also referred to as a segmented program and is generated from a sequential program, which is also referred to as a source program. The sequential program is prepared for a single-core processor system of an embedded system. 1-1. Design concept of an automatic parallelization compiler

[0014] The automatic parallelization compiler according to the present embodiment has the following functions. (1) Multigranular parallel processing (2) Inserting a code for static scheduling during compilation (3) Generating a code for dynamic scheduling during execution (4) Implementing a hierarchical macro data flow (5) Segmentation / aggregation of macro tasks, parallelism extraction from loop distribution / exchange (6) Improvement of data transmission efficiency through data localization (7) Energy consumption reduction through compilers 1-2. Internal processing of the automatic parallelization compiler

[0015] The automatic parallelization compiler has three stages: a frontend (FE), a middle path (MP), and a backend (BE). Each of these stages is independent of the others when executing, and code transfer is performed through an intermediate language generated by the FE and the MP.

[0016] The front end (FE) is configured to perform lexical and syntax analysis of the sequential program's source code and generate a parsable intermediate language within the program module (MP). The intermediate language generated by the FE is essentially expressed as a syntax tree with four operands, forming a single, unstructured block.

[0017] The MP is configured to perform tax dependency analysis, data dependency analysis, optimization, and the like, and performs multigranular parallel processing with coarse-grained, medium-grained, and near-fine-grained parallelization using data.

[0018] The BE is configured to read a parallelization intermediate language generated by the MP and to produce actual machine code. The BE includes a BE for generating assembly code for a multi-core architecture, which is the target architecture, as well as a BE for generating parallelized Fortran code and C code for Open MP. Furthermore, the BE includes a BE for outputting code according to different architectures, such as a BE for generating code that is parallelized with memory allocation and data transfer via a parallelization API, which will be described later. 1-3. Parallelism analysis of automatic parallelization compilers

[0019] The automatic parallelization compiler performs macro dataflow processing to segment a sequential program into three types of coarse-grained tasks: a base block (BB), a repeat block (RB), and a subroutine block (SB). The coarse-grained task is also referred to as a macro task (MT). In some cases, macro dataflow processing suffers from a problem such that processor utilization efficiency is not improved due to the program's structure, and sufficient coarse-grained parallelism cannot be extracted.

[0020] Under these circumstances, the automatic parallelization compiler employs hierarchical macro data flow processing, which extends a conventional single hierarchical macro data flow processing technique and uses hierarchical macro data flow processing within the MT. In hierarchical macro data flow processing, the MT is defined hierarchically, and the parallelism between macro tasks is analyzed for each hierarchy. (Generation of Macroflow Graphs (MFG))

[0021] The automatic parallelization compiler first analyzes control dependencies and data dependencies between the macro tasks generated in the respective hierarchies. The analysis results are expressed as a macroflow graph (MFG). (Generation of a macrotask graph (MTG))

[0022] The MFG represents the tax dependency and the data dependency between the macro tasks, but does not represent the parallelism. To extract the parallelism, it is necessary to analyze an earliest execution condition with respect to both the tax dependency and the data dependency: The earliest execution condition is a condition under which the MT can be executed at the earliest possible time and is obtained from the subsequent execution conditions. (1) If an MTi is data-dependent on an MTj, the MTi cannot be executed until the execution of the MTj is complete. (2) If a target of a conditional branch of the MTj is determined, the MTi which is control-dependent on the MTj may be executed even if the execution of the MTj is not yet complete.

[0023] Therefore, a general form of an earliest executability condition is expressed as follows.

[0024] Earliest executability condition: (The MTj on which the MTi is tax-dependent has branched to the MTi) and ((an MTk (0 ≤ k ≤ | N |) on which the MTi is data-dependent is completed) OR (it is determined that the MTk will not be executed)).

[0025] The condition for the earliest possible execution of the macro-task is represented by a macro-task graph (MTG). 1-4. Multigranular parallel processing

[0026] In addition to conventional loop parallelization, the automatic parallelization compiler implements multigranular parallel processing, effectively combining coarse-grained task parallelism with near-fine-grained parallel processing (compare "Parallelism Detection Method Between Fortran Program Coarse Grain Tasks" in the Institute of Electronics, Information and Communication Engineers Journal, 1990, by Hiroki Honda, Masahiko Iwata, and Hironori Kasahara). Coarse-grained task parallelism utilizes parallelism between coarse-grained tasks, between loops, and between subroutines, while near-fine-grained parallel processing utilizes parallelism between instructions. (Coarse-grained task parallel processing)

[0027] The automatic parallelization compiler generates a macroflow graph (MFG) that represents the control and data dependencies between the MTs of the BB, RB, and SB. The automatic parallelization compiler further expresses the parallelism of the MTs extracted from the MFG as the macrotask graph by analyzing the earliest executability condition (see "parallelism detection method between Fortran program coarse grain tasks" in the Institute of Electronics, Information and Communication Engineers Journal, 1990, by Hiroki Honda, Masahiko Iwata, and Hironori Kasahara, and "Macro task generation method of Fortran macro data flow processing," IEICE, 1992, Vol. J75-DI, No. 8, pages 511 to 525, by Kasahara, Goda, Yoshida, Okamoto, and Honda).

[0028] The automatic parallelization compiler then assigns the MT on the MTG to a processor group (PG) into which one or more processor elements (PE) are grouped. (Medium-granular parallel processing)

[0029] The MT assigned to the PG is subjected to medium-granular parallel processing by a processor within a processor cluster when parallel processing in the MT is enabled in a DOALL loop or iteration stage. Medium-granular parallel processing represents parallel processing using parallelism between DO loop iterations and is the most common form of parallel processing in multi-core processors. (Almost fine-grained parallel processing)

[0030] Parallel processing of the instruction level for near-fine-grained tasks is called near-fine-grained parallel processing. Consequently, parallel execution within the application can be performed without dependencies, thus reducing execution time. 1-5. Macro Task Scheduling

[0031] In coarse-grained task parallel processing, the macro task generated in each hierarchy is assigned to and executed by the relevant process group (PG). A scheduling technique for determining which PG the macro task is assigned to includes dynamic and static scheduling, which are described below. These schedules are executed based on a form of the macro task graph, execution time, indeterminacy, and similar factors. (Dynamic scheduling)

[0032] If execution time uncertainty exists, such as conditional branching, the macro task is assigned to the program group (PG) during execution by dynamic scheduling. The dynamic scheduling routine operates a macro task execution management table based on the completion of the macro task or the determination of a branching direction, and examines the earliest executability condition for each macro task.

[0033] If the macro tasks can be executed, they are placed in a ready queue. Within the ready queue, the macro tasks are sorted according to their priority, and a top-level macro task in the ready queue is assigned to the processor cluster in an idle state.

[0034] Similarly, at the time of creation and code generation for dynamic scheduling, a centralized scheduling system and a distributed scheduling system can be selectively used according to the number of processors to be used and the system's synchronization overhead. In the centralized scheduling system, a dedicated processor performs scheduling, while in the distributed scheduling system, a scheduling function is distributed among the respective processors. (Static scheduling)

[0035] On the other hand, static scheduling is a system used when the macro task graph has only one data dependency edge, where the automatic parallelization compiler determines the assignment of the macro task to the PG during compilation.

[0036] Static scheduling can be effectively used for scheduling fine-grained tasks because static scheduling can eliminate execution scheduling overhead and minimize overhead synchronized with data transmission.

[0037] During static scheduling, the effort is calculated using a task effort estimate in the automatic parallelization compiler, but task scheduling with a real effort can be performed using a so-called Profile Automatic Feedback Function of the automatic parallelization compiler.

[0038] When the Profile Automatic Feedback Function is used, the sequential program is decomposed into MTs (Mechanical Training Units) as a first phase, and a profiler function is inserted for each MT to generate the sequential program. The profiler function measures the task execution effort (clock cycle) and the number of task executions. The sequential program, into which the profiler function is inserted, is executed on a target machine, and a file containing information about the task execution effort and the number of tasks on the target machine is output.

[0039] Then, in a second phase, the parallelized program, which is planned based on the real effort, is generated using the output file and the sequential program as inputs. 1-6. Data localization

[0040] The automatic parallelization compiler can perform cache optimization for the entire program. If the automatic parallelization compiler detects a data dependency between loops after analyzing the parallelism, it attempts global cache optimization between the loops exhibiting the dependency (compare Japanese patent no. 4177681).

[0041] Specifically, a sequence that can be accessed in each loop is examined, and the same split loops are set up to access the same sequence segment, thereby assigning the same split loop to the same processor. Consequently, all sequence data is reused in a cache within the same split loop.

[0042] The above localization technology has evolved into a local storage management and data transmission technology, which is described below (compare GB patent no. 2,478,874). (1) If a local memory or distributed shared memory of an arbitrary size is provided before the memory is accessed using a DMA (DTU) (compare Japanese patent no. 4476267), data is preloaded into the local or distributed shared memory in close proximity to the processor and reused throughout the program. (2) If a destination memory is full after a DTU of a destination processor has been informed by a synchronization flag that data in the shared memory or the like has been transferred from the memory according to a transfer priority order, the DTU shall transfer the data to a memory which is automatically empty. (3) If data that is to be reused in the future is not used for a while and an area of ​​memory needs to be cleared, the DTU retrieves the data into a centralized shared memory after a task has been performed by the CPU and reloads the data into memory until a time of use. 1-7. Generation of a parallelized program

[0043] When generating the parallelized program in the automatic parallelization compiler, parallelization in source-to-source, such as parallelization C or parallelization Fortran, can be performed using an automatic parallelization API (compare "Optimally Scheduled Advanced Multiprocessor Application Program Interface", 2008 by Waseda University).

[0044] In this case, to make the parallelized program executable on different platforms, the automatic parallelization compiler converts a directive section of the C or Fortran code for each processor into a runtime library call using, for example, an interpretation system from an automatic parallelization API standard, which will be described later. The automatic parallelization API standard is an example of a predefined standard. Then, after the automatic parallelization compiler sequentially compiles code for each processor to generate binary code and concatenates the generated binary code, the automatic parallelization compiler can execute the parallelized program on the targeted multi-core processor. 2. Parallelization procedure and technique of a sequential program for a built-in system

[0045] The following describes the feature of a sequential program for the built-in system and a parallelization technique using the automatic parallelization compiler according to the present embodiment. The built-in system can be, for example, a vehicle component or an electronic device other than the vehicle component. The sequential program can be automatically generated by a model-based design (for example, a sequential program automatically generated by Matlab (registered trademark) or Simulink (registered trademark), provided by MathWorks, Inc.).

[0046] The automatic parallelization compiler is configured with conditional branching and an assignment statement, performs inline extension and renaming of the sequential program, which is finely tuned in processing, and extracts the parallelism. The automatic parallelization compiler performs task aggregation to obfuscate conditional branching in order to be consistent with real-time performance and executes static scheduling, thus minimizing overhead. Furthermore, to execute static scheduling with real-world overhead, the automatic parallelization compiler can utilize the Automatic Feedback Function profile.

[0047] Furthermore, in the sequential program, conditional compilation can be performed by a conditional compilation switch (instruction to the preprocessor) to select a description to be compiled according to each type of built-in system, which may differ in goal, function, and hardware configuration. In such a case, information (information specifying the goal, etc.) of some type is specified as an instruction for each conditional compilation or conditional compilation switch of the sequential program to generate binary code according to the type of the sequential program.

[0048] In contrast, according to the present embodiment, the automatic parallelization compiler ignores the selection of a target to be compiled by conditional compilation, performs the segmentation of the macro task, the extraction of parallelism, and static scheduling for all sections of the sequential program, and generates the parallelized program. The automatic parallelization compiler then identifies a description to be excluded from compilation by conditional compilation and generates binary data for operating the multi-core processor from the parallelized program in a state where the aforementioned description is excluded. 2-1. Operating environment of automatic parallelization compiler

[0049] An automatic parallelization compiler 1 is provided to a user in a state in which it is stored in a storage medium (memory) 18, which is an optical disc such as a DVD, a CD-ROM, a USB flash drive or a memory card (Memory Card, registered trademark), a magnetic disk or a semiconductor memory (compare Fig. 1) is configured. It goes without saying that the automatic parallelization compiler 1 can be made available to the user through a network.

[0050] A personal computer (PC) 10, in which the automatic parallelization compiler 1 is installed, operates as an automatic parallelization compiler. The PC 10 includes a display unit 11, a hard disk drive (HDD) 12, a central processing unit (CPU) 13, a read-only memory (ROM) 14, a random access memory (RAM) 15, an input device 16, and a read unit 17.

[0051] The display unit 11 shows an image to the user based on an image signal transmitted by the CPU 13.

[0052] The input device 16 is configured by a keyboard, a mouse and the like, and is operated by the user to output a signal to the CPU 13 according to the operation.

[0053] The read unit 17 is configured to read data from the storage medium 18, which contains the automatic parallelization compiler 1, etc.

[0054] The RAM 15 is a readable and writable volatile memory, the ROM 14 is a non-volatile read-only memory, and the hard disk 12 (HDD 12) is a non-volatile readable and writable memory. Programs to be read and executed by the CPU 13, and the like, are pre-stored in the ROM 14 and the HDD 12.

[0055] The RAM 15 is used as a memory area for temporarily storing programs or a memory area for temporarily storing working data when the CPU 13 executes the programs stored in the ROM 14 and the HDD 12.

[0056] The CPU 13 reads an operating system (OS) from the HDD 12 to execute the OS and processes various programs stored on the HDD 12. The CPU 13 receives a signal input from the input device 16 as required, outputs the video signal to the display unit 11, and controls the reading / writing of data to the RAM 15 and the HDD 12.

[0057] The automatic parallelization compiler 1, which is read from the storage medium 18 by the read unit 17, is installed in the PC 10 and the automatic parallelization compiler 1 functions as one of the applications stored in the HDD 12 and is executed as a process on the OS.

[0058] Furthermore, the automatic parallelization compiler is used in the development of the parallelized program for the built-in system, such as the vehicle's equipment. However, the automatic parallelization compiler is not limited to the above, but can be used in the development of the parallelized program for a built-in system for various applications, such as information devices, or in the development of the parallelized program in other applications besides the built-in system. 3. Configuration of the vehicle equipment

[0059] The following is in accordance with Fig. 2. A configuration of a vehicle device 20 is described, which operates with the aid of the parallelized program generated by the automatic parallelization compiler 1 of the present embodiment. It goes without saying that the automatic parallelization compiler 1 is not limited to the vehicle device 20, but can generate the parallelized program to operate different electronic devices that have the same configuration.

[0060] The vehicle device 20 includes a multi-core processor 21, a communication unit 22, a sensor unit 23, an input / output port 24, and the like. The multi-core processor 21 includes a ROM 21a, a RAM 21b, and several cores 21c, 21d, etc.

[0061] The ROM 21a stores a parallelized program 21a-1 (binary data) generated by the automatic parallelization compiler 1. The multi-core processor 21 operates according to the parallelized program 21a-1 and comprehensively controls the vehicle device 20.

[0062] RAM 21b is configured to be accessible to cores 21c, 21d, etc. Communication unit 22 is configured to communicate with another ECU connected to communication unit 22 via a vehicle-integrated LAN or similar.

[0063] Sensor unit 23 is configured with various sensors to detect the state of a controlled object and the like. Input / output port 24 is configured to transmit and receive various signals for controlling the controlled object. (Specific examples)

[0064] Specific examples of the processing for generating the parallelized program by the automatic parallelization compiler 1 of the present embodiment are described below. In the following description, although processing operations a, b, c, etc. are described, each processing operation a, b, c, etc., represents a description of a series of processing operations including different operations, assignments, branching, function calls, etc.

[0065] A specific example that is in Fig. 3A and Fig. Figure 3B illustrates parallel processing when no change scale minimization option is applied to the parallelization. Fig. Figure 3A illustrates a sequential program before the macro task is added, and a segmented program obtained by parallelizing the sequential program. Fig. Figure 3B illustrates a sequential program after a macro task x has been newly added, and a segmented program obtained by parallelizing the sequential program.

[0066] In Fig. 3A is a sequential program configured such that processes a, b, c, d, and e are executed sequentially. The execution times required for processes a, b, and e are equal. Process d requires an execution time twice that of process a. Process c requires an execution time twice that of process d.

[0067] If processing a through processing e is assigned to core 0 and core 1, and the processing is parallelized to minimize the overall execution time, processing a and processing c are assigned to core 0, and processing b, processing d, and processing e are assigned to core 1.

[0068] As in Fig. As shown in 3B, a processing task x, which is a macro task, is performed in Fig. 3A is added to the sequential program shown. When assigning processes a through e and processing x to kernel 0 and kernel 1, and parallelizing the processes so that the overall execution time is shortest, processes a, x, and d are assigned to kernel 0, and processes b, c, and e are assigned to kernel 1.

[0069] If you compare Fig. 3A with Fig. 3B is certain that parallelization is optimal from the perspective of minimizing the overall execution time. However, the processing c, which is in Fig. 3A is assigned to core 0, in Fig. 3B is assigned to core 1, and the processing of d, which is in Fig. 3A is assigned to core 1, in Fig. 3B is assigned to core 0. As described above, each of the processes c and d is assigned to different cores before and after the addition of process x. That is, processes c and d move or migrate between core 0 and core 1 when the program change of the sequential program is made.

[0070] The following describes the change scale minimization option, which prevents pre-assigned processing from moving or migrating between cores. A specific example, found in Fig. 4A and Fig. Figure 4B illustrates parallel processing when the change scale minimization option is applied to compiling the sequential program into the parallelized program. Fig. Figure 4A illustrates a sequential program before the macro task is added, and a segmented program obtained by parallelizing the sequential program (first unit). Fig. Figure 4B illustrates a sequential program after the macro task x has been added (second unit) and a segmented program obtained by parallelizing the sequential program to which the macro task has been added (third unit).

[0071] In Fig. 4A is configured as a sequential program such that processes a, b, c, d, and e are executed sequentially. The execution times required for processes a, b, and e are equal. Process d requires an execution time twice that of process a. Process c requires an execution time twice that of process d.

[0072] If processing a to processing e is assigned to core 0 and core 1, and the processing is parallelized to minimize execution time, processing a and processing c are assigned to core 0, and processing b, processing d, and processing e are assigned to core 1.

[0073] As in Fig. As shown in 4B, the processing x, which is a macro task, is assigned to the one in Fig. 4A is added to the sequential program shown. If the change scale minimization option is applied, the processing operations that used the respective cores in a previous assignment, which is shown in Fig. As shown in Figure 4A, the assignments are not changed. In particular, process x is assigned to core 1, which has a shorter execution time, without changing the assignment of processes to the cores. Specifically, the assignment of processes a and c to core 0 and the assignment of processes b, d, and e to core 1 remain unchanged, which is caused by adding process x to the sequential program.

[0074] Becomes Fig. 3B with Fig. Compared to 4B, the parallelization that is in Fig. As illustrated in 3B, from the perspective of maximizing the reduction of the overall execution time, it is excellent. However, the parallelization shown in Fig. 4B illustrates this from the perspective of maximally reducing the movement or migration of the processing that has already been allocated.

[0075] The following describes a modification of the parallel processing using the change scale minimization option, which is found in Fig. 4A and Fig. 4B is illustrated and described. The modification is described with reference to Fig. 5A and Fig. 5B described. A specific example, which is in Fig. 5A and Fig. Figure 5B illustrates parallel processing when the change scale minimization option is applied to parallelization. Fig. Figure 5A illustrates a sequential program before the macro task is added, and a segmented program obtained by parallelizing the sequential program (first unit). Fig. 5B illustrates a sequential program after the macro task x is newly added (second unit) and a segmented program obtained by parallelizing the sequential program to which the macro task is added (third unit).

[0076] In Fig. 5A is a sequential program configured such that processes a, b, c, d, and e are executed sequentially. The execution times required for processes a, b, and e are equal. Process d requires an execution time twice that of process a. Process c requires an execution time twice that of process d.

[0077] When assigning processes a through e to core 0 and core 1 and parallelizing the processes to minimize the overall execution time, processes a, b, and d are assigned to core 0, and processes c and e are assigned to core 1. The assignment of processes a through e differs from the one described in Fig. 4A shown processing assignment.

[0078] As in Fig. As shown in 5B, the processing x, which is a macro task, is assigned to the sequential program in Fig. 5A added. When the change scale minimization option is applied to parallelization, the processing already performed on the respective cores that are in Fig. The processes shown in section 5A have been assigned and have not been changed as far as possible. In particular, processing x is assigned to core 0, which has a shorter execution time, without changing the assignment of processing a, processing b and processing d to core 0 and the assignment of processing c and processing e to core 1.

[0079] The following describes parallelization when the macro task is removed from the sequential program. A specific example, which is in Fig. 6A and Fig. Figure 6B shows parallel processing when no change scale minimization option is applied to the parallelization. Fig. Figure 6A illustrates a sequential program before the macro task is deleted, and a segmented program obtained by parallelizing the sequential program (first unit). Fig. Figure 6B illustrates a sequential program after the macro task is deleted (second unit) and a segmented program obtained by parallelizing the sequential program (third unit).

[0080] In Fig. 6A The sequential program is configured such that processes a, b, c, d, and e are executed sequentially. The execution times required for processes a, b, and e are equal. Process d requires an execution time that is twice as long as the execution time of process a. Process c requires an execution time that is twice as long as the execution time of process d.

[0081] When assigning processing a to processing e to core 0 and core 1 and parallelizing the processing so that the overall execution time is shortest, processing a and processing c are assigned to core 0 and processing b, processing d and processing e are assigned to core 1.

[0082] As in Fig. Figure 6B shows the processing of d, which is a macro task, by the sequential program in Fig. 6A deleted. When assigning processing a to c and e to core 0 and core 1 and parallelizing the processing so that the overall execution time is shortest, processing c is assigned to core 0 and processing a, processing b and processing e are assigned to core 1.

[0083] If you compare Fig. 6A with Fig. 6B is certain that parallelization is optimal from the perspective of maximizing the reduction of the overall execution time. However, the processing a, which is in Fig. 6A is assigned to core 0, in Fig. 6B is assigned to core 1. As described above, processing a is assigned to different cores before and after the deletion of processing d. That is, processing a moves or migrates between core 0 and core 1 when the program change of the sequential program is made.

[0084] The following describes the change scale minimization option, which prevents a pre-assigned process from moving or migrating between cores. A specific example, found in Fig. 7A and Fig. Figure 7B illustrates parallel processing when the change scale minimization option is applied to the parallelization. Fig. Figure 7A illustrates a sequential program before the macro task d is deleted, and a segmented program obtained by parallelizing the sequential program (first unit). Fig. Figure 7B illustrates a sequential program after the macro task d is deleted (second unit) and a segmented program obtained by parallelizing the sequential program from which the macro task is deleted (third unit).

[0085] In Fig. 7A The sequential program is configured such that processes a, b, c, d, and e are executed sequentially. The execution times required for processes a, b, and e are equal. Process d requires twice the execution time of process a. Process c requires twice the execution time of process d.

[0086] When assigning processing a to processing e to core 0 and core 1 and parallelizing the processing so that the overall execution time is shortest, processing a and processing c are assigned to core 0 and processing b, processing d and processing e are assigned to core 1.

[0087] In Fig. 7B is the processing of d, which is a macro task, from which in Fig. The sequential program shown in 7A is deleted. When the change scale minimization option is applied to parallelization, the processing operations already performed by the respective cores that were in Fig. The processes shown in 7A, which have been assigned, are not changed. In particular, only the processing d, which was assigned to core 1, is deleted, without changing the assignment of processing a and processing c to core 0 and the assignment of processing b and processing e to core 1.

[0088] Becomes Fig. 6B with Fig. Compared to 7B, the parallelization that is in Fig. Figure 6B illustrates this from the perspective of maximizing the reduction of the overall execution time. However, the parallelization shown in Fig. 7B illustrates this from the point of view of maximally reducing the movement or migration of the processing that has already been allocated, which is excellent.

[0089] The following is in accordance with Fig. 8A and Fig. 8B describes a parallelization example where a data dependency exists between processing a and processing d, and a data dependency exists between processing d and processing e. In this example, it is assumed that the data dependencies in the sequential program are based on the one described in Fig. 7A and Fig. The case shown in 7B is defined.

[0090] The in Fig. 8A and Fig. 8B illustrated example shows parallel processing when the change scale minimization option is applied to the parallelization and data dependencies are defined between macro tasks included in the sequential program. Fig. Figure 8A illustrates a sequential program before the macro task is deleted and a segmented program obtained by parallelizing the sequential program (first unit). Fig. Figure 8B illustrates a sequential program after the macro task has been deleted (second unit), and a segmented program obtained by parallelizing the sequential program from which the macro task has been deleted (third unit).

[0091] In Fig. 8A The sequential program is configured such that processes a, b, c, d, and e are executed sequentially. The execution times required for processes a, b, and e are equal. Process d requires an execution time that is twice as long as the execution time of process a. Process c requires an execution time that is twice as long as the execution time of process d.

[0092] When assigning processing a to processing e to core 0 and core 1 and parallelizing the processing so that the overall execution time is shortest, processing a and processing c are assigned to core 0 and processing b, processing d and processing e are assigned to core 1.

[0093] In Fig. 8B is the processing of d, which is a macro task, from the sequential program of Fig. 8A deleted. When the change scale minimization option is applied to parallelization, the processing operations, the respective cores that are in Fig. The assignments shown in 8A, which have already been made, remain unchanged. In particular, the assignment of processing a and processing c to kernel 0 and the assignment of processing d and processing e to kernel 1 remain unchanged.

[0094] In the Fig. 8A and Fig.In the example illustrated in Figure 8B, it is assumed, as described above, that a data dependency exists between processing a and processing b, and a data dependency exists between processing d and processing e. If processing d is simply deleted, the data dependency between processing a and processing e is eliminated by processing d, and a problem may occur when executing processing e. Therefore, in the present example, only the processing instructions of processing d are deleted from the sequential program, leaving behind information indicating the existence of the dependency between processing d and processing a, and the dependency between processing d and processing e.For this reason, in core 1, the processing load caused by the instructions of processing d is reduced, and reliable execution of processing e is ensured.

[0095] The parallelization compilation procedure described above can be performed by the automatic parallelization compilation device 10 or can also be performed by the multi-core processor 21 of the vehicle device 20 instead of the automatic parallelization compilation device 10.

Claims

[1] A parallelization compilation method implemented by a multi-core processor (21) that simultaneously realizes an increase in processing speed and a reduction in power consumption by integrating a plurality of processor cores each having a low operation frequency on a single chip, the parallelization compilation method generating a plurality of segmented programs executable by the processor cores of the multi-core processor (21) from a sequential program executable by a single-core processor by dividing the sequential program into the segmented programs, the parallelization compilation method comprising: Assigning one or more macrotasks included in the sequential program to the processor cores included in the multi-core processor (21) to generate the segmented programs to be executed by the respective processor cores; Adding a new macro task to the sequential program or deleting one of the one or more macro tasks from the sequential program; and Compiling the sequential program into the segmented programs in response to adding the new macro task under a condition that the one or more macro tasks assigned to the respective processor cores and an execution order of the one or more macro tasks in the respective processor cores are not changed compared to the segmented programs before the addition, or compiling the sequential program into the segmented programs in response to deleting one of the one or more macro tasks under a condition that remaining ones of the one or more macro tasks assigned to the respective processor cores and an execution order of the one or more macro tasks in the respective processor cores are not changed compared to the segmented programs before the deletion. [2] The parallelization compiling method according to claim 1, wherein, when the new macro task is added to the sequential program upon compiling the sequential program into the segmented programs, an assignment of the one or more macro tasks to the processor cores is maintained without change, and a target core among the processor cores to which the new macro task is assigned is determined based on execution times of the segmented programs to which the new macro task is to be added. [3] The parallelization compiling method according to claim 2, wherein, among the processor cores, the target core to which the new macro task is assigned is determined so that the execution time of the segmented program to which the new macro task is to be added has a minimum value compared with a case where the new macro task is assigned to another core. [4] The parallelization compiling method according to claim 1, wherein, when the one of the one or more macro tasks is to be deleted from the sequential program in compiling the sequential program into the segmented programs, deletion of the one of the one or more macro tasks is executed and allocation of the remaining ones of the one or more macro tasks to the processor cores is maintained without change. [5] The parallelization compiling method according to claim 4, wherein when the one of the one or more macro tasks is deleted from the sequential program, information indicating a data dependency with respect to the one of the one or more macro tasks is retained without deletion. [6] A parallelization compiler stored in a non-transitory, tangible, computer-readable storage medium as a program product, the parallelization compiler being executed by a multi-core processor (21) that simultaneously realizes an increase in processing speed and a reduction in power consumption by integrating a plurality of processor cores each having a low operation frequency on a single chip, the parallelization compiler generating a plurality of segmented programs executable by the processor cores of the multi-core processor (21) from a sequential program executable by a single-core processor by dividing the sequential program into the segmented programs, the parallelization compiler comprising instructions to be executed by a parallelization compiling device, the instructions being for implementing: Assigning one or more macrotasks included in the sequential program to the processor cores included in the multi-core processor (21) to generate the segmented programs to be executed by the respective processor cores; Adding a new macro task to the sequential program or deleting one of the one or more macro tasks from the sequential program; and Compiling the sequential program into the segmented programs in response to adding the new macro task under a condition that the one or more macro tasks assigned to the respective processor cores and an execution order of the one or more macro tasks in the respective processor cores are not changed compared to the segmented programs before the addition, or compiling the sequential program into the segmented programs in response to deleting one of the one or more macro tasks under a condition that remaining ones of the one or more macro tasks assigned to the respective processor cores and an execution order of the one or more macro tasks in the respective processor cores are not changed compared to the segmented programs before the deletion. [7] The parallelization compiler according to claim 6, wherein, when the new macro task is added to the sequential program upon compiling the sequential program into the segmented programs, an assignment of the one or more macro tasks to the processor cores is maintained without change, and a target core of the processor cores to which the new macro task is assigned is determined based on execution times of the segmented programs to which the new macro task is to be added. [8] A parallelization compiler according to claim 7, wherein, among the processor cores, the target core to which the new macro task is assigned is determined such that the execution time of the segmented program to which the new macro task is to be added has a minimum value compared to a case where the new macro task is assigned to another core. [9] The parallelization compiler according to claim 6, wherein, when the one of the one or more macro tasks is to be deleted from the sequential program when compiling the sequential program into the segmented programs, deletion of the one of the one or more macro tasks is performed and allocation of the remaining ones of the one or more macro tasks to the processor cores is maintained without change. [10] The parallelization compiler according to claim 9, wherein when the one of the one or more macro tasks is deleted from the sequential program, information indicating a data dependency with respect to the one of the one or more macro tasks is retained without deletion. [11] Vehicle device, comprising: a multi-core processor (21), wherein the multi-core processor (21) simultaneously realizes an increase in processing speed and a reduction in energy consumption by integrating a plurality of processor cores, each having a low operation frequency, on a single chip, wherein the parallelization compilation method the multi-core processor (21) is configured to generating a plurality of segmented programs executable by the processor cores of the multi-core processor (21) from a sequential program executable by a single-core processor by dividing the sequential program into the segmented programs, assigning one or more macrotasks included in the sequential program to the processor cores included in the multi-core processor (21) to generate the segmented programs to be executed by the respective processor cores; add a new macro task to the sequential program or delete one of the one or more macro tasks from the sequential program; and compile the sequential program into the segmented programs in response to adding the new macro task under a condition that the one or more macro tasks assigned to the respective processor cores and an execution order of the one or more macro tasks in the respective processor cores are not changed compared to the segmented programs before the addition, or compile the sequential program into the segmented programs in response to deleting one of the one or more macro tasks under a condition that remaining ones of the one or more macro tasks assigned to the respective processor cores and an execution order of the one or more macro tasks in the respective processor cores are not changed compared to the segmented programs before the deletion. [12] The vehicle device according to claim 11, wherein, when the new macro task is added to the sequential program upon compiling the sequential program into the segmented programs, an assignment of the one or more macro tasks to the processor cores is maintained without change, and a target core among the processor cores to which the new macro task is assigned is determined based on execution times of the segmented programs to which the new macro task is to be added. [13] The vehicle device according to claim 12, wherein, among the processor cores, the target core to which the new macro task is assigned is determined such that the execution time of the segmented program to which the new macro task is to be added has a minimum value compared with a case where the new macro task is assigned to another core. [14] The vehicle device according to claim 11, wherein, when the one of the one or more macro tasks is to be deleted from the sequential program upon compiling the sequential program into the segmented programs, deletion of the one of the one or more macro tasks is executed and allocation of the remaining ones of the one or more macro tasks to the processor cores is maintained without change. [15] The vehicle device according to claim 14, wherein, when the one of the one or more macro tasks is deleted from the sequential program, information indicating a data dependency with respect to the one of the one or more macro tasks is retained without deletion.

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