Parallelization compilation method, parallelization compiler and vehicle device

Abstract

A parallelization compilation method implemented by a multi-core processor (21) that simultaneously increases processing speed and reduces energy consumption by integrating multiple processor cores, each with a low operating frequency, onto a single chip, wherein the parallelization compilation method generates multiple segmented programs executable by the processor cores of the multi-core processor (21) from a sequential program executable by a single-core processor by subdividing the sequential program into the segmented programs, wherein the sequential program includes multiple macro tasks and at least two of the multiple macro tasks have a data dependency relationship to each other, wherein the parallelization compilation method comprises: Determining the existence of cancellation information to cancel at least part of the data dependency relationship between at least two of the several macro tasks before compiling the sequential program into the segmented programs (S101, S201, S301); and Generating the segmented programs by compiling the sequential program into the segmented programs with respect to a determination result of the existence of the cancellation information, wherein, If it is determined that the cancellation information exists, at least one part of the data dependency relationship is cancelled before compiling the sequential program into the segmented programs (S103, S104, S203, S205, S303, S305), and then the sequential program is compiled into the segmented programs to be assigned to the respective processor cores of the multi-core processor, so that the execution time of the respective segmented programs is shortest. If it is determined for the cancellation information that it does not exist between the at least two of the macro tasks that have the data dependency relationship to each other, the sequential program is compiled into the segmented programs to be assigned to the respective processor cores of the multi-core processor, so that the at least two of the macro tasks are assigned to the same segmented program and executed by the same processor core of the multi-core processor.

Description

TECHNICAL FIELD

[0001] The present invention relates to a parallelization compiling method, a parallelization compiler, and a vehicle device, each of which generates a segmented parallelized program for a multi-core processor from a sequential program prepared for a single-core processor. BACKGROUND

[0002] To technically refine and integrate a control system and an information system in a vehicle, it is important to achieve higher processor capacity to implement the technical refinement and integration. For example, to technically refine an engine control system, which plays an important role in developing a safe, comfortable, and fuel-efficient vehicle, an increase in computational load such as the technical refinement of a control algorithm or the implementation of a new control function is required. To solve the above problem, increasing the processing speed of a process to implement real-time control is inevitable.

[0003] However, it is difficult to improve the processor's operating frequency as in the conventional art, because power consumption increases proportionally with the cube of the frequency. Therefore, multiple processor cores with low operating frequencies are integrated together on a single chip, and the processor cores, whose frequency and voltage are reduced to reduce power consumption, are operated in parallel, thereby transitioning to a multi-core processor that can simultaneously achieve an increase in processing speed and a reduction in power consumption at a rapid pace.

[0004] In order for the multi-core processor to execute processing at a higher speed than the single-core processor, processing of a sequential program for the single-core processor must be divided into subprocesses, and the respective subprocesses must be assigned to corresponding processing cores so that communication between the respective processing cores is minimized. Until now, the work of parallelizing the sequential program, as described above, has to be performed manually. However, such work is very difficult and time-consuming, and suffers from many problems, such as an increase in development effort and the reliability of the parallelized program.

[0005] JP 2015 - 1 807 A (equivalent to US 2014 / 0 372 995 A1) proposes a parallelization compilation method that can create a parallelized program for an on-vehicle device system that is highly reliable and can perform high-speed processing while keeping a development time and development effort low.

[0006] US 2015 / 0 074 257 A1 discloses a computer-implemented method for parallelizing a computer program on a plurality of processing cores, comprising receiving a computer program that includes a plurality of instructions, comprising: decomposing the plurality of instructions into a plurality of node networks, each node network corresponding to an instruction in the plurality of instructions and comprising one or more nodes corresponding to execution dependencies of the instruction, assigning the plurality of node networks to a plurality of systolic arrays, each systolic array comprising a plurality of cells and each non-data node in each node network being assigned to a cell in the plurality of cells, and assigning each cell in each systolic array to a processing core in the plurality of processing cores.

[0007] In conventional parallelization technology, a sequential program prepared for a single-core processor is compiled into a segmented program for a multi-core processor, taking into account the data dependency between multiple macrotasks and the execution time after segmentation. In the sequential program in an automotive field, the data dependency between the multiple macrotasks included in the sequential program becomes complicated, making it difficult to consider all these data dependencies. Furthermore, when the segmented program is generated with data dependency in mind, the segmented program is constrained by the data dependency. As a result, the execution time of the generated program cannot be averaged, and the parallelization effect cannot be sufficiently achieved. OVERVIEW

[0008] In view of the above difficulties, it is an object of the present invention to provide a parallelization compilation method, a parallelization compiler, and a vehicle device, each capable of averaging the execution time of a parallelized program generated based on a sequential program, even when macro tasks included in the sequential program have a complex data dependency on each other. This object is achieved with the features of the independent claims. The dependent claims are directed to advantageous developments of the invention.

[0009] According to the parallelization compiling method, the parallelization compiler and the vehicle device of the present invention, the execution time of the parallelized program can be effectively averaged even when the macro tasks included in the sequential program based on which the parallelized program is generated have a complicated data dependency among each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the drawings.

[0011] They show: Fig. 1 is a block diagram illustrating a parallelization compiler according to a first embodiment, a second embodiment, and a third embodiment of the present invention; Fig. 2 is a block diagram illustrating a vehicle device according to the first embodiment, the second embodiment, and the third embodiment of the present invention; Fig. 3 is a flowchart illustrating a parallelization compiling method according to the first embodiment of the present invention; Fig. 4 is a diagram illustrating a parallelization compilation method when no data dependency cancellation information exists; Fig. 5 is a diagram illustrating a parallelization compilation method when data dependency relationship cancellation information exists; Fig. 6 is a flowchart illustrating a parallelization compiling method according to the second embodiment of the present invention; Fig. 7 is a diagram illustrating an example of a data dependency relationship in the parallelization compiling method according to the second embodiment of the present invention; Fig. 8 is a diagram illustrating a parallelization compilation method when no data dependency relationship cancellation information exists; Fig. 9 is a diagram illustrating a parallelization compilation method when data dependency relationship cancellation information exists; Fig. 10 is a diagram illustrating a parallelization compilation method when data dependency relationship cancellation information and a synchronization condition exist; Fig. 11 is a diagram illustrating a parallelization compilation method when data dependency relationship cancellation information and a synchronization condition exist; Fig. 12 is a flowchart illustrating a parallelization compiling method according to the third embodiment of the present invention; Fig. 13 illustrates an example of a data dependency relationship in a parallelization compiling method according to the third embodiment of the present invention; Fig. 14 is a diagram illustrating a parallelization compilation method when no data dependency relationship cancellation information exists; Fig. 15 is a diagram illustrating a parallelization compilation method when data dependency relationship cancellation information exists; Fig. 16 is a diagram illustrating a parallelization compilation method when data dependency relationship cancellation information and a pseudo dependency condition exist; Fig. 17A and Fig. 17B are diagrams illustrating a parallelization compilation method when data dependency relationship cancellation information exists; Fig. 18A and Fig. 18B are diagrams illustrating a parallelization compilation method when data dependency relationship cancellation information exists; and Fig. 19A to Fig. 19C Diagrams illustrating a parallelization compilation method when data dependency relationship resolution information exists. DETAILED DESCRIPTION

[0012] An embodiment of the present invention will be explained below with reference to the drawings. For ease of understanding, identical or equivalent components in the respective drawings are designated by identical reference numerals, and redundant descriptions are omitted. 1: Automatic parallelization compiler

[0013] An automatic parallelization compiler according to a first embodiment, a second embodiment, and a third embodiment of the present invention has a function of generating a parallelized program (segmented program) for a multi-core processor system of a built-in system. The parallelized program is also referred to as a segmented program and is generated from a sequential program, also referred to as a source program. Here, the sequential program is prepared for a single-core processor system of a built-in system. 1-1. Design concept of automatic parallelization compiler

[0014] The automatic parallelization compiler according to the present embodiment has the following functions. (1) Multigranular parallel processing (2) Inserting static scheduling code during compilation (3) Generating dynamic scheduling code during execution (4) Implementing a hierarchical macro data flow (5) Segmentation / aggregation of macro task, parallelism extraction of loop distribution / exchange (6) Improving data transmission efficiency through data localization (7) Energy consumption reduction by compilers 1-2. Internal processing of automatic parallelization compiler

[0015] The automatic parallelization compiler has three stages: a front-end (FE), a middle-end (MP), and a back-end (BE). Each of these stages is independent of the others when executed, and code transfer is performed through an intermediate language generated by the FE and the MP.

[0016] The FE is configured to perform lexical and syntax analysis of the source code of the sequential program and generate a parsable intermediate language in the MP. The intermediate language generated by the FE is generally expressed by a syntax tree with four operands, forms a block as a whole, and is unstructured.

[0017] The MP is configured to perform control dependency analysis, data dependency analysis, optimization, and the like, and performs multi-grain parallel processing with coarse-grain, medium-grain, and near-fine-grain parallelization using data.

[0018] The BE is configured to read a parallelization intermediate language generated by the MP and generate actual machine code. The BE has a BE for generating assembly code for a target multi-core architecture, as well as a BE for generating parallelized Fortran code and C code for Open MP. Furthermore, the BE has a BE for outputting code corresponding to different architectures, such as a BE for generating code parallelized with the inclusion of a memory array and data transfer through a parallelization API, which will be described later. 1-3. Parallelism analysis of automatic parallelization compiler

[0019] The automatic parallelization compiler performs macro dataflow processing to segment a sequential program into three types of coarse-grained tasks: a basic block (BB), a repetition block (RB), and a subroutine block (SB). The coarse-grained task is also referred to as a macro task (MT). In some cases, macro dataflow processing suffers from a problem such that processor utilization efficiency is not improved due to the program's shape, and sufficient coarse-grained parallelism cannot be extracted.

[0020] Under these circumstances, the automatic parallelization compiler uses hierarchical macro dataflow processing, which extends a traditional single hierarchical macro dataflow processing technique and uses hierarchical macro dataflow processing within the MT. In hierarchical macro dataflow processing, the MT is defined hierarchically, and the parallelism between macro tasks is analyzed for each hierarchy. (Generation of macroflow graphs (MFG))

[0021] The automatic parallelization compiler first analyzes a control dependency and a data dependency between the macro tasks for the generated macro tasks of the respective hierarchies. The analysis results are expressed as a macroflow graph (MFG). (Creating a macro task graph (MTG))

[0022] The MFG represents the control dependency and data dependency between macrotasks, but does not represent parallelism. To extract parallelism, it is necessary to analyze an earliest executability condition with respect to both control dependency and data dependency: The earliest executability condition is a condition under which the MT is executable at the earliest time and is obtained from subsequent execution conditions. (1) If an MTi is data dependent on an MTj, the MTi cannot be executed until the execution of the MTj is completed. (2) When a destination of a conditional branch of the MTj is determined, the MTi that is control-dependent on the MTj can be executed even if the execution of the MTj is not completed.

[0023] Accordingly, a general form of an earliest feasibility condition is expressed as follows.

[0024] Earliest executability condition: (The MTj on which the MTi is control dependent has branched to the MTi) and ((an MTk (0 ≤ k ≤ | N |) on which the MTi is data dependent has completed) OR (it is determined that the MTk is not executed)).

[0025] The earliest executability condition of the macro task is represented by a macro task graph (MTG). 1-4. Multigranular parallel processing

[0026] The automatic parallelization compiler implements multi-grain parallelism in addition to conventional loop parallelism, effectively combining coarse-grained task parallelism with near-fine-grained parallelism (see "Parallelism Detection Method Between Fortran Program Coarse Grain Tasks" in the Institute of Electronics, Information and Communication Engineers Journal, 1990 by Hiroki Honda, Masahiko Iwata, and Hironori Kasahara). Coarse-grained task parallelism utilizes parallelism between coarse-grained tasks, between loops and between subroutines, while near-fine-grained parallelism utilizes parallelism between instructions. (Coarse-grained task parallel processing)

[0027] The automatic parallelization compiler generates a macroflow graph (MFG) that represents the control dependency and data dependency between the MTs of the BB, the RB, and the SB. The automatic parallelization compiler further expresses the parallelism of the MTs extracted by the MFG by analyzing the earliest executability condition as the macrotask graph (see "Parallelism Detection Method Between Fortran Program Coarse Grain Tasks" in the Institute of Electronics, Information and Communication Engineers Journal, 1990 by Hiroki Honda, Masahiko Iwata, and Hironori Kasahara and "Macro Task Generation Method of Fortran Macro Data Flow Processing," IEICE, 1992, Vol. J75-DI, No. 8, pages 511 to 525 by Kasahara, Goda, Yoshida, Okamoto, and Honda).

[0028] The automatic parallelization compiler then assigns the MT on the MTG to a processor group (PG) into which one or more processor elements (PE) are grouped. (Medium-grained parallel processing)

[0029] The MT assigned to the PG is subjected to medium-grained parallel processing by a processor within a processor cluster if parallel processing is enabled in the MT in a DOALL loop or an iteration stage. Medium-grained parallel processing represents parallel processing using parallelism between DO loop iterations and is most general in parallel processing on multi-core processors. (Almost fine-grained parallel processing)

[0030] Instruction-level parallel processing for near-fine-grained tasks is called near-fine-grained parallel processing. As a result, parallel execution in the application can be performed without dependencies, reducing execution time. 1-5. Macro task scheduling

[0031] In coarse-grained task parallel processing, the macrotask generated in each hierarchy is assigned to the PG and executed. A scheduling technique for determining which PG the macrotask is assigned to includes dynamic scheduling and static scheduling, which are described below. These scheduling techniques are performed based on the shape of the macrotask graph, the execution time, and the indeterminacy. (Dynamic scheduling)

[0032] When execution time uncertainty exists, such as conditional branching, the macro task is assigned to the PG during execution through dynamic scheduling. The dynamic scheduling routine maintains a macro task execution management table based on the completion of the macro task or the determination of a branch direction, and examines the earliest executability condition for each macro task.

[0033] If the macro tasks can be executed, they are placed in a ready queue. The macro tasks within the ready queue are sorted according to their priority, and a head or topmost macro task in the ready queue is assigned to the processor cluster of an idle state.

[0034] Similarly, at the time of generating and code development for dynamic scheduling, a centralized scheduling system and a distributed scheduling system can be selectively used according to the number of processors to be used and the synchronization overhead of the system. In the centralized scheduling system, a dedicated processor performs scheduling, and in the distributed scheduling system, a scheduling function is distributed among the respective processors. (Static scheduling)

[0035] On the other hand, static scheduling is a system used when the macrotask graph has only one data dependency edge, where the automatic parallelization compiler determines the allocation of the macrotask to the PG during compilation.

[0036] Static scheduling can be effectively used for scheduling the fine-grained task because static scheduling can eliminate execution scheduling overhead and minimize the overhead synchronous to data transmission.

[0037] During static scheduling, the effort is applied with a task effort estimate in the automatic parallelization compiler, but task scheduling with a real effort can be performed using a so-called Profile Automatic Feedback Function of the automatic parallelization compiler.

[0038] When using the Profile Automatic Feedback Function, the sequential program is decomposed into MTs as a first phase, and a profiler function is inserted for each MT to generate the sequential program. The profiler function measures the task execution overhead (clock cycle) and the number of task executions. The sequential program, into which the profiler function is inserted, is executed on a target machine, and a file containing information about the task execution overhead and the number of tasks on the target machine is output.

[0039] Then, in a second phase, the parallelized program, which is planned based on the real effort, is generated with the output file and the sequential program as inputs. 1-6. Data localization

[0040] The automatic parallelization compiler can perform cache optimization for the entire program. If the automatic parallelization compiler finds that there is a data dependency between loops after analyzing the parallelism, the automatic parallelization compiler attempts to globally optimize the cache between the loops that have the dependency (see Japanese Patent No. 4177681).

[0041] Specifically, a sequence to be accessed in each loop is examined, and the same split loops are set to access the same sequence portion, thereby assigning the same split loop to the same processor. Consequently, all sequence data in a cache is reused within the same split loop.

[0042] The above localization technology has evolved into a local storage management and data transmission technology, which is described below (see UK Patent No. 2,478,874). (1) When a local memory or distributed shared memory of an arbitrary size is provided before accessing the memory using a DMA (DTU) (see Japanese Patent No. 4476267), data is preloaded into the local or distributed shared memory in close proximity to the processor and reused throughout the program. (2) When a target memory is full after a DTU of a target processor is informed by a synchronization flag that data in the shared memory or the like has been transferred from the memory according to a transfer priority order, the DTU transfers the data to a memory that is automatically empty. (3) When data to be reused in the future is not used for a while and an area of ​​memory needs to be cleared, the DTU retrieves the data to a centralized shared memory after a task execution by the CPU and reloads the data into the memory until a use time. 1-7. Generation of parallelized program

[0043] When generating the parallelized program in the automatic parallelization compiler, parallelization can be performed in source-to-source languages ​​such as parallelized C or parallelized Fortran using an automatic parallelization API (see “Optimally Scheduled Advanced Multiprocessor Application Program Interface,” 2008 by Waseda University).

[0044] In this case, to make the parallelized program executable on different platforms, the automatic parallelization compiler converts a C or Fortran directive section for each processor into a runtime library call using, for example, an interpretation system of an automatic parallelization API standard (automatic parallelization API standard interpretation system), which will be described later. The automatic parallelization API standard is an example of a predetermined standard. After that, by sequentially compiling code for each processor to generate binary code and linking the generated binary code, the automatic parallelization compiler can execute the parallelized program on the target multi-core processor. 2. Parallelization procedure and technique of a sequential program for built-in system

[0045] The following describes the feature of the sequential program for the on-board system and a parallelization technique using the automatic parallelization compiler according to the present embodiment. The on-board system may be, for example, an in-vehicle device or an electronic device other than the in-vehicle device. The sequential program may be automatically generated by model-based design (for example, a sequential program automatically generated by Matlab (registered trademark) or Simulink (registered trademark) provided by MathWorks, Inc.).

[0046] The automatic parallelization compiler is configured with conditional branching and assignment statements, performs inline expansion and renaming for sequential programs with fine processing, and extracts parallelism. The automatic parallelization compiler performs task aggregation to conceal conditional branching for real-time performance and performs static scheduling to minimize overhead. Furthermore, the automatic parallelization compiler can implement the Profile Automatic Feedback Function to perform static scheduling with real-time overhead.

[0047] Furthermore, in the sequential program, conditional compilation can be performed to select a description to be compiled according to each type of built-in system that differs in target, function, and hardware configuration through a conditional compilation switch (command to the preprocessor). In such a case, information (information indicating the target, etc.) corresponding to any type is set as an instruction of each conditional compilation switch of the sequential program to generate a binary code corresponding to the type of the sequential program.

[0048] In contrast, the automatic parallelization compiler according to the present embodiment ignores the selection of a target to be compiled by conditional compilation, performs macro task segmentation, parallelism extraction, and static scheduling for all sections of the sequential program, and generates the parallelized program. The automatic parallelization compiler then identifies a description to be excluded from compilation by conditional compilation and generates binary data for operating the multi-core processor from the parallelized program in a state where the above description is excluded. 2-1. Operating environment of automatic parallelization compiler

[0049] An automatic parallelization compiler 1 is provided to a user in a state in which it is stored in a storage medium (memory) 18, which may be an optical disk such as a DVD, a CD-ROM, a USB memory or a memory card (Memory Card, registered trademark), a magnetic disk or a semiconductor memory (cf. Fig. 1) is configured. Needless to say, the automatic parallelization compiler 1 can be provided to the user over a network.

[0050] A personal computer (PC) 10, in which the automatic parallelization compiler 1 is installed, operates as an automatic parallelization compiler. The PC 10 includes a display unit 11, a hard disk drive (HDD) 12, a central processing unit (CPU) 13, a read-only memory (ROM) 14, a random access memory (RAM) 15, an input device 16, and a reading unit 17.

[0051] The display unit 11 displays an image to the user based on an image signal transmitted from the CPU 13.

[0052] The input device 16 is configured by a keyboard, a mouse, and the like, and is operated by the user to output a signal corresponding to the operation to the CPU 13.

[0053] The reading unit 17 is configured to read data from the storage medium 18 in which the automatic parallelization compiler 1, etc., are stored.

[0054] The RAM 15 is a readable and writable volatile memory, the ROM 14 is a non-volatile read-only memory, and the hard disk 12 or HDD 12 is a non-volatile readable and writable memory. Programs to be read and executed by the CPU 13, and the like, are prestored in the ROM 14 and the HDD 12.

[0055] The RAM 15 is used as a storage area for temporarily storing the programs or a storage area for temporarily storing work data when the CPU 13 executes the programs stored in the ROM 14 and the HDD 12.

[0056] The CPU 13 reads an operating system (OS) from the HDD 12 to execute the OS and executes various programs recorded in the HDD 12 as processing on the OS. The CPU 13 receives an input signal from the input device 16 as required, outputs the image signal to the display unit 11, and controls the reading / writing of data with respect to the RAM 15 and the HDD 12.

[0057] The automatic parallelization compiler 1, which is read from the storage medium 18 by the reading unit 17, is installed in the PC 10, and the automatic parallelization compiler 1 functions as one of applications stored in the HDD 12 and is executed as processing on the OS.

[0058] Furthermore, the automatic parallelization compiler is used in the development of the parallelized program for the on-board system, such as the vehicle device. However, the automatic parallelization compiler is not limited to the above, but can be used in the development of the parallelized program for an on-board system for various applications such as information devices, or the development of the parallelized program in applications other than the on-board system. 3. Configuration of the vehicle device

[0059] The following is in accordance with Fig. 2, a configuration of a vehicle device 20 operating with the aid of the parallelized program generated by the automatic parallelization compiler 1 of the present embodiment is described. Needless to say, the automatic parallelization compiler 1 is not limited to the vehicle device 20, but can generate the parallelized program for operating various electronic devices having the same configuration.

[0060] The vehicle device 20 includes a multi-core processor 21, a communication unit 22, a sensor unit 23, an input / output port 24, and the like. The multi-core processor 21 includes a ROM 21a, a RAM 21b, and a plurality of cores 21c, 21d, etc.

[0061] The ROM 21a stores a parallelized program 21a-1 (binary data) generated by the automatic parallelization compiler 1. The multi-core processor 21 operates according to the parallelized program 21a-1 and comprehensively controls the vehicle device 20.

[0062] The RAM 21b is configured to be accessible to the cores 21c, 21d, etc. The communication unit 22 is configured to communicate with another ECU connected to the communication unit 22 through an in-vehicle LAN or the like.

[0063] The sensor unit 23 is configured with various sensors for detecting the state of an object to be controlled, etc. The input / output port 24 is configured to transmit and receive various signals for controlling the object to be controlled. (Specific examples)

[0064] Specific examples of the processing for generating the parallelized program by the automatic parallelization compiler 1 of the present embodiment will be described below. In the following description, although processing A, etc., are described, processing A, etc., represents a description of a series of processing including various operations, assignments, branch processing, function calls, etc. (First embodiment)

[0065] Fig. 3 shows a parallelization compilation method according to a first embodiment, and this parallelization compilation method can be executed by the automatic parallelization compilation device 10. At S101, the existence of data dependency relationship cancellation information is determined (corresponding to the cancellation determination unit). If the data dependency relationship cancellation information exists, the flow proceeds to processing of S103, and if there is no data dependency relationship cancellation information, the flow proceeds to processing of S102. The data dependency relationship cancellation information is defined in advance in the sequential program between two or more macro tasks and is also referred to as cancellation information for convenience.

[0066] At S102, the same parallelization processing as that of the prior art is executed to generate a segmented program. One of specific examples in generating the segmented program is shown in Fig. 4. As in Fig. 4, it is assumed that a software (SW) C, which is a sequential program, includes a processing A, a processing B, a processing C, and a processing D, and there is a data dependency relationship between the processing A and the processing B. It is assumed that an execution time of the processing A is 100, an execution time of the processing B is 20, an execution time of the processing C is 30, and an execution time of the processing D is 35 (values ​​of these execution times are relative values).

[0067] Since processing A and processing B have a dependency relationship, processing A and processing B are assigned to core 0. Processing C and processing D are assigned to core 1, so the total execution time becomes the shortest under the above assumption. In this example, the execution time of core 1 is 120, and the execution time of core 1 is 65.

[0068] At S103, data dependency relationship cancellation information is acquired. In this example, it is assumed that there is data dependency relationship cancellation information so that the data dependency relationship between processing A and processing B can be canceled. At S104 following S103, a dependency relationship cancellation section is specified, and parallelization processing is executed to generate a segmented program (corresponding to a generation unit).

[0069] One of specific examples in generating the segmented program is in Fig. 5. As in Fig. 5, it is assumed that a software C, which is a sequential program, includes processing A, processing B, processing C, and processing D, and there is a data dependency relationship between processing A and processing B. It is assumed that an execution time of processing A is 100, an execution time of processing B is 20, an execution time of processing C is 30, and an execution time of processing D is 35 (values ​​of these execution times are relative values).

[0070] First, the dependency relationship between processing A and processing B is eliminated. Since a dependency relationship between processing A and processing B is eliminated, parallel processing is executed, so the total execution times are shorter. In this example, processing A is assigned to core 0, and processing B, processing C, and processing D are assigned to core 1. In this example, the execution time of core 0 is 100, and the execution time of core 1 is 85. Compared with the example described in the processing of S102, the total execution time is improved. (Second embodiment)

[0071] Fig. 6 shows a parallelization compilation method according to a second embodiment, and this parallelization compilation method can be executed by the automatic parallelization compilation device 10. At S210, the existence of data dependency relationship cancellation information is determined (corresponding to a cancellation determination unit). If there is data dependency relationship cancellation information, the flow proceeds to processing S203, and if there is no data dependency relationship cancellation information, the flow proceeds to processing S202.

[0072] At S202, the same parallelization processing as that of the prior art is executed to generate a segmented program. One of the specific examples of generating the segmented program is shown in Fig. 8. As in Fig. 8, a software C, which is a sequential program, includes a processing A, a processing B, a processing C, a processing D and a processing E. The processing A to processing E have a Fig. 7 illustrated data dependency relationship. As in Fig. 7, it is assumed that there are respective data dependency relationships between processing B and processing D, between processing C and processing D as well as processing E, and between processing D and processing E. It is assumed that an execution time of processing A is 15, an execution time of processing B is 10, an execution time of processing C is 50, an execution time of processing D is 30, and an execution time of processing E is 20 (values ​​of these execution times are relative values).

[0073] Considering these data dependency relationships, Process A, Process B, Process D, and Process E are assigned to core 0 so that the total execution time is the shortest, and Process C is assigned to core 1. A wait time is provided between Process B and Process D to maintain the data dependency relationship between Process C and Process B. In this example, the execution time of core 0 is 100, and the execution time of core 1 is 50.

[0074] At S203, data dependency relationship cancellation information is acquired. In this example, it is assumed that there is data dependency relationship cancellation information so that the data dependency relationship between processing C and processing D can be canceled.

[0075] At S204 following S203, it is determined whether or not there is a dependency relationship of a reference data cycle timing (synchronous processing timing) (corresponding to the timing determination unit). If the dependency relationship of the reference data cycle timing exists, the flow proceeds to processing of S206, and if there is no dependency relationship of the reference data cycle timing, the flow proceeds to processing of S205.

[0076] The reason the reference data cycle timing is thus confirmed is that even if the segmented program is generated based on the execution time of each processing, the execution time is not a constant value, but an average or maximum value, and therefore the actual execution time may be increased or decreased. If the execution time is thus increased or decreased, even if the cancellation of the data dependency relationship is permitted, trouble will arise between the respective processings whose context needs to be maintained. Therefore, it is additionally necessary to maintain the context. This fact is confirmed at S204.

[0077] At S205, a dependency relationship cancellation section is specified and parallelization processing is executed to generate a segmented program (corresponding to generation unit).

[0078] One of specific examples of generating the segmented program is in Fig. 9. As in Fig. 9, it is assumed that the software C, which is a sequential program, includes processing A, processing B, processing C, processing D and processing E, and that there is a Fig. 7 illustrated data dependency relationship.

[0079] First, the Fig. 7 is eliminated. Since the data dependency relationship is eliminated, parallel processing is executed so that the total execution time is as short as possible. In this example, processing B, processing D, and processing A are assigned to core 0, and processing C and processing E are assigned to core 1. In this example, the execution time of core 0 is 55, and the execution time of core 1 is 70.

[0080] At S206, a reference data cycle timing synchronization setting is obtained. In this example, the execution of processing D after processing C is a replacement prohibition condition for each processing cycle.

[0081] At S207 following S206, parallelization processing with a synchronization condition is executed to generate a segmented program. Fig. Figure 10 illustrates an example of parallel processing with the synchronization condition. An example of start synchronization is shown in Fig. 10 illustrates. Processing B, processing D, and processing A are assigned to core 1, and processing C and processing E are assigned to core 0. To prevent an execution order of processing D and processing C from replacing each other, a wait time is provided for setting a start time of processing C. In this example, an execution time of core 0 is 55, and an execution time of core 1 is 80.

[0082] Fig. Figure 11 illustrates another example of parallel processing with the synchronization condition. An example of end synchronization is shown in Fig. 11 illustrates. Processing B, processing D, and processing A are assigned to core 1, and processing C and processing E are assigned to core 0. To prevent an execution order of processing D and processing C from replacing each other, a wait time is provided for setting an end time of processing D. In this example, an execution time of core 0 is 65, and an execution time of core 1 is 70.

[0083] Whether the start synchronization, which is Fig. 10, or the final synchronization shown in Fig. 11 is used, is determined according to another condition to be prioritized. For example, if the total execution time is to be reduced, the Fig. 11 illustrated final synchronization is used. If the shorter execution time is emphasized more, the Fig. The startup synchronization illustrated in Figure 10 is used. Another condition to be prioritized is the processing capacity of each core, the capacity of a memory, or the like. (Third embodiment)

[0084] Fig. 12 shows a parallelization compilation method according to a third embodiment, and this parallelization compilation method can be executed by the automatic parallelization compilation device 10. At S301, the existence of data dependency relationship cancellation information is determined (corresponding to the cancellation determination unit). If the data dependency relationship cancellation information exists, a flow proceeds to processing of S303, and if there is no data dependency relationship cancellation information, the flow proceeds to processing of S302.

[0085] At S302, the same parallelization processing as that of the prior art is executed to generate a segmented program. One of specific examples of generating the segmented program is shown in Fig. 14. As in Fig. 14, a software C, which is a sequential program, includes a processing A, a processing B, a processing C, a processing D and a processing E. The processing A to processing E have a Fig. 13 illustrated data dependency relationship. As in Fig. 13, it is assumed that there are respective data dependency relationships between processing A and processing C, between processing B and processing C, between processing C and processing D, and between processing D and processing E. It is assumed that an execution time of processing A is 15, an execution time of processing B is 10, an execution time of processing C is 30, an execution time of processing D is 50, and an execution time of processing E is 20 (values ​​of these execution times are relative values).

[0086] Considering these data dependency relationships, Process A, Process C, Process D, and Process E are assigned to core 0 so that the total execution time is the shortest, and Process B is assigned to core 1. In this example, an execution time of core 0 is 115, and an execution time of core 1 is 10.

[0087] At S303, data dependency relationship cancellation information is acquired. In this example, it is assumed that data dependency relationship cancellation information exists so that the data dependency relationship between processing C and processing D can be canceled.

[0088] At S304 following S303, it is determined whether or not there is a dependency relationship of reference data cycle timing (synchronous processing timing) (corresponding to timing determination unit). If the dependency relationship of reference data cycle timing exists, the flow proceeds to processing of S306, and if there is no dependency relationship of reference data cycle timing, the flow proceeds to processing of S305.

[0089] The reason the reference data cycle timing is thus confirmed is that even if the segmented program is generated based on the execution time of each processing, the execution time is not a constant value, but an average or maximum value, and therefore the actual execution time may be increased or decreased. If the execution time is thus increased or decreased, even if the cancellation of the data dependency relationship is permitted, a discrepancy occurs between the respective processings whose context needs to be maintained. Therefore, it is additionally necessary to maintain the context. This fact is confirmed at S304.

[0090] At S305, a dependency relationship cancellation section is specified and parallelization processing is executed to generate a segmented program (corresponding to generation unit).

[0091] One of specific examples in generating the sequential program is in Fig. 15. As in Fig. 15, it is assumed that the software C, which is a sequential program, includes processing A, processing B, processing C, processing D and processing E and there is a Fig. 13 illustrated data dependency relationship.

[0092] First, the Fig. 13 is eliminated. Since the data dependency relationship is eliminated, parallel processing is executed so that the total execution time is as short as possible. In this example, processing A, processing B, and processing C are assigned to core 0, and processing D and processing B are assigned to core 1. In this example, the execution time of core 0 is 55, and the execution time of core 1 is 70.

[0093] At S306, a pseudo data dependency setting is acquired. In this example, it is necessary to reverse the data dependency relationship between processing C and processing D. Specifically, in the data dependency relationship in which processing D is executed after processing C is completed, the relationship is reversed, and the data dependency relationship in which processing C is executed after processing D is completed is necessary.

[0094] At S307 following S306, parallelization processing with a pseudo data dependency condition is executed to generate a segmented program. Fig. Figure 16 illustrates an example of parallel processing with the pseudo-data dependency constraint. Fig. In the example illustrated in Figure 16, Processing A, Processing B, and Processing C are assigned to Core 0, and Processing D and Processing E are assigned to Core 1. To prevent the execution order of Processing D and Processing C from being replaced, a pseudo-data dependency relationship is provided. In this example, the execution time of Core 0 is 80, and the execution time of Core 1 is 70.

[0095] In the present embodiment, in a state where a first macro task included in the two or more macro tasks determined to have the cancellation information having a data dependency relationship with another macro task no longer requires the data dependency relationship with the other macro task with the provision of the data dependency relationship with a second macro task included in the two or more macro tasks, it is determined whether the data dependency relationship with the other macro task is eliminated or not, and the data dependency relationship between the other macro task and the first macro task can be restored when compiling the segmented program.

[0096] Below is a specific example according to Fig. 17A and Fig. 17B. In Fig. 17A, it is assumed that there are respective data dependency relationships between processing X and processing C, between processing A and processing C, between processing B and processing C, between processing C and processing D, and between processing D and processing E. For example, if processing X is processing for assigning an initial value c, processing C is processing for assigning a value c by calculating A+D, and processing D is processing for obtaining a value d by the value c, a data dependency relationship between processing X and processing D is redundant and is thus eliminated.

[0097] In the Fig. 17A, when the data dependency between processing C and processing D is eliminated because a result of processing X is required in processing D, the eliminated data dependency relationship between processing X and processing D is restored as shown in Fig. 17B is illustrated.

[0098] Below is another example with reference to Fig. 18A and Fig. 18B. In Fig. 18A, there are respective data dependency relationships between a processing A and a processing B and a processing C, between the processing C and a processing D, and between a processing D and a processing E. The processing A is a processing for assigning a value A, the processing B is a processing for assigning a value B, the processing C is a processing for assigning a value C by calculating A+B, and the processing D is a processing for assigning a value D by calculating C+A+B.

[0099] In Fig. 18A, if the data dependency relationship between processing C and processing D is eliminated, since processing results of processing A and processing B are required for processing D, the data dependency relationships between processing A and processing B and processing D are introduced as in Fig. 18B is illustrated.

[0100] Below is another example according to Fig. 19A to Fig. 19C. In Fig. 19A, there are respective data dependency relationships between a processing A and a processing B and a processing C, between the processing C and a processing D and between a processing D and a processing E. If a data dependency relationship between the processing C and the processing D is eliminated, a state of Fig. 19 starting from the state of Fig. 19A. In order to eliminate a change in order for each processing cycle, a pseudo data dependency relationship is established from processing D to processing C as shown in Fig. 19 starting from the Fig. 19B shown state.

[0101] In the present embodiment, the parallelization compiling method and the parallelization compiler can be realized by the multi-core processor of the vehicle device instead of the automatic parallelization compiling device.

Claims

[1] A parallelization compilation method implemented by a multi-core processor (21) that simultaneously realizes an increase in processing speed and a reduction in power consumption by integrating a plurality of processor cores each having a low operation frequency on a single chip, the parallelization compilation method generating a plurality of segmented programs executable by the processor cores of the multi-core processor (21) from a sequential program executable by a single-core processor by dividing the sequential program into the segmented programs, the sequential program including a plurality of macrotasks, and at least two of the plurality of macrotasks have a data dependency relationship with each other, the parallelization compilation method comprising: Determining an existence of cancellation information for canceling at least part of the data dependency relationship between the at least two of the plurality of macro tasks before compiling the sequential program into the segmented programs (S101, S201, S301); and Generating the segmented programs by compiling the sequential program into the segmented programs with respect to a determination result of the existence of the cancellation information, wherein, if the cancellation information is determined to exist, the at least part of the data dependency relationship is canceled before compiling the sequential program into the segmented programs (S103, S104, S203, S205, S303, S305) and then the sequential program is compiled into the segmented programs to be assigned to the respective processor cores of the multi-core processor so that an execution time of the respective segmented programs becomes the shortest, when the cancellation information is determined not to exist between the at least two of the macro tasks having the data dependency relationship with each other, the sequential program is compiled into the segmented programs to be assigned to the respective processor cores of the multi-core processor, so that the at least two of the macro tasks are assigned to the same segmented program and executed by the same processor core of the multi-core processor. [2] The parallelization compilation method according to claim 1, further comprising: Determining whether the at least two of the plurality of macro tasks determined to have cancellation information have a processing synchronization timing dependency on each other when the existence of the cancellation information is determined (S204), wherein, when it is determined that the at least two of the plurality of macro tasks have the processing synchronization timing dependency on each other, compiling the segmented programs to maintain the processing synchronization timing dependency by adjusting respective execution times of the at least two of the plurality of macro tasks during generation of the segmented programs (S206, S207). [3] The parallelization compiling method according to claim 2, wherein, during the generation of the segmented programs, the respective execution time of the at least two of the plurality of macro tasks is adjusted to meet a predetermined standard for generating the segmented programs and to maintain the dependency of the processing synchronization timing. [4] The parallelization compilation method according to claim 1, further comprising: Determining whether the at least two of the plurality of macro tasks determined to have the cancellation information have a processing synchronization timing dependency on each other when the existence of the cancellation information is determined (S304), wherein when it is determined that the at least two of the plurality of macro tasks have the processing synchronization timing dependency on each other, compiling the segmented programs to maintain the processing synchronization timing dependency by reversing the data dependency relationship of the at least two of the plurality of macro tasks during generation of the segmented programs (S306, S307). [5] The parallelization compilation method according to claim 1, further comprising: in a case where (i) the existence of the cancellation information is determined, and (ii) a first macro task included in the at least two of the plurality of macro tasks determined to have the cancellation information had a data dependency relationship with another macro task, but no longer has the data dependency relationship with the other macro task by newly having the data dependency relationship with a second macro task included in the at least two of the plurality of macro tasks, determining whether the data dependency relationship with the other macro task is eliminated, wherein during the generation of the segmented programs, the data dependency relationship between the other macro task and the first macro task is restored when compiling the segmented programs. [6] A parallelization compiler stored in a non-transitory tangible computer-readable storage medium as a program product, wherein the parallelization compiler is executed by a multi-core processor (21) that simultaneously realizes an increase in processing speed and a reduction in power consumption by integrating a plurality of processor cores, each having a low operation frequency, on a single chip, wherein the parallelization compiler generates a plurality of segmented programs executable by the processor cores of the multi-core processor (21) from a sequential program executable by a single-core processor by dividing the sequential program into the segmented programs, and the sequential program includes a plurality of macro tasks, and at least two of the plurality of macro tasks have a data dependency relationship with each other,wherein the parallelization compiler comprises instructions to be executed by a parallelization compiler, the instructions serving to implement: Determining an existence of cancellation information for canceling at least part of the data dependency relationship between the at least two of the plurality of macro tasks before compiling the sequential program into the segmented programs (S101, S201, S301); and Generating the segmented programs by compiling the sequential program into the segmented programs with respect to a determination result of the existence of the cancellation information, wherein, if the cancellation information is determined to exist, the at least part of the data dependency relationship is canceled before compiling the sequential program into the segmented programs (S103, S104, S203, S205, S303, S305) and then the sequential program is compiled into the segmented programs to be assigned to the respective processor cores of the multi-core processor so that an execution time of the respective segmented programs becomes the shortest, when the cancellation information is determined not to exist between the at least two of the macro tasks having the data dependency relationship with each other, the sequential program is compiled into the segmented programs to be assigned to the respective processor cores of the multi-core processor, so that the at least two of the macro tasks are assigned to the same segmented program and executed by the same processor core of the multi-core processor. [7] Parallelization compiler according to claim 6, further comprising: an instruction to be executed by the parallelization compiling device and for determining whether the at least two of the plurality of macro tasks determined to have cancellation information have a processing synchronization timing dependency on each other when the existence of the cancellation information is determined (S204), wherein, when it is determined that the at least two of the plurality of macro tasks have the processing synchronization timing dependency on each other, compiling the segmented programs to maintain the processing synchronization timing dependency by adjusting respective execution times of the at least two of the plurality of macro tasks during generation of the segmented programs (S206, S207). [8] The parallelization compiler according to claim 7, wherein during the generation of the segmented programs, the respective execution time of the at least two of the plurality of macro tasks is adjusted to meet a predetermined standard for generating the segmented programs and to maintain the dependency of the processing synchronization timing. [9] Parallelization compiler according to claim 6, further comprising: an instruction to be executed by the parallelization compiling device and for determining whether the at least two of the plurality of macro tasks determined to have the cancellation information have a processing synchronization timing dependency on each other when the existence of the cancellation information is determined (S304), wherein when it is determined that the at least two of the plurality of macro tasks have the processing synchronization timing dependency on each other, compiling the segmented programs to maintain the processing synchronization timing dependency by reversing the data dependency relationship of the at least two of the plurality of macro tasks during generation of the segmented programs (S306, S307). [10] Parallelization compiler according to claim 6, further comprising: in a case where (i) the existence of the cancellation information is determined, and (ii) a first macro task included in the at least two of the plurality of macro tasks determined to have the cancellation information had a data dependency relationship with another macro task, but no longer has the data dependency relationship with the other macro task by newly having the data dependency relationship with a second macro task included in the at least two of the plurality of macro tasks, an instruction to be executed by the parallelization compiling device and to determine whether the data dependency relationship with the other macro task is eliminated, wherein during the generation of the segmented programs, the data dependency relationship between the other macro task and the first macro task is restored when compiling the segmented programs. [11] Vehicle device, comprising: a multi-core processor (21), wherein the multi-core processor contains multiple processor cores and simultaneously realizes an increase in processing speed and a reduction in energy consumption by integrating multiple processor cores, each having a low operating frequency, on a single chip, the multi-core processor (21) generates a plurality of segmented programs executable by the processor cores of the multi-core processor from a sequential program executable by a single-core processor by dividing the sequential program into the segmented programs, and the sequential program includes a plurality of macrotasks, and at least two of the plurality of macrotasks have a data dependency relationship with each other, wherein the multi-core processor (21) is configured to: determining the existence of cancellation information for canceling at least part of the data dependency relationship between the at least two of the plurality of macro tasks before compiling the sequential program into the segmented programs (S101, S201, S301); and to generate the segmented programs by compiling the sequential program into the segmented programs with respect to a determination result of the existence of the cancellation information, if the cancellation information is determined to exist, the at least part of the data dependency relationship is canceled before compiling the sequential program into the segmented programs (S103, S104, S203, S205, S303, S305) and then the sequential program is compiled into the segmented programs to be assigned to the respective processor cores of the multi-core processor so that an execution time of the respective segmented programs becomes the shortest, when the cancellation information is determined not to exist between the at least two of the macro tasks having the data dependency relationship with each other, the sequential program is compiled into the segmented programs to be assigned to the respective processor cores of the multi-core processor, so that the at least two of the macro tasks are assigned to the same segmented program and executed by the same processor core of the multi-core processor. [12] Vehicle device according to claim 11, wherein the multi-core processor (21) is further configured to determine whether the at least two of the plurality of macro tasks determined to have cancellation information have a processing synchronization timing dependency on each other when the existence of the cancellation information is determined (S204), and when it is determined that the at least two of the plurality of macro tasks have the processing synchronization timing dependency on each other, compiling the segmented programs to maintain the processing synchronization timing dependency by adjusting respective execution times of the at least two of the plurality of macro tasks during generation of the segmented programs (S206, S207). [13] The vehicle device according to claim 12, wherein during the generation of the segmented programs, the respective execution time of the at least two of the plurality of macro tasks is adjusted to meet a predetermined standard for generating the segmented programs and to maintain the dependency of the processing synchronization timing. [14] Vehicle device according to claim 11, wherein the multi-core processor (21) is further configured to determine whether the at least two of the plurality of macro tasks determined to have the cancellation information have a processing synchronization timing dependency on each other when the existence of the cancellation information is determined (S304), wherein when it is determined that the at least two of the plurality of macro tasks have the processing synchronization timing dependency on each other, compiling the segmented programs to maintain the processing synchronization timing dependency by reversing the data dependency relationship of the at least two of the plurality of macro tasks during generation of the segmented programs (S306, S307). [15] Vehicle device according to claim 11, wherein the multi-core processor (21) is further configured to in a case where (i) the existence of the cancellation information is determined, and (ii) a first macro task included in the at least two of the plurality of macro tasks determined to have the cancellation information had a data dependency relationship with another macro task, but no longer has the data dependency relationship with the other macro task by newly having the data dependency relationship with a second macro task included in the at least two of the plurality of macro tasks, determine whether the data dependency relationship with the other macro task is eliminated, and during the generation of the segmented programs, the data dependency relationship between the other macro task and the first macro task is restored when compiling the segmented programs.

Images