Method for adjusting the threshold voltage for a gate-all-around semiconductor structure

Abstract

A method comprising: providing a semiconductor structure (100) comprising a plurality of first semiconductor layers (108) interleaved with a plurality of second semiconductor layers (110), the first and second semiconductor layers having different material compositions; forming a dummy gate stack (105) over a topmost first semiconductor layer (108); performing a first etching process (200) to remove portions of the second semiconductor layer (110) not located beneath the dummy gate stack, thereby forming a plurality of cavities (210), the first etching process having etch selectivity with respect to the first semiconductor layer (108) and the second semiconductor layer (110); and subsequently performing a second etching process (300) to enlarge the cavities (210);wherein the second etching process (300) is performed to increase a horizontal dimension (230A) of each of the cavities (210), wherein forming the dummy gate stack (105) comprises forming a plurality of dummy gate stacks (105) in a first region (610) and a second region (620) of the semiconductor structure, and wherein the first etching process (200) and the second etching process (300) are performed such that cavities (210) in the first region (610) and cavities in the second region (620) have different horizontal dimensions.;

Description

BACKGROUND

[0001] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technical advances in IC materials and design have produced generations of ICs, with each generation featuring smaller and more complex circuits than the previous generation. As ICs have evolved, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This downsizing process generally provides benefits by increasing production efficiency and reducing associated costs. Such downsizing has also increased the complexity of IC processing and manufacturing, and for these advances to be realized, similar developments in IC processing and manufacturing are required.

[0002] For example, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reduce off-state current, and mitigate short-channel effects (SCEs). One such multi-gate device is a horizontal gate all-around (HGAA) transistor, whose gate structure extends around its horizontal channel region, allowing access to the channel region from all sides. HGAA transistors are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes, allowing them to be greatly downsized while maintaining gate control and reducing SCEs. However, conventional HGAA devices struggle to control their threshold voltage (Vt) due to issues such as smaller depletion regions and channel volumes, and mobility degradation caused by heavy doping.

[0003] Although conventional HGAA devices have generally been adequate for their intended purposes, they are not satisfactory in all respects.

[0004] US 2014 / 0001441 A1 relates to a semiconductor device comprising a nanowire stack arranged above a substrate, the nanowire stack comprising a plurality of vertically stacked nanowires, and a gate structure wrapped around each of the plurality of nanowires and defining a channel region of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. It is emphasized that, in accordance with standard industry practice, various elements are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily exaggerated or reduced for clarity of discussion. The Fig. 1A-5A are cross-sectional side views of a semiconductor structure at various stages of fabrication according to various aspects of the present disclosure. The Fig. 1B-5B are cross-sectional side views of a semiconductor structure at various stages of fabrication according to various aspects of the present disclosure. The Fig. 6-11 are cross-sectional side views of a semiconductor structure at various stages of fabrication according to various aspects of the present disclosure. Fig. 12 is a flow diagram illustrating a method of fabricating a semiconductor structure according to various aspects of the present disclosure. DETAILED DESCRIPTION

[0006] The invention results from the independent claims. The dependent claims relate to corresponding developments. The following disclosure provides many different embodiments or examples for implementing various features of the specified subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the formation of a first device over or on a second device in the following description may include embodiments in which the first and second devices are formed in direct contact, and may also include embodiments in which additional devices may be formed between the first device and the second device such that the first and second devices need not be in direct contact.Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, impose any relationship between the various described embodiments and / or configurations.

[0007] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or feature to other element(s) or feature(s) as shown in the figures. The spatially relative terms are intended to encompass various orientations of the device being used or operated in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative terms used herein may also be interpreted accordingly.

[0008] The present disclosure relates generally to semiconductor devices and methods of fabricating the same. More particularly, the present disclosure relates to gate-all-around (GAA) devices. A GAA device includes any device whose gate structure, or portions thereof, are formed on four sides of a channel region (e.g., surrounding a portion of a channel region). The channel region of a GAA device may include nanowire channels, bar-shaped channels, and / or other suitable channel configurations. In certain embodiments, the channel region of a GAA device may include multiple horizontal nanowires or horizontal bars that are vertically spaced, making the GAA device a stacked horizontal GAA (S-HGAA) device. The GAA devices presented herein may include p-type metal-oxide-semiconductor GAA devices or n-type metal-oxide-semiconductor GAA devices.Furthermore, the GAA devices may include one or more channel regions (e.g., nanowires) associated with a single, contiguous gate structure or multiple gate structures. One of ordinary skill in the art may recognize other examples of semiconductor devices that may benefit from aspects of the present disclosure.

[0009] The Fig. 1A-5A and 1B-5B show various cross-sectional side views of a semiconductor structure 100 at various stages of fabrication according to embodiments of the present disclosure. In particular, the Fig. 1A-5A are cross-sectional views along a Y-direction of the semiconductor structure 100 and the Fig. 1B-5B show cross-sectional views along an X-direction of the semiconductor structure 100, wherein the Y-direction is orthogonal or perpendicular to the X-direction. Fig. 1A-5A a Y-section of the semiconductor structure 100, while the Fig. 1B-5B show an X-section of the semiconductor structure 100.

[0010] In the illustrated embodiments, the semiconductor structure 100 includes a GAA device (e.g., an HGAA device). The GAA device may be fabricated during processing of an IC or a portion thereof, which may include static random access memory (SRAM) and / or logic circuits, passive components such as resistors, capacitors, and inductors, and active components such as p-type field-effect transistors (PFETs), n-type FETs (NFETs), multi-gate FETs such as FinFETs, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar transistors, power transistors, radio-frequency transistors, other memory cells, and combinations thereof.

[0011] With reference to Fig. 1A-1B, the semiconductor structure 100 includes a rib-like structure 104 (hereinafter referred to simply as a "rib") that protrudes vertically upward in a Z-direction, wherein the Z-direction is orthogonal to a horizontal plane defined by the Y-direction and the X-direction. The rib 104 includes a stack of alternately arranged semiconductor layers 108 and 110.

[0012] The semiconductor layers 108 and 110 are stacked vertically (along the Z-direction) in an interleaved or alternating manner (e.g., one layer 110 is disposed above a layer 108, then another layer 108 is disposed above the layer 110, and so on). In various embodiments, the structure 100 may include any number of fins 104, and the fins 104 may include any number of alternately stacked semiconductor layers 108 and 110. The material compositions of the semiconductor layers 108 and 110 are configured to exhibit etch selectivity in a subsequent etching process, which is described in more detail below. For example, in some embodiments, the semiconductor layer 108 comprises silicon (Si), while the semiconductor layer 110 comprises silicon germanium (SiGe). In some further embodiments, the semiconductor layer 108 comprises SiGe, while the semiconductor layer 110 comprises Si.It is understood that, although . Fig. 1A shows a rib 104, the semiconductor structure 100 may have a plurality of further ribs similar to the rib 104.

[0013] As in Fig. 1A, the lower portions of the fin 104 are surrounded by an isolation structure 106. In some embodiments, the isolation structure 106 comprises shallow trench isolation (STI). The isolation structure 106 may comprise an electrically insulating material such as silicon oxide. As shown in Fig. As shown in Figure 1A, spacers 112 and spacers 114 are also arranged around the bottom portion of the fin structure 104, for example, around one of the semiconductor layers 108. The spacers may comprise a suitable dielectric material, for example, silicon nitride, silicon oxide, silicon oxynitride, or combinations thereof.

[0014] A dummy gate stack 105 is formed over a topmost one of the semiconductor layers 108. The dummy stack 105 includes a dielectric layer 120. In some embodiments, the dielectric layer 120 includes silicon oxide. In other embodiments, the dielectric layer 120 includes a high-k dielectric material. A high-k dielectric material is a material with a dielectric constant greater than the dielectric constant of SiO2, which is about 4. For example, the high-k gate dielectric includes hafnium oxide (HfO2), which has a dielectric constant ranging from about 18 to about 40. As various other examples, the high-k gate dielectric may include ZrO2, Y2O3, La2O5, Gd2O5, TiO2, Ta2O5, HfErO, HfLaO, HfYO, HfGdO, HfAlO, HfZrO, HfTiO, HfTaO, or SrTiO. The dummy gate stack 105 also includes a polysilicon layer 130 formed over the dielectric layer 120.The dummy gate stack 105 may be subjected to a gate replacement process to form a high-k metal gate, as described in more detail below.

[0015] Gate spacers 140 are formed on sidewalls of the dielectric layer 120 and the polysilicon layer 130. The gate spacers 140 comprise a dielectric material, such as silicon nitride, silicon oxide, silicon carbide, silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), other materials, or a combination thereof. The gate spacers 140 may have a single-layer or multi-layer structure. In some embodiments, the gate spacers 140 have a thickness in the range of a few nanometers (nm). In some embodiments, the gate spacers 140 may be formed by depositing a spacer layer (comprising a dielectric material) over the dummy gate stack 105, followed by an anisotropic etch process to remove portions of the spacer layer 140 from a top surface of the dummy gate stack 105.After etching, portions of the spacer layer remain substantially on the sidewall surfaces of the dummy gate stack 105 and become the gate spacer 140. In some embodiments, the anisotropic etching process is a dry (e.g., plasma) etching process. It is understood that forming the gate spacers 140 may also include chemical oxidation, thermal oxidation, ALD, CVD, and / or other suitable processes. The gate spacers 140 are used together with the dummy gate stack 105 to help define the physical and / or electrical length of the channels of the semiconductor structure 100. In some embodiments, the gate spacers 140 may be considered part of the dummy gate stack 105, although the gate spacers 140 are not removed in the gate replacement process described below.

[0016] Openings 150 are defined by the distance between adjacent spacers 140. Openings 150 may be formed by an etching process (etching through the gate spacer material) and expose the underlying semiconductor layer 108. Openings 150 each have a horizontal dimension 160 measured in the X-direction. In addition, the dummy gate stacks (e.g., the polysilicon layer 130) each have a horizontal dimension 170 measured in the X direction, and the gate spacers 140 each have a horizontal dimension 180 measured in the X direction. In some embodiments, the horizontal dimension 160 is in a range of about 8 nm to about 12 nm (e.g., about 10 nm), the horizontal dimension 170 is in a range of about 10 nm to about 14 nm (e.g., about 12 nm), and the horizontal dimension 180 is in a range of about 5 nm to about 8 nm (e.g., about 6.5 nm).It is understood that the dimension 170 helps to define a physical gate length of the HGAA transistor.

[0017] With reference to the Fig. 2A-2B, an etching process 200 is applied to the semiconductor structure 100. During the etching process 200, the spacers 140 and the dummy gate stack 105 protect the underlying layers from being etched. The etching process 200 selectively removes portions of the semiconductor layer 110 that are vertically aligned with the openings 150, while leaving the semiconductor layer 108 substantially unetched. As a result of the etching process 200, gaps or cavities 210 are formed in place of the portions of the semiconductor layer 110 that are etched away. The gaps / cavities 210 are eventually filled with an epitaxially grown doped semiconductor material so that they can serve as the source / drain of HGAA transistors. This will be described in more detail below.

[0018] With reference to Fig. 2B, the gaps or cavities 210 each have a horizontal dimension (measured in the X-direction) 230 that is substantially equal to the horizontal dimension 160 that defines the width of each of the openings 150. At the same time, the semiconductor layer 110 has a horizontal dimension 250. In some embodiments, the horizontal dimension 250 is in a range between about 20 nm and about 30 nm.

[0019] In some embodiments, the etching process 200 may comprise a selective wet etching process. The selective wet etching process may use a hydrofluoric acid (HF) etchant or an NH4OH etchant. In an embodiment where the semiconductor layers 110 comprise SiGe and the semiconductor layers 108 comprise Si, the selective removal of the SiGe layers 110 may comprise a SiGe oxidation process (to convert the SiGe to SiGeOx) followed by a SiGeOx removal. The SiGe oxidation process may include forming and patterning various masking layers so that the oxidation is limited to the SiGe layers 110. In other embodiments, the SiGe oxidation process is a selective oxidation due to the different compositions of the semiconductor layers 110 and 108.In some examples, the SiGe oxidation process may be performed by subjecting structure 100 to a wet oxidation process, a dry oxidation process, or a combination thereof. Thereafter, the oxidized semiconductor layers (comprising SiGeOx) are removed using an etchant, such as NH4OH or diluted HF. In various embodiments, semiconductor layers 110 and 108 have different oxidation rates and / or different etch selectivity, enabling the selective removal of semiconductor layers 110 by etching.

[0020] Referring to the Fig. 3A-3B, after the etching process 200 has been performed, a lateral etching process 300 is applied to the semiconductor structure 100 to etch the semiconductor layer 110 laterally (e.g., horizontally in the X-direction). This lateral etching process 300 may also be referred to as a proximity push process. In some embodiments, the extent of the lateral etching (or the amount of the semiconductor layer 110 that is etched away) may be configured by controlling an etching time of the lateral etching process 300. In some embodiments, the etching process 300 is an isotropic etching process. In some embodiments, the etching process 300 is performed using wet etching or dry etching with low (e.g., <0.1 volts) or no vertical bias.

[0021] As a result of the lateral etching process 300, the Fig. 2B are converted into gaps / cavities 210A (e.g., enlarged laterally / horizontally), as shown in Fig. 3B. The laterally enlarged gaps / cavities 210A each have a horizontal dimension 230A (measured in the X-direction). Compared to the horizontal dimension 230 of the gaps / cavities 210, the horizontal dimension 230A of the enlarged gaps / cavities 210A is wider (in the X-direction) by a distance 240 on each side (the left and right sides). The distance 240 may also be referred to as a proximity push. In some embodiments, the distance 240 is greater than 0, but smaller than the thickness / horizontal dimension 180 of the gate spacer 140. For example, the distance 240 may be in a range greater than about 2 nm but less than about 6 nm, for example, about 4 nm.

[0022] The increased dimension 230A due to the lateral etching process 300 means that the dimension 250 of the semiconductor layer 110 is reduced to the dimension 250A. While the dimension 170 of the dummy gate stack (above with reference to Fig. 1B) defines the physical gate length of the transistor, dimension 250A corresponds to an electrical length of the channel of the HGAA transistor formed by semiconductor structure 100. Since dimension 250A can be adjusted by controlling the extent of lateral etching of semiconductor layer 110 by lateral etching process 300, the electrical length of the channel can also be adjusted accordingly. This aspect of the present disclosure is described in more detail below.

[0023] With reference to the Fig. 4A-4B, an etching process 400 is applied to the semiconductor structure 100. In some embodiments, the etching process 400 is configured to have low etch selectivity or no etch selectivity. As a result of the etching process 400, some portions of the semiconductor layer 108 surrounding the gaps / cavities 210A are thinned. The remaining portions of the semiconductor layer 108 surrounding the gaps / cavities 210A may be referred to as nanowires 108A. The nanowires 108A have reduced dimensions (measured in the Z-direction) compared to the portion of the semiconductor layer 108 disposed below the dummy gate stack, which is not affected by the etching process 400. As such, the etching process 400 may also be referred to as a nanowire shrinkage process.The nanowires 108A may serve as part of the source / drain (S / D) of the HGAA transistors, and regions corresponding to the locations of the nanowires 108A may be referred to as S / D regions 410. Furthermore, the remainder of the semiconductor layers 108 may serve as the channels of the HGAA transistors.

[0024] Referring to the Fig. 5A-5B, an epitaxial growth process 500 is performed to grow semiconductor elements 510 in the S / D regions 410 of the semiconductor structure 100. In some embodiments, the epitaxial growth process 500 comprises a molecular beam epitaxy (MBE) process or a chemical vapor deposition process and / or other suitable epitaxial growth processes. In some further embodiments, the semiconductor elements 510 are doped in situ or ex situ with an n-type dopant or a p-type dopant. For example, in some embodiments, the semiconductor elements 510 comprise silicon germanium (SiGe) doped with boron to form S / D features for a PFET. In some embodiments, the semiconductor elements 510 comprise silicon doped with phosphorus to form S / D features for an NFET. In various embodiments, arsenic and antimony are also used as dopants in the S / D features.To further enhance these embodiments, the semiconductor elements 510 may comprise Ge with a molar fraction ranging from about 10% to about 70%. In certain embodiments, the semiconductor elements 510 are heavily doped to form an ohmic contact with a later-formed S / D contact metal.

[0025] As a result of the epitaxial growth process 500, the semiconductor elements 510 fill the gaps / cavities 210A formed in Fig. 4B. The semiconductor elements 510 each enclose a corresponding one of the nanowires 108A (e.g., by approximately 360 degrees in the direction shown in Fig. 5A). For example, the semiconductor elements 510 may be in direct physical contact with the nanowires 108A on all four sides (in the embodiment shown, where the nanowires 108A each have a square shape in a cross-sectional side view). In some embodiments, a thickness 520 of the semiconductor elements 510 ranges from a few nanometers to several tens of nanometers.

[0026] In one embodiment, semiconductor elements 510 have the same material composition as semiconductor layer 108 (and nanowires 108A). For example, semiconductor elements 510 and semiconductor layer 108 both comprise silicon. In some alternative embodiments, semiconductor elements 510 and 108 may comprise different materials or compositions. In various embodiments, semiconductor elements 510 may comprise a semiconductor material such as silicon or germanium, a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, an alloy semiconductor such as GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP, or combinations thereof.

[0027] The semiconductor elements 510 and the nanowires 108A may jointly serve as the S / D features for the semiconductor structure 100. In some embodiments, the semiconductor elements 510 and the nanowires 108A may comprise the same type of dopant (e.g., both n-doped or both p-doped), but the dopant concentration in the semiconductor elements 510 may be higher than in the nanowires 108A. Alternatively, the semiconductor elements 510 and the nanowires 108A may comprise the same type of dopant but may have different doping species.

[0028] As mentioned above with reference to Fig. 3B, the electrical length (e.g., the horizontal dimension 250A of the semiconductor layer 110 below the gate stack) of the channel may be adjusted by the lateral etching process 300. According to various aspects of the present disclosure, different regions of the semiconductor structure 100 may be configured to have different electrical lengths. This will be described below with reference to the Fig. 6-10, which are schematic fragmentary cross-sectional side views (in the YZ plane, similar to the Fig. 1B-5B) of an embodiment of the semiconductor structure 100 in various stages of manufacture. Some of the manufacturing processes described in the Fig. 6-10 were described above with reference to the Fig. 1A-5A and 1B-5B. For clarity and consistency, similar elements are described in the Fig. 6-10 same as in the Fig. 1A-5A and 1B-5B, as appropriate.

[0029] With reference to Fig. 6, the semiconductor structure 100 includes the plurality of semiconductor layers 108 and 110 arranged alternately or interleaved in a vertical direction (e.g., Z-direction). A plurality of dummy gate stacks 105 are formed over the topmost semiconductor layer 108. The dummy gate stacks 105 each include a dielectric layer 120 and a polysilicon layer 130 formed over the dielectric layer 120. Gate spacers 140 are formed on sidewalls of the dielectric layer 120 and the polysilicon layer 130. The gate spacers 140 may also be considered part of the dummy gate stacks 105 in some embodiments. As described above, the polysilicon layer 130 will later undergo a gate replacement process to be replaced with a metal gate layer. In some embodiments, the dielectric layer 120 is also replaced with a high-k dielectric through the gate replacement process.

[0030] Some of the dummy gate stacks 105 are located in one region 610 of the semiconductor structure 100, while other dummy gate stacks 105 are located in another region 620 of the semiconductor structure 100. In some embodiments, the region 610 comprises a normal threshold voltage (SVt) region, while the region 620 has a high threshold voltage (HVt) region. Compared to transistors located in the SVt region 610, transistors located in the HVt region 620 have a higher threshold voltage (Vt) and consume less power. Therefore, the transistors in the HVt region may be suitable for power-critical applications.

[0031] With reference to Fig. 7, a patterned photoresist layer 640 is formed in region 620 over the topmost semiconductor layer 108 and over the dummy gate stacks 105. Forming the patterned photoresist layer 640 may include processes such as photoresist deposition, exposure, post-exposure baking, and development. The patterned photoresist layer 640 leaves an opening in region 610, exposing the dummy gate stacks 105 and the semiconductor layer 108 in the region 610.

[0032] While the patterned photoresist layer 640 serves as an etch mask, the etching processes 650 are performed to etch the semiconductor layers 110 in the region 610. For example, the etching processes 650 include the etching process 200 described above with reference to the Fig. 2A and Fig. 2B, which is performed here to selectively remove portions of the semiconductor layer 110 in the region 610, thereby forming gaps / cavities in the region 610. The etching processes 650 also include the lateral etching process 300 described above with reference to the Fig. 3A-3B, which is performed here to expand the gaps / cavities inward to form enlarged gaps / cavities 210A.

[0033] The remaining segments 110A of the semiconductor layer 110 below the dummy gate stack 105 in the region 610 each have a horizontal dimension 660 (measured in the X-direction). As described above, the value for the horizontal dimension 660 can be configured by adjusting the parameters of the lateral etch process 300, for example, by controlling the etch time. As an example, as the etch time of the lateral etch process 300 increases, the gaps / cavities 210A become wider (due to more lateral etching) and the dimension 660 shrinks. Again, the dimension 660 corresponds to the effective electrical length of the channel of the HGAA transistor in the region 610.

[0034] Since the patterned photoresist layer 640 serves as a protective mask during the etching process 650, the part of the semiconductor layer 110 located in the region 620 is Fig. 7 shown manufacturing stage is essentially unaffected.

[0035] With reference to Fig. 8, a patterned photoresist layer 670 is formed in the region 610 over the top semiconductor layer 108 and over the dummy gate stacks 105. Forming the patterned photoresist layer 670 may include processes such as photoresist deposition, exposure, post-exposure baking, and development. The patterned photoresist layer 670 leaves openings in the region 620 and exposes the dummy gate stacks 105 and the semiconductor layer 108 in the region 620.

[0036] While the patterned photoresist layer 670 serves as an etch mask, etching processes 680 are performed to etch the semiconductor layers 110 in the region 620. For example, the etching processes 680 include the etching process 200 described above with reference to the Fig. 2A and Fig. 2B, which is performed here to selectively remove portions of the semiconductor layer 110 in the region 620, thereby forming gaps / cavities 210 in the region 620.

[0037] The remaining segments 110B of the semiconductor layer 110 beneath the dummy gate stacks 105 in the region 620 each have a horizontal dimension 690 (measured in the X-direction). As described above, the value for the horizontal dimension 690 may be configured by adjusting the parameters of the lateral etch process 300, e.g., by controlling the etch time. As an example, if the etch time of the lateral etch process 300 is increased, the gaps / cavities 210A may become wider (due to more lateral etching), and the dimension 690 may shrink. Again, the dimension 690 corresponds to the effective electrical length of the channel of the HGAA transistor in the region 620.

[0038] It is understood that although the etching processes 680 in the Fig. 8 does not include the lateral etching process 300 described above with reference to the Fig. 3A-3B (which could be performed to increase the gaps / cavities 210 inward), the lateral etch process 300 may nevertheless be performed as part of the etch process 680 in alternative embodiments, if necessary. For example, optionally performing the lateral etch process 300 would provide strong control over the value of dimension 690.

[0039] With reference to Fig. 9, the epitaxial growth process 500 described above with reference to the Fig. 5A-5B is applied to the semiconductor structure 100 to epitaxially grow the semiconductor elements 510 to fill the gaps / cavities 210 / 210A. In some embodiments, it takes a longer time to fill the gaps 210A than the gaps 210. In embodiments where the same S / D epitaxy process is used for both gaps 210A and 210, the epitaxial material grown in the gaps 210 would be larger than the epitaxial material grown in the gaps 210A. This size difference is a result of the new process procedures described herein and may be an important characteristic of devices fabricated according to the methods of the present disclosure. As described above with reference to the Fig. As described in Figures 5A-5B, the semiconductor elements 510 each enclose a corresponding one of the semiconductor layers 108, for example, 360 degrees circumferentially. Again, the semiconductor elements 510 (together with the portions of the semiconductor layer 108 that are enclosed) may serve as the S / D features for the semiconductor structure 100.

[0040] Although it is in Fig. 9 is not explicitly shown in detail, it is understood that the etching process 400 described above with reference to the Fig. 4A and Fig. 4B, may also be performed to thin or reduce the size of portions of the semiconductor layer between the gaps / cavities 210 / 210A before performing the epitaxial growth process 500.

[0041] With reference to Fig. 10, a gate replacement process 700 is applied to the semiconductor structure 100 to replace the dummy gate stacks 105 and the underlying semiconductor layers 100 with high-k metal gates 720. As part of the gate replacement process 700, the polysilicon layer 130 (and the dielectric layer 120, if it is a dummy gate oxide) is removed, for example, by suitable etching techniques. Portions of the semiconductor layer 110 and 110A disposed beneath the dummy gate stacks 105 are also removed. Removing the polysilicon layer 130 and the dielectric layer 120 forms openings defined by the gate spacers 140. These openings are filled with high-k metal gates 720, each comprising a high-k gate dielectric and a metal gate electrode.

[0042] Fig. Figure 11 shows a more detailed cross-sectional view of the replacement high-k metal gate 720. The cross-sectional view is taken along the ZX plane. A dielectric isolation structure 730 is formed around the gate spacers 140, for example, before removing the dummy gate stacks. After removing the polysilicon layer 130 and the dielectric layer 120, the gate spacers 140 (together with the dielectric isolation structure 730) define an opening into which the high-k metal gate 720 is filled. A high-k dielectric 740 is formed, for example, in the opening. As described above, the high-k dielectric layer 740 may comprise a high-k material (e.g., having a higher dielectric constant than silicon oxide) such as hafnium oxide, zirconium oxide, lanthanum oxide, titanium oxide, yttrium oxide, strontium titanate, other suitable metal oxides, or combinations thereof.

[0043] A work function metal layer 750 may be formed over the high-k dielectric layer 740. The work function metal layer 750 may include work function metals configured to adjust a work function of a transistor. The work function metal layer 750 may be a p-type work function metal layer or an n-type work function metal layer. The p-type work function metal layer includes a metal selected, without limitation, from the group consisting of titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten, platinum, or combinations thereof. The n-type work function metal layer includes a metal selected, without limitation, from the group consisting of titanium, aluminum, tantalum carbide, tantalum carbide nitride, tantalum silicon nitride, or combinations thereof. The p- or n-work function metal layers may comprise a plurality of layers and may be deposited by CVD, PVD and / or other suitable processes.

[0044] A fill metal 760 is formed over the work function metal layer 750. The fill metal 760 may serve as the electrically conductive main portion of the metal gate electrode. The fill metal 760 may comprise aluminum, tungsten, cobalt, copper, and / or other suitable materials and may be formed by CVD, PVD, plating, and / or other suitable processes.

[0045] The high-k metal gates that fill the openings (formed by removing the semiconductor layer 110 / 110A) also include the high-k dielectric layer 740, the work function metal layer 750, and the fill metal 360. As shown in Fig. As shown in Figure 11, the work function metal layer 750 circumferentially encloses the fill metal 760, and the high-k dielectric layer 740 further circumferentially encloses the work function metal layer 750. At the same time, the portions of the semiconductor layer 108 are also enclosed by the high-k metal gates (which include the high-k dielectric layer 740 and the metal layers 750-760). These portions of the semiconductor layer 108 serve as the channels of the transistor. The semiconductor structure 100 includes a plurality of these vertically "stacked" high-k metal gates, and thus, the semiconductor structure 100 is a stacked horizontal gate all-around (S-HGAA) device.

[0046] If you turn again Fig. 10, it can be seen that the high-k metal gate structures 720A formed in the region 610 have different lateral dimensions than the high-k metal gate structures 720B formed in the region 620. In particular, the high-k metal gate structures 720A formed in the region 610 have the lateral dimension 660 (measured in the X-direction), while the high-k metal gate structures 720B formed in the region 620 have the lateral dimension 690 (measured in the X-direction). The lateral dimension 690 is larger or smaller than the lateral dimension 660. For example, in the case of the Fig. In the embodiment shown in Figure 10, the lateral dimension 690 may, in some embodiments, be approximately 5-10 nm larger than the lateral dimension 660. There is a fixed ratio between the lateral dimension 690 and the lateral dimension 660. In some embodiments, the ratio is in a range between approximately 1.5 and approximately 2.

[0047] As described above, the difference in lateral dimensions 660 and 690 can be configured by carefully controlling the process parameters of etching processes 650 and / or 680. Since lateral dimension 660 corresponds to the effective electrical length of the channel for the HGAA transistor in region 610 and lateral dimension 690 corresponds to the effective electrical length of the channel for the HGAA transistor in region 620, it can be seen that semiconductor structure 100 may have a different effective electrical length for different regions, even though the physical gate lengths (defined by the size of the dummy gate stacks) are substantially the same.

[0048] Fig. 12 is a flowchart illustrating a method 800 for fabricating a semiconductor structure, such as a GAA device. The method 800 includes a step 810 of providing a semiconductor structure comprising a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers. The first and second semiconductor layers have different material compositions.

[0049] The method 800 includes a step 820 of forming a dummy gate stack over a top first semiconductor layer. In some embodiments, forming the dummy gate stack comprises forming a plurality of dummy gate stacks in a first region and a second region of the semiconductor structure. In some embodiments, the first region is a normal threshold voltage (SVt) region and the second region is a high threshold voltage (HVt) region.

[0050] The method 800 includes a step 830 of performing a first etching process to remove portions of the second semiconductor layer that are not disposed beneath the dummy gate stack, thereby forming a plurality of cavities. The first etching process has etch selectivity with respect to the first semiconductor layer and the second semiconductor layer. In some embodiments, the etch selectivity with respect to the first semiconductor layer and the second semiconductor layer is configured such that the first etching process removes the portions of the second semiconductor layer without removing portions of the first semiconductor layer.

[0051] The method 800 includes a step 840 of performing a second etching process to enlarge the cavities. In some embodiments, the second etching process is performed to enlarge a horizontal dimension of each of the cavities. In some embodiments, the first etching process and the second etching process are performed such that cavities in the first region and cavities in the second region have different horizontal dimensions. In some embodiments, the second etching process is performed in the first region but not in the second region.

[0052] In some embodiments, the first semiconductor layers each comprise a silicon layer and the second semiconductor layers each comprise a silicon-germanium layer.

[0053] It is understood that additional methods may be performed before, during, or after steps 810-840. For example, method 800 may include a step of epitaxially growing a third semiconductor layer in the enlarged cavities. As another example, method 800 may include a step of replacing the dummy gate stack with a gate structure having a high-k gate dielectric and a metal gate electrode. In some embodiments, replacing the dummy gate stack includes replacing portions of the second semiconductor layer disposed beneath the dummy gate with a plurality of gate structures having a high-k gate dielectric and a metal gate electrode. In some embodiments, for each of the gate structures replacing the portion of the second semiconductor layer, the high-k gate dielectric circumferentially surrounds the metal gate electrode.As further examples, the method 800 may include steps of forming contact openings, contact metal, as well as various contacts, vias, wires, and multi-layer interconnect features (e.g., metal layers and interlayer dielectrics) to connect the various features to form a functional circuit that may include one or more multi-gate devices.

[0054] Based on the above description, it is apparent that the embodiments of the present disclosure offer advantages over conventional semiconductor devices. However, it should be understood that no particular advantage is required, that other embodiments may offer other advantages, and that not all advantages are necessarily disclosed here.

[0055] One advantage is that by configuring different effective electrical lengths for the channel, the threshold voltage Vt can be adjusted with greater flexibility. Specifically, as semiconductor device sizes shrink, transistor channels become shorter, leading to various problems, particularly for GAA devices. For example, GAA devices have smaller depletion regions than conventional planar devices or conventional FinFET devices. As a result, the Vt implant dosage may need to be higher than in conventional devices. However, the heavy doping can cause a reduction in mobility, which is undesirable.Furthermore, GAA devices have a smaller channel volume than conventional devices because the channels for GAA devices consist of a plurality of nanowires (rather than a single block of material as in conventional devices). As such, doping the nanowires can result in some of these nanowire channels receiving a significantly higher amount of dopant than some of the other nanowires. This leads to poorer doping random fluctuations for GAA devices. For these reasons described above, it is difficult to tune the Vt for GAA devices through implantation / doping.

[0056] In comparison, the present disclosure allows for adjustment of the threshold voltage by adjusting the effective electrical length of the channel of the transistor. For example, the method described above with reference to Fig.The lateral etching process described in Figure 3B can be configured to adjust the lateral dimension of the high-k metal gate stack, which corresponds to adjusting the electrical length for the channel. This allows the threshold voltage Vt to be configured accordingly.

[0057] Furthermore, the present disclosure allows for different effective gate lengths to be provided for different regions. For example, one gate length may be provided for a high Vt region, while a different gate length may be provided for a normal Vt region. This possibility further increases the flexibility of the semiconductor structure fabricated according to the present disclosure. Furthermore, this possibility also means that it is not necessary to arrange a dummy polysilicon between the high Vt region and the normal Vt region. This, in turn, leads to a reduction in cell size. Further advantages include the elimination of doping random errors in GAA devices, since the present disclosure no longer requires Vt implantation.

[0058] One embodiment of the present disclosure includes a method of fabricating a GAA device. A semiconductor structure is provided that includes a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers. The first and second semiconductor layers have different material compositions. A dummy gate stack is formed over an uppermost first semiconductor layer. A first etching process is performed to remove portions of the second semiconductor layer not located beneath the dummy gate stack, thereby forming a plurality of cavities. The first etching process has etch selectivity with respect to the first semiconductor layer and the second semiconductor layer. Thereafter, a second etching process is performed to enlarge the cavities.

[0059] Another embodiment of the present disclosure includes a method for fabricating a GAA device. A semiconductor structure is provided comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers. The first and second semiconductor layers have different material compositions and are arranged alternately in a vertical direction. A plurality of dummy gate stacks is formed over an uppermost first semiconductor layer. Portions of the second semiconductor layer in a first region of the semiconductor structure are removed, thereby forming a plurality of first gaps in place of the removed portions of the second semiconductor layer in the first region. The first gaps are enlarged horizontally via a lateral etching process.Thereafter, portions of the second semiconductor layer are removed in a second region of the semiconductor structure, forming a plurality of second gaps in place of the removed portions of the second semiconductor layer in the second region. The remaining portions of the second semiconductor layer in the first region have different horizontal dimensions than the remaining portions of the second semiconductor layer in the second region.

[0060] Yet another embodiment of the present disclosure includes a semiconductor structure. The semiconductor structure includes a plurality of nanowires each extending in a first direction. The nanowires are stacked one on top of the other in a second direction perpendicular to the first direction. The semiconductor structure includes a plurality of first gate structures and second gate structures, each enclosing a respective one of the nanowires. The first gate structures each have a first dimension in the first direction. The second gate structures each have a second dimension in the first direction, wherein the first dimension is greater or smaller than the second dimension.

Claims

[1] Method comprising: Providing a semiconductor structure (100) comprising a plurality of first semiconductor layers (108) interleaved with a plurality of second semiconductor layers (110), wherein the first and second semiconductor layers have different material compositions; Forming a dummy gate stack (105) over a top first semiconductor layer (108); Performing a first etching process (200) to remove portions of the second semiconductor layer (110) that are not located under the dummy gate stack, thereby forming a plurality of cavities (210), wherein the first etching process has etch selectivity with respect to the first semiconductor layer (108) and the second semiconductor layer (110); and then performing a second etching process (300) to enlarge the cavities (210); wherein the second etching process (300) is performed to increase a horizontal dimension (230A) of each of the cavities (210), wherein forming the dummy gate stack (105) comprises forming a plurality of dummy gate stacks (105) in a first region (610) and a second region (620) of the semiconductor structure, and wherein the first etching process (200) and the second etching process (300) are carried out such that cavities (210) in the first region (610) and cavities in the second region (620) have different horizontal dimensions. [2] The method of claim 1, wherein the etch selectivity with respect to the first semiconductor layer (108) and the second semiconductor layer (110) is configured such that the first etching process (200) removes the portions of the second semiconductor layer (110) without removing portions of the first semiconductor layer (110). [3] The method of claim 1 or 2, wherein the horizontal dimension (230A) is increased on both sides of each of the cavities (210A). [4] Method according to one of the preceding claims, wherein: the first semiconductor layers (108) each comprise a silicon layer; and the second semiconductor layers (110) each comprise a silicon-germanium layer. [5] The method of any preceding claim, further comprising: epitaxially growing (500) a third semiconductor layer (510) in the enlarged cavities. [6] The method of any preceding claim, further comprising: replacing the dummy gate stack (105) with a gate structure (720) having a high-k gate dielectric (740) and a metal gate electrode (760). [7] The method of claim 6, wherein replacing the dummy gate stack (105) comprises replacing portions of the second semiconductor layer (110) disposed beneath the dummy gate with a plurality of gate structures (720A) having a high-k gate dielectric and a metal gate electrode. [8] The method of claim 7, wherein for each of the gate structures (720A) replacing the portion of the second semiconductor layer (110), the high-k gate dielectric (740) circumferentially encloses the metal gate electrode (760). [9] Method according to one of the preceding claims, wherein the second etching process (200) is carried out in the first region (610) but not in the second region (620). [10] Method according to one of the preceding claims, wherein: the first region (610) is a normal threshold voltage region; and the second region (629) is a high threshold voltage region. [11] Method comprising: Providing a semiconductor structure (100) comprising a plurality of first semiconductor layers (108) and a plurality of second semiconductor layers (110), wherein the first and second semiconductor layers have different material compositions and are arranged alternately in a vertical direction; Forming a plurality of dummy gate stacks (105) over a top first semiconductor layer (108); Removing portions of the second semiconductor layer (110) in a first region of the semiconductor structure (610), thereby forming a plurality of first gaps (210) in place of the removed portions of the second semiconductor layer (110) in the first region; horizontally enlarging the first gaps (210) by a lateral etching process (200); and subsequently removing portions of the second semiconductor layer (110) in a second region (620) of the semiconductor structure, thereby forming a plurality of second gaps in place of the removed portions of the second semiconductor layer in the second region (620), wherein the remaining portions of the second semiconductor layer (110) in the first region (610) have different horizontal dimensions than the remaining portions (620) of the second semiconductor layer in the second region. [12] The method of claim 11, further comprising: Performing a gate replacement process to replace the dummy gates (105) and the remaining portions of the second semiconductor layer (110) in both the first region (610) and the second region (620) with gate structures (720) each comprising a high-k gate dielectric (740) and a metal gate electrode (760).

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