Display panel, shift register circuit and control method therefor

Abstract

A sliding register circuit, comprehensive: a first transistor (T1) which is configured to be switched on in response to a voltage signal at a first node (N1) so that an input signal (IN) is supplied to a second node (N2); wherein a control end of the first transistor (T1) is electrically connected to the first node (N1) and a first end of the first transistor (T1) receives the input signal (IN) and a second end of the first transistor (T1) is electrically connected to the second node (N2); a second transistor (T2) configured to be switched on in response to a first clock signal (CK) so that the input signal (IN) is supplied to the first node (N1), wherein a control end of the second transistor (T2) receives the first clock signal (CK), a first end of the second transistor (T2) receives the input signal (IN), and a second end of the second transistor (T2) is electrically connected to the first node (N1); a third transistor (T3) which is configured to be switched on in response to the first clock signal (CK) so that a second voltage signal (VGL) is supplied to the second node (N2), wherein a control end of the third transistor (T3) receives the first clock signal (CK), a first end of the third transistor (T3) receives the second voltage signal (VGL) and a second end of the third transistor (T3) is electrically connected to the second node (N2); a fourth transistor (T4) which is configured to be switched on in response to a voltage signal at the second node (N2), so that the first voltage signal (VGH) is supplied to a third node (N3);-, wherein a control end of the fourth transistor (T4) is electrically connected to the second node (N2) and a first end of the fourth transistor (T4) receives the first voltage signal (VGH); a fifth transistor (T5) which is configured to be switched on in response to a second clock signal (CK2) so that a voltage signal at the third node (N3) is supplied to the first node (N1); wherein a control end of the fifth transistor (T5) receives the second clock signal (CK2), a first end of the fifth transistor (T5) is electrically connected to the third node (N3) and a second end of the fifth transistor (T5) is electrically connected to the first node (N1); a sixth transistor (T6) which is configured to be switched on in response to a voltage signal at the second node (N2) so that the first voltage signal (VGH) is supplied to a signal output terminal (OUT), wherein a control end of the sixth transistor (T6) is electrically connected to the second node (N2), a first end of the sixth transistor (T6) receives the first voltage signal (VGH) and a second end of the sixth transistor (T6) is electrically connected to the signal output terminal (OUT); a seventh transistor (T7) configured to be turned on in response to a voltage signal at a fourth node (N4) such that the second clock signal (CK2) is supplied to the signal output terminal (OUT), wherein a voltage at the fourth node (N4) is positively correlated with a voltage at the first node (N1), wherein a control end of the seventh transistor (T7) is electrically connected to the fourth node (N4), a first end of the seventh transistor (T7) receives the second clock signal (CK2), and a second end of the seventh transistor (T7) is electrically connected to the signal output terminal (OUT); a first capacitor (C1) which is electrically connected between the fourth node (N4) and the signal output terminal (OUT); and a second capacitor (C2) which is electrically connected between the second node (N2) and the first voltage signal (VGH), the shift register circuit being designed to operate in five stages, comprising: In a first stage, the voltage signal at the second node (N2) is maintained by the second capacitor (C2). the fourth transistor (T4) and the sixth transistor (T6) are switched on as a result of the voltage signal at the second node (N2), the fifth transistor (T5) is switched on as a result of the second clock signal (CK2) and that the first voltage signal (VGH) is transmitted through the sixth transistor (T6) to the signal output terminal (OUT) and is transmitted proportionally through the fourth transistor (T4) and the fifth transistor (T5) to the first node (N1); in a second stage to control that the second transistor (T2), the third transistor (T3) are switched on as a result of the first clock signal (CK), the first voltage signal (VGH) is transmitted through the second transistor (T2) to the first node (N1) and stored in the first capacitor (C1), the first transistor (T1) is switched on as a result of the voltage signal at the first node (N1), the first voltage signal (VGH) is transmitted through the first transistor (T1) to the second node (N2), the second voltage signal (VGL) is transmitted through the third transistor (T3) to the second node (N2), the sixth transistor (T6) is switched on as a result of the voltage signal at the second node (N2), and the first voltage signal (VGH) is transmitted through the sixth transistor (T6) to the signal output terminal (OUT); in a third stage to control that the voltage signal at the first node (N1) is maintained by the first capacitor (C1), the first transistor (T1) and the seventh transistor (T7) are switched on as a result of the voltage signal at the first node (N1), the first voltage signal (VGH) is transmitted through the first transistor (T1) to the second node (N2), and the second clock signal (CK2) is transmitted through the seventh transistor (T7) to the signal output terminal (OUT); in a fourth stage to control that the second transistor (T2) and the third transistor (T3) are switched on as a result of the first clock signal (CK), the first voltage signal (VGH) is transmitted through the second transistor (T2) to the first node (N1), the second voltage signal (VGL) is transmitted through the third transistor (T3) to the second node (N2) and is stored in the second capacitor (C2), the sixth transistor (T6) is switched on as a result of the voltage signal at the second node (N2), and the first voltage signal (VGH) is transmitted through the sixth transistor (T6) to the signal output terminal (OUT); and in a fifth stage to control that the voltage signal at the second node (N2) is maintained by the second capacitor (C2), the fourth transistor (T4) and the sixth transistor (T6) are switched on as a result of the voltage signal at the second node (N2), the fifth transistor (T5) is switched on as a result of the second clock signal (CK2), and the first voltage signal (VGH) is transmitted through the sixth transistor (T6) to the signal output terminal (OUT) and is partially transmitted through the fourth transistor (T4) and the fifth transistor (T5) to the first node (N1).

Description

BACKGROUND

[0001] Shift register circuits can be configured to form a gate-electrode drive circuit. The gate-electrode drive circuit can comprise N cascaded shift register circuits. In particular, an input signal of an (m+1)th shift register circuit is an output signal of an mth shift register circuit, where m < N.

[0002] Fig. Figure 1A shows an existing circuit diagram of a shift register circuit. Fig. Figure 1B shows a timing diagram of a shift register circuit according to Fig. 1A. Referring to Fig. 1A and Fig. At time t1, node 1B has a clock signal CK and an input signal IN at low voltage levels. The low-voltage level signals are written to nodes N1 and N2, respectively, and a high-voltage level is output. At time t2, the input signal IN changes to a high voltage level. The high-voltage level signal is written to node N2, and node N1 retains a low voltage level.

[0003] Furthermore, when a falling edge of a second clock signal CKB arrives, a low-voltage level is output, and the voltage level at node N1 is further reduced due to the coupling of a capacitor C2, thus ensuring a complete output of the low-voltage level. At time t3, the first clock signal CK changes back to a low-voltage level. The low-voltage level is written to node N2, and a high voltage is written to node N1. Such a voltage relationship can be maintained to ensure the output of a high-voltage level. In such a circuit, the first clock signal CK and the second clock signal CKB behave inversely to each other.

[0004] At the in Fig. In the circuit shown in Figure 1A, nodes N1 and N2 do not have a continuous voltage supply to ensure a stable voltage level. After time t3 ends, the circuit is often expected to output a constant high-voltage signal. However, there is parasitic capacitance (also known as stray capacitance) between the gate electrode (node ​​N1) and the drain electrode (terminal CKB) of transistor M4, and the CKB signal coupled to the drain electrode of transistor M4 is a square wave that changes abruptly and frequently. The frequent changes in the CKB signal produce a corresponding change in the voltage level at node N1. Consequently, transistor M4 can be inadvertently switched on when the CKB signal is at a low voltage level, making the output signal unstable.

[0005] US Patent 2014 / 0375616A1 discloses a stepped switching system and an organic light-emitting display incorporating it.

[0006] The disclosed display field, the disclosed shift register circuit, and the disclosed control method therefor are therefore aimed at solving at least the sub-problems set out above, or other problems. It should be noted that the information disclosed in the aforementioned background section is used only to enhance the understanding of the background of the present disclosure and may therefore include existing information that is well known to the average person skilled in the art. BRIEF SUMMARY OF THE REVELATION

[0007] The problem is solved by the combination of features in the independent patent claims. Advantageous embodiments are defined in the dependent patent claims.

[0008] One aspect of the present disclosure provides a shift register circuit. The shift register circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor, and a second capacitor. The first transistor is configured to be turned on in response to a voltage signal at a first node, so that an input signal is delivered to a second node. The second transistor is configured to be turned on in response to a first clock signal, so that the input signal is delivered to the first node. The third transistor is configured to be turned on in response to the first clock signal, so that a load signal is delivered to a second node.The fourth transistor is configured to turn on in response to a voltage signal at the second node, so that the first voltage signal is delivered to a third node. The fifth transistor is configured to turn on in response to a second clock signal, so that a voltage signal at the third node is delivered to the first node. The sixth transistor is configured to turn on in response to the voltage signal at the second node, so that the first voltage signal is delivered to a signal output terminal. The seventh transistor is configured to turn on in response to a voltage signal at a fourth node, so that the second clock signal is delivered to the signal output terminal, with the voltage at the fourth node being positively correlated with the voltage at the first node.The first capacitor is electrically connected between the fourth node and the signal output terminal, and the second capacitor is electrically connected between the second node and the first voltage signal.

[0009] Another aspect of the present disclosure provides a control method for a shift register circuit. The shift register circuit comprises a first transistor configured to be switched on in response to a voltage signal at a first node to provide an input signal to a second node; a second transistor configured to be switched on in response to a first clock signal to provide the input signal to the first node; a third transistor configured to be switched on in response to the first clock signal to provide a load signal to a second node; a fourth transistor configured to be switched on in response to a voltage signal at the second node to provide a first voltage signal to a third node; and a fifth transistor configured to...a sixth transistor configured to be switched on in response to a second clock signal to supply a voltage signal at the third node to the first node, a seventh transistor configured to be switched on in response to a voltage signal at a fourth node to supply the second clock signal to the signal output terminal, a first capacitor electrically connected between the fourth node and the signal output terminal, and a second capacitor electrically connected between the second node and the first voltage signal.and a voltage at the fourth node is positively correlated with a voltage at the first node. The control method comprises, in a first stage, controlling the second, third, and seventh transistors by the first clock signal, the input signal, and the first voltage signal to be off; controlling the fifth transistor by the second clock signal to be on; and transmitting the first voltage signal through the sixth transistor to the signal output terminal.

[0010] Another aspect of the present disclosure provides a display panel comprising a shift register circuit. The shift register circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor, and a second capacitor. The first transistor is configured to be turned on in response to a voltage signal at a first node, thereby supplying an input signal to a second node. The second transistor is configured to be turned on in response to a first clock signal, thereby supplying the input signal to the first node. The third transistor is configured to be turned on in response to the first clock signal, thereby supplying a load signal to a second node.The fourth transistor is configured to turn on in response to a voltage signal at the second node, thereby supplying a first voltage signal to a third node. The fifth transistor is configured to turn on in response to a second clock signal, thereby supplying a voltage signal at the third node to the first node. The sixth transistor is configured to turn on in response to a voltage signal at the second node, thereby supplying the first voltage signal to a signal output terminal. The seventh transistor is configured to turn on in response to a voltage signal at a fourth node, thereby supplying the second clock signal to the signal output terminal, where a voltage at the fourth node is positively correlated with a voltage at the first node.The first capacitor is electrically connected between the fourth node and the signal output terminal, and the second capacitor is electrically connected between the second node and the first voltage signal.

[0011] Other aspects of the present disclosure can be understood by persons skilled in the field of the present invention in view of the description, claims and drawings of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings, which are included in and form part of the description, illustrate one or more embodiments of the present disclosure and, together with the detailed description, serve to illustrate the fundamentals and implementations of the disclosure. Obviously, the drawings described below correspond only to some embodiments of the present disclosure, and it is possible for the person skilled in the art to derive other drawings from the accompanying drawings without any creative effort. Fig. Figure 1A shows an existing circuit diagram of a shift register circuit; Fig. Figure 1B shows a timing diagram of a shift register circuit according to Fig. 1A; Fig. Figure 2 shows an exemplary circuit diagram of a shift register circuit according to embodiments of the present disclosure; Fig. Figure 3 shows an exemplary timing diagram of a shift register circuit according to Fig. 2; Fig. 4A- Fig. 4E show equivalent circuit diagrams of a shift register circuit according to Fig. 2 during each stage of a tax time sequence according to Fig. 3; Fig. Figure 5 shows another exemplary circuit diagram of a shift register circuit according to embodiments of the present disclosure; Fig. 6 shows another exemplary circuit diagram of a shift register circuit according to embodiments of the present disclosure; Fig. Figure 7 shows a further exemplary circuit diagram of a shift register circuit according to embodiments of the present disclosure; and Fig. Figures 8A-8C show exemplary operating data of a shift register circuit according to embodiments of the present disclosure. DETAILED DESCRIPTION

[0013] Exemplary embodiments are described in more detail below with reference to the accompanying drawings. However, embodiments of the present disclosure can be implemented in many different forms and should not be considered limited to those set forth herein. Rather, these embodiments are specified in such a way as to make the present disclosure more thorough and complete and to fully convey the scope of the exemplary embodiments to the person skilled in the art. The described features, structures, or properties can be combined in any suitable manner in one or more embodiments. Numerous specific details are given in the following description to enable a thorough understanding of embodiments of the present disclosure.However, the person skilled in the art recognizes that technical solutions of the present disclosure can be implemented without one or more of the specific details or with other methods, components, devices, or steps, etc. In other cases, known technical solutions are not shown or described in detail so as not to obscure the aspects of the present disclosure.

[0014] Furthermore, the accompanying drawings of this disclosure are only schematic; identical reference numerals in the drawings denote identical or similar elements, and therefore repeated descriptions are omitted. Certain block diagrams shown in the accompanying drawings are functional units and need not necessarily correspond to independent physical or logical units. These functional units may be implemented by software, one or more hardware modules, or an integrated circuit. These functional units may be implemented in various networks, processor devices, and / or microcontroller devices.

[0015] Exemplary embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. Fig. Figure 2 shows an exemplary circuit diagram of a shift register circuit according to embodiments of the present disclosure. As in Fig. As shown in Figure 2, a shift register circuit 200 can comprise the first to seventh transistors T1 to T7, a first capacitor C1, and a second capacitor C2. Optionally, the shift register circuit 200 can also include an eighth transistor T8.

[0016] More precisely, the first transistor T1 can be switched on in response to a voltage signal at a first node N1. A second transistor T2 can be switched on in response to a first clock signal CK1, thus supplying an input signal IN (also denoted as V(IN)) to the first node N1. A third transistor T3 can be switched on in response to the first clock signal CK1, thus supplying a load signal (e.g., a second voltage signal VGL) to a second node N2. A fourth transistor T4 can be switched on in response to a voltage signal at the second node N2, thus supplying a first voltage signal VGH to a third node N3.

[0017] Furthermore, a fifth transistor T5 can be switched on in response to a second clock signal CK2, thereby supplying a voltage signal at the third node N3 to the first node N1. A sixth transistor T6 can be switched on in response to a voltage signal at the second node N2, thereby supplying the first voltage signal VGH to a signal output terminal OUT. A seventh transistor T7 can be switched on in response to a voltage signal at a fourth node N4, thereby supplying the second clock signal CK2 to the signal output terminal OUT.

[0018] Furthermore, the eighth transistor T8 can be switched on in response to the second voltage signal VGL, thus electrically connecting the first node N1 and the fourth node N4. The voltage at the fourth node N4 can be positively correlated with the voltage at the first node N1. By configuring the eighth transistor T8, the relatively large crossover voltage that occurs during operation of the circuit can be reduced, thereby improving the reliability of the circuit.

[0019] Furthermore, the eighth transistor T8 can implement a circuit protection function. For example, the eighth transistor T8 can be a resistor with a predetermined resistance, and the present disclosure is not limited to this. Optionally, in some embodiments, the first node N1 and the fourth node N4 can be the same node. That is, the eighth transistor T8 does not need to be configured.

[0020] Furthermore, the first capacitor C1 can be electrically connected between the fourth node N4 and the signal output terminal OUT. The second capacitor C2 can be electrically connected to the second node N2 and the first voltage signal VGH.

[0021] More precisely, the first transistor T1 up to the seventh transistor T7 can each comprise a control end, a first end, and a second end. As in Fig. As shown in Figure 2, when represented schematically, the first and second ends of a transistor can be depicted as connected by a plate, and the control end can be depicted as connected to a plate in parallel with the plate connecting the first and second ends. P-type transistors can be represented by a circle connecting the control end to a corresponding plate, while N-type transistors do not have such a circle.

[0022] In one embodiment as in Fig. As shown in Figure 2, the first transistor T1 through the seventh transistor T7 can all be P-type transistors for illustrative purposes. Furthermore, the control end can be a gate electrode of the transistor, the first end can be a source electrode, and the second end can be a drain electrode. Since the source and drain electrodes cannot be strictly distinguished in a thin-film transistor, in some other embodiments the first end can be the drain electrode and the second end can be the drain electrode.

[0023] With reference to Fig. 2. The control end of the first transistor T1 can be electrically connected to the first node N1, the first end of the first transistor T1 can receive the input signal IN, and the second end of the first transistor T1 can be electrically connected to the second node N2. The control end of the second transistor T2 can receive the first clock signal CK1, the first end of the second transistor T2 can receive the input signal IN, and the second end of the second transistor can be electrically connected to the first node N1.

[0024] Furthermore, the control end of the third transistor T3 can receive the first clock signal CK1, the first end of the third transistor T3 can receive a charging signal (e.g., the second voltage signal VGL), and the second end of the third transistor T3 can be electrically connected to the second node N2. The control end of the fourth transistor T4 can be electrically connected to the second node N2, the first end of the fourth transistor T4 can receive the first voltage signal VGH, and the second end of the fourth transistor T4 can be electrically connected to the third node N3 or, optionally, to the first end of the fifth transistor T5.

[0025] Furthermore, the control end of the fifth transistor T5 can receive the second clock signal CK2, the first end of the fifth transistor T5 can be electrically connected to the third node N3 or optionally to the second end of the fourth transistor T4, and the second end of the fifth transistor T5 can be electrically connected to the first node N1. The control end of the sixth transistor T6 can be electrically connected to the second node N2, the first end of the sixth transistor T6 can receive the first voltage signal VGH, and the second end of the sixth transistor T6 can be electrically connected to the signal output terminal OUT. The control end of the seventh transistor T7 can be electrically connected to the fourth node N4, the first end of the seventh transistor T7 can receive the second clock signal CK2, and the seventh transistor T7 can be electrically connected to the signal output terminal OUT.

[0026] Furthermore, the eighth transistor T8 can also comprise a control end, a first end, and a second end. The control end can be the gate electrode of the eighth transistor T8, the first end can be the source electrode of the eighth transistor T8, and the second end can be the drain electrode of the eighth transistor T8. Optionally, the first end can be the drain electrode of the eighth transistor T8 and the second end can be the source electrode of the eighth transistor T8.

[0027] In one embodiment as in Fig. As shown in Figure 2, the eighth transistor T8 can also be a P-type transistor. The control end of the eighth transistor T8 can receive a charging signal (e.g., the second voltage signal VGL), the first end of the eighth transistor T8 can be connected to the first node N1, and the second end of the eighth transistor T8 can be connected to the fourth node N4.

[0028] In one embodiment, the charging signal can be the second voltage signal VGL, and the present disclosure is not limited thereto. For example, in another embodiment, the charging signal can be the first clock signal CK1 or the second clock signal CK2, etc.

[0029] Fig. Figure 3 shows an exemplary control timing sequence 300 of a shift register circuit according to Fig. 2. How n Fig. Figure 3 shows the voltage levels of the input signal IN, the first clock signal CK1, the second clock signal CK2 and the output signal OUT (also referred to as VOUT or V(OUT)) in five steps (t1~t5).

[0030] As in Fig. As shown in Figure 3, in one embodiment, the low-voltage duty cycle of the first clock signal CK1 and the second clock signal CK2 can both be less than 1 / 2, and the first clock signal CK1 and the second clock signal CK2 can differ by 1 / 2 signal cycle. The low-voltage duty cycle (hereinafter referred to as the "duty cycle") can refer to a percentage of the period during which a signal is at a low voltage level. In some other embodiments, the high-voltage duty cycle of the first clock signal CK1 and the second clock signal CK2 can both be less than 1 / 2, and the first clock signal CK1 and the second clock signal CK2 can differ by 1 / 2 signal period. The high-voltage duty cycle can refer to a percentage of the period during which a signal is at a high voltage level.

[0031] In practical applications, because an RC load may be present during circuit operation, the first clock signal CK1 and the second clock signal CK2 may exhibit delays. If the load cycle is 1 / 2 or greater, the clock signal delay can lead to abnormal operation of the circuit. If the number of cascaded shift register circuits in the circuit is relatively large, the entire circuit may fail. Accordingly, embodiments of the present disclosure can configure the duty cycle of the first clock signal CK1 and the second clock signal CK2 such that it is less than or equal to 1 / 2.

[0032] Fig. 4A-Fig. Fig. 4E show equivalent circuit diagrams of a shift register circuit according to Fig. 2 in each stage of a control timing sequence according to Fig. 3. As in Fig. 4A- Fig. As shown in Figure 4E, the first transistor T1 through the eighth transistor T8 can all be P-type transistors. If all transistors (T1-T8) are P-type transistors, the first voltage signal VGH can be a high-voltage level signal, and the second voltage signal VGL can be a low-voltage level signal. Furthermore, a P-type transistor can be turned on when a low voltage level is applied to the control end (i.e., the gate electrode) of the transistor, and can be turned off when a high voltage level is applied to the control end of the transistor.

[0033] Fig. 4A shows an equivalent circuit diagram of a shift register circuit in a first stage t1 of a control timing sequence according to Fig. 3. As in Fig. 4A shown and with reference to Fig. In the first stage, t1, the first clock signal CK1 and the input signal IN are both at a high voltage level, which switches off the second transistor T2 and the third transistor T3. The second clock signal CK2 can be at a low voltage level, which controls the fifth transistor T5 to be switched on. Then, due to the memory function of the second capacitor C2, the second node N2 can maintain a low voltage from a previous point in time, and the first node N1 can maintain a high voltage from a previous point in time. Accordingly, the fourth transistor T4 and the sixth transistor T6 can be continuously switched on.

[0034] Furthermore, the high voltage level of the first voltage signal VGH can be transmitted to the first node N1 via the fourth transistor T4 and the fifth transistor T5, thus actively maintaining the high voltage level at the first node N1. The high voltage level at the first node N1 can control the first transistor T1 to be switched off. Additionally, due to the low voltage level of the second voltage signal VGL, the eighth transistor T8 can be continuously switched on, and thus the high voltage level at the first node N1 can be transmitted to the fourth node N4, which controls the seventh transistor T7 to be switched off.

[0035] Therefore, when the first voltage signal VGH is transmitted to the signal output terminal OUT via the sixth transistor T6, and the circuit thus outputs a high voltage level, the low voltage level of the second clock signal CK2 may not be able to influence the first node N1 through the parasitic capacitance of the seventh transistor T7. The high voltage level of the output signal OUT can therefore be output stably.

[0036] Fig. 4B shows an equivalent circuit diagram of a shift register circuit in a second stage t2 of a control timing sequence according to Fig. 3. As in Fig. 4B shown and with reference to Fig. In the second stage, t2, the first clock signal CK1 can be the input signal IN at a low voltage level, thereby controlling the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 to be switched on. The second clock signal CK2 can be at a high voltage level, thereby controlling the fifth transistor T5 to be switched off.

[0037] The low-voltage level of the input signal IN can then be transferred to the first node N1 by the second transistor T2, allowing the first node N1 to transition to a low-voltage level. This low voltage can be stored in the first capacitor C1. Furthermore, the low-voltage level of the first node N1 can be applied to the gate electrode of the first transistor T1, enabling the low-voltage level of the input signal IN to be transferred to the second node N2. Simultaneously, the third transistor T3 can transfer the low-voltage level of the second voltage signal VGL to the second node N2, thus actively maintaining a low-voltage level at the second node N2.

[0038] Furthermore, the first voltage signal VGH can be transmitted to the signal output terminal OUT via the sixth transistor T6, and the circuit can thus output a high voltage level. Since the low voltage level at the first node N1 and the second node N2 is maintained by an active source, the high voltage level of the second clock signal CK2 cannot affect the first node N1 via the parasitic capacitance of the seventh transistor T7, nor the second node N2 via the parasitic capacitance of the sixth transistor T6. Accordingly, the high voltage level of the output signal OUT can be output stably.

[0039] Fig. 4C shows an equivalent circuit diagram of a shift register circuit in a third stage t3 of a control timing sequence according to Fig. 3. As in Fig. 4C shown and with reference to Fig. In the third stage, t3, the first clock signal CK1 and the input signal IN can both be at a high voltage level, thus controlling the second transistor T2, the third transistor T3, the fourth transistor T4, and the sixth transistor T6 to be switched off. The second clock signal CK2 can be at a low voltage level, thus controlling the fifth transistor T5 to be switched on.

[0040] Then, due to the low voltage level stored by the first capacitor C1 in the second stage t2, the first node N1 can maintain a low voltage level, allowing the first transistor T1 and the seventh transistor T7 to be continuously switched on. The high voltage level of the input signal IN can thus be transferred through the first transistor T1 to the second node N2, enabling the second node N2 to transition to a high voltage level.

[0041] Furthermore, the second clock signal CK2 can be transmitted via the seventh transistor T7 to the signal output terminal OUT to output a low-voltage level. The voltage level of the first node N1 can be lowered due to the low-voltage level of the second clock signal CK2 via the coupling effect of the parasitic capacitance of the seventh transistor T7. Consequently, the low-voltage level of the second clock signal CK2 can be output stably.

[0042] Fig. Figure 4D shows an equivalent circuit diagram of a shift register circuit in a fourth stage t4 of a control timing sequence 300 according to Fig. 3. As in Fig. shown in 4D and with reference to Fig. In the fourth stage t4, the first clock signal CK1 can be at a low voltage level, which controls the second transistor T2 and the third transistor T3 to be switched on. The input signal IN and the second clock signal CK2 can both be at a high voltage level, which controls the first transistor T1, the seventh transistor T7, and the fifth transistor T5 to be switched off.

[0043] The high voltage level of the input signal IN can then be transferred to the first node N1 via the second transistor T2, ensuring that the first node N1 is at a high voltage level. Simultaneously, the low voltage level of the second voltage signal VGL can be transferred to the second node N2 via the third transistor T3, thus actively maintaining a low voltage level at the second node N2. The second capacitor C2 stores the low voltage level. The first voltage signal VGH can then be transferred to the signal output terminal OUT via the sixth transistor T6, and the high voltage level of the output signal OUT can be stably output.

[0044] Fig. Figure 4E shows an equivalent circuit diagram of a shift register circuit in a fifth stage t5 of a control timing sequence 300 according to embodiments of the present disclosure. As in Fig. 4E shown and with reference to Fig. In the fifth stage, t5, the first clock signal CK1 and the input signal IN can both be at a high voltage level, thus controlling the second transistor T2, the third transistor T3, the first transistor T1, and the seventh transistor T7 to be switched off. The second clock signal CK2 can be at a low voltage level, thus controlling the fifth transistor T5 to be switched on.

[0045] Then, due to the storage effect of the second capacitor C2, the second node N2 can maintain the low voltage level of the previous state (i.e., stage t4), thereby controlling the fourth transistor T4 and the sixth transistor T6 to be switched on. The high voltage level of the first voltage signal VGH can be passed through the fourth transistor T4 and the fifth transistor T5 to the first node N1 to continuously maintain the first node N1 at a high voltage level, thus achieving active maintenance of the high voltage level at the first node N1.

[0046] Accordingly, the transition of the second clock signal CK2 from a high voltage level to a low voltage level cannot affect the high voltage level at the first node N1 via the coupling effect of the parasitic capacitance of the seventh transistor T7, and the turn-off state of the seventh transistor T7 cannot be affected. The first voltage signal VGH can be transmitted through the sixth transistor T6 to the signal output terminal OUT, and the high voltage level of the output signal OUT can be stably output.

[0047] Based on the aforementioned descriptions, the disclosed shift register circuit can maintain the active input of voltage levels at the first node N1 and the second node N2 and reduce the influence of the abrupt change of the second clock signal CK2 on the first node N1 and the second node N2 due to the coupling effect of the parasitic capacitance. Accordingly, the output signal OUT can be output stably.

[0048] Furthermore, the present disclosure also provides another connection method for a shift register circuit. Fig. Figure 5 shows a further exemplary circuit diagram of a shift register circuit 200 according to embodiments of the present disclosure. As in Fig. As shown in Figure 5, in one embodiment the control end of the first transistor T1 can be electrically connected to the first node N1, the first end of the first transistor T1 can receive the input signal IN and the second end of the first transistor T1 can be electrically connected to the second node N2.

[0049] Furthermore, the control end of the second transistor T2 can receive the second clock signal CK1, the first end of the second transistor can receive the input signal IN, and the second end of the second transistor T2 can be electrically connected to the first node N1. The control end of the third transistor T3 can receive the first clock signal CK1, the first end of the third transistor T3 can receive a charge signal (i.e., the second voltage signal VGL), and the second end of the third transistor T3 can be electrically connected to the second node N2.

[0050] The control end of the fourth transistor T4 can be electrically connected to the second node N2, the first end of the fourth transistor T4 can be electrically connected to the signal output terminal OUT, and the second end of the fourth transistor T4 can be electrically connected to the third node N3 or the first end of the fifth transistor T5. The control end of the fifth transistor T5 can receive the second clock signal CK2, the first end of the fifth transistor T5 can be electrically connected to the third node N3 or the second end of the fourth transistor T4, and the second end of the fifth transistor T5 can be electrically connected to the first node N1.

[0051] Furthermore, the control end of the sixth transistor T6 can be electrically connected to the second node N2, the first end of the sixth transistor T6 can receive the first voltage signal VGH, and the second end of the sixth transistor T6 can be electrically connected to the signal output terminal OUT. The control end of the seventh transistor T7 can be electrically connected to the fourth node N4, the first end of the seventh transistor T7 can receive the second clock signal CK2, and the second end of the seventh transistor T7 can be electrically connected to the signal output terminal OUT.

[0052] Furthermore, the control end of the eighth transistor T8 can receive a charging signal (i.e., the second voltage signal VGL), the first end of the eighth transistor T8 can be electrically connected to the first node N1, and the second end of the eighth transistor T8 can be electrically connected to the fourth node N4. The first capacitor C1 can be electrically connected between the fourth node N4 and the signal output terminal OUT. The second capacitor C2 can be electrically connected between the second node N2 and the first voltage signal VGH.

[0053] The in Fig. The shift register circuit shown in Figure 5 has a similar configuration to the shift register circuit 200 mentioned above. Accordingly, with reference to the descriptions of each stage of a timing sequence for the shift register circuit 200, the person skilled in the art can describe each stage of a timing sequence for the circuit shown in Figure 5. Fig. The 5 shown shift register circuit is obtained.

[0054] In the circuit mentioned above, the first node N1 and the fourth node N4 can be the same node, or they can be connected to the first and second ends of an eighth transistor T8. As shown in Fig. As shown in Figure 5, the eighth transistor T8 can be switched on in response to the second voltage signal VGL, thereby electrically connecting the first node N1 and the fourth node N4. The eighth transistor T8 reduces the relatively large crossover voltage present during operation of the circuit, thus improving the reliability of the circuit. Furthermore, the eighth transistor T8 can implement a circuit protection function in another way. For example, the eighth transistor T8 can be a resistor with a predetermined resistance, and the present disclosure is not limited to this.

[0055] Furthermore, in one embodiment, the charging signal can be the second voltage signal VGL. In other embodiments, the charging signal can also be the first clock signal CK1 or the second clock signal CK2, etc.

[0056] Fig. Figure 6 shows another exemplary circuit diagram of a shift register circuit according to embodiments of the present disclosure. Fig. Figure 7 shows another exemplary circuit diagram of a shift register circuit according to embodiments of the present disclosure. Fig. 6 and Fig. Figure 7 shows an example circuit diagram of a shift register circuit where the load signal is a first clock signal CK1. The in Fig. The shift register circuit shown in section 6 can be used in Fig. The shift register circuit shown in 2 corresponds to the one in Fig. The two shift register circuits shown can be used in Fig. correspond to the shift register circuit shown in section 5.

[0057] That means, Fig. 6 and Fig. 7 only specify shift register circuits, which are simple variations with respect to the one in Fig. 2 respectively Fig. The 5 shift register circuits shown are, and the voltage level at each node in each stage of the timing sequence for the shift register circuits will not be affected.

[0058] More precisely, unlike in Fig. 2, instead of receiving the second voltage signal VGL, the first end of the third transistor T3, which is in Fig. As shown in Figure 6, the first clock signal CK1 is received. Similarly, unlike in Fig. 5, instead of receiving the second voltage signal VGL, the first end of the third transistor T3, which is in Fig. As shown in Figure 7, the first clock signal CK1 is received. Other components remain essentially similar or the same and are not described again.

[0059] Fig. Figures 8A-8C show exemplary operating data of shift register circuits according to embodiments of the present disclosure. In particular, they correspond to Fig. 8A of an exemplary timing sequence of a shift register circuit 200 according to Fig. 3. In contrast to Fig. Figure 3 shows the sequence of events in Fig. 8A furthermore, the change in the voltage level V(N1) at the first node N1 and the change in the voltage level V(N2) at the second node N2. As in Fig. As shown in Figure 8A, the voltage level V(N1) at the first node N1 and the voltage level V(N2) at the second node N2 can be relatively stable, and the output voltage level V(OUT) can also be relatively stable.

[0060] In one embodiment with reference to Fig. In an operating process of a shift register circuit 200, the disclosed high voltage level in the aforementioned embodiments can be approximately 8 V, and the disclosed low voltage level can be approximately -7 V in the aforementioned embodiments. Furthermore, the output voltage level V(OUT) can be stabilized at approximately 8 V.

[0061] Fig. Figure 8B shows changes in a voltage level at an existing first node N11 and a change in a voltage level at an exemplary first node N1 according to embodiments of the present disclosure. More precisely, as in Fig. As shown in Figure 8B, V(N11) is a voltage level at an existing first node N11 when a parasitic capacitance of 2f is simulated between the first node N1 and the second clock signal CK2, and V(N1) is a voltage level at the first node N1 in the aforementioned embodiments.

[0062] If the parasitic capacitance between the first node N11 and the second clock signal CK2 is 2f, the second clock signal CK2 can have a relatively large influence on the low voltage level at the first node N11. However, the fluctuation in the voltage level at the first node N1 can be relatively small and may even be a positive fluctuation (i.e., the voltage level is slightly increased). Accordingly, the fluctuation in the voltage level at the first node N1 can have a relatively small influence on the output signal of the circuit. In a real circuit, the parasitic capacitance can be larger than the simulated parasitic capacitance of 2f.

[0063] With reference to Fig. 8C is the output waveform of the in Fig. 5, Fig. 6 and Fig. The shift register circuit shown in section 7 basically has the same output waveform as the one shown in Fig.2 shift register circuit shown. Accordingly, the aforementioned different connection types cannot affect the uniformity of the technical solutions of the present disclosure.

[0064] In the aforementioned embodiments, the transistors can all be P-type transistors. However, those skilled in the art can easily deduce that the disclosed shift register circuit can also be a shift register circuit comprising all N-type transistors. The use of only P-type thin-film transistors can offer advantages, such as high noise immunity. For example, since the P-type transistors are switched on when the gate electrode receives a relatively low voltage level, the low voltage level can be implemented relatively easily in the charge management, and the disclosed shift register circuit can be modified into a complementary metal-oxide-semiconductor (CMOS) circuit or other circuits, etc.

[0065] The present disclosure is not intended to restrict the configuration or components of the shift register circuit. If all transistors are P-type transistors, the first voltage signal VGH can be a high-voltage level signal and the second voltage signal VGL can be a low-voltage level signal. If all transistors are N-type transistors, the first voltage signal VGH can be a low-voltage signal and the second voltage signal VGL can be a high-voltage signal.

[0066] By using seven transistors with only two clock signals, the disclosed shift register circuit can ensure active input at the first and second nodes, thereby reducing the impact of the frequent transition of the second clock signal CK2 on these nodes due to the coupling effect of parasitic capacitance. Consequently, the output signal OUT can be stably output. Furthermore, the disclosed shift register circuit can save costs, maintain node voltage stability, and improve output signal stability.

[0067] Furthermore, embodiments of the present disclosure also provide a display device. The display device may include a gate electrode drive circuit formed by the shift register circuit S according to various embodiments of the present disclosure. Since the aforementioned shift register circuit can stabilize the output signal, the output signal of the gate electrode drive circuit can also be more stable. Accordingly, the disclosed display device can achieve a more stable output, thereby improving the display quality.

Claims

[1] A shift register circuit, comprising: a first transistor (T1) which is configured to be switched on in response to a voltage signal at a first node (N1) so that an input signal (IN) is supplied to a second node (N2); wherein a control end of the first transistor (T1) is electrically connected to the first node (N1) and a first end of the first transistor (T1) receives the input signal (IN) and a second end of the first transistor (T1) is electrically connected to the second node (N2); a second transistor (T2) configured to be switched on in response to a first clock signal (CK) so that the input signal (IN) is supplied to the first node (N1), wherein a control end of the second transistor (T2) receives the first clock signal (CK), a first end of the second transistor (T2) receives the input signal (IN), and a second end of the second transistor (T2) is electrically connected to the first node (N1); a third transistor (T3) which is configured to be switched on in response to the first clock signal (CK) so that a second voltage signal (VGL) is supplied to the second node (N2), wherein a control end of the third transistor (T3) receives the first clock signal (CK), a first end of the third transistor (T3) receives the second voltage signal (VGL) and a second end of the third transistor (T3) is electrically connected to the second node (N2); a fourth transistor (T4) which is configured to be switched on in response to a voltage signal at the second node (N2), so that the first voltage signal (VGH) is supplied to a third node (N3);-, wherein a control end of the fourth transistor (T4) is electrically connected to the second node (N2) and a first end of the fourth transistor (T4) receives the first voltage signal (VGH); a fifth transistor (T5) which is configured to be switched on in response to a second clock signal (CK2) so that a voltage signal at the third node (N3) is supplied to the first node (N1); wherein a control end of the fifth transistor (T5) receives the second clock signal (CK2), a first end of the fifth transistor (T5) is electrically connected to the third node (N3) and a second end of the fifth transistor (T5) is electrically connected to the first node (N1); a sixth transistor (T6) which is configured to be switched on in response to a voltage signal at the second node (N2) so that the first voltage signal (VGH) is supplied to a signal output terminal (OUT), wherein a control end of the sixth transistor (T6) is electrically connected to the second node (N2), a first end of the sixth transistor (T6) receives the first voltage signal (VGH) and a second end of the sixth transistor (T6) is electrically connected to the signal output terminal (OUT); a seventh transistor (T7) configured to be turned on in response to a voltage signal at a fourth node (N4) such that the second clock signal (CK2) is supplied to the signal output terminal (OUT), wherein a voltage at the fourth node (N4) is positively correlated with a voltage at the first node (N1), wherein a control end of the seventh transistor (T7) is electrically connected to the fourth node (N4), a first end of the seventh transistor (T7) receives the second clock signal (CK2), and a second end of the seventh transistor (T7) is electrically connected to the signal output terminal (OUT); a first capacitor (C1) which is electrically connected between the fourth node (N4) and the signal output terminal (OUT); and a second capacitor (C2) which is electrically connected between the second node (N2) and the first voltage signal (VGH), the shift register circuit being designed to operate in five stages, comprising: In a first stage, the voltage signal at the second node (N2) is maintained by the second capacitor (C2). the fourth transistor (T4) and the sixth transistor (T6) are switched on as a result of the voltage signal at the second node (N2), the fifth transistor (T5) is switched on as a result of the second clock signal (CK2) and that the first voltage signal (VGH) is transmitted through the sixth transistor (T6) to the signal output terminal (OUT) and is transmitted proportionally through the fourth transistor (T4) and the fifth transistor (T5) to the first node (N1); in a second stage to control that the second transistor (T2), the third transistor (T3) are switched on as a result of the first clock signal (CK), the first voltage signal (VGH) is transmitted through the second transistor (T2) to the first node (N1) and stored in the first capacitor (C1), the first transistor (T1) is switched on as a result of the voltage signal at the first node (N1), the first voltage signal (VGH) is transmitted through the first transistor (T1) to the second node (N2), the second voltage signal (VGL) is transmitted through the third transistor (T3) to the second node (N2), the sixth transistor (T6) is switched on as a result of the voltage signal at the second node (N2), and the first voltage signal (VGH) is transmitted through the sixth transistor (T6) to the signal output terminal (OUT); in a third stage to control that the voltage signal at the first node (N1) is maintained by the first capacitor (C1), the first transistor (T1) and the seventh transistor (T7) are switched on as a result of the voltage signal at the first node (N1), the first voltage signal (VGH) is transmitted through the first transistor (T1) to the second node (N2), and the second clock signal (CK2) is transmitted through the seventh transistor (T7) to the signal output terminal (OUT); in a fourth stage to control that the second transistor (T2) and the third transistor (T3) are switched on as a result of the first clock signal (CK), the first voltage signal (VGH) is transmitted through the second transistor (T2) to the first node (N1), the second voltage signal (VGL) is transmitted through the third transistor (T3) to the second node (N2) and is stored in the second capacitor (C2), the sixth transistor (T6) is switched on as a result of the voltage signal at the second node (N2), and the first voltage signal (VGH) is transmitted through the sixth transistor (T6) to the signal output terminal (OUT); and in a fifth stage to control that the voltage signal at the second node (N2) is maintained by the second capacitor (C2), the fourth transistor (T4) and the sixth transistor (T6) are switched on as a result of the voltage signal at the second node (N2), the fifth transistor (T5) is switched on as a result of the second clock signal (CK2), and the first voltage signal (VGH) is transmitted through the sixth transistor (T6) to the signal output terminal (OUT) and is partially transmitted through the fourth transistor (T4) and the fifth transistor (T5) to the first node (N1). [2] The shift register circuit according to claim 1, wherein: the first node (N1) and the fourth node (N4) are the same node. [3] The shift register circuit according to claim 1, further comprising: an eighth transistor T8, which is configured to be switched on in response to the second voltage signal (VGL), wherein the eighth transistor T8 is electrically connected between the first node (N1) and the fourth node (N4). [4] The shift register circuit according to one of claims 1-3, wherein: All of the transistors are P-type transistors or N-type transistors. [5] The shift register circuit according to claims 1 to 3, wherein: the first voltage signal (VGH) is a high-voltage level signal and the second voltage signal (VGL) is a low-voltage level signal; or the first voltage signal (VGH) is a low-voltage level signal 1 and the second voltage signal (VGH) is a high-voltage level signal. [6] The shift register circuit according to one of claims 1-3, wherein: Low-voltage duty cycles of the first clock signal (CK) and the second clock signal (CK2) are both less than 1 / 2 and the first clock signal (CK) and the second clock signal (CK2) differ by 1 / 2 signal cycle; or The high-voltage duty cycles of the first clock signal (CK) and the second clock signal (CK2) are both less than 1 / 2, and the first clock signal (CK) and the second clock signal (CK2) differ by 1 / 2 signal cycle. [7] A control method for a shift register circuit according to claim 1, wherein the control method comprises: In a first stage, the voltage signal at the second node (N2) is maintained by the second capacitor (C2). the fourth transistor (T4) and the sixth transistor (T6) are switched on as a result of the voltage signal at the second node (N2), the fifth transistor (T5) is switched on as a result of the second clock signal (CK2) and that the first voltage signal (VGH) is transmitted through the sixth transistor (T6) to the signal output terminal (OUT) and is transmitted proportionally through the fourth transistor (T4) and the fifth transistor (T5) to the first node (N1); In a second stage, control that the second transistor (T2) and the third transistor (T3) are switched on as a result of the first clock signal (CK). the first voltage signal (VGH) is transmitted through the second transistor (T2) to the first node (N1) and stored in the first capacitor (C1), the first transistor (T1) is switched on as a result of the voltage signal at the first node (N1), the first voltage signal (VGH) is transmitted through the first transistor (T1) to the second node (N2), the second voltage signal (VGL) is transmitted through the third transistor (T3) to the second node (N2), the sixth transistor (T6) is switched on as a result of the voltage signal at the second node (N2), and the first voltage signal (VGH) is transmitted through the sixth transistor (T6) to the signal output terminal (OUT); in a third stage to control that the voltage signal at the first node (N1) is maintained by the first capacitor (C1), the first transistor (T1) and the seventh transistor (T7) are switched on as a result of the voltage signal at the first node (N1), the first voltage signal (VGH) is transmitted through the first transistor (T1) to the second node (N2), and the second clock signal (CK2) is transmitted through the seventh transistor (T7) to the signal output terminal (OUT); in a fourth stage to control that the second transistor (T2) and the third transistor (T3) are switched on as a result of the first clock signal (CK), the first voltage signal (VGH) is transmitted through the second transistor (T2) to the first node (N1), the second voltage signal (VGL) is transmitted through the third transistor (T3) to the second node (N2) and is stored in the second capacitor (C2), the sixth transistor (T6) is switched on as a result of the voltage signal at the second node (N2), and the first voltage signal (VGH) is transmitted through the sixth transistor (T6) to the signal output terminal (OUT); and in a fifth stage to control that the voltage signal at the second node (N2) is maintained by the second capacitor (C2), the fourth transistor (T4) and the sixth transistor (T6) are switched on as a result of the voltage signal at the second node (N2), the fifth transistor (T5) is switched on as a result of the second clock signal (CK2), and the first voltage signal (VGH) is transmitted through the sixth transistor (T6) to the signal output terminal (OUT) and is partially transmitted through the fourth transistor (T4) and the fifth transistor (T5) to the first node (N1). [8] Display field comprising a shift register circuit according to any one of claims 1 to 6.

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