Housing structures and training methods

Abstract

A method comprising: bonding a first die (68) to a first side of an interposer (96) using first electrical connectors (77, 78); bonding a second die (88) to the first side of the interposer using second electrical connectors (77, 78); attaching a first dummy die (106) to the first side of the interposer adjacent to the second die (88); encapsulating the first die, the second die, and the first dummy die with an encapsulating agent (112); and singulating the interposer (96) and the first dummy die (68) to form a housing structure (200), wherein the singulating comprises sawing through the interposer (96) and the first dummy die (68) to form the housing structure, the dummy die (68) having a sidewall surface (106') that is flush with the lateral dimensions of the interposer (96).

Description

BACKGROUND Since the development of the integrated circuit (IC), the semiconductor industry has experienced sustained, rapid growth due to the continuous improvement in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). This improvement in integration density has largely resulted from repeatedly reducing the minimum feature size, allowing more components to be integrated into a given area. This integration improvement is essentially two-dimensional (2D), since the area occupied by the integrated components is primarily on the surface of the semiconductor wafer. The increased density and corresponding decrease in the area of ​​the integrated circuits have generally rendered direct bonding of integrated circuit chips to a substrate obsolete. Interposers have been used to redistribute spherical contact areas from the chip's surface to larger areas of the interposer. Furthermore, interposers have enabled three-dimensional (3D) packages containing multiple chips. Other packages have also been developed to integrate 3D aspects. US 2011 / 0215470 A1 relates to a package structure consisting of a dummy chip that lies over and is connected to a first chip, wherein the dummy chip includes a section that surrounds a second chip, and wherein the dummy chip is essentially composed of silicon and a metal. US 2015 / 0311182 A1 relates to a semiconductor package comprising a first semiconductor chip located on a first surface of an interposer and at least one second semiconductor chip located on the first surface and at a predefined distance from the first semiconductor chip. US 2016 / 0322330 A1 relates to a package consisting of a first device with one or more dies and a first molding compound extending along the side walls of the one or more dies of the first device. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. Figures 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 to 14 are cross-sectional and top views of an exemplary method for forming a housing structure according to some embodiments. Figures 15A-15F show top views of housing structures according to some embodiments. Figures 16A-16F show top views of housing structures according to some embodiments. Figures 17A-17D show top views of housing structures according to some embodiments. DETAILED DESCRIPTION The invention is defined according to the independent claims. The dependent claims relate to corresponding embodiments. The following disclosure provides many different embodiments or examples to implement various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, forming a first element above or on top of a second element in the following description may include embodiments in which the first and second elements are in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements, so that the first and second elements do not have to be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not in itself imply any relationship between the various described embodiments and / or configurations. Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and similar terms can be used here for the sake of simplicity to describe the relationship of one element or device to other element(s) or device(s), as shown in the figures. These spatially relative terms are intended to encompass various orientations of the component being used or operated, in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative terms used here may be interpreted accordingly. The embodiments described here can be described in a specific context, namely a package structure that incorporates dummy die structures adjacent to the active dies to reduce warpage of the package structure. This reduction in warpage enables a more reliable package structure by decreasing the likelihood of cold solder joints between the active dies and the interposer. In some embodiments, the dummy dies are located along the periphery of the package structure, for example, in or near the scribing line regions. Embodiments are described in relation to a specific context, namely a stacked die-interposer-substrate package using chip-on-wafer-on-substrate (CoWoS) processing. However, other embodiments can also be applied to other packages, such as a stacked die-die-substrate package, and other processing methods. The embodiments described herein are examples to facilitate the manufacture or use of the subject matter of this disclosure, and a person skilled in the art will readily recognize modifications that can be made while remaining within the considered range of the different embodiments. Identical reference numerals and letters in the following figures refer to identical components.Although some procedural execution forms can be described as being executed in a specific order, other procedural execution forms can be executed in any logical order. Fig. 1 shows the formation of one or more dies 68. A main body 60 of the dies 68 can comprise any number of dies, substrates, transistors, active devices, passive devices, or the like. In one embodiment, the main body 60 can comprise a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, a multilayer semiconductor substrate, or the like. The semiconductor material of the main body 60 can consist of silicon, germanium, a composite semiconductor comprising silicon-germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor comprising SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, can also be used. The main body 60 can be doped or undoped.Devices such as transistors, capacitors, resistors, diodes and the like can be formed in and / or on an active surface 62. An interconnect structure 64, comprising one or more dielectric layer(s) and associated metallization structures, is formed on the active surface 62. The metallization structure(s) in the dielectric layer(s) can conduct electrical signals between devices, such as through the use of vias and / or conductive traces, and can also include various electrical devices such as capacitors, resistors, inductors, or the like. The various devices and metallization structures can be interconnected to perform one or more functions. The functions can include memory structures, processing structures, sensors, amplifiers, power distribution, input / output circuits, or the like. Additionally, die connectors 66, such as conductive pillars (e.g.,(comprising a metal such as copper), formed in and / or on the intermediate interconnect structure 64 to provide an external electrical connection to the circuits and devices. In some embodiments, the die connectors 66 project from the intermediate interconnect structure 64 to form a pillar structure to be used when the dies 68 are bonded to other structures. A person skilled in the art will recognize that the above examples are for illustrative purposes only. Other circuits may be used for a given application. In particular, an intermediate metallization dielectric (IMD) layer can be formed in the intermediate structure 64. The IMD layer can be formed, for example, from a low-k dielectric material such as phosphosilicate glass (PSG), boron phosphosilicate glass (BPSG), fluorosilicate glass (FSG), SiOxCy, spin-on glass, spin-on polymer, silicon-carbon material, compounds thereof, composites thereof, combinations thereof, or the like, by any suitable process known in the art, such as spin coating, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), high-density plasma chemical vapor deposition (HDP-CVD), or the like. A metallization structure can be formed in the IMD layer, for example, by using photolithography techniques to deposit and pattern a photoresist material on the IMD layer to expose portions of the IMD layer that are to become the metallization structure.An etching process, such as an anisotropic dry etching process, can be used to create depressions and / or openings in the IMD layer that correspond to the exposed portions of the IMD layer. The depressions and / or openings can be lined with a diffusion barrier and filled with a conductive material. The diffusion barrier can comprise one or more layers of tantalum nitride, tantalum, titanium nitride, titanium, cobalt-tungsten, the like, or a combination thereof, deposited by atomic layer deposition (ALD) or the like. The conductive material of the metallization structures can comprise copper, aluminum, tungsten, silver, and combinations thereof, or the like, deposited by CVD, physical vapor deposition (PVD), or the like.Excess material of the diffusion barrier layer and / or conductive material on the IMD layer can be removed, for example by using chemical-mechanical polishing (CMP). In Fig. 2, the main body 60 with the intermediate connection structure 64 is separated into individual dies 68. Typically, the dies 68 have the same circuitry, for example, fixtures and metallization structures, although the dies may have different circuitry. The separation process may include sawing, cutting, or the like. Each of the dies 68 can include one or more logic dies (e.g., a central processing unit, a graphics processing unit, a system-on-chip, a field-programmable gate array (FPGA), a microcontroller, or the like), memory dies (e.g., a dynamic random access memory (DRAM), a static random access memory (SRAM), or the like), power management dies (e.g., a power supply integrated circuit (PMIC)), radio frequency (RF) dies, microelectromechanical (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) dies), front-end dies (e.g., analog front-end (AFE) dies), the like, or a combination thereof. In some embodiments, the dies 68 may have different sizes (e.g., different heights and / or areas), and in other embodiments, the dies 68 may have the same size (e.g., the same height and / or area). Fig. 3 shows the formation of a first side of components 96 (see Fig. 13). A substrate 70 comprises one or more components 96 during processing. The components 96 can be an interposer or another die. The substrate 70 can be a wafer. The substrate 70 can comprise a bulk semiconductor substrate, an SOI substrate, a multilayer semiconductor substrate, or the like. The semiconductor material of the substrate 70 can consist of silicon, germanium, a composite semiconductor comprising silicon-germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor comprising SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, can also be used. Substrate 70 can be doped or undoped.Devices such as transistors, capacitors, resistors, diodes, and the like can be formed in and / or on a first surface 72, which can also be referred to as the active surface of the substrate 70. In embodiments in which the component 96 is an interposer, the component 96 generally does not have any active devices, although the interposer may include passive devices formed in and / or on a first surface 72. Through-hole vias (TVs) 74 are formed such that they extend from the first surface 72 of the substrate 70 to the substrate 70. The TVs 74 are also sometimes referred to as substrate vias, or silicon vias if the substrate 70 is a silicon substrate. The TVs 74 can be formed by creating cavities in the substrate 70, for example, by etching, milling, laser techniques, a combination thereof, and / or the like. A thin dielectric material can be formed in the cavities, for example, by using an oxidation technique. A thin barrier layer can be conformally deposited over the front surface of the substrate 70 and in the cavities, for example, by CVD, ALD, PVD, thermal oxidation, a combination thereof, and / or the like.The barrier layer can comprise a nitride or an oxynitride such as titanium nitride, titanium oxynitride, tantalum nitride, tantalum oxynitride, tungsten nitride, a combination thereof, and / or the like. A conductive material can be deposited over the thin barrier layer and in the openings. The conductive material can be formed by an electrochemical plating process, CVD, ALD, PVD, a combination thereof, and / or the like. Examples of conductive materials are copper, tungsten, aluminum, silver, gold, a combination thereof, and / or the like. Excess amounts of the conductive material and the barrier layer are removed from the front face of the substrate 70, for example, by CMP. Thus, the TVs 74 can comprise a conductive material and a thin barrier layer between the conductive material and the substrate 70. A redistribution structure 76 is formed over the first surface 72 of the substrate 70 and is used to electrically connect the integrated circuit devices, if present, and / or the TVs 74 to each other and / or to external devices. The redistribution structure 76 may comprise one or more dielectric layer(s) and associated metallization structure(s) within the dielectric layer(s). The metallization structures may include vias and / or conductor tracks to connect any devices and / or TVs 74 to each other and / or to an external device. The metallization structures are sometimes referred to as redistribution lines (RDLs).The dielectric layers can comprise silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, low-k dielectric materials such as PSG, BPSG, FSG, SiOxCy, spin-on glass, spin-on polymer, silicon-carbon materials, compounds thereof, composites thereof, combinations thereof, or the like. The dielectric layers can be deposited by any suitable process known in the art, such as spin coating, CVD, PECVD, HDP-CVD, or the like. A metallization structure can be formed within the dielectric layer, for example, by using photolithography techniques to deposit and pattern a photoresist material onto the dielectric layer to expose portions of the dielectric layer that will become the metallization structure.An etching process, such as an anisotropic dry etching process, can be used to create depressions and / or openings in the dielectric layer that correspond to the exposed portions of the dielectric layer. The depressions and / or openings can be lined with a diffusion barrier and filled with a conductive material. The diffusion barrier can comprise one or more layers of TaN, Ta, TiN, Ti, CoW, or the like, deposited by ALD or the like, and the conductive material can comprise copper, aluminum, tungsten, silver, and combinations thereof, or the like, deposited by CVD, PVC, or the like. Any excess portions of the diffusion barrier and / or conductive material on the dielectric layer can be removed, for example, by using a CMP. Electrical connectors 77 / 78 are formed on conductive pads on the upper surface of the redistribution structure 76. In some embodiments, the conductive pads comprise under-bump metallurgies (UBMs). In the embodiment shown, the pads are formed in openings in the dielectric layers of the redistribution structure 76. In another embodiment, the pads (UBMs) can extend through an opening in a dielectric layer of the redistribution structure 76 and also extend over the upper surface of the redistribution structure 76. As an example of pad formation, a nucleation layer (not shown) is formed at least in the opening in the dielectric layer of the redistribution structure 76. In some embodiments, the nucleation layer is a metal layer, which can be a single layer or a composite layer comprising a plurality of sublayers formed from different materials.In some embodiments, the seed layer comprises a titanium layer and a copper layer overlying the titanium layer. The seed layer can be formed using, for example, PVD or similar processes. A photoresist is then formed and patterned on the seed layer. The photoresist can be formed by spin coating or similar processes and can be exposed to light for patterning. The pattern of the photoresist corresponds to the pads. The patterning creates openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating, such as electroplating or electroless plating, or similar processes. The conductive material can be a metal such as copper, titanium, tungsten, aluminum, or similar.The photoresist and portions of the nucleation layer where the conductive material is not formed are then removed. The photoresist can be removed by a suitable ashing or peeling process, for example, using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the nucleation layer are removed, for example, by using a suitable etching process, such as wet or dry etching. The remaining portions of the nucleation layer and the conductive material form the pads. In an embodiment where the pads are formed differently, more photoresist and structuring steps can be used. In some embodiments, the electrical connectors 77 / 78 comprise a metal column 77 with a metal cap layer 78, which may be a solder cap, overlying the metal column 77. The electrical connectors 77 / 78, including the column 77 and the cap layer 78, are sometimes referred to as micro-bumps (micro-contact bumps) 77 / 78. In some embodiments, the metal columns 77 comprise a conductive material such as copper, aluminum, gold, nickel, palladium, the like, or a combination thereof, and may be formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal columns 77 may be solderless and have substantially vertical sidewalls. In some embodiments, the metal cap layer 78 is formed on the top of the metal column 77.The metal cap layer 78 can comprise nickel, tin, tin-lead, gold, copper, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like or a combination thereof and can be formed by a plating process. In another embodiment, the electrical connectors 77 / 78 do not have the metal columns and are solder balls and / or bumps, such as those formed by flip-chip (C4), electroless nickel immersion gold (ENIG), electroless nickel electroless palladium immersion gold (ENEPIG) techniques, or the like. In this embodiment, the electrical connectors 77 / 78 can comprise a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In this embodiment, the electrical connectors 77 / 78 are formed by initially forming a solder layer by commonly used methods such as evaporation, electroplating, printing, solder transfer, ball placement, or the like. After a solder layer has been formed on the structure, melting can be performed to shape the material into the desired bump shape. In Fig. 4, the dies 68 and dies 88 are attached to the first side of the components 96, for example, by flip-chip bonding over the electrical connectors 77 / 78 and metal pillars 79 on the dies to form conductive connections 91. The metal pillars 79 can be similar to the metal pillars 77, and their description is not repeated here. The dies 68 and dies 88 can be positioned on the electrical connectors 77 / 78 using, for example, a pick-and-place tool. In some embodiments, the metal cap layers 78 are formed on the metal pillars 77 (as shown in Fig. 3), on the metal pillars 79 of the dies 68 and dies 88, or on both. The Dies 88 can be formed by a similar process to that described above with reference to the Dies 68. In some embodiments, the Dies 88 comprise one or more memory dies, such as a stack of memory dies (e.g., DRAM dies, SRAM dies, High Bandwidth Memory (HBM) dies, Hybrid Memory Cube (HMC) dies, or the like). In the stack of memory die embodiments, a Die 88 can comprise both memory dies and a memory controller, such as a stack of four or eight memory dies with a memory controller. Also, in some embodiments, the Dies 88 can have different sizes (e.g., different heights and / or areas), and in other embodiments, the Dies 88 can have the same size (e.g., the same height and / or area). In some embodiments, the dies 88 may have a similar height to the dies 68 (as shown in Fig. 4), or the dies 68 and 88 may have different heights in some embodiments. The dies 88 comprise a main body 80, an interconnect structure 84, and die connectors 86. The main body 80 of the dies 88 can comprise any number of dies, substrates, transistors, active devices, passive devices, or the like. In one embodiment, the main body 80 can comprise a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, a multilayer semiconductor substrate, or the like. The semiconductor material of the main body 80 can consist of silicon, germanium, a composite semiconductor comprising silicon-germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor comprising SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, can also be used. The main body 80 can be doped or undoped.Devices such as transistors, capacitors, resistors, diodes and the like can be formed in and / or on an active surface. An interconnect structure 84, comprising one or more dielectric layer(s) and associated metallization structure(s), is formed on the active surface. The metallization structure(s) in the dielectric layer(s) can conduct electrical signals between devices, such as by using vias and / or conductive traces, and can also include various electrical devices such as capacitors, resistors, inductors, or the like. The various devices and metallization structures can be interconnected to perform one or more functions. The functions can include memory structures, processing structures, sensors, amplifiers, power distribution, input / output circuits, or the like. Additionally, die connectors 86, such as conductive pillars (e.g.,(comprising a metal such as copper), formed in and / or on the intermediate interconnect structure 84 to provide an external electrical connection to the circuits and devices. In some embodiments, the die connectors 86 project from the intermediate interconnect structure 84 to form a pillar structure to be used when the dies 88 are bonded to other structures. A person skilled in the art will recognize that the above examples are for illustrative purposes only. Other circuits may be used as required for a given application. In particular, an IMD layer can be formed in the intermediate structure 84. The IMD layer can be formed, for example, from a low-k dielectric material such as PSG, BPSG, FSG, SiOxCy, spin-on glass, spin-on polymer, silicon-carbon material, compounds thereof, composites thereof, combinations thereof, or the like, by any suitable process known in the art, such as spin coating, CVD, PECVD, HDP-CVD, or the like. A metallization structure can be formed in the IMD layer, for example, by using photolithography techniques to deposit and pattern a photoresist material on the IMD layer to expose portions of the IMD layer that are to become the metallization structure.An etching process, such as an anisotropic dry etching process, can be used to create depressions and / or openings in the IMD layer that correspond to the exposed portions of the IMD layer. The depressions and / or openings can be lined with a diffusion barrier and filled with a conductive material. The diffusion barrier can comprise one or more layers of tantalum nitride, tantalum, titanium nitride, titanium, cobalt-tungsten, the like, or a combination thereof, deposited by ALD or the like. The conductive material of the metallization structure can comprise copper, aluminum, tungsten, silver, and combinations thereof, or the like, deposited by CVD, PVD, or the like. Any excess portions of the diffusion barrier and / or the conductive material on the IMD layer can be removed, for example, by using a CMP. In embodiments where the die connectors 66 and 86 protrude from the intermediate connection structures 64 and 84 respectively, the metal columns 79 can be omitted from the dies 68 and 86, since the protruding die connectors 66 and 86 can be used as columns for the metal cap layers 78. The conductive connections 91 electrically connect the circuits in the dies 68 and the dies 88 through the intermediate connection structures 84 and 64 respectively and the die connectors 86 and 66 respectively to the redistribution structure 76 and the TVs 74 in the components 96. In some embodiments, the electrical connectors 77 / 78 are coated with a flux (not shown), such as a residue-free flux, before being joined. The electrical connectors 77 / 78 can be immersed in the flux, or the flux can be ejected onto the electrical connectors 77 / 78. In another embodiment, the flux can also be applied to the electrical connectors 79 / 78. In some embodiments, the electrical connectors 77 / 78 and / or 79 / 78 can have an epoxy flux (not shown) formed on them before they are melted, with at least a portion of the epoxy flux remaining after the dies 68 and dies 88 have been attached to the components 96.This remaining epoxy component can serve as a backing to reduce the stress and protect the connections resulting from the melting of the electrical connectors 77 / 78 / 79. The bonding between dies 68 and 88 and components 96 can be solder bonding or direct metal-to-metal bonding (such as copper-to-copper or tin-to-tin). In one embodiment, dies 68 and dies 88 are bonded to components 96 by a melting process. During this melting process, electrical connectors 77 / 78 / 79 are in contact with die connectors 66 and 86, respectively, and the pads of the redistribution structure 76 to physically and electrically connect dies 68 and dies 88 to components 96. After the bonding process, an IMC (not shown) can form at the interface between the metal columns 77 and 79 and the metal cap layers 78. Figure 4 and the following figures show a first housing area 90 and a second housing area 92 for forming a first housing and a second housing, respectively. Scribble line areas 94 lie between adjacent housing areas. As shown in Figure 4, a first die and several second dies are placed in both the first housing area 90 and the second housing area 92. In some embodiments, the Dies 68 are a system-on-a-chip (SoC) or a graphics processing unit (GPU), and the second Dies are memory Dies that can be used by the Dies 68. In one embodiment, the Dies 88 are stacked memory Dies. For example, the stacked memory Dies 88 can comprise low-power (LP) DDR memory modules, such as LPDDR1, LPDDR2, LPDDR3, LPDDR4, or similar memory modules. In Fig. 5, a backer rod 100 is dispensed into the spaces between dies 68, dies 88, and the redistribution structure 76. The backer rod 100 can extend along the sidewall of dies 68 and dies 88. The backer rod 100 can be any suitable material, such as a polymer, an epoxy resin, a mold backer rod, or the like. The backer rod 100 can be formed by a capillary flow process after dies 68 and 88 are fixed, or it can be formed by a suitable deposition process before dies 68 and 88 are fixed. Figures 6A, 6B, 6C, 6D, 6E, and 6F show top views of housing structures comprising dummy dies 106 bonded to components 96. Figure 7 is a cross-sectional view showing the dummy dies 106 within the housing structure. Figure 7 was taken along line AA of the top view in Figure 6C. The dummy dies 106 can be positioned on the components 96 using, for example, a pick-and-place tool. In Fig. 6A, the dummy dies 106 are located in the scribing line regions 94 and extend along the scribing line regions 94, which are arranged along a first direction (e.g., the vertical direction of Fig. 6A). In Fig. 6B, the dummy dies 106 are located between adjacent dies 88 of the same region 90 and / or 92. In Fig. 6C, the dummy dies 106 are located in the scribing line regions 94 and extend along the scribing line regions 94, which are arranged along a first direction and a second direction (e.g., both the vertical and horizontal directions of Fig. 6C), and are also located between adjacent dies 88 of the same region 90 and / or 92. In Fig. 6D, the dummy dies 106 are mounted between adjacent dies 88 of the same region 90 and / or 92 and are not located in the scoring line regions 94, but are close to them. In Fig. 6E, the configuration of the dummy dies 106 is similar to that of Fig. 6D, except that the dummy dies 106 are also mounted near the corners of regions 90 and / or 92, adjacent to the dies 88. Again, in this embodiment, the dummy dies 106 are not located in the scoring line regions 94, but are close to them. In Fig. 6F, the dummy dies 106 are mounted near the corners of regions 90 and / or 92, adjacent to the dies 88, and are not located in the scoring line regions 94, but are close to them. The dummy dies 106, arranged in or near the scoring line regions 94, can help to prevent deflection during and after singulation of the housings (see Fig. 13) into the first and second housing regions 90 and 92. For example, the embodiment of Fig. 6C (and the singulated housing in Fig. 15C, which will be described later) can reduce the deflection of the housing by up to about 60% compared to a housing without any dummy dies 106. One way in which the dummy dies 106 can help reduce deflection is by providing support for the housing during the actual singulation process. Another way in which the dummy dies 106 can prevent deflection is by reducing the difference in the coefficient of thermal expansion (CTE) between the components 96 and the subsequently formed encapsulating material 112 (see Fig. 8), since the dummy dies 106 have a similar CTE to the components 96 and thus reduce the amount of encapsulating material 112 required in the housing. Referring to Fig. 7, the dummy dies 106 are glued in the scribed line regions 94 adjacent to the dies 88. The dummy dies 106 are attached to the components 96 by a mounting structure 104. In some embodiments, the mounting structure 104 is an adhesive that bonds the dummy dies 106 to the components 96. In some embodiments, the mounting structure 104 consists of one or more metal pillars with metal cap layers (sometimes referred to as micro-bumps) that connect the dummy dies 106 to the components. The dummy dies 106 may be made of silicon, a dielectric material, the like, or a combination thereof. In some embodiments, the dummy dies 106 are actually defective active dies that have been reused as dummy dies 106. In some embodiments, the upper surfaces of the dummy dies 106 are planar with the back surfaces of the dies 68. In embodiments of the adhesive fastening structure 104, the adhesive 104 is located on the base surfaces of the dummy dies 106 and fastens the dummy dies 106 to the components 96, for example, the redistribution structure 76 shown in the illustration. The adhesive 104 can be any suitable adhesive, epoxy resin, die-fixing film (DAF), or the like. The adhesive 104 can be applied to a base surface of the dummy dies 106 or over the surface of the redistribution structure 76. The dummy dies 106 can be bonded to the redistribution structure 76 by the adhesive 104 using, for example, a pick-and-place tool. The underfill 100 can be cured before or after the dummy dies 106 are bonded. In embodiments of the micro-bump fastening structure 104, the micro-bumps 104 are formed on the bottom surfaces of the dummy dies 106, the top surfaces of the components 96, or both. The micro-bumps 104 can be formed simultaneously with those micro-bumps (e.g., the electrical connectors 77 / 78) that bond the dies 68 and 88. The micro-bumps 104 bond the dummy dies 106 to the components 96, such as the redistribution structure 76 in the illustration. The micro-bumps 104 of the dummy dies 106 can be melted together with the electrical connectors 77 / 78 / 79 of the dies 68 and 88. The dummy dies 106 can be positioned on the micro-bumps 104, for example, by using a pick-and-place tool. The underfill 100 can be cured before or after bonding the dummy dies 106. In Fig. 8, an encapsulating agent 112 is formed on the various components. The encapsulating agent 112 can be a molding compound, an epoxy resin, or the like, and can be applied by compression molding, transfer molding, or the like. A curing step is carried out to harden the encapsulating agent 112, such as thermal curing, ultraviolet (UV) curing, or the like. In some embodiments, the dies 68, the dies 88, and the dummy dies 106 are embedded in the encapsulating agent 112, and after the encapsulating agent 112 has cured, a planarization step, such as grinding, can be carried out to remove excess portions of the encapsulating agent 112 that lie above the top surfaces of the dies 68, the dies 88, and the dummy dies 106. Accordingly, the upper surfaces of Dies 68, Dies 88 and Dummy Dies 106 are exposed and planar with an upper surface of the encapsulating agent 112.In some embodiments, dies 88 and / or dummy dies 106 may have a different height than dies 68, and dies 88 and / or dies 106 are still covered by the encapsulation means 112 after the planarization step. In some embodiments, dies 106 have a greater height than both dies 68 and 88, and both dies 68 and 88 are still covered by the encapsulation 112 after the planarization step. Figures 9, 10, 11 to 12 show the formation of the second side of the components 96. In Figure 9, the structure from Figure 8 is reversed to prepare for the formation of the second side of the components 96. Although not shown, the structure can be arranged on a carrier or support structure for the process of Figures 9, 10, 11 to 12. As shown in Figure 9, at this stage of processing, the substrate 70 and the redistribution structure 76 of the components 96 have a combined thickness T1 in a range of about 50 µm to about 775 µm. The dummy dies 106 (including the mounting structure 104) have a thickness T2 in a range of about 30 µm to about 775 µm, such as about 760 µm. In some embodiments, the dies 68 and / or 88 (including the conductive links 91) have a thickness T2. In Fig. 10, a thinning process is applied to the second side of the substrate 70 to thin the substrate 70 to a second surface 116 until the TVs 74 are exposed. The thinning process may include an etching process, a grinding process, the like, or a combination thereof. In some embodiments, after the thinning process, the substrate 70 and the redistribution structure 76 of the components 96 have a combined thickness T3 in a range of about 30 µm to about 200 µm, such as about 100 µm. In Fig. 11, a redistribution structure is formed on the second surface 116 of the substrate 70 and is used to electrically connect the TVs 74 to each other and / or to external devices. The redistribution structure comprises one or more dielectric layers 117 and metallization structures 118 within the one or more dielectric layers 117. The metallization structures may include vias and / or conductive traces to connect the TVs 74 to each other and / or to an external device. The metallization structures 118 are sometimes referred to as redistribution lines (RDLs). The dielectric layers 117 may comprise silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, low-k dielectric material such as PSG, BPSG, FSG, SiOxCy, spin-on glass, spin-on polymer, silicon-carbon material, compounds thereof, composites thereof, combinations thereof, or the like.The dielectric layers 117 can be deposited by any suitable process known in the art, such as rotational coating, CVD, PECVD, HDP-CVD, or the like. The metallization structures 118 can be formed in the dielectric layer 117, for example, using photolithography techniques to deposit and pattern a photoresist material onto the dielectric layer 117 in order to expose portions of the dielectric layer 117 that are to become the metallization structures 118. An etching process, such as an anisotropic dry etching process, can be used to create depressions and / or openings in the dielectric layer 117 that correspond to the exposed portions of the dielectric layer 117. The depressions and / or openings can be lined with a diffusion barrier layer and filled with a conductive material.The diffusion barrier layer can comprise one or more layers of TaN, Ta, TiN, Ti, CoW, or the like, deposited by ALD or the like, and the conductive material can comprise copper, aluminum, tungsten, silver, and combinations thereof, or the like, deposited by CVD, PVD, plating, or the like. Any excess portion of the diffusion barrier layer and / or conductive material on the dielectric layer can be removed, for example, by using a CMP. In Fig. 12, electrical connectors 120 are also formed on the metallization structures 118 and electrically connected to the TVs 74. The electrical connectors 120 are formed on the upper surface of the redistribution structure on the metallization structures 118. In some embodiments, the metallization structures 118 comprise UBMs. In the embodiment shown, the pads are formed in openings in the dielectric layers 117 of the redistribution structure. In another embodiment, the pads (UBMs) can extend through an opening in a dielectric layer 117 of the redistribution structure and also over the upper surface of the redistribution structure. As an example of pad formation, a seed layer (not shown) is formed at least in the opening in one of the dielectric layers 117 of the redistribution structure. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed from different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer overlying the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the pads. The patterning forms openings through the photoresist to expose the seed layer.A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating, such as electroplating or electroless plating, or the like. The conductive material can be a metal such as copper, titanium, tungsten, aluminum, or the like. The photoresist and portions of the seed layer where the conductive material is not formed are then removed. The photoresist can be removed by a suitable ashing or removal process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, for example, by using a suitable etching process, such as wet or dry etching. The remaining portions of the seed layer and the conductive material form the pads.In the embodiment where the pads are shaped differently, more photoresist and structuring steps can be used. In some embodiments, the electrical connectors 120 are solder balls and / or bumps, such as ball grid array (BGA) balls, C4 micro-bumps, ENIG-formed bumps, ENEPIG-formed bumps, or the like. The electrical connectors 120 can comprise a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the electrical connectors 120 are formed by initially forming a solder layer by such commonly used methods as evaporation, electroplating, printing, solder transfer, ball placement, or the like. After a layer of solder has been formed on the structure, melting can be performed to shape the material into the desired bump shape.In another embodiment, the electrical connectors 120 are metal columns (such as copper columns) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal columns can be solderless and have substantially vertical sidewalls. In some embodiments, a metal cap layer (not shown) is formed on the top of the metal column connectors 120. The metal cap layer can comprise nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof, and can be formed by a plating process. The electrical connectors 120 can be used to bond to an additional electrical component, which may be a semiconductor substrate, a housing substrate, a printed circuit board (PCB) or the like (see 300 in Fig. 14). In Fig. 13, components 96 and dummy dies 106 are singulated between adjacent areas 90 and 92 along the scoring line areas 94 to form component housings 200, which include, among other things, a die 68, a component 96, the dies 88, and sections 106' of the dummy dies 106. Singulation can be carried out by sawing, cutting, or the like. As described above, the dummy dies 106 help to reduce the stress and deflection caused during and after the singulation process. After the singulation process, the remaining sections 106' of the dummy dies 106 have side wall surfaces that are flush with the lateral dimensions of the component housing 200 (see, for example, Fig. 13 and Fig. 14). Fig. 14 shows the mounting of a component housing 200 onto a substrate 300. Electrical connectors 120 are aligned with bond pads on the substrate 300 and pressed against them. The electrical connectors 120 can be melted to create a bond between the substrate 300 and the component 96. The substrate 300 can comprise a housing substrate, such as a build-up substrate containing a core, a laminate substrate having multiple laminated dielectric films, a PCB, or the like. The substrate 300 can have electrical connectors (not shown), such as solder balls, facing the component housing to allow the substrate 300 to be mounted on another device. A backer rod (not shown) can be dispensed between the component housing 200 and the substrate 300, surrounding the electrical connectors 120.The backing material can be any suitable material, such as a polymer, an epoxy resin, a mold backing, or the like. Additionally, one or more surface devices 140 can be connected to the substrate 300. The surface devices 140 can be used to provide additional functionality or programming to the component housing 200 or the housing as a whole. In one embodiment, the surface devices 140 can comprise surface-mount devices (SMDs) or integrated passive devices (IPDs) that include passive devices such as resistors, inductors, capacitors, jumpers, combinations thereof, or the like, which are intended to be used in conjunction with and connected to the component housing 200 or other parts of the housing. According to various embodiments, the surface devices 140 can be arranged on a first major surface of the substrate 300, an opposing major surface of the substrate 300, or both. Figures 15A, 15B, 15C, 15D, 15E, and 15F show top views of the individual housing structures in each of the embodiments of the dummy die 106 shown in Figures 6A, 6B, 6C, 6D, 6E, and 6F, respectively. These embodiments are symmetrical, with die 88 and dummy die 106 located on opposite sides of die 68. Figures 16A, 16B, 16C, 16D, 16E, and 16F show top views of a single housing structure in further embodiments of each of the embodiments of the dummy die 106 shown in Figures 6A, 6B, 6C, 6D, 6E, and 6F, respectively. In these embodiments, the single housing structures are asymmetrical because the dies 88 and the dummy dies 106 are located only on one side (e.g., the top side of the plan view in Figures 16A, 16B, 16C, 16D, 16E, and 16F) of the die 68. These housing structures can be manufactured using similar materials, structures, and processes as described above in Figures 1 to 5 and 7 to 14, and the description is not repeated here. Figures 17A, 17B, and 17C show top views at a similar processing point and similar to the configurations of the dummy die 106 as in Figures 6A, 6B, and 6C, respectively, except that in these embodiments, each of the housing structures contains more dies 88. These housing structures can be manufactured using similar materials, structures, and processes as described above in Figures 1 to 5 and 7 to 14, and the description is not repeated here. Fig. 17D shows a top view of another embodiment of a dummy die 106 configuration, similar to that shown in Figs. 17A-17C, except that in this embodiment the dummy dies 106 are located within regions 90 and 92 and not in the scribing line regions 94. These housing structures can be manufactured using similar materials, structures, and methods as described above in Figs. 1 to 5 and 7 to 14, and the description is not repeated here. This type of configuration (e.g., without dummy dies 106 in the scribing line regions 94) can also be applied to any of the previous configurations described above. The disclosed embodiments of a housing structure, which incorporate dummy die structures adjacent to the active dies, can help to reduce housing structure deflection. This reduction in housing structure deflection enables a more reliable housing structure by decreasing the likelihood of cold solder joints between the active dies and the interposer. For example, the disclosed embodiments can reduce housing deflection by approximately 60% compared to a housing without any dummy dies. In some embodiments, the dummy dies are located in or near the scribing line regions to help prevent deflection during and after die singulation. One way in which the dummy dies can contribute to reducing deflection is by supporting the housing during the actual singulation process.Another way that dummy dies can prevent deflection is by reducing the CTE mismatch between the interposer and the encapsulator, since the dummy dies have a similar CTE to the interposer and the dummy dies reduce the amount of encapsulator required in the housing. In one embodiment, a method comprises: bonding a first die to a first side of an interposer using first electrical connectors; bonding a second die to the first side of the interposer using second electrical connectors; attaching a first dummy die to the first side of the interposer adjacent to the second die; encapsulating the first die, the second die, and the first dummy die with an encapsulating agent; and singulating the interposer and the first dummy die to form a housing structure. Embodiments may include one or more of the following features. The method, wherein the interposer is a third die. The method, wherein the interposer is a bulk substrate having a redistribution structure, the first die and the second die being bonded to the redistribution structure. The method, wherein the singulation includes sawing through the interposer and the first dummy die to form the housing structure. The method, wherein the first die has one or more logic dies and the second die has one or more memory dies. The method, further comprising: forming an underfill between the interposer and the first die and the second die, surrounding the first electrical connector and the second electrical connector, wherein the encapsulation means is formed over the underfill.The method further comprising: forming vias extending through the interposer, wherein the first and second dies are electrically connected to the vias; forming third electrical connectors on a second side of the interposer, the second side facing the first side, wherein the third electrical connectors are electrically connected to the vias; attaching the package structure to a substrate using the third electrical connectors; and bonding a surface-mount device (SMD) to the substrate. The method, wherein the first dummy die comprises silicon. The method, wherein attaching the first dummy die to the first side of the interposer comprises: bonding the first dummy die to the first side of the interposer with an adhesive layer.The method, comprising attaching the first dummy die to the first side of the interposer, includes: bonding the first dummy die to the first side of the interposer with fourth electrical connectors. In one embodiment, a method comprises: forming vias in a substrate; forming a first redistribution structure on a first side of the substrate, wherein the first redistribution structure is electrically connected to the vias; bonding a logic die to the first redistribution structure using first electrical connectors, wherein the first electrical connectors are electrically connected to the first redistribution structure; bonding a stack of memory dies to the first redistribution structure using second electrical connectors, wherein the stack of memory dies is adjacent to the logic die, and the second electrical connectors are electrically connected to the first redistribution structure; and attaching a dummy die over the first redistribution structure in scribing line regions adjacent to the stack of memory dies.and singulation of the substrate, the first redistribution structure, and the dummy die to form a housing structure. Embodiments may include one or more of the following features. The method, wherein the singulation comprises sawing through the substrate, the first redistribution structure, and the dummy die in the scribing line regions to form the housing structure. The method further comprises: forming an underfill between the first redistribution structure and the logic die and the stack of memory dies, surrounding the first electrical connector and the second electrical connector; and encapsulating the logic die, the stack of memory dies, and the dummy die with an encapsulating agent, wherein the encapsulating agent is adjacent to portions of the underfill. The method, wherein the dummy die is made of silicon. The method, wherein attaching the dummy die over the first redistribution structure comprises: bonding the dummy die to the first redistribution structure with an adhesive layer.The method, wherein mounting the dummy die over the first redistribution structure comprises: bonding the dummy die to the first redistribution structure with third electrical connectors. The method further comprises: thinning a second side of the substrate to expose the ends of the vias, the second side being opposite the first side; forming a second redistribution structure on the second side of the substrate, the second redistribution structure being electrically connected to the exposed ends of the vias; forming fourth electrical connectors on and electrically connected to the second redistribution structure; bonding the fourth electrical connectors to a second substrate; and bonding a surface-mount device (SMD) to the second substrate adjacent to one of the fourth electrical connectors. In one embodiment, a structure comprises: a first side of an interposer bonded to a substrate; a logic die and a memory stack bonded to a second side of the interposer, the second side facing the first side; a dummy die attached to the second side of the interposer, the dummy die being adjacent to the logic die or the memory stack; and a molding material extending along side walls of the logic die, the memory stack, and the dummy die, the upper faces of the logic die and the dummy die being exposed by the molding material. Embodiments may include one or more of the following features: The structure wherein the dummy die has a side wall surface that is flush with the lateral dimensions of the interposer. The structure wherein the dummy die is made of silicon.

Claims

A method comprising: bonding a first die (68) to a first side of an interposer (96) using first electrical connectors (77, 78); bonding a second die (88) to the first side of the interposer using second electrical connectors (77, 78); attaching a first dummy die (106) to the first side of the interposer adjacent to the second die (88); encapsulating the first die, the second die, and the first dummy die with an encapsulating agent (112); and singulating the interposer (96) and the first dummy die (68) to form a housing structure (200), wherein the singulating comprises sawing through the interposer (96) and the first dummy die (68) to form the housing structure, the dummy die (68) having a sidewall surface (106') that is flush with the lateral dimensions of the interposer (96). Method according to claim 1, wherein the interposer (96) is a third die. Method according to claim 1 or 2, wherein the interposer (96) is a bulk substrate having a redistribution structure (76), wherein the first die (68) and the second die (88) are bonded to the redistribution structure (76). Method according to any of the preceding claims, wherein the first die (68) comprises one or more logic dies and wherein the second die (88) comprises one or more memory dies. Method according to one of the preceding claims, further comprising: forming an underfill (100) between the interposer and the first die and the second die and surrounding the first electrical connectors (77, 78) and the second electrical connectors (77, 78), wherein the encapsulation means (112) is formed over the underfill (100). A method according to any one of the preceding claims, further comprising: forming vias (74) extending through the interposer (96), wherein the first and second dies (68, 88) are electrically connected to the vias (74); forming third electrical connectors (120) on a second side of the interposer, the second side being opposite to the first side, wherein the third electrical connectors (120) are electrically connected to the vias (74); attaching the housing structure (200) to a substrate (300) using the third electrical connectors (120); and bonding a surface-mount device (140) to the substrate (300). Method according to one of the preceding claims, wherein the first dummy die (106) consists of silicon. Method according to one of the preceding claims, wherein attaching the first dummy die (106) to the first side of the interposer (96) comprises: gluing the first dummy die (106) to the first side of the interposer (96) with an adhesive layer. Method according to one of the preceding claims, wherein attaching the first dummy die (106) to the first side of the interposer (96) comprises: bonding the first dummy die (106) to the first side of the interposer (96) with fourth electrical connectors (104). Method comprising: forming vias (74) in a substrate; forming a first redistribution structure (76) on a first side of the substrate, wherein the first redistribution structure is electrically connected to the vias (74); bonding a logic die (68) to the first redistribution structure (76) using first electrical connectors (77, 78), wherein the first electrical connectors are electrically connected to the first redistribution structure (76); bonding a stack of memory dies (88) to the first redistribution structure (76) using second electrical connectors (77, 78), wherein the stack of memory dies (88) is adjacent to the logic die (68), and wherein the second electrical connectors (77, 78) are electrically connected to the first redistribution structure (76); attaching a dummy die (106) over the first redistribution structure (76) in scribing line regions (94) adjacent to the stack of memory dies;and singling out the substrate, the first redistribution structure and the dummy die to form a housing structure (200), wherein the dummy die (106) has a side wall surface (106') that is flush with the lateral dimensions of the interposer (96). Method according to claim 10, wherein the singulation comprises sawing through the substrate, the first redistribution structure (76) and the dummy die (106) in the scoring line areas (94) to form the housing structure (200). The method of claim 10 or 11, further comprising: forming an underfill (100) between the first redistribution structure (76) and the logic die (68) and the stack of memory dies (88) and surrounding the first electrical connectors (77, 78) and the second electrical connectors (77, 78); and encapsulating the logic die (68), the stack of memory dies (88) and the dummy die (106) with an encapsulating means (112), wherein the encapsulating means is adjacent to portions of the underfill (100). Method according to one of claims 10 to 12, wherein the dummy die (106) consists of silicon. Method according to any one of claims 10 to 13, wherein attaching the dummy die (106) over the first redistribution structure (76) comprises: bonding the dummy die (106) to the first redistribution structure (76) with an adhesive layer. Method according to any one of claims 10 to 14, wherein attaching the dummy die (106) over the first redistribution structure (76) comprises: bonding the dummy die (106) to the first redistribution structure (76) with third electrical connectors (120). A method according to any one of claims 10 to 15, further comprising: thinning a second side of the substrate (70) to expose the ends of the vias (74), wherein the second side is opposite to the first side; forming a second redistribution structure (76) on the second side of the substrate (118), wherein the second redistribution structure (118) is electrically connected to the exposed ends of the vias (74); forming fourth electrical connectors (120) on and electrically connected to the second redistribution structure (118); bonding the fourth electrical connectors (120) to a second substrate (300); and bonding a surface-mounted device (140) to the second substrate (300) adjacent to one of the fourth electrical connectors (120). Structure comprising: a first side of an interposer (96) bonded to a substrate (70); a logic die (68) and a memory stack (88) bonded to a second side of the interposer (96), the second side being opposite to the first side; a dummy die (106) attached to the second side of the interposer (96), the dummy die (106) being adjacent to the logic die (68) or the memory stack (88); and a molding material (112) extending along side walls of the logic die (68), the memory stack (88) and the dummy die (106), wherein the upper surfaces of the logic die (68) and the dummy die (106) are exposed by the molding material, wherein the dummy die (106) has a side wall surface (106') that is flush with the lateral dimensions of the interposer (96). Structure according to claim 17, wherein the dummy die (106) consists of silicon.

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