Manufacturing process for a semiconductor device and a semiconductor device

Abstract

Method for manufacturing a semiconductor device comprising the following steps: Producing a fin structure (29) in which first semiconductor layers (20) and second semiconductor layers (25) are stacked alternately on top of each other; Establishing a victim-gate structure (49) over the fin structure (29); Etching a source / drain area of ​​the fin structure (29) that is not covered by the sacrificial gate structure (49), creating a source / drain gap (27); lateral etching of the first semiconductor layers (20) through the source / drain space (27), wherein by selecting a suitable crystal orientation for the first semiconductor layers (20) and an etching agent the etched surface of the lateral ends of the first semiconductor layers (20) has a V-shaped cross-section; Establishing a first insulating layer (33) in the source / drain space (27) at least on the etched first semiconductor layers (20); and Establishing an epitaxial source / drain layer (50) in the source / drain space (27) such that air gaps (37) are created between the epitaxial source / drain layer (50) and the first semiconductor layers (20).

Description

Technical field

[0001] The invention relates to a method for manufacturing integrated semiconductor circuits and in particular a method for manufacturing semiconductor devices comprising fin field-effect transistors (FinFETs) and / or gate-allaround (GAA) FETs, and semiconductor devices. background

[0002] As the semiconductor industry has advanced to nanometer-scale process nodes in its pursuit of higher device density, higher performance, and lower costs, challenges posed by manufacturing and design problems have led to the development of three-dimensional designs, such as multi-gate field-effect transistors (FETs), which include fin field-effect transistors (FinFETs) and gate-all-around (GAA) FETs. In a FinFET, a gate electrode borders three sides of a channel region, with a dielectric gate layer sandwiched between them. Because the gate structure surrounds the fin on three sides, the transistor essentially has three gates that control the current through the fin or channel region. Unfortunately, the fourth side, the bottom of the channel, is far from the gate electrode and therefore difficult to control with the gates.In contrast, in a GAA-FET, all side faces of the channel region are enclosed by the gate electrode, allowing for more complete depletion in the channel region and resulting in reduced short-channel effects due to a stronger subthreshold current swing (SS) and less drain-induced barrier lowering (DIBL). As transistor dimensions are further reduced into the sub-10-15 nm technology range, further improvements to the GAA-FET are necessary.

[0003] Document US 2017 / 0110554 A1 describes a semiconductor device with a fin structure in which a first semiconductor layer and a second semiconductor layer are stacked alternately, wherein a first and a second insulating layer are arranged between the lateral ends of the second semiconductor layers and a source / drain region, and wherein air gaps are present between the first insulating layer and the second insulating layer. Document US 2017 / 0194430 A1 discloses a method for forming nanowire spacers with multimaterial layers in horizontal-gate all-round (hGAA) structures, wherein the multimaterial layers contain repeating pairs of a first layer and a second layer. A recess in the second layer is formed by a lateral etching process, wherein the recess is filled with a dielectric material.Document US 2017 / 0069481 A1 describes a semiconductor device with a gate structure comprising a stacked channel structure and a composite spacer, wherein the composite spacer includes an inner spacer positioned between adjacent channel semiconductor layers of the channel structure. Document CN 106784001 A discloses a field-effect transistor with a gate structure and a source / drain region, wherein an etch stop layer and a dielectric layer are positioned between the gate structure and the source / drain region. Brief description of the drawings

[0004] The present invention is best understood with reference to the detailed description below in conjunction with the accompanying drawings. It should be noted that, in accordance with common industry practice, various elements are not drawn to scale. Rather, for the sake of clarity, the dimensions of the various elements may be enlarged or reduced as desired. The Fig. Figures 1A to 1D show different representations of a FET semiconductor device according to an embodiment of the present invention. Fig. 1A is a section view along the x-direction (source / drain direction). Fig. 1B is a section view that follows the line Y1 - Y1 from Fig. 1A corresponds to this. Fig. 1C is a section view that follows the line Y2 - Y2 from Fig. 1A corresponds to this. Fig. 1D is a section view that follows the line Y3 - Y3 from Fig. 1A corresponds to this. The Fig. Figures 1E to 1H show different representations of a FET semiconductor device according to an embodiment of the present invention. Fig. 1E is a section view along the x-direction (source / drain direction). Fig. 1F is a section view that follows the line Y1 - Y1 from Fig. 1E corresponds to this. Fig. 1G is a section view that follows the line Y2 - Y2 from Fig. 1E corresponds to this. Fig. 1H is a section view that follows the line Y3 - Y3 from Fig. 1E corresponds to this. The Fig. Figures 2A to 2D show different representations of a FET semiconductor device according to a further embodiment of the present invention. Fig. 2A is a section view along the x-direction (source / drain direction). Fig. 2B is a section view that follows the line Y1 - Y1 from Fig. 2A corresponds to this. Fig. 2C is a section view that follows the line Y2 - Y2 from Fig. 2A corresponds to this. Fig. 2D is a section view that follows the line Y3 - Y3 from Fig. 2A corresponds to this. The Fig. Figures 2E to 2H show different representations of a FET semiconductor device according to an embodiment of the present invention. Fig. 2E is a section view along the x-direction (source / drain direction). Fig. 2F is a section view that follows the line Y1 - Y1 from Fig. 2E is equivalent. Fig. 2G is a section view that follows the line Y2 - Y2 from Fig. 2E is equivalent. Fig. 2H is a section view that follows the line Y3 - Y3 from Fig. 2E is equivalent. The Fig. Figures 3A to 3F show different configurations of internal spacer areas according to some embodiments of the present invention. The Fig. Figures 4A to 4D show one of several stages in the fabrication of a FET semiconductor device according to an embodiment of the present invention. Fig. 4A is a section view along the x-direction (source / drain direction). Fig. 4B is a section view that follows the line Y1 - Y1 from Fig. 4A corresponds to this. Fig. 4C is a section view that follows the line Y2 - Y2 from Fig. 4A corresponds to this. Fig. 4D is a section view that follows the line Y3 - Y3 from Fig. 4A corresponds to this. The Fig. Figures 5A to 5D show one of several stages in the fabrication of a FET semiconductor device according to an embodiment of the present invention. Fig. 5A is a section view along the x-direction (source / drain direction). Fig. 5B is a section view that follows the line Y1 - Y1 from Fig. 5A is equivalent. Fig. 5C is a section view that follows the line Y2 - Y2 from Fig. 5A is equivalent. Fig. 5D is a section view that follows the line Y3 - Y3 from Fig. 5A is equivalent. The Fig. Figures 6A to 6D show one of several stages in the fabrication of a FET semiconductor device according to an embodiment of the present invention. Fig. 6A is a section view along the x-direction (source / drain direction). Fig. 6B is a section view that follows the line Y1 - Y1 from Fig. 6A corresponds to this. Fig. 6C is a section view that follows the line Y2 - Y2 from Fig. 6A corresponds to this. Fig. 6D is a section view that follows the line Y3 - Y3 from Fig. 6A corresponds to this. The Fig. Figures 7A to 7D show one of several stages in the fabrication of a FET semiconductor device according to an embodiment of the present invention. Fig. 7A is a section view along the x-direction (source / drain direction). Fig. 7B is a section view that follows the line Y1 - Y1 from Fig. 7A corresponds to this. Fig. 7C is a section view that follows the line Y2 - Y2 from Fig. 7A corresponds to this. Fig. 7D is a section view that follows the line Y3 - Y3 from Fig. 7A corresponds to this. The Fig. Figures 8A to 8D show one of several stages in the fabrication of a FET semiconductor device according to an embodiment of the present invention. Fig. 8A is a section view along the x-direction (source / drain direction). Fig. 8B is a section view that follows the line Y1 - Y1 from Fig. 8A is equivalent. Fig. 8C is a section view that follows the line Y2 - Y2 from Fig. 8A is equivalent. Fig. 8D is a section view that follows the line Y3 - Y3 from Fig. 8A is equivalent. The Fig. Figures 9A to 9D show one of several stages in the fabrication of a FET semiconductor device according to an embodiment of the present invention. Fig. 9A is a section view along the x-direction (source / drain direction). Fig. 9B is a section view that follows the line Y1 - Y1 from Fig. 9A corresponds to this. Fig. 9C is a section view that follows the line Y2 - Y2 from Fig. 9A corresponds to this. Fig. 9D is a section view that follows the line Y3 - Y3 from Fig. 9A corresponds to this. The Fig. Figures 10A to 10D show one of several stages in the fabrication of a FET semiconductor device according to an embodiment of the present invention. Fig. 10A is a section view along the x-direction (source / drain direction). Fig. 10B is a section view that follows the line Y1 - Y1 from Fig. 10A is equivalent. Fig. 10C is a section view that follows the line Y2 - Y2 from Fig. 10A is equivalent. Fig. 10D is a section view that follows the line Y3 - Y3 from Fig. 10A is equivalent. The Fig. Figures 11A to 11D show one of several stages in the fabrication of a FET semiconductor device according to an embodiment of the present invention. Fig. 11A is a section view along the x-direction (source / drain direction). Fig. 11B is a section view that follows the line Y1 - Y1 from Fig. 11A corresponds to this. Fig. 11C is a section view that follows the line Y2 - Y2 from Fig. 11A corresponds to this. Fig. 11D is a section view that follows the line Y3 - Y3 from Fig. 11A corresponds to this. The Fig. Figures 12A to 12D show one of several stages in the fabrication of a FET semiconductor device according to an embodiment of the present invention. Fig. 12A is a section view along the x-direction (source / drain direction). Fig. 12B is a section view that follows the line Y1 - Y1 from Fig. 12A is equivalent. Fig. 12C is a section view that follows the line Y2 - Y2 from Fig. 12A is equivalent. Fig. 12D is a section view that follows the line Y3 - Y3 from Fig. 12A is equivalent. The Fig. Figures 13A to 13D show one of several stages in the fabrication of a FET semiconductor device according to an embodiment of the present invention. Fig. 13A is a section view along the x-direction (source / drain direction). Fig. 13B is a section view that follows the line Y1 - Y1 from Fig. 13A corresponds to this. Fig. 13C is a section view that follows the line Y2 - Y2 from Fig. 13A corresponds to this. Fig. 13D is a section view that follows the line Y3 - Y3 from Fig. 13A corresponds to this. The Fig. Figures 14A to 14D show one of several stages in the fabrication of a FET semiconductor device according to an embodiment of the present invention. Fig. 14A is a section view along the x-direction (source / drain direction). Fig. 14B is a section view that follows the line Y1 - Y1 from Fig. 14A is equivalent. Fig. 14C is a section view that follows the line Y2 - Y2 from Fig. 14A is equivalent. Fig. 14D is a section view that follows the line Y3 - Y3 from Fig. 14A is equivalent. The Fig. Figures 15A to 15D show one of several stages in the fabrication of a FET semiconductor device according to an embodiment of the present invention. Fig. 15A is a section view along the x-direction (source / drain direction). Fig. 15B is a section view that follows the line Y1 - Y1 from Fig. 15A is equivalent. Fig. 15C is a section view that follows the line Y2 - Y2 from Fig. 15A is equivalent. Fig. 15D is a section view that follows the line Y3 - Y3 from Fig. 15A is equivalent. The Fig. Figures 16A to 16D show one of several stages in the fabrication of a FET semiconductor device according to an embodiment of the present invention. Fig. 16A is a section view along the x-direction (source / drain direction). Fig. 16B is a section view that follows the line Y1 - Y1 from Fig. 16A is equivalent. Fig. 16C is a section view that follows the line Y2 - Y2 from Fig. 16A is equivalent. Fig. 16D is a section view that follows the line Y3 - Y3 from Fig. 16A is equivalent. The Fig. Figures 17A to 17D show one of several stages in the fabrication of a FET semiconductor device according to an embodiment of the present invention. Fig. 17A is a section view along the x-direction (source / drain direction). Fig. 17B is a section view that follows the line Y1 - Y1 from Fig. 17A corresponds to this. Fig. 17C is a section view that follows the line Y2 - Y2 from Fig. 17A corresponds to this. Fig. 17D is a section view that follows the line Y3 - Y3 from Fig. 17A corresponds to this. The Fig. Figures 18A to 18D show one of several stages in the fabrication of a FET semiconductor device according to an embodiment of the present invention. Fig. 18A is a section view along the x-direction (source / drain direction). Fig. 18B is a section view that follows the line Y1 - Y1 from Fig. 18A is equivalent. Fig. 18C is a section view that follows the line Y2 - Y2 from Fig. 18A is equivalent. Fig. 18D is a section view that follows the line Y3 - Y3 from Fig. 18A is equivalent. The Fig. Figures 19A to 19D show one of several stages in the fabrication of a FET semiconductor device according to an embodiment of the present invention. Fig. 19A is a section view along the x-direction (source / drain direction). Fig. 19B is a section view that follows the line Y1 - Y1 from Fig. 19A corresponds to this. Fig. 19C is a section view that follows line Y2 - Y2 from Fig. 19A corresponds to this. Fig. 19D is a section view that follows the line Y3 - Y3 from Fig. 19A corresponds to this. The Fig. Figures 20A to 20D show one of several stages in the fabrication of a FET semiconductor device according to an embodiment of the present invention. Fig. 20A is a section view along the x-direction (source / drain direction). Fig. 20B is a section view that follows the line Y1 - Y1 from Fig. 20A is equivalent. Fig. 20C is a section view that follows the line Y2 - Y2 from Fig. 20A is equivalent. Fig. 20D is a section view that follows the line Y3 - Y3 from Fig. 20A is equivalent. The Fig. Figures 21A to 21D show one of several stages in the fabrication of a FET semiconductor device according to an embodiment of the present invention. Fig. 21A is a section view along the x-direction (source / drain direction). Fig. 21B is a section view that follows the line Y1 - Y1 from Fig. 21A corresponds to this. Fig. 21C is a section view that follows the line Y2 - Y2 from Fig. 21A corresponds to this. Fig. 21D is a section view that follows the line Y3 - Y3 from Fig. 21A corresponds to this. The Fig. Figures 22A to 22D show one of several stages in the fabrication of a FET semiconductor device according to an embodiment of the present invention. Fig. 22A is a section view along the x-direction (source / drain direction). Fig. 22B is a section view that follows the line Y1 - Y1 from Fig. 22A is equivalent. Fig. 22C is a section view that follows the line Y2 - Y2 from Fig. 22A is equivalent. Fig. 22D is a section view that follows the line Y3 - Y3 from Fig. 22A is equivalent. The Fig. Figures 23A to 23D show one of several stages in the fabrication of a FET semiconductor device according to an embodiment of the present invention. Fig. 23A is a section view along the x-direction (source / drain direction). Fig. 23B is a section view that follows the line Y1 - Y1 from Fig. 23A corresponds to this. Fig. 23C is a section view that follows the line Y2 - Y2 from Fig. 23A corresponds to this. Fig. 23D is a section view that follows the line Y3 - Y3 from Fig. 23A corresponds to this. The Fig. Figures 24A to 24D show one of several stages in the fabrication of a FET semiconductor device according to an embodiment of the present invention. Fig. 24A is a section view along the x-direction (source / drain direction). Fig. 24B is a section view that follows the line Y1 - Y1 from Fig. 24A is equivalent. Fig. 24C is a section view that follows the line Y2 - Y2 from Fig. 24A is equivalent. Fig. 24D is a section view that follows the line Y3 - Y3 from Fig. 24A is equivalent. The Fig. Figures 25A to 25D show one of several stages in the fabrication of a FET semiconductor device according to an embodiment of the present invention. Fig. 25A is a section view along the x-direction (source / drain direction). Fig. 25B is a section view that follows the line Y1 - Y1 from Fig. 25A is equivalent. Fig. 25C is a section view that follows the line Y2 - Y2 from Fig. 25A is equivalent. Fig. 25D is a section view that follows the line Y3 - Y3 from Fig. 25A is equivalent. The Fig. 26A, Fig. 26B and Fig. Figure 26C shows various configurations of a source / drain area according to some embodiments of the present invention. The Fig. Figures 27A to 27D show one of several stages in the fabrication of a FET semiconductor device according to an embodiment of the present invention. Fig. 27A is a section view along the x-direction (source / drain direction). Fig. 27B is a section view that follows the line Y1 - Y1 from Fig. 27A corresponds to this. Fig. 27C is a section view that follows the line Y2 - Y2 from Fig. 27A corresponds to this. Fig. 27D is a section view that follows the line Y3 - Y3 from Fig. 27A corresponds to this. The Fig. Figures 28A to 28D show one of several stages in the fabrication of a FET semiconductor device according to an embodiment of the present invention. Fig. 28A is a section view along the x-direction (source / drain direction). Fig. 28B is a section view that follows the line Y1 - Y1 from Fig. 28A is equivalent. Fig. 28C is a section view that follows the line Y2 - Y2 from Fig. 28A is equivalent. Fig. 28D is a section view that follows the line Y3 - Y3 from Fig. 28A is equivalent. The Fig. Figures 29A to 29D show one of several stages in the fabrication of a FET semiconductor device according to an embodiment of the present invention. Fig. 29A is a section view along the x-direction (source / drain direction). Fig. 29B is a section view that follows the line Y1 - Y1 from Fig. 29A corresponds to this. Fig. 29C is a section view that follows the line Y2 - Y2 from Fig. 29A corresponds to this. Fig. 29D is a section view that follows the line Y3 - Y3 from Fig. 29A corresponds to this. The Fig. Figures 30A to 30D show one of several stages in the fabrication of a FET semiconductor device according to an embodiment of the present invention. Fig. 30A is a section view along the x-direction (source / drain direction). Fig. 30B is a section view that follows the line Y1 - Y1 from Fig. 30A is equivalent. Fig. 30C is a section view that follows the line Y2 - Y2 from Fig. 30A is equivalent. Fig. 30D is a section view that follows the line Y3 - Y3 from Fig. 30A is equivalent. The Fig. 31A and Fig. Figure 31B shows one of several stages in the fabrication of a FET semiconductor device according to an embodiment of the present invention. The Fig. 32A and Fig. Figure 32B shows one of several stages in the fabrication of a FET semiconductor device according to a further embodiment of the present invention. Fig. Figure 33 shows one of several stages in the manufacture of a FET semiconductor device according to some embodiments of the present invention. Fig. Figure 34 shows one of several stages in the manufacture of a FET semiconductor device according to some embodiments of the present invention. Fig. Figure 35 shows one of several stages in the manufacture of a FET semiconductor device according to some embodiments of the present invention. Fig. Figure 36 shows one of several stages in the manufacture of a FET semiconductor device according to some embodiments of the present invention. Fig. Figure 37 shows one of several stages in the manufacture of a FET semiconductor device according to some embodiments of the present invention. Fig. Figure 38 shows one of several stages in the manufacture of a FET semiconductor device according to some embodiments of the present invention. Detailed description

[0005] It is clear that the following description provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present invention. For example, the dimensions of elements are not limited to the specified range or values, but may depend on process conditions and / or desired properties of the component. Furthermore, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are in direct contact, and it may also include embodiments in which additional elements can be formed between the first and second elements such that the first and second elements are not in direct contact.For the sake of simplicity and clarity, various elements can be drawn at different scales.

[0006] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. These spatially relative terms are intended to encompass orientations of the component in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative descriptors used here may be interpreted accordingly. Additionally, the term "made of" can mean either "has features" or "consists of."In the present invention, the phrase “an element from the group A, B and C” means “A, B and / or C” (A, B, C, A and B, A and C, B and C, or A, B and C) and does not mean an element of A, an element of B and an element of C, unless otherwise specified.

[0007] In general, controlling lateral etch rates is difficult when nanowires (NWs) are exposed by selective etching of semiconductor sacrificial layers. The lateral ends of the NWs can be etched when an etching process is performed to expose the NWs after a dummy polysilicon gate has been removed, as controlling the lateral etch or having an etch budget for NW exposure is insufficient. Without an etch stop layer, a gate electrode can contact an epitaxial source / drain (S / D) layer. Furthermore, the gate-drain capacitance Cgd is more significantly affected. If there is no dielectric layer between the gate and the S / D region, Cgd will be larger, which would reduce the circuit speed.

[0008] The present invention provides a method for fabricating an internal spacer between a metal gate electrode and an epitaxial S / D layer, as well as a stacked-channel FET. In particular, the present invention relates to a semiconductor device and a method for overcoming the "lateral etching problem" when a selective etching process is performed for nanowire (NW) fabrication. Specifically, the present invention provides one or more low-k layers and / or air gaps between a gate electrode and an epitaxial S / D layer to reduce the capacitance between them.

[0009] In the present invention, a source / drain refers to a source and / or a drain. It should be noted that in the present invention, a source and a drain are used interchangeably and their structures are essentially the same.

[0010] The Fig. Figures 1A to 1D show different representations of a FET semiconductor device according to an embodiment of the present invention. Fig. 1A is a section view along the x-direction (source / drain direction). Fig. 1B is a section view that follows the line Y1 - Y1 from Fig. 1A corresponds to this. Fig. 1C is a section view that follows the line Y2 - Y2 from Fig. 1A corresponds to this. Fig. 1D is a section view that follows the line Y3 - Y3 from Fig. 1A corresponds to this.

[0011] As in the Fig. As shown in Figures 1A to 1D, semiconductor wires 25 are provided above a semiconductor substrate 10, arranged vertically along the z-direction (perpendicular to the main surface of the substrate 10). In some embodiments, the substrate 10 has a single-crystal semiconductor layer, at least on its surface portion. The substrate 10 can comprise a single-crystal semiconductor material such as Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaAsSb, and InP. In certain embodiments, the substrate 10 consists of crystalline Si.

[0012] The substrate 10 can have one or more buffer layers (not shown) in its surface region. The buffer layers can serve to change the lattice constant from that of the substrate to that of the source / drain regions. The buffer layers can consist of epitaxially grown single-crystal semiconductor materials, such as Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, and InP. In a particular embodiment, the substrate 10 has silicon germanium (SiGe) buffer layers that are epitaxially grown on the silicon substrate 10. The germanium concentration of the SiGe buffer layers can increase from 30 atomic percent germanium for the bottommost buffer layer to 70 atomic percent germanium for the topmost buffer layer.

[0013] As in the Fig. As shown in Figures 1A to 1C, the semiconductor wires 25, which are channel layers, are arranged over the substrate 10. In some embodiments, the semiconductor wires 25 are arranged over a fin structure (not shown) that projects from the substrate 10. The channel layers 25 are each enclosed by a dielectric gate layer 82 and a gate electrode layer 84. In some embodiments, the dielectric gate layer 82 has an intermediate layer and a dielectric high-k layer. The gate structure comprises the dielectric gate layer 82, the gate electrode layer 84, and sidewall spacers 40. Fig. Although four semiconductor wires 25 are shown in 1A to 1C, the number of semiconductor wires 25 is not limited to four, and only one semiconductor wire or more than four or up to ten semiconductor wires can be used.

[0014] An epitaxial S / D layer 50 is arranged above the substrate 10. The epitaxial S / D layer 50 is in direct contact with the channel layer 25 and is separated by internal spacer regions 31 and the dielectric gate layer 82. In some embodiments, the internal spacer regions 31 each comprise a first insulating layer 33 and an air gap 37. The first insulating layer 33 is conformally formed on the inner surface of the internal spacer regions 31, which comprise portions of the end sections of two adjacent semiconductor wires 25 and the dielectric gate layer 82. As shown in Fig. As shown in Figure 1A, the cross-section along the x-direction of the internal spacer areas 31 has an essentially rectangular shape.

[0015] An interlayer dielectric layer (ILD layer) 70 is arranged above the epitaxial S / D layer 50, a conductive contact layer 72 is arranged on the epitaxial S / D layer 50, and a conductive pin 75 is arranged above the conductive contact layer 72, extending through the ILD layer 70. The conductive contact layer 72 comprises one or more layers of a conductive material. In some embodiments, the conductive contact layer 72 comprises a silicide layer, such as WSi, NiSi, TiSi, or CoSi, or another suitable silicide material.

[0016] The Fig. Figures 1E to 1H show different representations of a FET semiconductor device according to an embodiment of the present invention. Fig. 1E is a section view along the x-direction (source / drain direction). Fig. 1F is a section view that follows the line Y1 - Y1 from Fig. 1E corresponds to this. Fig. 1G is a section view that follows the line Y2 - Y2 from Fig. 1E corresponds to this. Fig. 1H is a section view that follows the line Y3 - Y3 from Fig. 1E corresponds to this.

[0017] In this embodiment, the epitaxial S / D layer 50 surrounds the second semiconductor layer 25, which is arranged on the S / D regions.

[0018] The Fig. Figures 2A to 2D show different representations of a FET semiconductor device according to a further embodiment of the present invention. Fig. 2A is a section view along the x-direction (source / drain direction). Fig. 2B is a section view that follows the line Y1 - Y1 from Fig. 2A corresponds to this. Fig. 2C is a section view that follows the line Y2 - Y2 from Fig. 2A corresponds to this. Fig. 2D is a section view that follows the line Y3 - Y3 from Fig. 2A corresponds to materials, configurations, dimensions and / or processes that are different from those of the foregoing embodiment, which refers to the Fig. The embodiments described in sections 1A to 1D, which are the same or similar, may also be identical or similar in the embodiment of the Fig. 2A to 2D can be used, and their detailed description can be omitted.

[0019] In this embodiment, the cross-section along the x-direction of the internal spacer area 31 has a substantially triangular shape, as shown in Fig. 2A is shown. The triangular shape is defined by (111)-surfaces of the semiconductor wires 25.

[0020] The Fig. Figures 2E to 2H show different representations of a FET semiconductor device according to an embodiment of the present invention. Fig. 2E is a section view along the x-direction (source / drain direction). Fig. 2F is a section view that follows the line Y1 - Y1 from Fig. 2E is equivalent. Fig. 2G is a section view that follows the line Y2 - Y2 from Fig. 2E is equivalent. Fig. 2H is a section view that follows the line Y3 - Y3 from Fig. 2E is equivalent.

[0021] In this embodiment, the epitaxial S / D layer 50 surrounds the second semiconductor layer 25, which is arranged on the source / drain regions.

[0022] The Fig. Figures 3A to 3F show different configurations of internal spacer areas according to some embodiments of the present invention. Fig. 3A to 3C show the internal spacer areas with a rectangular cross-section, and the Fig. 3D to 3F show the internal spacer areas with a triangular cross-section.

[0023] As in the Fig. 3A and Fig. As shown in the 3D figure, in some embodiments the internal spacer area 31 has the first insulating layer 33 and the air gap 37. The first insulating layer 33 has a U-shaped (rotated by 90 degrees) cross-section. The air gap 37 is arranged on one S / D side so that it is in contact with the epitaxial S / D layer 50.

[0024] In other embodiments, the internal spacer area 31 comprises the first insulating layer 33, a second insulating layer 35, and the air gap 37, as shown in the Fig. 3B and Fig. Figure 3E is shown. In some embodiments, the air gap 37 is arranged on one S / D side so that it is in contact with the epitaxial S / D layer 50, and the second insulating layer 35 is arranged on the gate electrode side and is not in contact with the epitaxial S / D layer 50. The width Wa of the air gap 37 is in the range of about 0.5 nm to about 2.0 nm in some embodiments and in the range of about 0.8 nm to about 1.5 nm in other embodiments.

[0025] In certain embodiments, which are described in the Fig. 3C and Fig. As shown in Figure 3F, no air gap is created in the internal spacer area 31. In this case, the internal spacer area 31 has two or more insulating layers. In some embodiments, the internal spacer area 31 has the first insulating layer 33 and the second insulating layer 35, which are in contact with the epitaxial S / D layer 50.

[0026] In some embodiments, the first insulating layer 33 comprises silicon nitride (SiN) or silicon oxide (SiO2) and has a thickness in the range of about 0.5 nm to about 3.0 nm. In other embodiments, the first insulating layer 33 has a thickness in the range of about 1.0 nm to about 2.0 nm.

[0027] In some embodiments, the second insulating layer 35 consists of a low-k material (whose dielectric constant is smaller than that of SiO2). The low-k material includes SiOC, SiOCN, an organic or porous material, or another suitable material. In some embodiments, the second insulating layer 35 has a thickness in the range of about 0.5 nm to about 3.0 nm, and in other embodiments, it has a thickness in the range of about 1.0 nm to about 2.0 nm.

[0028] The Fig. Figures 4A-4D to 13A-13D show different stages in the fabrication of a FET semiconductor device according to an embodiment of the present invention. Fig. Figures 4A to 13D, designated with the letter A, are sectional views along the x-direction (source / drain direction); figures designated with the letter B are sectional views corresponding to the Y1-Y1 line of the respective figure designated with the letter A; figures designated with the letter C are sectional views corresponding to the Y2-Y2 line of the respective figure designated with the letter A; and figures designated with the letter D are sectional views corresponding to the Y3-Y3 line of the respective figure designated with the letter A. It is clear that further steps before, during, and after the operations described in the Fig. The processes shown in 4A to 13D can be implemented, and some of the steps described below can be replaced or omitted in other embodiments of the method. The sequence of steps / processes is interchangeable. Materials, configurations, dimensions, and / or processes that are similar to those of the preceding embodiments, which are referenced in the Fig. 1A to 3F, which are the same or similar, can also be used in the embodiment of the Fig. 4A to 13D can be used, and their detailed description can be omitted.

[0029] The Fig. Figures 4A to 4D show the structure after the dummy gate structure has been fabricated over a fin structure, in which the first semiconductor layer 20 and the second semiconductor layer 25 are stacked alternately on top of each other. This structure can be fabricated using the following steps, which are described in the Fig. Figures 33 to 38 are shown. Methods for manufacturing a GAA-FET up to this stage of the process can also be found in US documents 9,627,540 B1, US 2017 / 0154958 A1 and US 9,583,399 B1, which are incorporated by reference.

[0030] As in Fig. As shown in Figure 33, dopant ions (dotandes) 12 are doped into a silicon substrate 10 to create a trough region. Ion implantation is performed to prevent penetration. The substrate 10 can have different regions, which have been doped accordingly with dopant materials (which are, for example, p- or n-type). The dopants 12 are, for example, boron (BF₂) for an n-type FinFET and phosphorus for a p-type FinFET.

[0031] Then semiconductor stack layers are produced over substrate 10, as in Fig. Figure 34 shows that the semiconductor stack layers comprise first semiconductor layers 20 and second semiconductor layers 25. A mask layer 16 is also produced over the stack layers.

[0032] The first semiconductor layers 20 and the second semiconductor layers 25 consist of materials having different lattice constants, and they can comprise one or more layers of Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb or InP.

[0033] In some embodiments, the first semiconductor layers 20 and the second semiconductor layers 25 consist of Si, a Si compound, SiGe, Ge, or a Ge compound. In one embodiment, the first semiconductor layers 20 consist of Si 1-x Ge x , where x is greater than approximately 0.3, or Ge (x = 1.0), and the second semiconductor layers 25 consist of Si or Si 1-y Ge y, where y is less than about 0.4 and x > y. In the present invention, an M-compound or an M-based compound is a compound in which most of the compound is M.

[0034] In another embodiment, the second semiconductor layers 25 consist of Si 1-y Ge y , where y is greater than about 0.3, or Ge, and the first semiconductor layers 20 consist of Si or Si 1-x Ge x , where x is less than approximately 0.4 and x < y. In further embodiments, the first semiconductor layers 20 consist of Si 1-x Ge x , where x is approximately 0.3 to approximately 0.8, and the second semiconductor layers 25 consist of Si 1-y Ge y , where y is approximately 0.1 to approximately 0.4.

[0035] In Fig. In the 34, four layers of the first semiconductor layer 20 and four layers of the second semiconductor layer 25 are arranged. However, the number of layers is not limited to four, and only one layer (in each layer) can be produced. In some embodiments, two to ten layers each can be produced in the first and second semiconductor layers. By changing the number of stacked layers, the drive current of the GAA-FET device can be adjusted.

[0036] The first semiconductor layers 20 and the second semiconductor layers 25 are produced epitaxially over the substrate 10. The thickness of the first semiconductor layers 20 can be equal to or greater than that of the second semiconductor layers 25 and, in some embodiments, is in the range of approximately 2 nm to approximately 20 nm, and in other embodiments, in the range of approximately 5 nm to approximately 15 nm. The thickness of the second semiconductor layers 25 is, in some embodiments, in the range of approximately 2 nm to approximately 20 nm, and in other embodiments, in the range of approximately 5 nm to approximately 15 nm. The thickness of each of the first semiconductor layers 20 can be the same or different.

[0037] In some embodiments, the lower first semiconductor layer (the layer closest to substrate 10) is thicker than the other semiconductor layers. The thickness of the lower first semiconductor layer ranges from about 10 nm to about 50 nm in some embodiments and from about 20 nm to about 40 nm in other embodiments.

[0038] In some embodiments, the mask layer 16 comprises a first mask layer 16A and a second mask layer 16B. The first mask layer 16A is a pad oxide layer consisting of silicon oxide, which can be produced by thermal oxidation. The second mask layer 16B consists of silicon nitride (SiN) and is produced by chemical vapor deposition (CVD), including low-pressure gravure chemical vapor deposition (LPCVD) and plasma-assisted chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or by another suitable method. The mask layer 16 is structured into a mask structure using structuring processes that include photolithography and etching.

[0039] As in Fig. As shown in Figure 35, the stacked layers of the first and second semiconductor layers 20 and 25 are then structured using the structured mask layer 16, so that fin structures 29 are formed from the stacked layers, which extend in the x-direction. Fig. 36 Two fin structures 29 are arranged in the y-direction. However, the number of fin structures is not limited to two and can be one, three, or more. In some embodiments, one or more dummy fin structures are produced on both sides of the fin structures 29 to improve the shape fidelity of the structure in the structuring processes. As shown in Fig. As shown in Figure 35, the fin structures have 29 upper parts formed by the semiconductor stack layers 20 and 25 and trough parts 11.

[0040] The width W1 of the upper part of the fin structure along the y-direction is approximately 10 nm to approximately 40 nm in some embodiments and approximately 20 nm to approximately 30 nm in other embodiments. The height H1 along the z-direction of the fin structure is approximately 100 nm to approximately 200 nm.

[0041] The fin stack structure 29 can be structured using any suitable method. For example, the structures can be structured using one or more photolithographic processes, such as dual or multiple structuring. Typically, dual and multiple structuring processes combine photolithographic and self-aligning processes to produce structures with, for example, smaller grid spacings than those achievable with a simple direct photolithographic process. For example, in one embodiment, a sacrificial layer is produced over a substrate and structured using a photolithographic process. Spacers are produced along the structured sacrificial layer using a self-aligning process.The sacrificial layer is then removed, and the remaining spacers are then used to structure the fin stack structure 29.

[0042] After the fin structures 29 have been fabricated, an insulating layer, comprising one or more layers of an insulating material, is deposited over the substrate so that the fin structures are completely embedded in the insulating layer. The insulating material for the insulating layer can include silicon oxide, silicon nitride, silicon oxide nitride (SiON), SiOCN, SiCN, fluorosilicate glass (FSG), or a dielectric low-k material deposited by low-pressure gravure chemical vapor deposition (LPCVD), plasma CVD, or flowable CVD. After fabrication of the insulating layer, annealing may be performed. Then, planarization, such as chemical-mechanical polishing (CMP) and / or back-etching, is carried out so that the top surface of the uppermost second semiconductor layer 25 is freed from the insulating material layer.In some embodiments, a fin cover layer 13 is produced over the fin structures before the insulating material layer is produced. The fin cover layer 13 consists of SiN or a silicon nitride-based material (e.g., SiON, SiCN, or SiOCN).

[0043] In some embodiments, the fin cover layer 13 comprises a first fin cover layer, which is produced over the substrate 10 and sidewalls of the lower part of the fin structures 11, and a second fin cover layer, which is produced on top of the first fin cover layer. In some embodiments, the cover layers each have a thickness of about 1 nm to about 20 nm. In some embodiments, the first fin cover layer comprises silicon oxide and has a thickness of about 0.5 nm to about 5 nm, and the second fin cover layer comprises silicon nitride and also has a thickness of about 0.5 nm to about 5 nm. The cover layers can be deposited by one or more methods, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD), but any suitable method can be used.

[0044] As in Fig. As shown in Figure 36, the insulating material layer is then removed to create a dielectric barrier 15, exposing the upper parts of the fin structures 29. In this step, the fin structures 29 are separated from each other by the dielectric barrier 15, also referred to as a shallow trench insulation (STI). The dielectric barrier 15 can consist of suitable dielectric materials, such as silicon oxide, silicon nitride, silicon oxide nitride, fluorosilicate glass (FSG), low-k dielectrics such as carbon-doped oxides, extremely low-k dielectrics such as porous carbon-doped silicon dioxide, a polymer such as polyimide, combinations thereof, or the like. In some embodiments, the dielectric barrier 15 is produced by a process such as CVD, flowable CVD (FCVD), or spin-on-glass, but another suitable process may also be used.

[0045] At the in Fig. In the embodiment shown in Figure 36, the dielectric separator layer 15 is omitted until the upper part of the fin structure (well layer) 11 is exposed. In other embodiments, the upper part of the fin structure 11 is not exposed. The first semiconductor layers 20 are sacrificial layers that are subsequently partially removed, and the second semiconductor layers 25 are then formed into semiconductor wires as channel layers of a GAA-FET.

[0046] After the production of the dielectric separating layer 15, a sacrificial gate structure (dummy gate structure) 49 is produced, as shown in Fig. 37 is shown. Fig. Figure 37 shows a structure after fabrication of the sacrificial gate structure 49 over the exposed fin structures 29. The sacrificial gate structure 49 is fabricated over a portion of the fin structures that is intended to be a channel region. The sacrificial gate structure 49 defines the channel region of the GAA FET. The sacrificial gate structure 49 comprises a dielectric sacrificial gate layer 41 and a sacrificial gate electrode layer 42. The dielectric sacrificial gate layer 41 comprises one or more layers of an insulating material, such as a silicon oxide-based material. In one embodiment, silicon oxide deposited by CVD is used. The thickness of the dielectric sacrificial gate layer 41 is in the range of approximately 1 nm to approximately 5 nm in some embodiments.

[0047] The sacrificial gate structure 49 is fabricated as follows. First, a dielectric sacrificial gate layer 41 is produced by protective deposition over the fin structures. Then, a sacrificial gate electrode layer is produced by protective deposition on the dielectric sacrificial gate layer and over the fin structures, such that the fin structures are completely embedded in the sacrificial gate electrode layer. The sacrificial gate electrode layer comprises silicon, such as polycrystalline silicon or amorphous silicon. The thickness of the sacrificial gate electrode layer is in the range of approximately 100 nm to approximately 200 nm in some embodiments. In some embodiments, the sacrificial gate electrode layer is planarized. The dielectric sacrificial gate layer and the sacrificial gate electrode layer are deposited by CVD, including LPCVD and PECVD, PVD, ALD, or by another suitable method.A mask layer is then produced over the sacrificial gate electrode layer. The mask layer comprises a SiN pad layer 43 and a silicon oxide mask layer 44.

[0048] Then, structuring is performed on the mask layer, and the sacrificial gate electrode layer is structured to the sacrificial gate structure 49, as shown in Fig. Figure 37 shows that the sacrificial gate structure comprises the dielectric sacrificial gate layer 41, the sacrificial gate electrode layer 42 (e.g., polysilicon), the SiN pad layer 43, and the silicon oxide mask layer 44. By structuring the sacrificial gate structure, the stack layers of the first and second semiconductor layers on opposite sides of the sacrificial gate structure are partially exposed, thus defining S / D regions, as shown in Fig. Figure 37 shows that in the present invention, a source and a drain are used interchangeably, and their structures are essentially the same. Fig. In Figure 37, only one sacrificial gate structure is manufactured, but the number of sacrificial gate structures is not limited to one. In some embodiments, two or more sacrificial gate structures are arranged in the x-direction. In certain embodiments, one or more dummy sacrificial gate structures are manufactured on both sides of the sacrificial gate structures to improve the shape fidelity of the structure.

[0049] Furthermore, a cover layer 40 for side wall spacers is produced over the sacrificial gate structure 49, as shown in Fig. Figure 38 shows that the cover layer 40 is conformally deposited so that it is produced with substantially the same thickness on vertical surfaces, such as the side walls, on horizontal surfaces, and on the top surface of the sacrificial gate structure. In some embodiments, the cover layer 40 has a thickness greater than that of the first cover layer, ranging from about 5 nm to about 20 nm. The cover layer 40 comprises one or more of the compounds SiN, SiON, and SiCN, or another suitable dielectric material. The cover layer 40 can be produced by ALD or CVD, or by another suitable method.

[0050] In certain embodiments, a further cover layer 47, consisting of an insulating material, is conformally fabricated over the exposed fin structures and the sacrificial gate structure 49 before the cover layer 40 is fabricated. In this case, the further cover layer 47 and the cover layer 40 are composed of different materials, so that one of them can be selectively etched. The further cover layer 47 comprises a dielectric low-k material, such as SiOC and / or SiOCN, or another suitable dielectric material, and can be fabricated by ALD or CVD or by another suitable method.

[0051] With the steps that are involved in the Fig. As explained in sections 33 to 38, the structure of the Fig. 4A to 4D will be obtained. In the Fig. Figures 4A to 4D do not show the upper part of the sacrificial gate structure.

[0052] As in the Fig. As shown in Figures 5A to 5D, the stacked structure consisting of the first semiconductor layers 20 and the second semiconductor layers 25 is then etched down to the S / D region using one or more lithographic and etching processes, creating an S / D gap 27. In some embodiments, the substrate 10 (or the lower part of the fin structures 11) is also partially etched.

[0053] As in the Fig. As shown in Figures 6A to 6D, the first semiconductor layers 20 are also etched laterally in the x-direction within the S / D gap 27, creating cavities 22. The etching depth for the first semiconductor layers 20 ranges from approximately 2 nm to approximately 10 nm in some embodiments. If the first semiconductor layers 20 are made of Ge or SiGe and the second semiconductor layers 25 are made of Si, the first semiconductor layers 20 can be selectively etched using a wet etching agent, such as solutions of hydrated ammonia (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH).

[0054] As in the Fig. As shown in Figures 7A to 7D, in other embodiments, by selecting a suitable crystal orientation for the first semiconductor layers 20 and an etching agent, the etched surface of the lateral ends of the first semiconductor layers 20 has a quadrilateral cavity 23 defined by (111) surfaces. In the cross-section along the x-direction, the cavity 23 has a V-shape (or the shape of an open triangle), as shown in Figures 7A to 7D. Fig. 7A is shown.

[0055] The following figures illustrate the manufacturing processes after the production of the components described in the... Fig. The structure shown in sections 6A to 6D is explained. However, these steps can also be applied to the structures shown in the Fig. The structure shown in 7A to 7D can be used.

[0056] As in the Fig. As shown in Figures 8A to 8D, a first insulating layer 33 is conformally fabricated on the lateral ends of the first semiconductor layer 20 and on the second semiconductor layer 25 in the S / D gap 27. The first insulating layer 33 comprises silicon nitride (SiN) or silicon oxide (SiO2) and has a thickness in the range of about 0.5 nm to about 3.0 nm. In other embodiments, the first insulating layer 33 has a thickness in the range of about 1.0 nm to about 2.0 nm. The first insulating layer 33 can be fabricated by ALD or by another suitable method. Conformally fabricating the first insulating layer 33 reduces the size of a cavity 22.

[0057] After the first insulating layer 33 has been produced, an etching process is carried out to partially remove the first insulating layer, as described in the Fig. Figures 9A to 9D show that, due to this etching process, the first insulating layer 33 remains essentially within the cavity 22, as it has a small volume. Typically, in plasma dry etching, a layer in wide and flat areas is etched faster than a layer in concave areas (e.g., holes, grooves, and / or slots). Therefore, the first insulating layer 33 can remain within the cavities 22. In some embodiments, one or more additional insulating layers are produced on top of the first insulating layer 33 and then etched.

[0058] As in the Fig. As shown in Figures 10A to 10D, an epitaxial source / drain layer 50 is subsequently fabricated in the source / drain space 27. The epitaxial source / drain layer 50 comprises one or more layers of Si, SiP, SiC, and SiCP for an n-channel FET, or of Si, SiGe, or Ge for a p-channel FET. In the p-channel FET, boron (B) may also be included in the source / drain. The epitaxial source / drain layer 50 is fabricated by epitaxial growth using CVD, ALD, or molecular beam epitaxy (MBE). As shown in the Fig. As shown in Figures 10A to 10D, the epitaxial S / D layer 50 is brought into contact with the second semiconductor layers 25 and is produced in such a way that air gaps 37 are created between the epitaxial S / D layer 50 and the first insulating layer 33.

[0059] As in the Fig. As shown in Figures 11A to 11D, an interlayer dielectric layer (ILD layer) 70 is then fabricated over the epitaxial S / D layer 50. Materials for the ILD layer 70 include compounds containing Si, O, C, and / or H, such as silicon dioxide, SiCOH, and SiOC. Organic materials, such as polymers, can also be used for the ILD layer 70. After the ILD layer 70 has been fabricated, planarization, such as CMP, is performed to expose the upper part of the sacrificial gate electrode layer 42.

[0060] The sacrificial gate electrode layer 42 and the dielectric sacrificial gate layer 41 are then removed. The ILD layer 70 protects the epitaxial S / D layer 50 during the removal of the sacrificial gate structures. The sacrificial gate structures can be removed by plasma dry etching and / or wet etching. If the sacrificial gate electrode layer 42 is made of polysilicon and the ILD layer 70 is made of silicon dioxide, a wet etchant, such as a TMAH solution, can be used for the selective removal of the sacrificial gate electrode layer 42. Subsequently, the dielectric sacrificial gate layer 41 is removed by plasma dry etching and / or wet etching.

[0061] After the sacrificial gate structures have been removed, the first semiconductor layers 20 are removed, so that wires are formed from the second semiconductor layers 25, as shown in the Fig. Figures 12A to 12D show that the first semiconductor layers 20 can be removed or etched using an etchant that can selectively etch the first semiconductor layers 20 relative to the second semiconductor layers 25, as explained above. Since, as shown in the Fig. As shown in Figures 12A to 12D, once the first insulating layer 33 has been produced, the etching of the first semiconductor layers 20 ends at the first insulating layer 33. In other words, the first insulating layer 33 acts as an etch stop layer for etching the first semiconductor layers 20.

[0062] After the semiconductor wires have been fabricated from the second semiconductor layers 25, a dielectric gate layer 82 is fabricated around each channel layer (wires of the second semiconductor layers 25), and a gate electrode layer 84 is fabricated on the dielectric gate layer 82, as shown in the Fig. 13A to 13D are shown.

[0063] In certain embodiments, the dielectric gate layer 82 comprises one or more layers of a dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric material, another suitable dielectric material, and / or combinations thereof. Examples of high-k dielectric materials include HfO₂, HfSiO₂, HfSiON₄, HfTaO, HfTiO₂, HfZrO₂, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO₂-Al₂O₃) alloy, other suitable high-k dielectric materials, and / or combinations thereof. In some embodiments, the dielectric gate layer 82 has an intermediate layer (not shown) formed between the channel layers and the dielectric material.

[0064] The dielectric gate layer 82 can be fabricated by CVD, ALD, or another suitable method. In one embodiment, the dielectric gate layer 82 is fabricated using a highly conformal deposition method, such as ALD, to ensure the fabrication of a dielectric gate layer with a uniform thickness around each channel layer. In one embodiment, the thickness of the dielectric gate layer 82 is in the range of approximately 1 nm to approximately 6 nm.

[0065] The gate electrode layer 84 is fabricated on the dielectric gate layer 82 such that it surrounds each channel layer. The gate electrode layer 84 comprises one or more layers of a conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof.

[0066] The gate electrode layer 84 can be fabricated by CVD, ALD, electroplating, or another suitable method. The gate electrode layer 84 is also deposited over the top surface of the ILD layer 70. The dielectric gate layer 82 and the gate electrode layer 84 fabricated over the ILD layer 70 are then planarized, for example, by CMP, until the top surface of the ILD layer 70 is exposed. In some embodiments, after planarization, the gate electrode layer 84 is recessed, and a cover insulating layer (not shown) is fabricated over the recessed gate electrode layer 84. The cover insulating layer comprises one or more layers of a silicon nitride-based material, such as SiN. The cover insulating layer can be fabricated by depositing an insulating material and subsequent planarization.

[0067] In certain embodiments of the present invention, one or more output function setting layers (not shown) are layered between the dielectric gate layer 82 and the gate electrode layer 84. The output function setting layers consist of a conductive material, such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC, or a multiple layer of two or more of these materials. In the n-channel FET, one or more of the compounds / elements TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi, and TaSi are used for the output function setting layer, and in the p-channel FET, one or more of the compounds / elements TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, and Co are used for the output function setting layer. The work function setting layer can be produced by ALD, PVD, CVD, electron beam evaporation or by any other suitable method.Furthermore, the output work setting layers for the n-channel FET and the p-channel FET can be manufactured separately, and different metal layers can be used for this purpose.

[0068] Subsequently, contact holes are produced in the ILD layer 70 by dry etching, exposing the upper part of the epitaxial S / D layer 50. In some embodiments, a silicide layer is produced over the epitaxial S / D layer 50. The silicide layer comprises one or more of the compounds WSi, CoSi, NiSi, TiSi, MoSi, and TaSi. Then, a conductive contact layer 72 is produced in the contact holes, as shown in the Fig. Figures 1A to 1D show the conductive contact layer 72 comprising one or more of the elements / compounds Co, Ni, W, Ti, Ta, Cu, Al, TiN, and TaN. A conductive contact pin 75 is also fabricated on the conductive contact layer 72. The conductive contact pin 75 comprises one or more layers of Co, Ni, W, Ti, Ta, Cu, Al, TiN, and TaN.

[0069] It is clear that the GAA-FETs undergo further CMOS processes to produce various structural elements, such as contacts / vias, metal compound layers, dielectric layers, passivation layers, etc.

[0070] The Fig. Figures 14A-14D to 25A-25D show different stages of the fabrication of a FET semiconductor device according to a further embodiment of the present invention. Fig. Figures 14A to 25D, designated with the letter A, are sectional views along the x-direction (source / drain direction); figures designated with the letter B are sectional views corresponding to the line Y1-Y1 of the respective figure designated with the letter A; figures designated with the letter C are sectional views corresponding to the line Y2-Y2 of the respective figure designated with the letter A; and figures designated with the letter D are sectional views corresponding to the line Y3-Y3 of the respective figure designated with the letter A. It is clear that further steps before, during, and after the [projects] described in the Fig. The processes shown in Figures 14A to 25D can be implemented, and some of the steps described below can be replaced or omitted in other embodiments of the method. The sequence of steps / processes is interchangeable. Materials, configurations, dimensions, and / or processes that are similar to those of the preceding embodiments, which are referenced in the above figures, are not subject to change without notice. Fig. 1A to 13D, which are the same or similar, can also be used in the embodiment of the Fig. 14A to 25D can be used, and their detailed description can be omitted.

[0071] The Fig. 14A to 14D are the same as the Fig. 4A to 4D, and the resulting structure produced by these manufacturing steps is described with reference to the Fig. Explained in sections 33 to 38.

[0072] In contrast to the steps taken in the Fig. As explained in sections 5A to 5D, source / drain etching is performed to selectively remove the first semiconductor layers 20, leaving the second semiconductor layers 25 in the S / D region, as shown in the Fig. Figures 15A to 15D are shown. The etching can be dry and / or wet. This creates an S / D gap 28 in which the second semiconductor layers 25 intersect laterally. In some embodiments, the substrate 10 (or the lower part of the fin structures 11) is not substantially etched.

[0073] Furthermore, similar to the steps involved in the Fig. As explained in sections 6A to 6D, the first semiconductor layers 20 are etched laterally in the x-direction in the S / D gap 28, creating cavities 22, as shown in the Fig. Figures 16A to 16D are shown. The etching quantity for the first semiconductor layers 20 is in the range of about 2 nm to about 10 nm in some embodiments. If the first semiconductor layers 20 consist of Ge or SiGe and the second semiconductor layers 25 consist of Si, the first semiconductor layers 20 can be selectively etched using a wet etching agent, such as solutions of hydrated ammonia (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH).

[0074] Similar to the Fig. In other embodiments 7A to 7D, by selecting a suitable crystal orientation for the first semiconductor layers 20 and an etching agent, the etched surface of the lateral ends of the first semiconductor layers 20 has a quadrilateral cavity 23 defined by (111) surfaces, as shown in the Fig. Figures 17A to 17D show that in the cross-section along the x-direction, the cavity 23 has a V-shape (or the shape of an open triangle), as shown in Fig. 17A is shown.

[0075] The following figures illustrate the manufacturing processes after the production of the components described in the... Fig. The structure shown in Figures 16A to 16D is explained. However, these steps can also be applied to the structure shown in the Fig. The structure shown in 17A to 17D can be used.

[0076] As in the Fig. As shown in Figures 18A to 18D, a first insulating layer 33 is conformally fabricated on the lateral ends of the first semiconductor layer 20 and on the second semiconductor layer 25 in the S / D gap 28. In this embodiment, the first insulating layer 33 surrounds the second semiconductor layers 25 in the S / D gap 28. The first insulating layer 33 comprises silicon nitride (SiN) or silicon oxide (SiO2) and has a thickness in the range of about 0.5 nm to about 3.0 nm. In other embodiments, the first insulating layer 33 has a thickness in the range of about 1.0 nm to about 2.0 nm. The first insulating layer 33 can be fabricated by ALD or by another suitable method. Conformally fabricating the first insulating layer 33 reduces the size of the cavity 22.

[0077] As in the Fig. As shown in Figures 19A to 19D, a second insulating layer 35 is then produced on the first insulating layer 33 in the S / D space 28. The second insulating layer 35 consists of suitable dielectric materials, such as silicon oxide, silicon nitride, fluorosilicate glass (FSG), low-k dielectrics such as carbon-doped oxides (SiOC, SiOCN), extremely low-k dielectrics such as porous carbon-doped silicon dioxide, a polymer such as polyimide, combinations thereof, or the like. In some embodiments, the second insulating layer 35 comprises one or more layers of a low-k dielectric material. In some embodiments, the second insulating layer 35 is produced such that it completely fills the remaining S / D space 28. In certain embodiments, the second insulating layer 35 does not completely fill the space between adjacent sacrificial gate structures (between opposing sidewalls), as shown in Figures 19A to 19D. Fig. Figure 19A shows the second insulating layer 35. It can be produced using a process such as CVD, flowable CVD (FCVD) or spin-on-glass, but another suitable method can also be used.

[0078] As in the Fig. As shown in Figures 20A to 20D, the second insulating layer 35 is then etched such that it is partially removed from the S / D gap 28. Since the first insulating layer 33 and the second insulating layer 35 are made of different materials, the first insulating layer 33 essentially remains on the second semiconductor layers 25. In some embodiments, the second insulating layer 35 remains on the side faces of the sacrificial gate structure (side wall 40), while in other embodiments it does not remain on the side faces of the sacrificial gate structure.

[0079] As in the Fig. As shown in Figures 21A to 21D, a portion of any remaining second insulating layer 35 and the first insulating layer 33, which is produced on the second semiconductor layer 25, are removed by a suitable etching process. This etching leaves the first insulating layer 33 and the second insulating layer 35 each within the cavities 22. In some embodiments, the end of the first insulating layer 33 protrudes from the second insulating layer 35 into the S / D gap 28 in the cavity 22.

[0080] As in the Fig. 22A to 22D is shown, similar to the Fig. Subsequently, an epitaxial S / D layer 50 is fabricated in the S / D space 28 at 10A to 10D. The epitaxial S / D layer 50 comprises one or more layers of Si, SiP, SiC, and SiCP for an n-channel FET or of Si, SiGe, and Ge for a p-channel FET. In the p-channel FET, boron (B) may also be included in the source / drain. The epitaxial S / D layer 50 is fabricated by epitaxial growth using CVD, ALD, or molecular beam epitaxy (MBE). As described in the Fig. As shown in Figures 22A to 22D, the epitaxial S / D layer 50 is brought into contact with the second semiconductor layers 25 and is produced in such a way that air gaps 37 are created between the epitaxial S / D layer 50 and the first and second insulating layers 33 and 35.

[0081] As in the Fig. As shown in Figures 23A to 23D, an interlayer dielectric layer (ILD layer) 70 is then fabricated over the epitaxial S / D layer 50. Materials for the ILD layer 70 include compounds containing Si, O, C, and / or H, such as silicon dioxide, SiCOH, and SiOC. Organic materials, such as polymers, can also be used for the ILD layer 70. After the ILD layer 70 has been fabricated, planarization, such as CMP, is performed to expose the upper part of the sacrificial gate electrode layer 42.

[0082] Then, similar or the same processes as those described with reference to the Fig. As described in sections 12A to 12D, the sacrificial gate electrode layer 42 and the dielectric sacrificial gate layer 41 are removed, and subsequently the first semiconductor layers 20 are removed, so that wires are formed from the second semiconductor layers 25, as described in the Fig. 24A to 24D is shown.

[0083] After the semiconductor wires have been manufactured from the second semiconductor layers 25, similar or the same processes are used as described with reference to the Fig. As described in sections 13A to 13D, a dielectric gate layer 82 is produced around each channel layer (wires of the second semiconductor layers 25), and a gate electrode layer 84 is produced on the dielectric gate layer 82, as described in the Fig. 25A to 25D is shown.

[0084] The Fig. Figures 26A to 26C show various configurations of a source / drain region according to some embodiments of the present invention. Fig. 26A to 26C are similar to Fig. 25D sectional views along the y-direction (gate orientation). In some embodiments, the epitaxial S / D layer 50 is fabricated on the second semiconductor layers 25, resulting in a rhombic shape over the second semiconductor layers 25, as shown in Fig. 26A. In some embodiments, the epitaxial S / D layer 50 is conformally produced epitaxially on the second semiconductor layers 25, as shown in Fig. 26B. In other embodiments, the epitaxial S / D layer 50 is produced epitaxially on the second semiconductor layers 25 such that an rhombic shape is formed over the second semiconductor layers 25 as a whole, as shown in Fig. Figure 26C shows that in certain embodiments the cross-section of the epitaxial S / D layer 50 has a hexagonal shape, another polygonal shape, or a semicircular shape.

[0085] It is clear that the GAA-FETs undergo further CMOS processes to produce various structural elements, such as contacts / vias, metal compound layers, dielectric layers, passivation layers, etc.

[0086] The Fig. Figures 27A-27D to 30A-30D show various stages of the fabrication of a FET semiconductor device according to a further embodiment of the present invention. Fig. Figures 27A to 30D, designated with the letter A, are sectional views along the x-direction (source / drain direction); figures designated with the letter B are sectional views corresponding to the line Y1-Y1 of the respective figure designated with the letter A; figures designated with the letter C are sectional views corresponding to the line Y2-Y2 of the respective figure designated with the letter A; and figures designated with the letter D are sectional views corresponding to the line Y3-Y3 of the respective figure designated with the letter A. It is clear that further steps before, during, and after the [projects] described in the Fig. The processes shown in 27A to 30D can be implemented, and some of the steps described below can be replaced or omitted in other embodiments of the method. The sequence of steps / processes is interchangeable. Materials, configurations, dimensions, and / or processes that are similar to those of the preceding embodiments, which are referenced in the Fig. 1A to 26D, which are the same or similar, may also be used in the embodiment of the Fig. 27A to 30D can be used, and their detailed description can be omitted.

[0087] After, as in the Fig. As shown in Figures 19A to 19D, after the second insulating layer 35 has been produced, a structural modification is carried out on the second insulating layer 35 to partially change its structure and / or properties. A modified layer 36, which is shown in the Fig. The second insulating layer 35, shown in Figures 27A to 27D, has a lower oxide density and / or a higher etch rate than the deposited second insulating layer 35. In some embodiments, ion implantation is performed on the second insulating layer 35. By implanting ions, for example, nitrogen ions, into the second insulating layer 35 from the top, the structure of the second insulating layer 35 is modified, with the exception of the portion of the second insulating layer 35 located beneath the sidewall spacers 40. Other ions, such as Ge, P, B, and / or As, can also be used. The ions are also implanted into the second semiconductor layer 25 in the S / D region.

[0088] As in the Fig. As shown in Figures 28A to 28D, the modified second insulating layer 36 is subsequently removed using a suitable etching method. In some embodiments, wet etching is used. Since the first insulating layer 33 and the second insulating layer 35 (the modified layer 36) are made of different materials, the first insulating layer 33 essentially remains on the second semiconductor layers 25. The ion implantation to modify the second insulating layer 35 and the removal of the modified layer 36 can be repeated so that the second insulating layer 35 is removed step by step.

[0089] Furthermore, similar to the Fig. In sections 21A to 21D, the first insulating layer 33, which is produced on the second semiconductor layer 25, is removed using a suitable etching process. After this etching, the first insulating layer 33 and the second insulating layer 35 each remain in the cavities 22, as shown in the Fig. Figures 29A to 29D are shown. In some embodiments, the end of the first insulating layer 33 protrudes from the second insulating layer 35 to the S / D gap 28 in the cavity 22.

[0090] Similar to the Fig. Subsequently, an epitaxial S / D layer 50 is produced in the S / D space 28 at 22A to 22D, and an interlayer dielectric layer (ILD layer) 70 is produced over the epitaxial S / D layer 50, as shown in the Fig. 30A to 30D are shown. As shown in the Fig. As shown in Figures 30A to 30D, the epitaxial S / D layer 50 is brought into contact with the second semiconductor layers 25 and is produced in such a way that air gaps 37 are created between the epitaxial S / D layer 50 and the first and second insulating layers 33 and 35.

[0091] Then, similar or the same processes as those described with reference to the Fig. 12A to 12D and the Fig. As described in sections 24A to 24D, the sacrificial gate electrode layer 42 and the dielectric sacrificial gate layer 41 are removed. After the semiconductor wires have been fabricated from the second semiconductor layers 25, similar or the same processes as described in the Fig. 13A to 13D and the Fig. As described in sections 25A to 25D, a dielectric gate layer 82 is produced around each channel layer (wires of the second semiconductor layers 25), and a gate electrode layer 84 is produced on the dielectric gate layer 82.

[0092] It is clear that the GAA-FETs undergo further CMOS processes to produce various structural elements, such as contacts / vias, metal compound layers, dielectric layers, passivation layers, etc.

[0093] The Fig. 31A and Fig. Figure 31B shows various configurations of a FET semiconductor device according to embodiments of the present invention.

[0094] In Fig. 31A is after the lateral etching of the second semiconductor layer 25, which is with reference to the Fig. As described in Figures 16A to 16D, the width W2 of the second semiconductor layer 25 is equal to or less than the width W1 of the sacrificial gate electrode 42. Therefore, after fabrication of the metal gate electrode 84, the gate length Lg2 (along the x-direction) at the lower part of the gate electrode 84 (between the semiconductors 25) is equal to or less than the gate length Lg1 (along the x-direction) at the upper part of the gate electrode 84, as described in Figures 16A to 16D. Fig. 31B is shown.

[0095] In Fig. 32A is after the lateral etching of the second semiconductor layer 25, which is with reference to the Fig. As described in 16A to 16D, the width W2' of the second semiconductor layer 25 is greater than the width W1' of the sacrificial gate electrode 42. In some embodiments, the sidewall spacers 40 are manufactured such that they have a greater thickness than described in 16A to 16D. Fig. 31A. In certain embodiments, the thickness of the sidewall spacers 40 is in the range of approximately 5 nm to approximately 15 nm, and in other embodiments in the range of approximately 6 nm to 10 nm. Furthermore, it is possible to adjust the width of the sacrificial gate electrode 42 and / or the lateral etching quantity of the second semiconductor layers 25. Therefore, after fabrication of the metal gate electrode 84, the gate length Lg2' at the lower part of the gate electrode 84 is greater than the gate length Lg1' (along the x-direction) at the upper part of the gate electrode 84, as shown in Fig.Figure 32B shows that in some embodiments the ratio W2' / W1' is in the range of approximately 1.2 to approximately 1.5, and the ratio Lg2' / Lg1' is also in the range of approximately 1.2 to approximately 1.5. By adjusting Lg2' to be larger than Lg1', the effective gate length can be increased, and the gate control can be improved.

[0096] The various embodiments or examples described herein offer several advantages over the prior art. For example, since the internal spacer areas in the present invention have an air gap, the capacitance can be reduced. Furthermore, by using a first insulating layer as an etch stop layer, it is possible to control the etching of the first semiconductor layers more precisely when the nanowires are fabricated. With the aforementioned embodiments, it is possible to control the thickness, shape, and / or position of the internal spacers more precisely, thereby controlling the capacitances around the S / D area and the gate.

[0097] According to one aspect of the present invention, a method for manufacturing a semiconductor device involves producing a fin structure in which first semiconductor layers and second semiconductor layers are stacked alternately. A sacrificial gate structure is fabricated over the fin structure. A source / drain region of the fin structure, not covered by the sacrificial gate structure, is etched, creating a source / drain gap. The first semiconductor layers are etched laterally through the source / drain gap. A first insulating layer is fabricated in the source / drain gap, at least on the etched first semiconductor layers. An epitaxial source / drain layer is fabricated in the source / drain gap, creating air gaps between the epitaxial source / drain layer and the first semiconductor layers.In one or more of the preceding or following embodiments, the air gaps are defined by the epitaxial source / drain layer and the first insulating layer, which is arranged on a lateral end of one of the first semiconductor layers and on two adjacent second semiconductor layers. In one or more of the preceding or following embodiments, the lateral end of one of the first semiconductor layers has a flat surface. In one or more of the preceding or following embodiments, the lateral end of one of the first semiconductor layers has a V-shaped cross-section. In one or more of the preceding or following embodiments, the first insulating layer comprises silicon nitride and / or silicon oxide. In one or more of the preceding or following embodiments, a second insulating layer is further produced on top of the first insulating layer.The air gaps are defined by the epitaxial source / drain layer and the second insulating layer. In one or more of the preceding or following embodiments, the second insulating layer comprises a dielectric low-k material. In one or more of the preceding or following embodiments, after fabrication of the epitaxial source / drain layer, the sacrificial gate structure is removed, exposing part of the fin structure. The first semiconductor layers are removed from the exposed fin structure, creating channel layers that encompass the second semiconductor layers. A dielectric gate layer and a gate electrode layer are fabricated around the channel layers. In one or more of the preceding or following embodiments, the gate electrode layer is separated from the epitaxial source / drain layer by the air gaps and the first insulating layer.In one or more of the preceding or following embodiments, the first semiconductor layers consist of SiGe, and the second semiconductor layers consist of Si.

[0098] According to a further aspect of the present invention, a method for manufacturing a semiconductor device involves producing a fin structure in which first semiconductor layers and second semiconductor layers are stacked alternately. A sacrificial gate structure is fabricated over the fin structure. The first semiconductor layers are removed from a source / drain region of the fin structure that is not covered by the sacrificial gate structure. A first insulating layer is fabricated around the second semiconductor layers in the source / drain region and on the lateral ends of the first semiconductor layers. The first insulating layer is partially removed from the second semiconductor layers in the source / drain region. An epitaxial source / drain layer is fabricated on the source / drain region, creating air gaps between the epitaxial source / drain layer and the lateral ends of the first semiconductor layers.In one or more of the preceding or following embodiments, the first semiconductor layers are etched laterally beneath the sacrificial gate structure during removal. In one or more of the preceding or following embodiments, a second insulating layer is produced on top of the first insulating layer after the first insulating layer has been produced and before the first insulating layer has been partially removed, and the second insulating layer is partially etched. The air gaps are defined at least by the epitaxial source / drain layer and the second insulating layer. In one or more of the preceding or following embodiments, the structure of the second insulating layer is partially modified before the second insulating layer is partially etched. In one or more of the preceding or following embodiments, the structure of the second insulating layer is partially modified by ion implantation.In one or more of the preceding or following embodiments, the second insulating layer comprises a dielectric low-k material. In one or more of the preceding or following embodiments, the first insulating layer comprises silicon nitride and / or silicon oxide deposited by atomic layer deposition.

[0099] According to a further aspect of the present invention, a method for manufacturing a semiconductor device involves producing a fin structure in which first semiconductor layers and second semiconductor layers are stacked alternately. A sacrificial gate structure is produced above the fin structure. At least the first semiconductor layers are partially removed from a source / drain region of the fin structure that is not covered by the sacrificial gate structure. A first insulating layer is produced at least on the lateral ends of the first semiconductor layers. A second insulating layer is produced on the first semiconductor layers. An epitaxial source / drain layer is produced in contact with the second semiconductor layers.In one or more of the preceding or following embodiments, after the formation of the epitaxial source / drain layer, the sacrificial gate structure is removed, exposing part of the fin structure. The first semiconductor layers are removed from the exposed fin structure, creating channel layers that encompass the second semiconductor layers. A dielectric gate layer and a gate electrode layer are formed around the channel layers. In one or more of the preceding or following embodiments, the gate electrode layer is separated from the epitaxial source / drain layer by the first and second insulating layers.

[0100] According to one aspect of the present invention, a semiconductor device comprises: semiconductor wires arranged over a substrate; a source / drain region in contact with the semiconductor wires; a dielectric gate layer arranged on and surrounding each channel region of the semiconductor wires; a gate electrode layer arranged on the dielectric gate layer and surrounding each channel region; first insulating spacers arranged in the spaces between; and air gaps arranged in the spaces between. The spaces between are defined by adjacent semiconductor wires, the gate electrode layer, and the source / drain region. In one or more of the foregoing or following embodiments, the semiconductor device further comprises second insulating spacers arranged in the spaces between.In one or more of the preceding or following embodiments, the second insulating spacers consist of a dielectric low-k material. In one or more of the preceding or following embodiments, the first insulating spacers consist of at least one compound from the SiO₂ and SiN group. In one or more of the preceding or following embodiments, the first insulating spacers each have a V-shaped cross-section. In one or more of the preceding or following embodiments, the source / drain region and the gate electrode layer are separated by the first insulating spacers, the air gaps, and a dielectric gate layer. In one or more of the preceding or following embodiments, the source / drain region is in contact with the ends of the semiconductor wires.In one or more of the preceding or following embodiments, the source / drain region encloses parts of the semiconductor wires.

[0101] According to a further aspect of the present invention, a semiconductor device comprises: semiconductor wires arranged over a substrate; an epitaxial source / drain layer enclosing source / drain regions of the semiconductor wires; a dielectric gate layer arranged on and enclosing each channel region of the semiconductor wires; a gate electrode layer arranged on the dielectric gate layer and enclosing each channel region; first insulating spacers arranged in interstitial spaces; and air gaps arranged in interstitial spaces. The interstitial spaces are defined by adjacent semiconductor wires, the gate electrode layer, and the source / drain region. In one or more of the preceding or following embodiments, the semiconductor wires are made of SiGe or Ge.In one or more of the preceding or following embodiments, the semiconductor device further comprises second insulating spacers, each arranged in the gaps. In one or more of the preceding or following embodiments, the air gaps are in contact with the source / drain region. In one or more of the preceding or following embodiments, the second insulating spacers consist of a dielectric low-k material. In one or more of the preceding or following embodiments, the first insulating spacers consist of at least one compound from the SiO₂ and SiN group. In one or more of the preceding or following embodiments, the first insulating spacers each have a V-shaped cross-section.In one or more of the preceding or following embodiments, the source / drain region and the gate electrode layer are separated by the first insulating spacers, the air gaps and the dielectric gate layer.

[0102] According to a further aspect of the present invention, a semiconductor device comprises: semiconductor wires arranged over a substrate; an epitaxial source / drain layer enclosing source / drain regions of the semiconductor wires; a dielectric gate layer arranged on and enclosing each channel region of the semiconductor wires; a gate electrode layer arranged on the dielectric gate layer and enclosing each channel region; first insulating spacers arranged in interstitial spaces; and second insulating spacers arranged in interstitial spaces. The interstitial spaces are defined by adjacent semiconductor wires, the gate electrode layer, and the source / drain region. In one or more of the preceding or following embodiments, the first insulating spacers consist of at least one compound from the SiO₂ and SiN group.In one or more of the preceding or following embodiments, the second insulating spacers consist of at least one compound from the SiOC and SiOCN group.

Claims

[1] A method of manufacturing a semiconductor device comprising the following steps: Producing a fin structure (29) in which first semiconductor layers (20) and second semiconductor layers (25) are alternately stacked on top of one another; Producing a sacrificial gate structure (49) over the fin structure (29); Etching a source / drain region of the fin structure (29) that is not covered by the sacrificial gate structure (49) to form a source / drain gap (27); lateral etching of the first semiconductor layers (20) through the source / drain gap (27), wherein by selecting an appropriate crystal orientation for the first semiconductor layers (20) and an etchant, the etched surface of the lateral ends of the first semiconductor layers (20) has a V-shaped cross-section; Producing a first insulating layer (33) in the source / drain gap (27) at least on the etched first semiconductor layers (20); and Producing an epitaxial source / drain layer (50) in the source / drain gap (27) such that air gaps (37) are formed between the epitaxial source / drain layer (50) and the first semiconductor layers (20). [2] The method of claim 1, wherein the air gaps (37) are each defined by the epitaxial source / drain layer (50) and the first insulating layer (33) disposed on a lateral end of one of the first semiconductor layers (20) and on two adjacent second semiconductor layers (25). [3] The method of claim 2, wherein the air gaps (37) are in direct contact with the epitaxial source / drain layer (50). [4] The method according to claim 2 or 3, wherein a width (Wa) of the air gaps (37) is in the range of 0.5 nm to 2.0 nm. [5] Method according to one of the preceding claims, wherein the first insulating layer (33) comprises silicon nitride and / or silicon oxide. [6] A method according to any one of the preceding claims, further comprising forming a second insulating layer (35) on the first insulating layer (33), wherein the air gaps (37) are defined by the epitaxial source / drain layer (50) and the second insulating layer (35), respectively. [7] The method of claim 6, wherein the second insulating layer (35) comprises a low-k dielectric material. [8] A method according to any one of the preceding claims, further comprising, after forming the epitaxial source / drain layer (50): Removing the sacrificial gate structure (49) so that a part of the fin structure (29) is exposed; Removing the first semiconductor layers (20) from the exposed fin structure (29) to form channel layers comprising the second semiconductor layers (25); and Forming a gate dielectric layer (41) and a gate electrode layer (42) around the channel layers. [9] The method of claim 8, wherein the gate electrode layer (42) is separated from the epitaxial source / drain layer (50) by the air gaps (37) and the first insulating layer (33). [10] Method according to one of the preceding claims, wherein the first semiconductor layers (20) consist of SiGe, and the second semiconductor layers (25) consist of Si. [11] A method of manufacturing a semiconductor device comprising the following steps: Producing a fin structure (29) in which first semiconductor layers (20) and second semiconductor layers (25) are alternately stacked on top of one another; Producing a sacrificial gate structure (49) over the fin structure (29); Removing the first semiconductor layers (20) from a source / drain region (28) of the fin structure (29) that is not covered by the sacrificial gate structure (49); Producing a first insulating layer (33) around the second semiconductor layers (25) in the source / drain region (28) and on lateral ends of the first semiconductor layers (20); Producing a second insulating layer (35) on the first insulating layer (33); partially modifying a structure of the second insulating layer (35), wherein the structure of the second insulating layer (35) is partially modified by ion implantation; etching the second insulating layer (35); partially removing the first insulating layer (33) from the second semiconductor layers (25) in the source / drain region (28); and Producing an epitaxial source / drain layer (50) on the source / drain region (28) so that air gaps (37) are formed between the epitaxial source / drain layer (50) and the lateral ends of the first semiconductor layers (20), wherein the air gaps (37) are each defined at least by the epitaxial source / drain layer (50) and the second insulating layer (35). [12] Method according to claim 11, wherein, when removing the first semiconductor layers (20), they are etched laterally under the sacrificial gate structure (49). [13] The method according to claim 11 or 12, wherein a width (Wa) of the air gaps (37) is in the range of 0.5 nm to 2.0 nm. [14] The method of claim 11, 12 or 13, wherein the second insulating layer (35) comprises a low-k dielectric material. [15] A method according to any one of claims 11 to 14, wherein the first insulating layer (33) comprises silicon nitride and / or silicon oxide deposited by atomic layer deposition. [16] Semiconductor device comprising: semiconductor wires (25) arranged above a substrate (10); a source / drain region (50) in contact with the semiconductor wires (25); a dielectric gate layer (82) disposed on and surrounding each channel region of the semiconductor wires (25); a gate electrode layer (84) disposed on the gate dielectric layer (82) and surrounding each channel region; first insulating spacers, each arranged in spaces, wherein the spaces are defined by adjacent semiconductor wires (25), the gate electrode layer (84), and the source / drain region (50); and wherein the first insulating spacers each have a first insulating layer (33) and an air gap (37), and wherein the first insulating spacers each have a V-shaped cross-section, and wherein the air gap (37) is in direct contact with the source / drain region (50). [17] A semiconductor device according to claim 16, further comprising second insulating spacers each disposed in said gaps and each having a V-shaped cross section. [18] A semiconductor device according to claim 16, wherein the first insulating spacers consist of at least one compound selected from the group consisting of silicon nitride (SiN) and / or silicon oxide (SiO2). [19] The semiconductor device according to claim 17, wherein the second insulating spacers consist of at least one compound selected from the group consisting of SiOC and SiOCN.

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