METHOD FOR MAKING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Abstract

Method for manufacturing a semiconductor device, comprising: Forming a fin structure (29) in which first semiconductor layers (20) and second semiconductor layers (25) are stacked alternately; Forming a victim-gate structure (38) over the fin structure (29); Etching of the first semiconductor layers (20), the second semiconductor layers (25) and an upper section of a trough section (11) of the fin structure (29) at a source / drain region of the fin structure (29) that is not covered by the sacrificial gate structure (38); Forming a dielectric layer (35) over the etched section of the tub section (11), and Forming an epitaxial source / drain layer (50), wherein: the epitaxial source / drain layer (50) is connected to the ends of the second semiconductor layers (25), and a bottom of the epitaxial source / drain layer (50) is separated from the trough section (11) by the dielectric layer (35).

Description

TECHNICAL FIELD

[0001] The invention relates to a method for manufacturing semiconductor integrated circuits and, in particular, to a method for manufacturing semiconductor devices comprising fin field-effect transistors (FinFETs) and / or gate-all-around (GAA) FETs, and to semiconductor devices. STATE OF THE ART

[0002] As the semiconductor industry has evolved into nanometer technology process nodes in search of higher device density, higher performance, and lower cost, challenges have arisen in both manufacturing and design issues when developing three-dimensional designs, such as a multi-gate field-effect transistor (FET) featuring a FinFET (FinFET). In a FinFET, a gate electrode is adjacent to three side surfaces of a channel region with a gate dielectric layer in between. Because the gate structure surrounds (wraps) the fin on three surfaces, the transistor essentially has three gates that control the current through the fin or channel region. Unfortunately, the fourth side, the bottom portion of the channel, is far from the gate electrode and therefore not under close gate control.In contrast, in a GAA-FET, all side surfaces of the channel region are surrounded by the gate electrode, allowing for fuller depletion in the channel region and resulting in fewer short-channel effects due to steeper subthreshold current swing (SS) and smaller drain-induced barrier lowering (DIBL). As transistor dimensions are continuously scaled down to 10-15 nanometer subtechnology nodes, further improvements to GAA-FETs are required.

[0003] US 2014 / 0 312 432 A1 discloses a method for manufacturing a semiconductor device having fin structures with alternately stacked semiconductor layers and source / drain regions, wherein the source / drain regions are separated from well regions of the fin structures by insulation structures.

[0004] Similar methods are also known from US 9 590 038 B1 and US 2017 / 0 194 213 A1. Further methods for manufacturing semiconductor devices are known, for example, from US 9 660 028 B1, WO 2016 / 209 285 A1, and WO 2016 / 209 210 A1. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The present invention is best understood by reading the following detailed description with reference to the accompanying figures. It is emphasized that, in accordance with standard industry practice, various elements are not drawn to scale and are used for illustrative purposes only. Indeed, the dimensions of the various elements may be arbitrarily exaggerated or reduced for clarity of discussion. Fig. 1 A shows a perspective view, and the Fig. 1B and Fig. 1C show cross-sectional views of a FET semiconductor device according to an embodiment of the present invention. Fig. 1D and Fig. 1E show enlarged cross-sectional views showing AR1 of the Fig. 1a and Fig. 1B, and Fig. Figure 1F shows an enlarged cross-sectional view showing AR2 of the Fig. 1a and Fig. 1C corresponds. Fig. 1 A shows a perspective view, and the Fig. 2B and Fig. 2C show cross-sectional views of a FET semiconductor device according to an embodiment of the present invention. Fig. 2D and Fig. 2E show enlarged cross-sectional views showing AR1 of the Fig. 2A and Fig. 2B, and Fig. Figure 2F shows an enlarged cross-sectional view showing AR2 of the Fig. 2A and Fig. 2C corresponds. Fig. 3A shows a perspective view, and the Fig. 3B and Fig. 3C show cross-sectional views of a FET semiconductor device according to an embodiment of the present invention. Fig. 3D shows an enlarged cross-sectional view showing AR1 of the Fig. 3A and Fig. 3B, and Fig. Figure 3E shows an enlarged cross-sectional view showing AR2 of the Fig. 3A and Fig. 3C corresponds. Fig. 4A shows a perspective view, and the Fig. 4B and Fig. 4C show cross-sectional views of a FET semiconductor device according to an embodiment of the present invention. Fig. Figure 4D shows an enlarged cross-sectional view showing AR1 of the Fig. 4A and Fig. 4B, and Fig. Figure 4E shows an enlarged cross-sectional view showing AR2 of the Fig. 4A and Fig. 4C corresponds. Fig. 5 shows one of the various stages of fabricating a semiconductor FET device according to an embodiment of the present invention. Fig. 6 shows one of the various stages of fabricating a semiconductor FET device according to an embodiment of the present invention. Fig. 7 shows one of the various stages of fabricating a semiconductor FET device according to an embodiment of the present invention. Fig. 8 shows one of the various stages of fabricating a semiconductor FET device according to an embodiment of the present invention. The Fig. 9A, Fig. 9B and Fig. 9C illustrate one of the various stages of fabricating a semiconductor FET device according to embodiments of the present invention. The Fig. 10A, Fig. 10B and Fig. 10C illustrate one of the various stages of fabricating a semiconductor FET device according to an embodiment of the present invention. The Fig. 11A, Fig. 11B and Fig. 11C illustrate one of the various stages of fabricating a semiconductor FET device according to an embodiment of the present invention. The Fig. 12A, Fig. 12B and Fig. 12C illustrate one of the various stages of fabricating a semiconductor FET device according to an embodiment of the present invention. The Fig. 13A, Fig. 13B and Fig. 13C illustrate one of the various stages of fabricating a semiconductor FET device according to an embodiment of the present invention. The Fig. 14A, Fig. 14B and Fig. 14C illustrate one of the various stages of fabricating a semiconductor FET device according to an embodiment of the present invention. The Fig. 15A, Fig. 15B and Fig. 15C illustrate one of the various stages of fabricating a semiconductor FET device according to an embodiment of the present invention. The Fig. 16A, Fig. 16B and Fig. 16C illustrate one of the various stages of fabricating a semiconductor FET device according to an embodiment of the present invention. The Fig. 17A, Fig. 17B and Fig. 17C illustrate one of the various stages of fabricating a semiconductor FET device according to an embodiment of the present invention. The Fig. 18A, Fig. 18B and Fig. 18C illustrate one of the various stages of fabricating a semiconductor FET device according to an embodiment of the present invention. The Fig. 19A, Fig. 19B and Fig. 1C show one of the various stages of fabricating a semiconductor FET device according to an embodiment of the present invention. The Fig. 20A, Fig. 20B and Fig. 20C illustrate one of the various stages of fabricating a semiconductor FET device according to an embodiment of the present invention. Fig. 20D shows one of the various stages of fabricating a semiconductor FET device according to another embodiment of the present invention. Fig. 21 shows one of the various stages of fabricating a semiconductor FET device according to an embodiment of the present invention. Fig. 22 shows one of the various stages of fabricating a semiconductor FET device according to an embodiment of the present invention. Fig. 23 shows one of the various stages of fabricating a semiconductor FET device according to an embodiment of the present invention. Fig. 24 shows one of the various stages of fabricating a semiconductor FET device according to an embodiment of the present invention. The Fig. 25A, Fig. 25B and Fig. 25C show one of the various stages of fabricating a semiconductor FET device according to another embodiment of the present invention. The Fig. 26A, Fig. 26B and Fig. 26C show one of the various stages of fabricating a semiconductor FET device according to another embodiment of the present invention. The Fig. 27A, Fig. 27B and Fig. 27C show one of the various stages of fabricating a semiconductor FET device according to another embodiment of the present invention. The Fig. 28A, Fig. 28B and Fig. 28C show one of the various stages of fabricating a semiconductor FET device according to another embodiment of the present invention. The Fig. 29A, Fig. 29B and Fig. 29C show one of the various stages of fabricating a semiconductor FET device according to another embodiment of the present invention. The Fig. 30A, Fig. 30B and Fig. 30C illustrate one of the various stages of fabricating a semiconductor FET device according to another embodiment of the present invention. The Fig. 31A, Fig. 31B and Fig. 31C show one of the various stages of fabricating a semiconductor FET device according to another embodiment of the present invention. The Fig. 32A, Fig. 32B and Fig. 32C show one of the various stages of fabricating a semiconductor FET device according to another embodiment of the present invention. The Fig. 33A, Fig. 33B and Fig. 33C show one of the various stages of fabricating a semiconductor FET device according to another embodiment of the present invention. The Fig. 34A, Fig. 34B and Fig. 34C show one of the various stages of fabricating a semiconductor FET device according to another embodiment of the present invention. The Fig. 35A, Fig. 35B and Fig. 35C show one of the various stages of fabricating a semiconductor FET device according to another embodiment of the present invention. The Fig. 36A, Fig. 36B and Fig. 36D show one of the various stages of fabricating a semiconductor FET device according to another embodiment of the present invention. The Fig. 37A, Fig. 37 and Fig. 37C show one of the various stages of fabricating a semiconductor FET device according to another embodiment of the present invention. The Fig. 38A, Fig. 38B and Fig. 38C show one of the various stages of fabricating a semiconductor FET device according to another embodiment of the present invention. The Fig. 39A, Fig. 39B and Fig. 39C show one of the various stages of fabricating a semiconductor FET device according to another embodiment of the present invention. The Fig. 40A, Fig. 40B and Fig. 40C show one of the various stages of fabricating a semiconductor FET device according to another embodiment of the present invention. The Fig. 41A, Fig. 41B and Fig. 41C show one of the various stages of fabricating a semiconductor FET device according to another embodiment of the present invention. The Fig. 42A, Fig. 42B and Fig. 42C show one of the various stages of fabricating a semiconductor FET device according to another embodiment of the present invention. The Fig. 43A, Fig. 43B and Fig. 43C show one of the various stages of fabricating a semiconductor FET device according to another embodiment of the present invention. The Fig. 44A, Fig. 44B and Fig. 44C show one of the various stages of fabricating a semiconductor FET device according to another embodiment of the present invention. DETAILED DESCRIPTION

[0006] The present invention provides methods for manufacturing a semiconductor device having the features of claims 1 and 13, respectively, and a semiconductor device having the features of claim 18. Exemplary embodiments are specified in the dependent claims.

[0007] It should be understood that the following disclosure discloses many different embodiments or examples for implementing various features of the invention. Specific embodiments or examples of components and devices are described below to simplify the present disclosure. These are, of course, only examples. For example, the dimensions of features are not limited to the disclosed range or values, but may depend on process circumstances and / or desired device characteristics.The formation of a first feature over or on a second feature in the following description may also include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed interposed between the first and second features such that the first and second features may not be in direct contact. Various features may be arbitrarily drawn at different scales for simplicity and clarity.

[0008] Furthermore, spatial reference terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein for ease of description to describe the relationship of one feature or features to one or more other features or features as illustrated in the FIGS. The spatial reference terms may be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the FIGS. The device may be oriented differently (rotated 90 degrees or at other orientations), and the spatial reference descriptors used herein will be interpreted accordingly. Additionally, the term "made of" can mean either "including" or "consisting of."In the present disclosure, a phrase "one of A, B, and C" means "A, B, and / or C" (A; B; C; A and B; A and C; B and C; or A, B, and C), and does not mean an element of A, an element of B, and an element of C, unless otherwise described.

[0009] A gate-all-around FET (GAA-FET) generally comprises one or more semiconductor wires, each having a channel region and source / drain regions located at either end of the channel region. To fabricate the semiconductor wire(s), stacked layers of different semiconductor materials, one of which is a sacrificial layer, are formed, and then the sacrificial layer(s) are removed, leaving the semiconductor wire(s). An epitaxial source / drain layer is formed in the source / drain regions to be connected to the channel regions (semiconductor wires). In such a structure, eliminating leakage current from the epitaxial source / drain layer is a significant problem for transistor performance. In some cases, anti-punch-through (APT) implantation is used on the fin structure to reduce leakage current.However, APT impurities can diffuse into the channel region through subsequent thermal processes, affecting channel mobility and degrading transistor performance.

[0010] The present invention provides a semiconductor device, such as a GAA FET, that can reduce leakage current. In this disclosure, source / drain refers to a source and / or a drain. Note that in this disclosure, a source and a drain are used interchangeably, and their structures are essentially the same unless otherwise described.

[0011] Fig. 1 A shows a perspective view, and the Fig. 1B and Fig. 1C show cross-sectional views of an n-type GAA-FET semiconductor device according to an embodiment of the present invention.

[0012] As in Fig. 1, a GAA-FET is arranged over a substrate 10. In the GAA-FET, semiconductor wires 25 are provided over the semiconductor substrate 10 and arranged vertically along the Z direction (the normal direction of the main surface of the substrate 10). In some embodiments, the substrate 10 has a single-crystal semiconductor layer at least on its surface portion. The substrate 10 may comprise a single-crystal semiconductor material such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In certain embodiments, the substrate 10 is made of crystalline Si.

[0013] The substrate 10 may have one or more buffer layers (not shown) on its surface region. The buffer layers may serve to gradually change the lattice constant from that of the substrate to that of the source / drain regions. The buffer layers may be formed from epitaxially grown single-crystal semiconductor materials, such as, but not limited to, Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP. In a particular embodiment, the substrate 10 includes epitaxially grown silicon-germanium (SiGe) buffer layers on the silicon substrate 10. The germanium concentration of the SiGe buffer layers may also increase from 30 atomic percent germanium for the bottommost buffer layer to 70 atomic percent germanium for the topmost buffer layer.

[0014] In the GAA-FET, the semiconductor wires 25, which are channel layers, are arranged over the substrate 10. In some embodiments, the semiconductor wires 25 are made of Si. In other embodiments, the semiconductor wires 25 are made of Si 1-x Ge x , where 0 ≤ x ≤ 0.3. In some embodiments, the semiconductor wires 25 are arranged over a well portion 11 protruding from the substrate 10. The well portion 11 is embedded in an isolation insulating layer 15. The well portion 11 is covered by a first fin liner layer 13A and a second fin liner layer 13B arranged over the first fin liner layer 13A. The fin liner layers are made of silicon oxide, SiN, or a silicon nitride-based material (e.g., SiON, SiCN, or SiOCN).

[0015] Each of the channel layers 25 is surrounded by a gate dielectric layer 102 and a gate electrode layer 104. In some embodiments, the gate dielectric layer 102 includes an interface layer 102A and a high-k dielectric layer 102B. The gate structure includes the gate dielectric layer 102, the gate electrode layer 104, and sidewall spacers 32. Although Fig. 1 shows five semiconductor wires 25, the number of semiconductor wires 25 is not limited to five, and may be as small as one or more than five and may be up to fifteen (15).

[0016] In certain embodiments of the present invention, one or more work function matching layers 104A and 104B are inserted between the gate dielectric layer 102 and the gate electrode layer 104C.

[0017] In the GAA-FET, an epitaxial source / drain layer 50 is disposed over the well section 11. The epitaxial source / drain layer 50 comprises one or more layers of Si, SiP, SiC, and SiCP for an n-channel FET. The epitaxial source / drain layer 50 is in direct contact with the channel layer 25 and is separated from the gate electrode layer 104 by a dielectric layer 35 as an internal spacer and the gate dielectric layer 102. The dielectric layer 35, in some embodiments, is made of a low-k (dielectric constant lower than the dielectric constant of SiO2) material. The low-k material includes SiOC, SiOCN, organic material, porous material, or any other suitable material. In other embodiments, the dielectric layer 35 is made of silicon oxide and / or silicon nitride, or any other suitable dielectric material.

[0018] Furthermore, a contact etch stop layer (CESL) 60 is formed over the epitaxial source / drain layer 50 and sidewall spacers 32, and an interlayer dielectric (ILD) layer 80 is disposed over the CESL 60. The CESL 60 is made of SiN or a silicon nitride-based material (e.g., SiON, SiCN, or SiOCN). Materials for the ILD layer 80 include compounds including Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials, such as polymers, can be used for the ILD layer 80.

[0019] In the present invention, as shown in the Fig. As shown in Figures 1A to 1C, the semiconductor wires 25 and the epitaxial source / drain layer 50 are disposed above the well portion 11, and a bottom surface of the epitaxial source / drain layer 50 is separated from the well portion 11 by the dielectric layer 35. Furthermore, the same dielectric layer 35 is used as an inner spacer between the epitaxial source / drain layer 50 and the gate electrode 104.

[0020] Below the epitaxial source / drain layer 50, the uppermost portion of the well portion 11 is recessed to have a groove in which the dielectric layer 35 is disposed. In the present invention, the groove has a unique structure.

[0021] The Fig. 1D and Fig. 1E show enlarged cross-sectional views of the groove along the X direction (source to drain direction) that AR1 of the Fig. 1A and Fig. 1B, and Fig. Figure 1F shows an enlarged cross-sectional view of the groove along the Y direction (gate extension direction) that AR2 of the Fig. 1A and Fig. 1C corresponds.

[0022] As explained below with reference to the Fig. 5 to 20C, the groove 18 has a V-shaped groove and in particular has a “double-etched profile” caused by two dry etching processes performed at different process steps, as shown in the Fig. 1D and Fig. 1E. In some embodiments, as shown in Fig. 1D, the dielectric layer 35 filled in the groove 18 has a height (highest position measured from the bottom of the groove) corresponding to the interface between the lowest-positioned gate electrode 104 and the lowest-positioned semiconductor wire 25. In other embodiments, the dielectric layer 35 filled in the groove 18 has the height corresponding to the bottom of the lowest-positioned gate electrode 104 or lower, as shown in Fig. 1E. The height of the dielectric layer 35 can be varied between the cases of Fig. 1D and Fig. 1E. The dielectric layer 35 is connected to the inner spacer formed at the end of the lowermost gate electrode 104.

[0023] As in Fig. 1E, the groove has a depth D11, which in some embodiments is in a range of about 5 nm to about 50 nm, a top width W11, which in some embodiments is in a range of about 10 nm to about 50 nm, and a base width W12, which in some embodiments is in a range of about 1 nm to about 10 nm, all in the X-direction. In Fig. 1E, the groove 18 has a step at its center. The location of the step D12, measured from the top of the groove, is in a range from about 2 nm to about 40 nm in some embodiments, and the width W13 at the step is in a range from about 5 nm to about 25 nm in some embodiments. The sidewall of the groove 18 has a wall angle with respect to the Z-axis that changes from small to large to small starting at the bottom of the groove. Even if the dielectric layer 35 filled in the groove 18 has a height that is lower than the bottom of the lowermost gate electrode 104, the distance W14 between the gate electrode 104 and the dielectric layer 35 is less than about 1 nm. In contrast, in the cross-section along the Y-direction, as shown in Fig. As shown in Figure 1F, the groove 18 has a U-shape.

[0024] Fig. 2A shows a perspective view, and the Fig. 2B and Fig. 2C show cross-sectional views of an n-type GAA-FET device according to another embodiment of the present invention. Fig. 2D and Fig. 2E show enlarged cross-sectional views showing AR1 of the Fig. 2A and Fig. 2B, and Fig. Figure 2F shows an enlarged cross-sectional view showing AR2 of the Fig. 2A and Fig. 2C. The material, configuration, dimensions and / or processes are the same as in the above embodiments described with reference to the Fig. 1A to 1F, or similar, can be used in the embodiment of the Fig. 2A to 2F, and a detailed explanation can be omitted.

[0025] The gate structure and the source / drain structures of the n-type GAA FET used in the Fig. 2A to 2C are essentially the same as those of the n-type GAA-FET shown in the Fig. 1A to 1C, except for the shape of the groove 18 formed at the upper portion of the tub portion 11.

[0026] As explained below with reference to the Fig. 25A to 30C, the groove 18 is formed by using wet etching, and therefore has a (111) facet on its side walls, as shown in the Fig. 2D and Fig. 2E. In some embodiments, as shown in Fig. As shown in Figure 2D, the dielectric layer 35 filled in the groove 18 has a height (highest position measured from the bottom of the groove) corresponding to the interface between the lowest-positioned gate electrode 104 and the lowest-positioned semiconductor wire 25. In other embodiments, the dielectric layer 35 filled in the groove 18 has a height corresponding to the bottom of the lowest-positioned gate electrode 104 or lower, as shown in Figure 2D. Fig. 2E. The height of the dielectric layer 35 can be varied between the cases of Fig. 2D and Fig. 2E. The dielectric layer 35 is connected to the inner spacer formed at the end of the lowermost gate electrode 104.

[0027] As in Fig. 2E, the groove has a depth D21, which in some embodiments is in a range of about 5 nm to about 50 nm, a top width W21, which in some embodiments is in a range of about 10 nm to about 50 nm, and a base width W22, which in some embodiments is in a range of about 1 nm to about 10 nm, all in the X-direction. In Fig. 2E, the groove 18 has a largest width W23 at the center in the depth direction of the groove 18. The width of the groove therefore increases and decreases from the bottom to the top. The largest width W23 is in a range from about 12 nm to about 60 nm in some embodiments. The largest width layer D22, measured from the top of the groove, is in a range from about 2 nm to about 40 nm in some embodiments. Even if the dielectric layer 35 filled in the groove 18 has a height lower than the bottom of the lowermost gate electrode 104, the distance W24 between the gate electrode 104 and the dielectric layer 35 is less than about 1 nm. As stated above, when the well portion is formed from a Si substrate having a (100) major surface, the bottom sidewalls have a (111) facet of Si. In contrast, in the cross section along the Y-direction, as in Fig. As shown in Figure 2F, the groove 18 has a U-shape.

[0028] Fig. 3A shows a perspective view, and the Fig. 3B and Fig. 3C show cross-sectional views of a p-type GAA-FET device according to another embodiment of the present invention. Fig. 3D shows an enlarged cross-sectional view showing AR1 of the Fig. 3A and Fig. 3B, and Fig. Figure 3E shows an enlarged cross-sectional view showing AR2 of the Fig. 3A and Fig. 3C. The material, configuration, dimensions and / or processes are the same as in the above embodiments described with reference to the Fig. 1A to 2F, or similar, can be used in the embodiment of the Fig. 3A to 3E, and a detailed explanation can be omitted.

[0029] In the p-type GAA-FET, the channel layers are formed by semiconductor wires 20 made of a semiconductor material different from the substrate 10 and / or the well portion 11. In some embodiments, the semiconductor wires 25 are made of Si 1-x Ge x , where 0.2 ≤ x ≤ 0.8. The epitaxial source / drain layer 50 comprises one or more layers of Si, SiGe, or Ge for a p-channel FET.

[0030] As explained below with reference to the Fig. 31A to 38C, the groove 18 has a “double etched profile” caused by two dry etching processes performed at different process steps, as shown in Fig. 3D shown. As shown in Fig. 3D, the groove has a depth D31, which in some embodiments is in a range of about 5 nm to about 50 nm, a top width W31, which in some embodiments is in a range of about 10 nm to about 50 nm, and a base width W32, which in some embodiments is in a range of about 1 nm to about 10 nm, all in the X direction.

[0031] In Fig. 3D, the groove 18 has a step at its center. The location of the step D32, measured from the top of the groove, is in a range of about 2 nm to about 40 nm in some embodiments, and the width W33 at the step is in a range of about 5 nm to about 25 nm in some embodiments. The sidewall of the groove 18 has a wall angle with respect to the Z-axis that changes from small to large to small starting at the bottom of the groove. In some embodiments, the groove 18 has a greatest width W34 near the bottom of the gate electrode 104, which is in a range of about 12 nm to about 60 nm. The distance W35 between the channel layer 20 closest to the bottom and the dielectric layer 35 is less than 1 nm. In contrast, in the cross-section along the Y-direction, as in Fig. As shown in Figure 3E, the groove 18 has a U-shape.

[0032] Fig. 4A shows a perspective view, and the Fig. 4B and Fig. 4C show cross-sectional views of a p-type GAA-FET device according to another embodiment of the present invention. Fig. Figure 4D shows an enlarged cross-sectional view showing AR1 of the Fig. 4A and Fig. 4B, and Fig. Figure 4E shows an enlarged cross-sectional view showing AR2 of the Fig. 4A and Fig. 4C. The material, configuration, dimensions and / or processes are the same as in the above embodiments described with reference to the Fig. 1A to 3E, or similar, can be used in the embodiment of the Fig. 4A to 4E can be used, and a detailed explanation can be omitted.

[0033] The gate structure and the source / drain structures of the p-type GAA FET used in the Fig. 4A to 4C are essentially the same as those of the p-type GAA-FET shown in the Fig. 3A to 3C, except for the shape of the groove 18 formed at the upper portion of the tub portion 11. As described below with reference to Fig. 39A to 44C, the groove 18 is formed by using wet etching, and therefore has a (111) facet on its side walls, as shown in the Fig. 4D and Fig. 4E shown.

[0034] As in Fig. 4E, the groove has a depth D41, which in some embodiments is in a range from about 5 nm to about 50 nm, a top width W41, which in some embodiments is in a range from about 10 nm to about 50 nm, and a base width W42, which in some embodiments is in a range from about 1 nm to about 10 nm, all in the X-direction. In Fig. 4D, the groove 18 has a greatest width W43 at the center in the depth direction of the groove 18. The width of the groove therefore increases and decreases from the bottom to the top. In some embodiments, the width of the groove increases from the bottom to the top, decreases, increases, decreases, and then decreases. The greatest width W43 is in a range from about 12 nm to about 60 nm in some embodiments. The layer D42 of the greatest width, measured from the top of the groove, is in a range from about 2 nm to about 40 nm in some embodiments. The distance W45 between the channel layer 20 closest to the bottom and the dielectric layer 35 is less than 1 nm. As stated above, the bottom sidewalls have a (111) facet of Si when the well portion is formed from a Si substrate having a (100) major surface. In contrast, in the cross-section along the Y direction, as in Fig. As shown in Figure 4E, the groove 18 has a U-shape.

[0035] The Fig. Figures 5 to 24 show various stages of fabricating a GAA-FET device according to an embodiment of the present invention. It is understood that additional operations may be performed before, during, and after the processes described by the Fig. 5 to 24, and some of the operations described below may be replaced or omitted for additional embodiments of the method. The order of the operations / processes may be interchangeable. The material, configuration, dimensions and / or processes that are the same as in the above embodiments described with reference to the Fig. 1A to 4E, or similar, can be used in the embodiment of the Fig. 5 to 24, and a detailed explanation can be omitted. In the Fig. 9A to 20 are the “A” FIGS. ( Fig. 9A, Fig. 10A, ...) perspective views, the "B"-FIG. ( Fig. 9B, Fig. 10B, ...) are cross-sectional views cutting a channel region along the X-direction, and the "C" FIG. ( Fig. 9C, Fig. 10C, ...) are cross-sectional views of a source / drain region along the Y direction. In this embodiment, a manufacturing process for an n-type GAA FET is explained.

[0036] As in Fig. As shown in Figure 5, impurity ions (dopants) 12 are implanted into a silicon substrate 10 to form a well region. The ion implantation is performed to avoid a punch-through effect. The substrate 10 may have various regions that have been appropriately doped with impurities (e.g., p-type or n-type conductivity). The dopants 12 are, for example, boron (BF2) for an n-type FinFET and phosphorus for a p-type FinFET.

[0037] Then, as in Fig. As shown in Figure 6, stacked semiconductor layers are formed over the substrate 10. The stacked semiconductor layers include first semiconductor layers 20 and second semiconductor layers 25. Furthermore, a mask layer 16 is formed over the stacked layers.

[0038] The first semiconductor layers 20 and the second semiconductor layers 25 are made of materials having different lattice constants and may include one or more layers of Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb or InP.

[0039] In some embodiments, the first semiconductor layers 20 and the second semiconductor layers 25 are made of Si, a Si compound, SiGe, Ge, or a Ge compound. In one embodiment, the first semiconductor layers 20 are made of Si 1-x Ge x , where x is greater than about 0.2, or Ge (x=1.0), and the second semiconductor layers 25 consist of Si or Si 1-y Gey , where y is less than about 0.4 and x > y. In this disclosure, an "M" compound or an "M"-based compound means that the majority of the compound consists of M.

[0040] In another embodiment, the second semiconductor layers 25 consist of Si 1-y Ge y , where y is greater than about 0.2, or Ge, and the first semiconductor layers 25 consist of Si or Si 1-x Ge x , where x is less than about 0.4 and x < y. In still other embodiments, the first semiconductor layer 20 is made of Si 1-x Ge x , where x is in a range from about 0.2 to about 0.8, and the second semiconductor layer 25 consists of Si 1-y Ge y , where y is in a range from about 0.1 to about 0.4.

[0041] In Fig. 6, four layers of the first semiconductor layer 20 and four layers of the second semiconductor layer 25 are arranged. However, the number of layers is not limited to four and can be as small as one (each layer), and in some embodiments, two to ten layers of both the first and second semiconductor layers are formed. By adjusting the number of stacked layers, a control current of the GAA-FET device can be adjusted.

[0042] The first semiconductor layers 20 and the second semiconductor layers 25 are formed epitaxially over the substrate 10. The thickness of the first semiconductor layers 20 may be equal to or greater than that of the second semiconductor layers 25, and in some embodiments is in a range of about 2 nm to about 20 nm, and in other embodiments is in a range of about 5 nm to about 15 nm. The thickness of the second semiconductor layers 25 is in some embodiments in a range of about 2 nm to about 20 nm, and in other embodiments is in a range of about 5 nm to about 15 nm. The thickness of each of the first semiconductor layers 20 may be the same or vary.

[0043] In some embodiments, the bottom semiconductor layer (the layer closest to substrate 10) is thicker than the remaining first semiconductor layers. The thickness of the bottom semiconductor layer is in a range of about 10 nm to about 50 nm in some embodiments, or in a range of about 20 nm to about 40 nm in other embodiments.

[0044] In some embodiments, the mask layer 16 includes a first mask layer 16A and a second mask layer 16B. The first mask layer 16A is a pad oxide layer consisting of silicon dioxide, which may be formed by thermal oxidation. The second mask layer 16B is composed of silicon nitride (SiN) formed by chemical vapor deposition (CVD), including low-pressure CVD (LPCVD) and plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable process. The mask layer 16 is patterned into a mask pattern using patterning processes, including photolithography and etching.

[0045] Then, as in Fig. As shown in Figure 7, the stacked layers of the first and second semiconductor layers 20, 25 are patterned by using the patterned mask layer, wherein the stacked layers are formed into fin structures 29 extending in the X-direction. In Fig. 7, two fin structures 29 are arranged in the Y-direction. However, the number of fin structures is not limited to two and can be as small as one and three or more. In some embodiments, one or more dummy fin structures are formed on both sides of the fin structures 29 to improve patterning fidelity during patterning processes. As shown in Fig. As shown in Figure 7, the fin structures 29 have upper sections consisting of the stacked semiconductor layers 20, 25, and well sections 11.

[0046] The thickness W1 of the upper portion of the fin structure in the Y direction is in a range from about 10 nm to about 40 nm in some embodiments, and is in a range from about 20 nm to about 30 nm in other embodiments. The height H1 along the Z direction of the fin structure is in a range from about 100 nm to about 200 nm.

[0047] The stacked fin structure 29 can be patterned using any suitable method. The structures can be patterned, for example, using one or more photolithographic processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing for the creation of structures that have, for example, pitches smaller than those otherwise obtainable using a single direct photolithography process. In one embodiment, for example, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-aligning process.The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the stacked fin structure 29.

[0048] After the fin structures 29 have been formed, an insulating material layer comprising one or more layers of insulating material is formed over the substrate such that the fin structures are completely embedded in the insulating layer. The insulating material for the insulating layer may comprise silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), or a low-k dielectric material formed by low-pressure chemical vapor deposition (LPCVD), plasma CVD, or flowable CVD. A hardening process may be performed after forming the insulating layer.Then, a planarization process, such as a chemical mechanical polishing (CMP) process and / or an etch-back process, is performed such that the surface of the topmost second semiconductor layer 25 is exposed from the insulating material layer. In some embodiments, a fin liner layer 13 is formed over the fin structures before the insulating material layer is formed. The fin liner layer 13 is made of SiN or a silicon nitride-based material (e.g., SiON, SiCN, or SiOCN).

[0049] In some embodiments, the fin liner layers 13 include a first fin liner layer formed over the substrate 10 and sidewalls of the bottom portion of the well section 11, and a second fin liner layer formed on the first fin liner layer. Each of the liner layers, in some embodiments, has a thickness between 1 nm and about 20 nm. In some embodiments, the first fin liner layer comprises silicon oxide and has a thickness between about 0.5 nm and about 5 nm, and the second fin liner layer comprises silicon nitride and has a thickness between about 0.5 nm and about 5 nm. The liner layers may be deposited using one or more processes, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD), although any acceptable process may be used.

[0050] Then, as in Fig. As shown in Figure 8, the layer of insulating material is recessed to form an isolation layer 15 such that the uppermost portion of the fin structures 29 is exposed. With this process, the fin structures 29 are electrically separated from each other by the isolation layer 15, also called shallow trench isolation (STI). The isolation layer 15 can be made of suitable dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics such as carbon-doped oxides, extremely low-k dielectrics such as porous carbon-doped silicon dioxide, a polymer such as polyimide, combinations of these, or the like.In some embodiments, the separation insulating layer 15 is formed by a process such as CVD, flowable CVD deposition (FCVD), or a spin-on-glass process, although any acceptable process may be used.

[0051] At the Fig. In the embodiment shown in Figure 8, the isolation insulating layer 15 is recessed until the upper portion of the well portion 11 is exposed. In other embodiments, the upper portion of the well portion 11 is not exposed. The first semiconductor layers 20 are sacrificial layers that are subsequently partially removed, and the second semiconductor layers 25 are subsequently formed into semiconductor wires as channel layers of an n-type GAA-FET. In other embodiments, the second semiconductor layers 25 are sacrificial layers that are subsequently partially removed, and the first semiconductor layers 20 are subsequently formed into semiconductor wires as channel layers of a p-type GAA-FET.

[0052] The Fig. 9A, Fig. 9B and Fig. 9C show one of the various stages of fabricating a semiconductor FET device according to embodiments of the present invention. After forming the isolation insulating layer 15, as shown in Fig. 9A to 9C, a sacrificial (dummy) gate structure 38 is formed. The Fig. 9A through 9C illustrate a structure after a sacrificial gate structure 38 has been formed over the exposed fin structures 29. The sacrificial gate structure 38 is formed over a portion of the fin structures that is to be a channel region. The sacrificial gate structure 38 defines the channel region of the GAA-FET. The sacrificial gate structure 38 includes a sacrificial gate dielectric layer 31 and a sacrificial gate electrode layer 30. The sacrificial gate dielectric layer 31 includes one or more layers of insulating material, such as a silicon oxide-based material. In one embodiment, a silicon oxide formed by CVD is used. The thickness of the sacrificial gate dielectric layer 31 is in a range of about 1 nm to about 5 nm in some embodiments.

[0053] The sacrificial gate structure 38 is first formed by depositing a full-area layer of the sacrificial gate dielectric layer 31 over the fin structures. A sacrificial gate electrode layer is then deposited as a full-area layer on the sacrificial gate dielectric layer and over the fin structures such that the fin structures are completely embedded in the sacrificial gate electrode layer. The sacrificial gate electrode layer comprises silicon, such as polycrystalline silicon or amorphous silicon. The thickness of the sacrificial gate electrode layer, in some embodiments, is in a range of about 100 nm to about 200 nm. In some embodiments, a planarization process is performed on the sacrificial gate electrode layer. The sacrificial gate dielectric layer and the sacrificial gate electrode layer are deposited using CVD, including LPCVD and PECVD, PVD, ALD, or another suitable process.A mask layer is then formed over the sacrificial gate electrode layer. In some embodiments, the mask layer includes a pad SiN layer and a silicon oxide mask layer.

[0054] Subsequently, a patterning process is carried out on the mask layer, and the sacrificial gate electrode layer is formed into a sacrificial gate structure 30 as shown in the Fig. 9A and Fig. 9B. The sacrificial gate structure includes the sacrificial gate dielectric layer 31, the sacrificial gate electrode layer 30 (e.g., polysilicon), the pad SiN layer, and the silicon oxide mask layer (not shown). In some embodiments, the source / drain regions of the fin structures are covered by the sacrificial gate dielectric layer 31. In the Fig. 9A to 9C, one sacrificial gate structure is formed, but the number of sacrificial gate structures is not limited to one. Two or more sacrificial gate structures are arranged in the X direction in some embodiments. In certain embodiments, one or more dummy sacrificial gate structures are formed on both sides of the sacrificial gate structures to improve patterning fidelity.

[0055] Then, the sacrificial gate dielectric layer 31 covering the source / drain regions of the fin structures is formed by dry etching and / or wet etching as shown in the Fig. 10A to 10C. This process exposes the stacked layers of the first and second semiconductor layers on opposite sides of the sacrificial gate structure 38.

[0056] Furthermore, a cover layer for sidewall spacers 32 is formed over the sacrificial gate structure 38, as shown in the Fig. 11A to 11C. The cap layer 32 is deposited in a conformal manner such that it is formed with substantially equal thickness on vertical surfaces, such as sidewalls, horizontal surfaces, and the top surface of the sacrificial gate structure, respectively. In some embodiments, the cap layer 32 has a thickness in a range of about 5 nm to about 20 nm. The cap layer 32 comprises SiN and / or SiON and / or SiCN or another suitable dielectric material. The cap layer 32 may be formed by ALD or CVD or by another suitable method.

[0057] Next, as in the Fig. As shown in Figures 12A to 12C, the source / drain regions are etched below the surface of the isolation insulating layer 15 using one or more lithography and etching processes. One or more etching processes are performed to remove the fin sidewall spacers 32, and then to remove the stacked structures of the first and second semiconductor layers and a portion of the upper portion of the well portion 11.

[0058] Then, as in the Fig. As shown in Figures 13A to 13C, the first semiconductor layers 20 are etched laterally in the X-direction. The etching amount of the first semiconductor layer 20 in some embodiments is in a range from about 2 nm to about 10 nm. When the first semiconductor layers 20 are Ge or SiGe, and the second semiconductor layers 25 are Si, the first semiconductor layers 20 may be selectively removed using a wet etchant, such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solutions.

[0059] Then, as in the Fig. 14A to 14C, a protective layer is formed to protect the structures formed by the Fig. 13A to 13C. The protection layer includes a first protection layer 33 made of a silicon oxide-based dielectric material (e.g., SiO2) and a second protection layer 34 made of a silicon nitride-based dielectric material (e.g., SiN, SiON). The first and second protection layers may be formed using a process such as CVD or ALD or any other suitable method. The thickness of the first protection layer 33 is in a range of about 1 nm to about 5 nm in some embodiments, and the thickness of the second protection layer 34 is in a range of about 2 nm to about 10 nm in some embodiments.

[0060] After the protective layers are formed, anisotropic etching is carried out to remove the protective layers from at least the upper portion of the well portion 11 while the protective layers cover lateral ends of the first and second semiconductor layers, as shown in the Fig. 15A to 15C shown.

[0061] Then, additional dry etching is performed on the exposed upper portion of the tub section to deepen the depth of the groove 18, as shown in the Fig. 16A to 16C. The depth D1 of the groove, measured from the upper surface of the isolation insulating layer 15, is in a range of about 5 nm to about 50 nm in some embodiments. Since the upper portion of the well portion at the source / drain regions is subjected to at least two dry etching processes, the groove 18 has a step in the center of the groove 18, as shown in the Fig. 1D and Fig. 1E shown.

[0062] After the groove 18 has been formed, the second protective layer 34 and the first protective layer 33 are formed by appropriate etching processes as shown in the Fig. 17A to 17C shown, removed.

[0063] Then a dielectric layer 35, as shown in the Fig. 18A to 18C, is formed to fill the groove 18 and cover the surrounding portions and lateral ends of the first and second semiconductor layers. In particular, the dielectric layer 35 is formed on the lateral ends of the first semiconductor layers that have been laterally etched. The dielectric layer 35 is made of suitable dielectric materials, such as silicon oxide, silicon oxynitride, silicon nitride, fluorine-doped silicate glass (FSG), low-k dielectrics such as carbon-doped oxides, extremely low-k dielectrics such as porous carbon-doped silicon dioxide, a polymer such as polyimide, combinations thereof, or the like. In some embodiments, the dielectric layer 35 comprises one or more layers of low-k dielectric materials.The dielectric layer 35 may be formed by a process such as CVD, flowable CVD deposition (FCVD), or a spin-on-glass process, although any acceptable process may be used.

[0064] In some embodiments, prior to forming the dielectric layer 35, an insulating layer is conformally formed on the lateral ends of the first semiconductor layer 20 and on the second semiconductor layer 25. The insulating layer functions as an etch stop layer during subsequent channel formation processes. The insulating layer comprises silicon nitride (SiN) and silicon oxide (SiO2) and has a thickness in a range of about 0.5 nm to about 3.0 nm. In other embodiments, the insulating layer has a thickness in a range of about 1.0 nm to about 2.0 nm. The insulating layer may be formed by ALD or by another suitable method.

[0065] After the dielectric layer 35 has been formed, one or more etching operations are performed to remove unnecessary portions of the dielectric layer 35, as shown in the Fig. 19A to 19C. Through this etching process, internal spacers are formed on the lateral ends of the first semiconductor layers 20 that have been laterally etched, and dielectric spacers are formed in the grooves 18 and on the surface of the surrounding portion of the isolation insulating layer 15. Furthermore, through this etching, the lateral ends of the second semiconductor layer 25 are exposed.

[0066] Subsequently, an epitaxial source / drain layer 50 is formed as shown in the Fig. 20A-20C. The epitaxial source / drain layer 50 comprises one or more layers of Si, SiP, SiC, and SiCP for an n-channel FET. The epitaxial source / drain layer 50 is formed by an epitaxial growth process using CVD, ALD, or molecular beam epitaxy (MBE). As shown in the Fig. 20A to 20C, in some embodiments, the epitaxial source / drain layer 50 is formed individually over each corresponding well portion 11. In other embodiments, as shown in Fig. 20D, the adjacent epitaxial source / drain layers 50 combine to form a merged source / drain layer 50 with a void 51.

[0067] As in the Fig. As shown in Figures 20A to 20D, a bottom of the epitaxial source / drain layer 50 is separated from the well portion 11 by the dielectric layer 35. Further, the inner spacers 35, which are made of the same material as the dielectric layer 35, are formed between the epitaxial source / drain layer 50 and the side ends of the first semiconductor layer.

[0068] The Fig. Figures 21 to 24 show processes for the fabrication of a metal gate structure using a gate replacement technology. Fig. 21 to 24, a merged source / drain structure similar to Fig. 20D is used for the purpose of explanation, but the individual epitaxial source / drain layer structure as shown in the Fig. 20A-20C, can be adapted to the processes of Fig. 21 to 24 can be applied.

[0069] After the epitaxial source / drain layer 50 is formed, a contact etch stop layer (CESL) 60 is formed over the isolation insulating layer 50, the sidewall spacers 32, and the epitaxial source / drain layer 50, and an interface dielectric layer (ILD) 80 is formed over the CESL 60, as shown in Fig. 21. The CESL 60 is formed of SiN or a silicon nitride-based material (e.g., SiON, SiCN, or SiOCN). Materials for the ILD layer 80 include compounds including Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials, such as polymers, may be used for the ILD layer 80. The CESL 60 may be formed using CVD, ALD, or any other suitable film formation techniques. The ILD layer 80 may be formed using CVD, ALD, or any other suitable film formation techniques. A annealing process may be performed after forming the ILD layer. After the ILD layer 80 is formed, a planarization process, such as CMP, is performed to expose the upper portion of the sacrificial gate electrode layer 30.

[0070] Then, the sacrificial gate structure 38 comprising the sacrificial electrode layer 30 and the sacrificial gate dielectric layer 31 is removed, thereby forming a gate space 39 as shown in Fig. 22. The ILD layer 80 protects the S / D structure 50 during the removal of the sacrificial gate structures. The sacrificial gate structures may be removed using plasma dry etching and / or wet etching. If the sacrificial gate electrode layer 30 is polysilicon and the ILD layer 36 is silicon oxide, a wet etchant, such as a TMAH solution, may be used to selectively remove the sacrificial gate electrode layer 30. The sacrificial gate layer 31 is then removed using plasma dry etching and / or wet etching.

[0071] After the sacrificial gate structures have been removed, the first semiconductor layers 20 are removed, leaving wires of the second semiconductor layers 25, as shown in Fig. 23. The first semiconductor layers 20 may be removed or etched using an etchant that can selectively etch the first semiconductor layers 20 against the second semiconductor layers 25, as set forth above. In some embodiments, if the insulating layer is formed before the dielectric layer 35 is formed, the etching of the first semiconductor layers stops at the insulating layer.

[0072] After the semiconductor wires of the second semiconductor layers 25 are formed, a gate dielectric layer 102 is formed around each channel layer (wires of the second semiconductor layers 25), and a gate electrode layer 104 is formed on the gate dielectric layer 102 as shown in Fig. 24 shown, formed.

[0073] In some embodiments, the gate dielectric layer 102 includes an interface layer 102A and a high-k dielectric layer 102B. The interface layer 102A, in some embodiments, is a chemically formed silicon oxide. In certain embodiments, the high-k gate dielectric layer 102B includes one or more layers of a dielectric material such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconia, alumina, titania, hafnia-alumina (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, and / or combinations thereof.

[0074] The high-k gate dielectric layer 102B may be formed by CVD, ALD, or another suitable method. In one embodiment, the high-k gate dielectric layer 102B is formed using a highly conformal deposition process, such as ALD, to ensure the formation of a gate dielectric layer having a uniform thickness around each of the channel layers. The thickness of the high-k gate dielectric layer 102B, in one embodiment, is in a range of about 1 nm to about 6 nm.

[0075] The gate electrode layer 104 (a body gate electrode layer) is formed on the gate dielectric layer 102 to surround each channel layer. The gate electrode layer 103 comprises one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof.

[0076] The gate electrode layer 104 may be formed by CVD, ALD, electroplating, or another suitable method. The gate electrode layer is also deposited over the top surface of the ILD layer 80. The gate dielectric layer and the gate electrode layer formed over the ILD layer 80 are then planarized, for example, using CMP, until the surface of the ILD layer 80 is exposed. In some embodiments, after the planarization process, the gate electrode layer 104 is recessed, and an insulating cap layer 106 is formed over the recessed gate electrode 104. The insulating cap layer comprises one or more layers of silicon nitride-based material, such as SiN. The insulating cap layer 106 may be formed by applying an insulating material followed by a planarization process.

[0077] In certain embodiments, one or more work-function matching layers 104A and 104B are inserted between the gate dielectric layer 102 and the gate electrode layer 104C. The work-function matching layers are made of a conductive material, such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC, or a multilayer of two or more of these materials. For the n-channel FET, TaN and / or TaAlC and / or TiN and / or TiC and / or Co and / or TiAl and / or HfTi and / or TiSi and / or TaSi is / are used as the work-function matching layer. The work-function matching layer can be formed by ALD, PVD, CVD, electron beam evaporation, or another suitable process.

[0078] Through these processes, the structure that is present in the Fig. 1A to 1E. It goes without saying that the GAA-FETs undergo further CMOS processes to form various features, such as contacts / vias, metal interconnect layers, dielectric layers, passivation layers, etc.

[0079] The Fig. 25A to 30C show various stages of fabricating a GAA-FET device according to another embodiment of the present invention. It is understood that additional operations may be performed before, during, and after the processes described by the Fig. 35A to 30C, and some of the operations described below may be replaced or omitted in additional embodiments of the method. The order of the operations / processes may be interchangeable. The material, configuration, dimensions, and / or processes that are the same as in the above embodiments described with reference to the Fig. 1A to 24, or similar, can be used in the embodiment of the Fig. 25A to 30C, and a detailed explanation can be omitted. In the Fig. 25A to 30C are the “A” FIGS. ( Fig. 25A, Fig. 26A, ...) perspective views, the "B"-FIG. ( Fig. 25B, Fig. 26B, ...) are cross-sectional views cutting a channel region along the X-direction, and the "C" FIG. ( Fig. 25, Fig. 26C, ...) are cross-sectional views of a source / drain region along the Y direction. In this embodiment, a manufacturing process for an n-type GAA FET is explained.

[0080] The Fig. 25A to 25C are the same as the Fig. 15A to 5C as set forth above. In this embodiment, the groove 18 is formed by using wet etching as shown in the Fig. 26A to 26C. If the well portion 11 is made of Si, tetramethylammonium hydroxide (TMAH) can be used as a wet etchant. Since TMAH etches crystalline Si anisotropically, the sidewalls of the groove 18 have a (111) facet of Si crystal, as shown in FIGS. Fig. 2D and Fig. 2E. The depth D2 of the groove, measured from the top surface of the isolation insulating layer 15, is in a range of about 5 nm to about 50 nm in some embodiments.

[0081] After the groove 18 has been formed by wet etching, the second protective layer 34 and the first protective layer 33 are formed by appropriate etching processes as shown in the Fig. 27A to 27C. The processes for removing the protective layers are essentially the same as those described with reference to Fig. 17A to 17C explained.

[0082] Then, similar to the Fig. 18A to 18C, a dielectric layer 35 as shown in Fig. 28A to 28C, formed to fill the groove 18 and cover the surrounding portions and lateral ends of the first and second semiconductor layers. The operations for removing the dielectric layer 35 are substantially the same as those described with reference to FIGS. Fig. 18A to 18C explained.

[0083] After the dielectric layer 35 has been formed, one or more etching operations are performed to remove unnecessary portions of the dielectric layer 35, as shown in the Fig. 29A to 29C. The operations for partially etching the dielectric layer 35 are essentially the same as those described with reference to Fig. 19A to 19C. Through this etching process, internal spacers are formed on the lateral ends of the first semiconductor layers 20 that have been laterally etched, and dielectric spacers are formed in the grooves 18 and on the surface of the surrounding portion of the isolation insulating layer 15. Furthermore, through this etching, the lateral ends of the second semiconductor layer 25 are exposed.

[0084] Subsequently, an epitaxial source / drain layer 50 is formed as shown in the Fig. 30A to 30C. The processes for removing the epitaxial source / drain layer 50 are essentially the same as those described with reference to Fig. 20A to 20C explained.

[0085] After the epitaxial source / drain layer 50 has been formed, the same or similar operations as those described with reference to Fig. 21 to 24, and which are explained in the Fig. The structure shown in Figures 2A to 2E is obtained. It goes without saying that the GAA-FETs undergo further CMOS processes to form various features, such as contacts / vias, metal interconnect layers, dielectric layers, passivation layers, etc.

[0086] The Fig. 31A to 38C show various stages of fabricating a GAA-FET device according to another embodiment of the present invention. It is understood that additional operations may be performed before, during, and after the processes described by the Fig. 31A to 38C, and some of the operations described below may be replaced or omitted for additional embodiments of the method. The order of the operations / processes may be interchangeable. The material, configuration, dimensions, and / or processes that are the same as in the above embodiments described with reference to the Fig. 1A to 30C, or similar, can be used in the embodiment of the Fig. 31A to 38C, and a detailed explanation can be omitted. In the Fig. 31A to 38C are the “A” FIGS. ( Fig. 31A, Fig. 32A, ...) perspective views, the "B"-FIG. ( Fig. 31B, Fig. 32B, ...) are cross-sectional views cutting a channel region along the X-direction, and the "C" FIG. ( Fig. 31C, Fig. 32C, ...) are cross-sectional views of a source / drain region along the Y direction. In this embodiment, a manufacturing process for a p-type GAA FET is explained.

[0087] After the structure that is in the Fig. 12A to 12C, the second semiconductor layers 25 are laterally formed in the X-direction as shown in the Fig. 31A to 31. The etching amount of the second semiconductor layer 25 is in a range of about 2 nm to about 10 nm in some embodiments. When the first semiconductor layers 20 are made of Ge or SiGe, and the second semiconductor layers 25 are made of Si, the second semiconductor layers 25 may be selectively removed using a wet etchant, such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solutions.

[0088] Then, as in the Fig. 32A to 32C, a protective layer is formed to protect the structures formed by the Fig. 30A to 39C. The processes for removing the protective layer are essentially the same as or similar to those described with reference to Fig. 14A to 14C explained.

[0089] After the protective layers are formed, anisotropic etching is carried out to remove the protective layers from at least the upper portion of the well portions 11 while the protective layers cover lateral ends of the first and second semiconductor layers, as shown in the Fig. 33A to 33C similar to the Fig. 15A to 15 shown.

[0090] Then, an additional dry etching is performed on the exposed upper portion of the tub section to deepen the depth of the groove 18, as shown in the Fig. 34A to 34C. The depth D3 of the groove, measured from the upper surface of the isolation insulating layer 15, is in a range of about 5 nm to about 50 nm in some embodiments. Since the upper portion of the well portion at the source / drain regions is subjected to at least two dry etching processes, the groove 18 has a step in the center of the groove 18, as shown in Fig. Shown in 3D.

[0091] After the groove 18 has been formed by wet etching, the second protective layer 34 and the first protective layer 33 are formed by appropriate etching processes as shown in the Fig. 35A to 35C. The processes for removing the protective layers are essentially the same as those described with reference to Fig. 17A to 17C explained.

[0092] Then, similar to the Fig. 18A to 18C, a dielectric layer 35 as shown in Fig. 36A to 36C, formed to fill the groove 18 and cover the surrounding portions and lateral ends of the first and second semiconductor layers. The operations for removing the dielectric layer 35 are substantially the same as those described with reference to FIGS. Fig. 18A to 18C explained.

[0093] After the dielectric layer 35 has been formed, one or more etching operations are performed to remove unnecessary portions of the dielectric layer 35, as shown in the Fig. 37A to 37C. The operations for partially etching the dielectric layer 35 are essentially the same as those described with reference to Fig. 19A to 19C. Through this etching process, internal spacers are formed on the lateral ends of the first semiconductor layers 25 that have been laterally etched, and dielectric spacers are formed in the grooves 18 and on the surface of the surrounding portion of the insulating layer 15. Furthermore, through this etching, the lateral ends of the first semiconductor layer 20 are exposed.

[0094] Subsequently, an epitaxial source / drain layer 50 is formed as shown in the Fig. 38A to 38C. The epitaxial source / drain layer 50 comprises one or more layers of Si, SiGe, or Ge for a p-channel FET. The processes for removing the epitaxial source / drain layer 50 are essentially the same as those described with reference to FIGS. Fig. 20A to 20C explained.

[0095] After the epitaxial source / drain layer 50 is formed, the same or similar operations as those described with reference to the Fig. 21 to 24, and which are explained in the Fig. 3A to 3D is obtained. In the channel formation process described with reference to Fig. 23, the second semiconductor layers 25 are removed, leaving the first semiconductor layer as the channel regions of the GAA-FET. Furthermore, in this process, the upper portion of the well portion 11 below the channel regions is also partially etched, and the gate dielectric layer and the gate electrode layer fill the space formed above the well portion 11 and the lowermost first semiconductor layer 20 (see Fig. 3A and Fig. 3B). Furthermore, the one or more work function matching layers 104A and 104B comprise TiAlC and / or Al and / or TiAl and / or TaN and / or TaAlC and / or TiN and / or TiC and / or Co or any other suitable conductive material.

[0096] It goes without saying that GAA FETs undergo further CMOS processes to form various features such as contacts / vias, metal interconnect layers, dielectric layers, passivation layers, etc.

[0097] The Fig. 39A to 43C show various stages of fabricating a GAA-FET device according to another embodiment of the present invention. It is understood that additional operations may be performed before, during, and after the processes described by the Fig. 39A to 43C, and some of the operations described below may be replaced or omitted for additional embodiments of the method. The order of the operations / processes may be interchangeable. The material, configuration, dimensions, and / or processes that are the same as in the above embodiments described with reference to the Fig. 1A to 30C, or similar, can be used in the embodiment of the Fig. 39A to 43C, and a detailed explanation can be omitted. In the Fig. 39A to 43C are the “A” FIGS. ( Fig. 39A, Fig. 40A, ...) perspective views, the "B"-FIG. ( Fig. 39B, Fig. 40B, ...) are cross-sectional views cutting a channel region along the X-direction, and the "C" FIG. ( Fig. 39C, Fig. 40C, ...) are cross-sectional views of a source / drain region along the Y direction. In this embodiment, a manufacturing process for a p-type GAA FET is explained.

[0098] The Fig. 39A-39C are the same as the Fig. 33A to 33C.

[0099] After the protective layers have been removed, the groove 18 is formed using wet etching as shown in the Fig. 40A to 40C, similar to the Fig. 26A-26C. If the well section 11 is made of Si, tetramethylammonium hydroxide (TMAH) can be used as a wet etchant. Since TMAH etches crystalline Si anisotropically, the sidewalls of the groove 18 have a (111) facet of Si crystal, as shown in Fig. 4D. The depth D4 of the groove, measured from the top surface of the isolation insulating layer 15, is in a range of about 5 nm to about 50 nm in some embodiments.

[0100] After the groove 18 has been formed by wet etching, the second protective layer 34 and the first protective layer 33 are formed by appropriate etching processes as shown in the Fig. 41A to 41C. The processes for removing the protective layers are essentially the same as those described with reference to Fig. 17A to 17C explained.

[0101] Then, similar to the Fig. 18A to 18C, a dielectric layer 35 as shown in Fig. 42A to 42C, formed to fill the groove 18 and cover the surrounding portions and lateral ends of the first and second semiconductor layers. The operations for removing the dielectric layer 35 are substantially the same as those described with reference to FIGS. Fig. 18A to 18C explained.

[0102] After the dielectric layer 35 has been formed, one or more etching operations are performed to remove unnecessary portions of the dielectric layer 35, as shown in the Fig. 43A to 43C. The operations for partially etching the dielectric layer 35 are essentially the same as those described with reference to Fig. 19A to 19C. Through this etching process, internal spacers are formed on the lateral ends of the first semiconductor layers 25 that have been laterally etched, and dielectric spacers are formed in the grooves 18 and on the surface of the surrounding portion of the insulating layer 15. Furthermore, through this etching, the lateral ends of the first semiconductor layer 20 are exposed.

[0103] Subsequently, an epitaxial source / drain layer 50 is formed as shown in the Fig. 44A to 44C. The epitaxial source / drain layer 50 comprises one or more layers of Si, SiGe, or Ge for a p-channel FET. The processes for removing the epitaxial source / drain layer 50 are essentially the same as those described with reference to FIGS. Fig. 20A to 20C explained.

[0104] After the epitaxial source / drain layer 50 is formed, the same or similar operations as those described with reference to the Fig. 21 to 24, and which are explained in the Fig. 4A to 4D is obtained. In the channel formation process described with reference to Fig. 23, the second semiconductor layers 25 are removed, leaving the first semiconductor layer as the channel regions of the GAA-FET. Furthermore, in this process, the upper portion of the well portion 11 below the channel regions is also partially etched, and the gate dielectric layer and the gate electrode layer fill the space formed above the well portion 11 and the lowermost first semiconductor layer 20 (see Fig. 4A and Fig.4B). Furthermore, the one or more work function matching layers 104A and 104B comprise TiAlC and / or Al and / or TiAl and / or TaN and / or TaAlC and / or TiN and / or TiC and / or Co or any other suitable conductive material.

[0105] It goes without saying that GAA FETs undergo further CMOS processes to form various features such as contacts / vias, metal interconnect layers, dielectric layers, passivation layers, etc.

[0106] The various embodiments or examples described herein offer several advantages over the prior art. For example, in the present invention, since a dielectric layer is interposed between the base of the epitaxial source / drain layer and the well portion, it is possible to reduce off-state leakage current while reducing the amount of APT dose. Furthermore, since the internal spacers and the dielectric layer are formed using the same processes, the process for forming the internal spacers can be simplified.

[0107] It is understood that not all advantages have necessarily been discussed here, no particular advantage is required for all embodiments or examples, and other embodiments or examples may provide different advantages.

[0108] In accordance with one aspect of the present invention, in a method for manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers, the second semiconductor layers, and an upper portion of a well portion of the fin structure at a source / drain region of the fin structure not covered by the sacrificial gate structure are etched. A dielectric layer is formed over the etched upper portion of the well portion. An epitaxial source / drain layer is formed. The source / drain layer is connected to ends of the second semiconductor layers, and a bottom of the epitaxial source / drain layer is separated from the well portion by the dielectric layer.In one or more of the above and following embodiments, after the first semiconductor layers, the second semiconductor layers and the upper portion of the well portion are etched, and the first semiconductor layers are laterally etched. In one or more of the above and following embodiments, the dielectric layer is also formed on laterally etched ends of the first semiconductor layers. In one or more of the above and following embodiments, after the first semiconductor layers, the second semiconductor layers and the upper portion of the well portion are etched, and the etched upper portion of the well portion is further etched while the first and second semiconductor layers are protected by a cap layer. In one or more of the above and following embodiments, the etched upper portion of the well portion is etched by wet etching.In one or more of the above and following embodiments, the cap layer is removed after the etched upper portion of the well portion is etched and before the dielectric layer is formed. In one or more of the above and following embodiments, after the epitaxial source / drain layer is formed, an interface dielectric (ILD) layer is formed, the sacrificial gate structure is removed, thereby exposing a portion of the fin structure, the first semiconductor layers are removed from the exposed fin structure, thereby forming channel layers including the second semiconductor layers, and a gate dielectric layer and a gate electrode layer are formed around the channel layers.In one or more of the above and following embodiments, a base portion of the fin structure is embedded in the isolation insulating layer, and the dielectric layer is made of a material different from that of the isolation insulating layer and the ILD layer. In one or more of the above and following embodiments, the first semiconductor layers are made of Si. 1-x Ge x , and the second semiconductor layers consist of Si 1-y Ge y , where 0 ≤ x < y < 1. In one or more of the above and following embodiments, the first semiconductor layers consist of Si 1-x Ge x, where 0.2 ≤ x ≤ 0.8, and the second semiconductor layers are made of Si. In one or more of the above and following embodiments, the dielectric layer is made of SiCO or SiOCN. In one or more of the above and following embodiments, the dielectric layer is made of silicon oxide or silicon nitride.

[0109] In accordance with another aspect of the present invention, in a method for manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed. A sacrificial gate structure is formed over the fin structure. A sidewall spacer is formed on one side of the sacrificial gate structure. The first semiconductor layers, the second semiconductor layers, and an upper portion of a well portion of the fin structure, which are not covered by the sacrificial gate structure and the sidewall spacer, are etched. A cap layer is formed to cover the first semiconductor layers and the second semiconductor layers. The upper portion of the well portion is etched. A dielectric layer is formed over the etched upper portion of the well portion. An epitaxial source / drain layer is formed.In one or more of the above and following embodiments, the capping layer comprises a silicon oxide layer and a silicon nitride layer. In one or more of the above and following embodiments, after the first semiconductor layers, the second semiconductor layers and the upper portion of the well portion are etched, and before the capping layer is formed, the first semiconductor layers below the sidewall spacer are laterally etched. In one or more of the above and following embodiments, the capping layer is removed after the etched upper portion of the well portion has been further etched and before the dielectric layer is formed. In one or more of the above and following embodiments, the etched upper portion of the well portion is etched by wet etching.

[0110] In accordance with another aspect of the present invention, in a method for manufacturing a semiconductor device, a first fin structure and a second fin structure are formed, in which first semiconductor layers and second semiconductor layers are alternately stacked, respectively. A sacrificial gate structure is formed over the first and second fin structures. The first semiconductor layers, the second semiconductor layers, and an upper portion of a well portion of the fin structure at a source / drain region of the first and second fin structures not covered by the sacrificial gate structure are etched. A dielectric layer is formed over the etched upper portion of the first and second fin structures. A first epitaxial source / drain layer is formed over the first fin structure, and a second epitaxial source / drain layer is formed over the second fin structure.A bottom of the first epitaxial source / drain layer is separated from the first fin structure by the dielectric layer, and a bottom of the second epitaxial source / drain layer is separated from the second fin structure by the dielectric layer. In one or more of the above and following embodiments, the first epitaxial source / drain layer is separated from the second epitaxial source / drain layer. In one or more of the above and following embodiments, the first epitaxial source / drain layer is connected to the second epitaxial source / drain layer.

[0111] In accordance with one aspect of the present invention, a semiconductor device comprises vertically arranged semiconductor wires extending in a first direction, each having a channel region, and an epitaxial source / drain layer connected to ends of the semiconductor wires. The semiconductor wires and the epitaxial source / drain layer are disposed above a well portion, and a bottom of the epitaxial source / drain layer is separated from the well portion by a dielectric layer. The dielectric layer is disposed in a groove in the well portion beneath the epitaxial source / drain layer, wherein the groove in the well portion has been etched by one or more etching processes and has a U-shape or a V-shape in a cross-section along a second direction perpendicular to the first direction.In one or more of the above and following embodiments, the semiconductor device further comprises an isolation insulating layer in which the well portion is embedded, and an interface layer (ILD) covering the epitaxial source / drain layer. The dielectric layer is made of a material different from that of the isolation insulating layer and the ILD layer. In one or more of the above and following embodiments, the dielectric layer is made of SiCO or SiOCN. In one or more of the above and following embodiments, the dielectric layer is in contact with the epitaxial source / drain layer and the well portion. In one or more of the above and following embodiments, an upper surface of the well portion in contact with the dielectric layer has a V-shaped groove.In one or more of the above and following embodiments, the well portion is made of Si, and the V-shaped groove has a (111) crystal facet made of Si. In one or more of the above and following embodiments, the semiconductor device further comprises a gate structure wrapped around the channel region of each of the semiconductor wires, and internal spacers disposed between the epitaxial source / drain layer and portions of the gate structure disposed between adjacent semiconductor wires. In one or more of the above and following embodiments, the internal spacers are made of the same material as the dielectric layer. In one or more of the above and following embodiments, the first semiconductor wires are made of Si.In one or more of the above and following embodiments, the semiconductor wires are made of SiGe and the well sections are made of Si.

[0112] In accordance with another aspect of the present invention, a semiconductor device includes a first group of semiconductor wires arranged vertically above a first well portion and extending in a first direction, each of which has a channel region, a first epitaxial source / drain layer connected to ends of the semiconductor wires of the first group and disposed above the first well portion, a second group of semiconductor wires arranged vertically above a second well portion and extending in a first direction, each of which has a channel region, and a second epitaxial source / drain layer connected to the ends of the semiconductor wires of the second group and disposed above the second well portion. The first well portion is adjacent to the second well portion with an isolation insulating layer interposed between the first and second well portions.A bottom of the first epitaxial source / drain layer is separated from the first well portion by a dielectric layer, and a bottom of the second epitaxial source / drain layer is separated from the second well portion by the dielectric layer. The dielectric layer is disposed in a groove in each of the first and second well portions beneath the corresponding epitaxial source / drain layer. The groove in each of the first and second well portions has been etched by one or more etching processes and has a U-shape or a V-shape in a cross-section along a second direction perpendicular to the first direction. In one or more of the above and following embodiments, the first epitaxial source / drain layer is separated from the second epitaxial source / drain layer.In one or more of the above and following embodiments, the first epitaxial source / drain layer is connected to the second epitaxial source / drain layer. In one or more of the above and following embodiments, the semiconductor device further comprises an interface dielectric (ILD) layer covering the epitaxial source / drain layer. The dielectric layer is made of a material different from that of the isolation insulating layer and the ILD layer. In one or more of the above and following embodiments, the dielectric layer is made of SiCO or SiOCN. In one or more of the above and following embodiments, the dielectric layer is made of silicon oxide or silicon nitride.

[0113] In accordance with another aspect of the present invention, a semiconductor device includes vertically arranged semiconductor wires extending in a first direction, each of which has a channel region, and an epitaxial source / drain layer connected to ends of the semiconductor wires. The semiconductor wires and the source / drain region are disposed above a well portion. A bottom of the epitaxial source / drain layer is separated from the well portion by a dielectric layer. The dielectric layer is in contact with the well portion, and an upper surface of the well portion, which is in contact with the dielectric layer, has a groove in which the dielectric layer is disposed. The groove has been etched by one or more etching processes and has a U-shape or a V-shape in a cross-section along a second direction perpendicular to the first direction.In one or more of the above and following embodiments, the groove has, in a cross section defined by the first direction and the vertical direction, a central portion whose width is greater than the widths of a base portion and a top portion of the groove. In one or more of the above and following embodiments, a width of the groove in a cross section defined by the first direction and the vertical direction becomes larger, smaller, larger, and then smaller from the bottom to a top. In one or more of the above and following embodiments, the groove has a (111) crystal facet made of Si.

Claims

[1] A method of manufacturing a semiconductor device, comprising: Forming a fin structure (29) in which first semiconductor layers (20) and second semiconductor layers (25) are alternately stacked; Forming a sacrificial gate structure (38) over the fin structure (29); Etching the first semiconductor layers (20), the second semiconductor layers (25) and an upper portion of a well portion (11) of the fin structure (29) at a source / drain region of the fin structure (29) that is not covered by the sacrificial gate structure (38); Forming a dielectric layer (35) over the etched portion of the well portion (11), and Forming an epitaxial source / drain layer (50), wherein: the epitaxial source / drain layer (50) is connected to ends of the second semiconductor layers (25), and a bottom of the epitaxial source / drain layer (50) is separated from the well portion (11) by the dielectric layer (35). [2] The method of claim 1, further comprising, after the first semiconductor layers (20), the second semiconductor layers (25) and the upper portion of the well portion (11) are etched, laterally etching the first semiconductor layers (20). [3] The method of claim 2, wherein the dielectric layer (35) is also formed on laterally etched ends of the first semiconductor layers (20). [4] A method according to any one of the preceding claims, wherein, after the first semiconductor layers (20), the second semiconductor layers (25) and the upper portion of the well portion (11) have been etched, the etched upper portion of the well portion (11) is further etched while the first (20) and second semiconductor layers (25) are protected by a cap layer (34). [5] The method of claim 4, wherein the etched upper portion of the tub portion (11) is etched by wet etching. [6] A method according to any one of claims 4 or 5, wherein the cap layer (34) is removed after the etched upper portion of the well portion (11) is further etched and before the dielectric layer (35) is formed. [7] The method of any preceding claim, further comprising, after forming the epitaxial source / drain layer (50): Forming a dielectric interface layer, hereinafter referred to as ILD layer, (80); Removing the sacrificial gate structure (38), thereby exposing a portion of the fin structure (29); Removing the first semiconductor layers (20) from the exposed fin structure (29), thereby forming channel layers (25) comprising the second semiconductor layers (25), and Forming a gate dielectric layer (102) and a gate electrode layer (104) around the channel layers (25). [8] The method of claim 7, wherein: a bottom section of the fin structure (29) is embedded in a separating insulating layer (15), and the dielectric layer (35) consists of a material that is different from that of the isolation insulating layer (15) and the ILD layer (80). [9] Method according to claim 7 or 8, wherein the first semiconductor layers (20) are made of Si 1-x Ge x , and the second semiconductor layers (25) made of Si 1-y Ge y where 0 ≤ x < y < 1. [10] Method according to claim 7 or 8, wherein the first semiconductor layers (20) are made of Si 1-x Ge x and the second semiconductor layers (25) consist of Si, where 0.2 ≤ x ≤ 0.

8. [11] Method according to one of the preceding claims, wherein the dielectric layer (35) consists of SiCO or SiOCN. [12] Method according to one of claims 1 to 10, wherein the dielectric layer (35) consists of silicon oxide or silicon nitride. [13] A method of manufacturing a semiconductor device, comprising: Forming a fin structure (29) in which first semiconductor layers (20) and second semiconductor layers (25) are alternately stacked; Forming a sacrificial gate structure (38) over the fin structure (29); Forming a sidewall spacer (32) on one side of the sacrificial gate structure (38); Etching the first semiconductor layers (20), the second semiconductor layers (25) and an upper portion of a well portion (11) of the fin structure (29) that are not covered by the sacrificial gate structure (38) and the sidewall spacer (32); Forming a cover layer (34) to cover the first semiconductor layers (20) and the second semiconductor layers (25). Etching the upper portion of the tub portion (11); Forming a dielectric layer (35) over the etched portion of the well portion (11), and Forming an epitaxial source / drain layer (50). [14] The method of claim 13, wherein the cover layer (34) comprises a silicon oxide layer and a silicon nitride layer. [15] The method of claim 13 or 14, further comprising, after the first semiconductor layers (20), the second semiconductor layers (25) and the upper portion of the well portion (11) have been etched and before the cap layer (34) is formed, laterally etching the first semiconductor layers (20) under the sidewall spacer (32). [16] The method of claim 15, wherein the cap layer (34) is removed after the etched upper portion of the well portion (11) is further etched and before the dielectric layer (35) is formed. [17] A method according to any one of claims 13 to 16, wherein the etched upper portion of the tub portion (11) is etched by wet etching. [18] A semiconductor device comprising: Semiconductor wires (25) arranged vertically and extending in a first direction (X), each of which has a channel region, and an epitaxial source / drain layer (50) connected to ends of the semiconductor wires (25), wherein the semiconductor wires (25) and the epitaxial source / drain layer (50) are arranged over a well section (11), and a bottom of the epitaxial source / drain layer (50) is separated from the well section (11) by a dielectric layer (35) which is arranged in a groove (18) in the well section (11) below the epitaxial source / drain layer (50), wherein the groove (18) in the well section (11) has been etched by one or more etching processes and has a U-shape or a V-shape in a cross-section along a second direction (Y) perpendicular to the first direction. [19] A semiconductor device according to claim 18, further comprising: a separating insulating layer (15) in which the tub section (11) is embedded, and a dielectric interface layer, hereinafter referred to as ILD layer, (80) covering the epitaxial source / drain layer (50), wherein the dielectric layer (35) is made of a material different from that of the isolation insulating layer (15) and the ILD layer (80). [20] A semiconductor device according to claim 18 or 19, wherein the dielectric layer (35) is in contact with the epitaxial source / drain layer (50) and the well portion (11).

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