Threshold voltage tuning for fin-based integrated circuit device and associated equipment

Abstract

Procedure, comprehensive: Forming a first opening (130A, 130B, 130C, 130D) in a first gate structure (110A, 110B, 110C, 110D) and a second opening (130A, 130B, 130C, 130D) in a second gate structure (110A, 110B, 110C, 110D), wherein the first gate structure (110A, 110B, 110C, 110D) is arranged over a first fin structure (106A, 106B, 106C, 106D) and the second gate structure (110A, 110B, 110C, 110D) is arranged over a second fin structure (106A, 106B, 106C, 106D); and Filling the first opening (130A, 130B, 130C, 130D) and the second opening (130A, 130B, 130C, 130D) using: Formation of a gate dielectric layer (140), Forming a threshold voltage tuning layer (144) over the gate dielectric layer (140), wherein the threshold voltage tuning layer (144) comprises tantalum and nitrogen, Etching back the threshold voltage tuning layer (144) in the second opening (130A, 130B, 130C, 130D) using a tungsten chloride-containing precursor, Forming an output work layer (146, 172) above the threshold voltage tuning layer (144), and Formation of a metal fill layer (182) over the work function layer (146, 172), wherein the re-etching of the threshold voltage tuning layer (144) includes tuning etching parameters to reduce a threshold voltage belonging to the second gate structure (110A, 110B, 110C, 110D) with respect to a threshold voltage belonging to the first gate structure (110A, 110B, 110C, 110D).

Description

STATE OF THE ART

[0001] The integrated semiconductor (IC) circuit manufacturing industry has experienced exponential growth. Technological advances in materials and IC design have spawned generations of ICs, each generation featuring smaller and more complex circuits than the previous one. As ICs have evolved, functional density (i.e., the number of interconnected components per unit area of ​​the chip) has generally increased, while geometric dimensions (i.e., the smallest component (or lead) that can be manufactured using a given process) have decreased. This process of downscaling is generally beneficial due to increased productivity and reduced associated costs.

[0002] With such downscaling, the complexity of IC processing and fabrication has also increased, and similar developments in IC processing and fabrication are needed to realize these advances. For example, gate-swapping processes have been implemented, which typically involve replacing polysilicon gate electrodes with metal gate electrodes to improve device performance. The work function values ​​of the metal gate electrodes are matched during the gate-swapping process to provide different devices with varying threshold (operating) voltages. While existing gate-swapping processes and corresponding threshold voltage matching processes have generally been adequate for their intended purposes, they have not been entirely satisfactory as IC technologies have been scaled down.

[0003] US 2017 / 0 110 324 A1 describes a method for manufacturing a fin-like field-effect transistor using a pretreatment process to remove oxide layers on a tantalum nitride and a titanium nitride layer.

[0004] The pretreatment process removes a respective oxide layer that has formed through the oxidation of part of the tantalum nitride and titanium nitride layers.

[0005] US 2015 / 0 357 244 A1 describes a semiconductor device with transistors, each having a gate stack with a different effective work function.

[0006] US 2016 / 0 093 536 A1 concerns an integrated circuit comprising a substrate, a first transistor, a second transistor, and a third transistor. The first transistor has a first metal gate comprising a first lower barrier layer, a first metal layer with a specified work function, and a first metal layer. The second transistor has a second metal gate comprising a second lower barrier layer, a second metal layer with a specified work function, and a second metal layer. The third transistor has a third metal gate comprising a third lower barrier layer, a third metal layer with a work function, and a third metal layer.

[0007] US 2016 / 0086946A1 describes the fabrication of gate stacks of an NMOS and a PMOS transistor, wherein a sacrificial layer is doped and a dopant diffuses from the sacrificial layer into an underlying tantalum nitride etch stop layer and a titanium nitride barrier layer. Subsequently, the sacrificial layer is removed and the thickness of the tantalum nitride etch stop layer in the NMOS region is reduced.

[0008] US 2016 / 0 276 214 A1 describes an etching process using tungsten chloride.

[0009] CN 1 03 531540 A describes the fabrication of gate structures in an NMOS region and a PMOS region, wherein a gate consisting of titanium nitride, tantalum nitride, and / or MoN is formed on a gate dielectric in both regions. The gate in the PMOS region is then etched, reducing its layer thickness compared to the NMOS region. Subsequently, an aluminum layer is formed over the gates in both regions, and an annealing process is performed. The reduced layer thickness of the gate in the PMOS region results in more aluminum atoms diffusing into the underlying gate dielectric than in the NMOS region.

[0010] The invention is defined by the main claim and the dependent claims. Further embodiments of the invention are described by the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The present disclosure is best understood with reference to the detailed description below, when read together with the accompanying figures. It is emphasized that, in accordance with standard industry practice, the various features are not drawn to scale and are used for illustrative purposes only. In fact, the dimensions of the various features may have been enlarged or reduced at will for the sake of clarity. Fig. Figure 1A is a flowchart of a method for manufacturing a fin-based integrated circuit device according to various embodiments of the present disclosure. Fig. 1B is a flowchart of a process for manufacturing metal gate stacks for a fin-based integrated circuit device, which is described in the process of Fig. 1A can be realized according to the various forms of the present revelation. The Fig. 2A-2L are incomplete graphical representations of a fin-based integrated circuit device, in part or in its entirety, at various stages of manufacture, such as those relating to the process of Fig. 1 belong, according to the various forms of the present revelation. Fig. Figure 3 is an incomplete graphical representation of a multi-chamber processing system of an integrated circuit according to various embodiments of the present disclosure. DETAILED DESCRIPTION

[0012] The present disclosure relates generally to integrated circuit devices and in particular to a fin-based voltage threshold tuning for integrated circuit devices.

[0013] The following disclosure provides many different embodiments or examples to realize the various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the formation of a first feature above or on top of a second feature in the following description may include embodiments in which the first and second features are in direct contact, and it may also include embodiments in which additional features may be formed between the first and second features such that the first and second features cannot make direct contact.

[0014] Furthermore, reference numerals and / or letters may be repeated in the various examples in this disclosure. This repetition serves the purpose of simplicity and clarity and does not in itself imply any relationship between the various embodiments and / or configurations discussed. Furthermore, the formation of a feature on another feature connected to and / or coupled to it in the following description may include embodiments in which the features are in direct contact, and it may also include embodiments in which additional features inserted between the features are formed in such a way that the features cannot directly contact each other. In addition, spatial relational terms such as "lower", "upper", "horizontal", "vertical", "above", "over", "below", "under", "up", "down", "top", "bottom", etc., as well as their derivatives (e.g.,The terms "horizontal", "downward", "upward", etc.) are used to simplify the present disclosure and describe the relationship of one feature to another. These spatial relational terms are intended to encompass various orientations of the component, including its features.

[0015] This disclosure reveals various methods for forming gate stacks and associated gate structures that can be implemented in any of a variety of device types. For example, embodiments of this disclosure can be designed to form gate stacks suitable for planar field-effect transistors (FETs), multi-gate transistors (planar or vertical), such as fin-type FETs (FinFETs), all-around gate (GAA) devices, omega-gate (Ω-gate) devices, or pi-gate (Π-gate) devices, as well as strained semiconductor devices, semiconductor-on-insulator (SOI) devices, partially depleted SOI devices, fully depleted SOI devices, or other devices.In the present disclosure, it is assumed that a person skilled in the art will recognize further integrated circuit devices that can benefit from the gate fabrication methods and / or gate structures described herein.

[0016] Fig. Figure 1A is a flowchart of a method 10 for fabricating an integrated circuit device according to various embodiments of the present disclosure. At block 12, the method 10 comprises forming a first gate structure over a first fin structure and a second gate structure over a second fin structure. A first FinFET has the first gate structure and a second FinFET has the second gate structure. At block 14, the method 10 comprises removing a portion of the first gate structure and the second gate structure, thereby forming a first opening and a second opening. In some embodiments, a dummy gate stack (which, for example, has a polysilicon gate electrode) is removed from the first gate structure and the second gate structure.At block 16, process 10 comprises filling the first and second orifices with stacks of metal gates such that the first threshold voltage of the first FinFET is greater than the second threshold voltage of the second FinFET. Process 10 can be continued to complete the fabrication of the first and second FinFETs. For example, a multilayer interconnect structure can be fabricated to enable the operation of the first and second FinFETs. Additional steps can be provided before, during, and after process 10, and some of the described steps can be deferred, substituted, or omitted for additional embodiments of process 10.

[0017] Fig. Figure 1B is a flowchart of a process 20 for the production of metal gate stacks, which are described in block 16 of process 10 of Fig. 1A can be realized according to various embodiments of the present disclosure. At block 22, the method 20 comprises forming a gate dielectric layer, such as a high-k dielectric layer, in a first opening of a first gate structure and a second opening of a second gate structure. A first FinFET can have the first gate structure, and a second FinFET can have the second gate structure. At block 24, the method 20 comprises forming a threshold voltage tuning layer over the gate dielectric layer. The threshold voltage tuning layer comprises a material with a work function value that depends on the thickness of the threshold voltage tuning layer. The threshold voltage tuning layer comprises, for example, tantalum and nitrogen. In some embodiments, a cover layer is formed over the gate dielectric layer before the threshold voltage tuning layer is formed.At block 26, the process 20 comprises back-etching the threshold voltage tuning layer in the second orifice using a tungsten chloride-containing precursor. Back-etching reduces the thickness of the threshold voltage tuning layer of the second gate structure, thereby lowering the threshold voltage of the second FinFET. At block 28, the process 20 comprises forming a work function layer over the threshold voltage tuning layer. In some embodiments, the work function layer is formed after back-etching. In other embodiments, the work function layer is formed before back-etching. In such embodiments, the work function layer is removed from the second orifice before back-etching.In some embodiments, the work-of-flow layer comprises a first work-of-flow layer formed over the threshold voltage tuning layer before back-etching, and a second work-of-flow layer formed after back-etching. In such embodiments, the first work-of-flow layer is removed from the second opening before back-etching. In some embodiments, the second work-of-flow layer is formed only in the first opening. On block 30, method 20 includes forming a metal fill layer over the work-of-flow layer. Additional steps may be provided before, during, and after method 20, and some of the described steps may be deferred, substituted, or omitted for additional embodiments of method 20.

[0018] The Fig. Figures 2A-2L are incomplete graphical representations of a fin-based integrated circuit device 100, in part or in its entirety, in the various manufacturing stages (such as those relating to the process 10 in Fig. 1A and Fig. 1B) according to various embodiments of the present disclosure. The fin-based integrated circuit device 100 may be contained in a microprocessor, a memory, and / or another integrated circuit device. In some embodiments, the fin-based integrated circuit device 100 may be part of an IC chip, a system-on-a-chip (SoC), or part thereof comprising various passive and active microelectronic components, such as resistors, capacitors, inductive components, diodes, p-type FETs (PFETs), n-type FETs (NFETs), metal-oxide-semiconductor FETs (MOSFETs), complementary MOS transistors (CMOS transistors), bipolar transistors (BJTs), laterally diffused MOS transistors (LDMOS transistors), high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof.The various types of transistors can be planar transistors or multi-gate transistors, such as FinFETs, depending on the design requirements of the fin-based integrated circuit device 100. The... Fig. For clarity, figures 2A-2L have been simplified to better illustrate the inventive concept of the present disclosure. In other embodiments of the fin-based integrated circuit device 100, additional features may be added, and some of the features described below may be replaced, modified, or omitted.

[0019] With reference to Fig. In section 2A, the fin-based integrated circuit device 100 has a substrate (wafer) 102. Various regions are defined for the substrate 102, such as a high-voltage n-type region (HV-N region) 104A, a low-voltage n-type region (LV-N region) 104B, a low-voltage p-type region (LV-P region) 104C, and a high-voltage p-type region (HV-P region) 104D. The HV-N region 104A and the HV-P region 104D have high-voltage transistors (HVTs), and the LV-N region 104B and the LV-P region 104C have low-voltage transistors (LVTs), with a threshold voltage (Vth). tThe threshold voltage of the high-voltage transistors (HVTs) is greater than the threshold voltage of the low-voltage transistors (LVTs). In some configurations, the n-type transistors have a threshold voltage of approximately 0.1 V to approximately 0.25 V, and the p-type transistors have a threshold voltage of approximately 0.14 V to approximately 0.29 V, where the threshold voltage of an n-type transistor in the HV-N range (104A) is higher than the threshold voltage of an n-type transistor in the LV-N range (104B), and the threshold voltage of a p-type transistor in the HV-P range (104D) is higher than the threshold voltage of a p-type transistor in the LV-P range (104C). In some configurations, the LVTs are logic transistors, core transistors, SRAM transistors, input / output (I / O) transistors, or other devices that are operated by essentially using a rated voltage.In some embodiments, the HVTs feature I / O transistors that convert a higher input threshold voltage (for example, a power supply voltage) into a lower threshold voltage suitable for LVTs, such as core transistors. Continuing the described embodiment, the HV-N range 104A, LV-N range 104B, LV-P range 104C, and HV-P range 104D feature one or more FinFETs configured as HVTs and / or LVTs, as further described below.In some embodiments, the HV-N area 104A, LV-N area 104B, LV-P area 104C, and / or HV-P area 104D may be adjacent to one another, but this is not mandatory. Depending on the design requirements of the fin-based integrated circuit device 100, any number of components or component features (e.g., insulation features, dummy features, and / or other component features) may be configured between the HV-N area 104A, LV-N area 104B, LV-P area 104C, and / or HV-P area 104D. Furthermore, depending on the design requirements of the fin-based integrated circuit device 100, the HVTs and / or LVTs may have different threshold voltages (operating voltages) than those explicitly specified here.

[0020] In the illustrated embodiment, the substrate 102 is a semiconductor substrate comprising, for example, silicon. Alternatively or additionally, the substrate 102 comprises another elemental semiconductor, such as germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, such as silicon-germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Alternatively, the substrate 102 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. Semiconductor-on-insulator substrates can be fabricated using separation by oxygen implantation (SIMOX), wafer bonding and / or other suitable methods.Depending on the device requirements of the HV-N range 104A, LV-N range 104B, LV-P range 104C, and / or HV-P range 104D, the substrate 102 can have various doped regions (not shown). In some versions, the substrate 102 has p-doped regions (for example, p-type wells) doped with p-type dopants such as boron (for example, BF₂), indium, another p-type dopant, or combinations thereof. In some versions, the substrate 102 has n-doped regions (for example, n-type wells) doped with n-type dopants such as phosphorus, arsenic, another n-type dopant, or combinations thereof. In some embodiments, the substrate has 102 doped regions that are doped with a combination of p-type dopants and p-type dopants.The differently doped regions can be formed directly on and / or in a substrate 102 by, for example, providing a p-well structure, an n-well structure, a double-well structure, a raised structure, or combinations thereof. To form the differently doped regions of the substrate 102, an ion implantation process, a diffusion process, and / or another suitable doping process can be carried out.

[0021] The HV-N region 104A, LV-N region 104B, LV-P region 104C, and HV-P region 104D each feature at least one fin structure, such as fin structure 106A, fin structure 106B, fin structure 106C, and fin structure 106D, respectively. Although not apparent from the illustration, fin structure 106A, fin structure 106B, fin structure 106C, and / or fin structure 106D may have more than one fin, depending on the design requirements of their respective FinFET device. In some embodiments, fin structures 106A-106D are part of the substrate 102 (such as part of a material layer of the substrate 102). For example, fin structures 106A-106D feature silicon if the substrate 102 contains silicon.

[0022] Alternatively, in some embodiments, the fin structures 106A-106D are formed in a material layer, such as one or more semiconductor material layers, located on top of the substrate 102. For example, the fin structures 106A-106D can comprise a semiconductor layer stack having different semiconductor layers (such as a heterostructure) arranged on top of the substrate 102. The semiconductor layers can have any suitable semiconductor materials, such as silicon, germanium, silicon-germanium, other suitable semiconductor materials, or combinations thereof. Depending on the design requirements of the fin-based integrated circuit device 100, the semiconductor layers can have the same or different materials, etch rates, atomic percentages of the components, weight percentages of the components, thicknesses, and / or configurations.In some designs, the semiconductor layer stacks feature alternating semiconductor layers, such as semiconductor layers composed of one material and semiconductor layers composed of a second material. For example, silicon layers and silicon-germanium layers alternate in the semiconductor layer stack (e.g., SiGe / Si / SiGe / Si / SiGe / Si from bottom to top). In some designs, the semiconductor layer stack features semiconductor layers of the same material but with alternating atomic percentages of the constituents, such as semiconductor layers containing one constituent with a first atomic percentage and semiconductor layers containing a constituent with a second atomic percentage. For example, the semiconductor layer stack features silicon-germanium layers with alternating silicon and / or germanium atomic percentages (e.g., Si). a Ge b / Si cGe d / Si a Ge b / Si c Ge d / Si a Ge b / Si c Ge d (from bottom to top, where a and c represent different silicon atom percentages and b and d represent different germanium atom percentages). In some embodiments, fin structure 106A, fin structure 106B, fin structure 106C, and / or fin structure 106D feature the same materials and / or the same semiconductor layer stacks, depending on the design requirements of their respective FinFET device. In some embodiments, fin structure 106A, fin structure 106B, fin structure 106C, and / or fin structure 106D feature different materials and / or different semiconductor layer stacks, depending on the design requirements of their respective FinFET device.

[0023] The fin structures 106A-106D are produced on top of the substrate 102 using a suitable process. In some embodiments, a combination of deposition, lithography, and / or etching processes is used to establish fin structures 106A-106D extending from the substrate 102, as shown in Fig. Figure 2A illustrates the formation of the fin structures 106A-106D. This process includes, for example, performing a lithography process to form a structured photoresist layer (or a material layer, such as a heterostructure arranged over the substrate 102) on top of the substrate 102, and performing an etching process to transfer a structure defined in the structured photoresist layer to the substrate 102 (or the material layer, such as the heterostructure arranged over the substrate 102). The lithography process may include forming a photoresist layer on the substrate 102 (for example, by rotoplating), performing a pre-irradiation bake-off process, performing an irradiation process using a mask, performing a post-irradiation bake-off process, and performing a development process.During the irradiation process, the photoresist layer is exposed to radiant energy (such as ultraviolet (UV) light, deep UV (DUV) light, or extreme UV (EUV) light). Depending on the mask's structure and / or type (e.g., binary mask, phase-shift mask, or EUV mask), the mask blocks, transmits, and / or reflects the radiation towards the photoresist layer in such a way that an image corresponding to the mask structure is projected onto the photoresist layer. Because the photoresist layer is sensitive to radiant energy, the exposed parts of the photoresist layer undergo chemical changes. These exposed (or non-exposed) parts are then dissolved during the development process, depending on the properties of the photoresist layer and the properties of the developer solution used.After development, the structured photoresist layer exhibits a photoresist pattern corresponding to the mask. During the etching process, the structured photoresist layer is used as an etching mask to remove portions of the substrate 102 (or a material layer placed above the substrate 102). The etching process can include a dry etching process (for example, a reactive ion etching (RIE) process), a wet etching process, another suitable etching process, or combinations thereof. After the etching process, the structured photoresist layer is removed from the substrate 102, for example, by a photoresist removal process. Alternatively, the fin structures 106A-106D are formed by a multi-structuring process, such as…a double structuring lithography process (DPL process) (for example, a lithography-etch-lithography-etch process (LELE process), a self-alignment double structuring process (SADP process), a spacer-is-dielectric (SID) SADP process, another double structuring process, or combinations thereof), a triple structuring process (for example, a lithography-etch-lithography-etch-lithography-etch process (LELELE process), a self-alignment triple structuring process (SATP process), another triple structuring process, or combinations thereof), another multiple structuring process (for example, a self-alignment quadruple structuring process (SAQP process)), or combinations thereof. In some embodiments, directed self-assembly techniques (DSA techniques) are implemented during the formation of the fin structures 106A-106D.Furthermore, in some versions, the irradiation process can employ maskless lithography, electron beam (E-beam) writing, ion beam writing and / or nanoprint technology to structure the photoresist layer.

[0024] Insulation features are formed above and / or within the substrate 102 to isolate various regions and / or features of a fin-based integrated circuit device 100. For example, the insulation features define and electrically isolate an HV-N region 104A, an LV-N region 104B, an LV-P region 104C, and / or an HV-P region 104D, the fin structures 106A-106D, and / or the fins of the fin structures 106A-106D from one another. The insulation features comprise silicon oxide, silicon nitride, silicon oxynitride, another suitable insulating material (comprising, for example, silicon, oxygen, nitrogen, carbon, or another suitable insulating material), or combinations thereof. The insulation features can have different structures, such as shallow trench insulation (STI) structures, deep trench insulation (DTI) structures, and / or structures with local oxidation of silicon (LOCOS structures).In some embodiments, insulation features are formed by etching a trench in the substrate 102 and filling the trench with an insulator material (for example, using a chemical vapor deposition process or a glass spin-deposition process). To remove excess insulator material and / or to planarize a cover surface of insulation features, a chemical-mechanical polishing (CMP) process can be performed. In some embodiments, the insulation features can be formed by depositing an insulator material over the substrate 102 after the fin structures 106A-106D have been formed (in some embodiments such that the insulator material layer fills the gaps (trenches) between the fin structures 106A-106D) and then etching back the insulator material layer. In some embodiments, the insulation features have a multilayer structure that fills the trenches, such as...A bulk dielectric layer arranged over a lining dielectric layer, wherein the bulk dielectric layer and the lining dielectric layer comprise materials that depend on design requirements (where, for example, a bulk dielectric layer comprising silicon nitride is arranged over a lining dielectric layer comprising a thermal oxide). In some embodiments, the insulating features include a dielectric layer arranged over a doped lining layer (which comprises, for example, boron-doped silicon glass (BSG) or phosphorus silicate glass (PSG)).

[0025] Various gate structures are arranged above the fin structures 106A-106D, such as gate structure 110A above fin structure 106A, gate structure 110B above fin structure 106B, gate structure 110C above fin structure 106C, and gate structure 110D above fin structure 106D. Although not apparent from the illustrated view, gate structures 110A-110D each enclose a portion of the corresponding fin structure 106A-106D in such a way that gate structures 110A-110D are positioned between a source region and a drain region (collectively referred to as source / drain regions) of the fin structures 106A-106D. The gate structures 110A-110D attack the channel areas defined between the source areas and the drain areas in such a way that a current can flow between the source / drain areas during operation.In the illustrated embodiment, the gate structures 110A-110D have gate stacks configured for a gate-load process. For example, the gate structures 110A-110D each have interface layers 112A-112D (which, for example, have silicon and oxygen, such as silicon oxide) and dummy gate layers 114A-114D (which, for example, have polysilicon). The dummy gate layers 114A-114D can have a multilayer structure. For example, in some embodiments, the dummy gate layers 114A-114D have a dummy gate dielectric layer and a dummy gate electrode layer. In some embodiments, the gate structures 110A-110D have polysilicon gates such that the dummy gate layers 114A-114D have a polysilicon layer. The gate structures 110A-110D are formed by deposition processes, lithography processes, etching processes, other suitable processes or combinations thereof.For example, a thermal oxidation process can be performed to form an interface layer over substrate 102, particularly over the fin structures 106A-106D. One or more deposition processes are then performed to form a dummy gate layer over the interface layer. In some embodiments, a deposition process is performed to form a dummy gate dielectric layer over the interface layer, and a deposition process is performed to form a dummy gate electrode layer over the dummy gate dielectric layer. Deposition processes include CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), high plasma density CVD (HDPCVD), metal-organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma-enhanced CVD (PECVD), low pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), plating, other suitable methods or combinations thereof.A lithographic structuring and etching process is then performed to structure the interface layer and the dummy gate layer (in some embodiments, a dummy gate dielectric layer and a dummy gate electrode layer) to form dummy gate stacks such that the dummy gate stacks (including the interface layers 112A-112D and the dummy gate layers 114A-114D) enclose the channel regions of the fin structures 106A-106D. The lithographic structuring processes include photoresist coating (e.g., rotary coating), weak annealing, mask alignment, irradiation, post-irradiation annealing, photoresist development, rinsing, drying (e.g., baking), other suitable processes, or combinations thereof. Alternatively, the lithographic irradiation process is supported, implemented, or replaced by other methods, such as maskless lithography, electron beam writing, or ion beam writing.In yet another alternative, the lithography structuring process utilizes nanoprinting technology. The etching processes include dry etching, wet etching, other etching methods, or combinations thereof.

[0026] The gate structures 110A-110D further comprise spacers 116A-116D arranged adjacent to the gate stacks (here, the respective interface layers 112A-112D and dummy gate layers 114A-114D) (for example, along the side walls of the gate stacks). The spacers 116A-116D are formed by any suitable process and comprise a dielectric material. The dielectric material can be silicon, oxygen, carbon, nitrogen, another suitable material, or combinations thereof (for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide). For example, in the illustrated embodiment, a dielectric layer comprising silicon and nitrogen, such as a silicon nitride layer, can be deposited over a substrate 102 and subsequently anisotropically etched to form the spacers 116A-116D. In some versions, the 116A-116D spacers have a multi-layer structure, such as...A first dielectric layer comprising silicon nitride and a second dielectric layer comprising silicon oxide. In some embodiments, more than one set of spacers, such as sealing spacers, offset spacers, sacrificial spacers, dummy spacers, and / or main spacers, is formed adjacent to the gate stacks. In such embodiments, the different sets of spacers may have materials with different etch rates.For example, a first dielectric layer containing silicon and oxygen (e.g., silicon oxide) can be deposited on substrate 102 and subsequently anisotropically etched to form a first set of spacers adjacent to the gate stacks. Similarly, a second dielectric layer containing silicon and nitrogen (e.g., silicon nitride) can be deposited on substrate 102 and subsequently anisotropically etched to form a second set of spacers adjacent to the first. Depending on the design requirements of the fin-based integrated circuit device 100, implantation, diffusion, and / or annealing processes can be performed before and / or after the formation of the spacers 116A-116D to create weakly doped source and drain features (LDD features) and / or heavily doped source and drain features (HDD features) in the source / drain regions of the fin structures 106A-106D.

[0027] Epitaxial source features and epitaxial drain features (referred to as epitaxial source / drain features) are arranged in the source / drain regions of the fin structures 106A-106D. For example, a semiconductor material is grown epitaxially on the fin structures 106A-106D, with the epitaxial source / drain features 118A-118D forming over the fin structures 106A-106D. In the illustrated embodiment, the gate structures 110A-110D are positioned between the epitaxial source / drain features 118A-118D. In some embodiments, the epitaxial source / drain features 118A-118D enclose the source / drain regions of the fin structures 106A-106D. An epitaxy process can employ CVD deposition techniques (for example, vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), LPCVD and / or PECVD), molecular beam epitaxy, other suitable SEG processes or combinations thereof.In the epitaxial process, gaseous and / or liquid precursors can be used, which interact with the composition of the fin structures 106A-106D. The epitaxial source / drain features 118A-118D are doped with n-type and / or p-type dopants, depending on whether the HVTs and / or LVTs are configured as n-type devices (which, for example, have n channels) or p-type devices (which, for example, have p channels).In the illustrated embodiment, in which the HV-N region 104A and the LV-N region 104B are configured with n-type FinFETs, the epitaxial source / drain features 118A and the epitaxial source / drain features 118B are epitaxial layers comprising silicon and / or carbon, wherein the silicon-containing epitaxial layers or silicon-carbon-containing epitaxial layers are doped with phosphorus, another n-type dopant, or combinations thereof (forming, for example, a Si:P epitaxial layer or a Si:C:P epitaxial layer).Further developing the described embodiment in which the LV-P region 104C and the HV-P region 104D are configured with p-type FinFETs, the epitaxial source / drain features 118C and 118D are epitaxial layers comprising silicon and germanium, wherein the silicon-germanium-containing epitaxial layers are doped with boron, another p-type dopant, or combinations thereof (for example, forming a Si:Ge:B epitaxial layer). This disclosure considers embodiments in which the epitaxial source / drain features 118A-118D comprise the same or different materials and / or the same or different dopants.This disclosure further considers embodiments in which the fin structures 106A-106D are recessed such that the epitaxial source / drain features 118A-118D grow from recessed portions of the fin structures 106A-106D. In some embodiments, the epitaxial source / drain features 118A-118D include materials and / or dopants with which the desired tensile and / or compressive stress is achieved in the channel regions. In some embodiments, the epitaxial source / drain features 118A-118D are doped during deposition by adding foreign atoms to a starting material of the epitaxial process. In some embodiments, the epitaxial source / drain features 118A-118D are doped by an ion implantation process following a deposition process.In some versions, tempering processes are performed to activate the dopants in the epitaxial source / drain features 118A-118D and / or other source / drain areas (for example, HDD areas and / or LDD areas).

[0028] An interlayer dielectric (ILD) layer 120 is deposited over the substrate 102, in particular over the fin structures 106A-106D and gate structures 110A-110D. In some embodiments, the ILD layer 120 is part of a multilayer interconnect (MLI) feature that electrically connects various devices (for example, transistors, resistors, capacitors and / or inductive devices) and / or components (for example, gate structures and / or source / drain features) of a fin-based integrated circuit device 100 in such a way that the various devices and / or components can function as specified by the design requirements of the fin-based integrated circuit device 100.The ILD layer 120 comprises a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, TEOS-shaped oxide, PSG, BPSG, low-k dielectric material, other suitable dielectric material, or combinations thereof. Examples of low-k dielectric materials include FSG, carbon-doped silicon oxide, Black Diamond® (Applied Materials of Santa Clara, California), xerogel, aerogel, amorphous fluorinated carbon, parylene, BCB, SiLK (Dow Chemical, Midland, Michigan), polyimide, other low-k dielectric material, or combinations thereof. In some embodiments, the ILD layer 120 has a multilayer structure with several dielectric materials. In some embodiments, a contact etch stop layer (CESL) is placed between the ILD layer 120 and the fin structures 106A-106D and / or gate structures 110A-110D. The CESL has a different material than the ILD layer 120, such as...a dielectric material that differs from the dielectric material of the ILD layer 120. In the illustrated embodiment, where the ILD layer 120 comprises a low-k dielectric material, the CESL comprises silicon and nitrogen (for example, silicon nitride or silicon oxynitride). The ILD layer 120 and / or the CESL are formed over the substrate 102, for example, by a deposition process (such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, plating, other suitable processes, or combinations thereof). In some embodiments, the ILD layers 120 and / or the CESL are formed by a flowable CVD (FCVD) process, which, for example, involves the deposition of a flowable material (such as...The process comprises the deposition of a liquid compound onto the substrate 102 and the conversion of the flowable material into a solid material by a suitable technique, such as thermal curing and / or ultraviolet radiation treatment. Following the deposition of the ILD layer 120 and / or the CESL, a CMP process and / or another planarization process is carried out such that an upper part of the gate structures 110A-110D is reached (exposed). In the illustrated embodiment, the cover surfaces of the dummy gate layers 114A-114D lie essentially in one plane with a cover surface of the ILD layer 120.

[0029] With reference to the Fig. In 2B-2L, a gate replacement process is performed in which dummy gate stacks of gate structures 110A-110D are replaced by metal gate stacks. With reference to Fig. 2B An etching process selectively removes the dummy gate layers 114A-114D of the gate structures 110A-110D, thereby forming an opening 130A in gate structure 110A, an opening 130B in gate structure 110B, an opening 130C in gate structure 110C, and an opening 130D in gate structure 110D. In the illustrated embodiment, the openings 130A-130D (also referred to as gate trenches) have sidewall surfaces, each defined by the spacers 116A-116D, and bottom surfaces, each defined by the interface layers 112A-112D. In some versions, where the interface layers 112A-112D are omitted from the gate structures 110A-110D, the openings 130A-130D have bottom surfaces defined by the fin structures 106A-106D. The etching process is a dry etching process, a wet etching process, or a combination thereof.The etching process can be tuned such that the dummy gate layers 114A-114D are removed without (or with minimal) etching of other features of the fin-based integrated circuit device 100, such as the ILD layer 120, the spacers 116A-116D, interface layers 112A-112D, and / or fin structures 106A-106D.

[0030] With reference to Fig. In step 2C, a gate dielectric layer 140 is formed over the fin-based integrated circuit device 100. For example, in an ALD process, a gate dielectric layer 140 is conformally deposited over the fin-based integrated circuit device 100 such that the gate dielectric layer 140 has a substantially uniform thickness and partially fills the openings 130A-130D. In the illustrated embodiment, the gate dielectric layer 140 is arranged on the sidewall and bottom surfaces that define the openings 130A-130D such that the gate dielectric layer 140 is located on the interface layers 112A-112D and the spacers 116A-116D. In some embodiments, the gate dielectric layer 140 has a thickness of approximately 0.5 nm to approximately 2.5 nm.In the illustrated embodiment, the gate dielectric layer 140 comprises a high-k dielectric material (and can thus be referred to as a high-k dielectric layer), such as hafnium dioxide (HfO₂), HfSiO₂, HfSiON₄, HfTaO, HfTiO₂, HfZrO₂, zirconium oxide, aluminum oxide, a hafnium dioxide-aluminum oxide (HfO₂-Al₂O₃) alloy, another suitable high-k dielectric material, or combinations thereof. High-k dielectric material generally refers to dielectric materials that have a high dielectric constant, for example, greater than that of silicon dioxide (k ≈ 3.9). In some embodiments, the gate dielectric layer 140 comprises a dielectric material such as silicon dioxide or another suitable dielectric material. Alternatively, the gate dielectric layer 140 is formed using another suitable deposition process, such as…CVD, PVD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, rotational coating, plating, another deposition process or combinations thereof.

[0031] With reference to Fig. In 2D, a cover layer 142 is formed over the gate dielectric layer 140. For example, using an ALD process, the cover layer 142 is conformally deposited on the gate dielectric layer 140 such that the cover layer 142 has a substantially uniform thickness and partially fills the openings 130A-130D. In some embodiments, the cover layer 142 has a thickness of approximately 0.5 nm to approximately 2.5 nm. The cover layer 142 comprises a material that prevents or inhibits diffusion and / or reaction of components between the gate dielectric layer 140 and other layers of the gate structures 110A-110D (especially gate layers containing metal). In some versions, the cover layer 142 contains a metal and nitrogen, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (W2N), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN) or combinations thereof.In the illustrated embodiment, the cover layer 142 comprises, for example, titanium and nitrogen (e.g., TiN). Alternatively, the cover layer 142 is deposited using another suitable deposition process, such as CVD, PVD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, rotational coating, plating, another deposition process, or combinations thereof.

[0032] The process continues to create different types of layers to provide the desired threshold voltages for LVTs in the low-voltage ranges, such as in the LV-N range 104B and LV-P range 104C, and for HVTs in the high-voltage ranges, such as in the HV-N range 104A and HV-P range 104D. The lower threshold voltages in the low-voltage ranges are typically achieved by increasing the thickness of a work function layer, such as a p-type and / or an n-type work function layer (described further below), relative to the thickness of the work function layer in the high-voltage ranges, and / or by incorporating dopants into the work function layer (for example, using an ion implantation process) in either the low-voltage or high-voltage ranges.However, as IC technology nodes shrink, preferably to 10 nm and beyond, the openings formed during the gate replacement process also shrink. Consequently, increasing the thickness of the work function layer to achieve lower threshold voltages negatively impacts gap filling. For example, increasing the thickness of the work function layer reduces the dimensions of the openings for the formation of subsequent gate layers, such as metal-filled layers. This can cause gaps and / or voids in the resulting gate structures, reducing the device's performance.Furthermore, the ion implantation processes are restricted by the fin height and fin spacing associated with the smaller technology nodes (as well as by the height of masking elements (e.g., photoresist layers) used to cover adjacent features during the ion implantation processes) in such a way that an upper part of the work function layer has a higher dopant concentration than a lower part. This phenomenon, which prevents uniform doping of the work function layer, is generally referred to as shadowing effects and can undesirably alter the device performance.The present disclosure overcomes the problems of gap filling and / or shadowing effects by implementing a threshold voltage tuning layer. This layer is composed of a material with an aluminum blocking capacity that decreases with decreasing thickness of the threshold voltage tuning layer, such that the threshold voltage decreases with decreasing thickness. As described in detail below, the gate structures in the low-voltage and high-voltage regions thus incorporate a threshold voltage tuning layer, with the thickness of the threshold voltage tuning layer in the low-voltage regions being smaller than the thickness of the threshold voltage tuning layer in the high-voltage regions.

[0033] With reference to Fig. In step 2E, a threshold voltage tuning layer 144 is formed over the cover layer 142. For example, an ALD process is used to conformally deposit a threshold voltage tuning layer 144 onto the cover layer 142 such that the threshold voltage tuning layer 144 has a substantially uniform thickness and partially fills the openings 130A-130D. In some embodiments, the threshold voltage tuning layer 144 has a thickness of approximately 1.0 nm to approximately 1.5 nm. In some embodiments, the ALD process comprises approximately twenty to approximately thirty ALD cycles. In some embodiments, the ALD process is carried out at a temperature of approximately 200°C to approximately 300°C. The threshold voltage tuning layer 144 has a material that has a work function value that depends on the thickness of the threshold voltage tuning layer 144, with the work function value decreasing as the thickness of the threshold voltage tuning layer 144 decreases.The threshold voltage tuning layer 144, for example, incorporates a material that can block aluminum (e.g., from a work function layer), thus preventing aluminum from penetrating other gate layers of the gate stack of the gate structures 110A-110D. The material's ability to block aluminum depends on the thickness of the threshold voltage tuning layer 144; the ability to block aluminum decreases as the thickness of the threshold voltage tuning layer 144 decreases. Accordingly, a decrease in the thickness of the threshold voltage tuning layer 144 reduces the ability to block aluminum, and the work function of the corresponding device also decreases. Conversely, an increase in the thickness of the threshold voltage tuning layer 144 increases the ability to block aluminum, and the work function of the corresponding device also increases.Examples of materials for the threshold voltage tuning layer 144 include tantalum and nitrogen, such as TaN, TaSiN, TaCN, another tantalum-containing and nitrogen-containing material, or combinations thereof. In the illustrated embodiment, the threshold voltage tuning layer 144 comprises TaN. In such embodiments, the ALD process can include a tantalum-containing precursor and a nitrogen-containing precursor. Alternatively, the threshold voltage tuning layer 144 can be formed using another suitable deposition process, such as CVD, PVD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, spin coating, plating, another deposition process, or combinations thereof.

[0034] With reference to Fig. In 2F, a p-type work function layer 146 is formed over the threshold voltage tuning layer 144. For example, an ALD process is used to conformally deposit a p-type work function layer 146 on the threshold voltage tuning layer 144 such that the p-type work function layer has a substantially uniform thickness and partially fills the openings 130A-130D. In some embodiments, the p-type work function layer 146 has a thickness of approximately 1.0 nm to approximately 4.0 nm. In the illustrated embodiment, the thickness of the p-type 146 work function layer in n-type component areas (here the HV-N area 104A and the LV-N area 104B) is smaller than the thickness of the p-type 146 work function layer in p-type component areas (here the HV-P area 104D and the LV-P area 104C).For example, the thickness of the p-type 146 work function layer in the HV-N range 104A and / or LV-N range 104B is approximately 1.0 nm to approximately 2.0 nm, while the thickness of the p-type 146 work function layer in the HV-P range 104D and / or LV-P range 104C is approximately 2.0 nm to approximately 4.0 nm. In some embodiments, the ALD process comprises approximately twenty to approximately fifty ALD cycles. In some embodiments, the ALD process is carried out at a temperature of approximately 400°C to approximately 450°C (which is higher than the temperature achieved in the ALD process for forming the threshold voltage tuning layer 144). The p-type 146 work function layer incorporates any suitable p-type work function material, such as TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, another p-type work function material, or combinations thereof.In the illustrated embodiment, the p-type 146 work function layer comprises titanium and nitrogen, such as TiN. Alternatively, the p-type 146 work function layer is formed using another suitable deposition process, such as CVD, PVD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, spin coating, plating, another deposition process, or combinations thereof.

[0035] With reference to Fig. In step 2G, the p-type 146 work function layer is removed from the low-voltage regions of the fin-based integrated circuit device 100, such as the LV-N region 104B and the LV-P region 104C. For example, a structured masking layer 150 is formed over the fin-based integrated circuit device 100. The structured masking layer 150 has one or more openings 152 that expose the LV-N region 104B and the LV-P region 104C, in particular exposing the p-type 146 work function layer in the LV-N region 104B and the LV-P region 104C. The structured masking layer 150 is formed by any suitable process, including deposition processes, lithography processes, and / or the etching process described herein.In some embodiments, the structured masking layer 150 comprises a material with a different etching characteristic than the p-type work function layer 146 and / or the threshold voltage tuning layer 144. For example, the structured masking layer 150 comprises silicon, amorphous silicon, semiconductor oxide (e.g., silicon oxide (SiO2)), semiconductor nitride (e.g., silicon nitride (SiN)), semiconductor oxynitride (e.g., silicon oxynitride (SiON)), and / or semiconductor carbide (e.g., silicon carbide (SiC)), another semiconductor material, and / or another dielectric material. In some embodiments, the structured masking layer 150 comprises a photoresist material (and can thus be referred to as a structured photoresist layer and / or a structured photoresist layer).Then, any suitable process is used to remove the p-type 146 work function layer from the low-voltage regions, thereby exposing the threshold voltage tuning layer 144 in the LV-N region 104B and the LV-P region 104C, as shown. For example, the p-type 146 work function layer is removed in a wet etching process using an etching solution containing ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), sulfuric acid (H2SO4), tetramethylammonium hydroxide (TMAH), hydrochloric acid (HCl), another suitable wet etching solution, or combinations thereof. For example, the wet etching solution uses an NH4OH:H2O2 solution, an HCl:H2O2:H2O solution (known as a hydrogen chloride peroxide mixture (HPM)), an NH4OH:H2O2:H2O solution (known as an ammonium peroxide mixture (APM)), or an H2SO4:H2O2 solution (known as a sulfuric acid peroxide mixture (SPM)).In the illustrated embodiment, the work function layer of p-type 146 is removed by a wet etching process that employs an HPM.

[0036] With reference to Fig. In 2H, a threshold voltage tuning treatment 160 is performed on the threshold voltage tuning layer 144 in the low-voltage regions of the fin-based integrated circuit device 100, thereby reducing the threshold voltage of the LVTs in the LV-N region 104B and LV-P region 104C. During the threshold voltage tuning treatment 160, the threshold voltage tuning layer 144 in the LV-N region 104B and LV-P region 104C is back-etched using a chloride-containing precursor. In the illustrated embodiment, for example, the threshold voltage tuning treatment 160 back-etches the threshold voltage tuning layer 144 in the LV-N region 104B and LV-P region 104C using a tungsten chloride-containing precursor, such as tungsten pentachloride (WCl5).By reducing the thickness of the threshold voltage tuning layer 144 in the LV-N region 104B and LV-P region 104C, the ability of the threshold voltage tuning layer 144 to block aluminium in the LV-N region 104B and LV-P region 104C is reduced, thereby increasing the penetration of aluminium from the gate layers above the threshold voltage tuning layer 144 into the gate layers below the threshold voltage tuning layer 144, thus reducing the threshold voltage of the LVTs in the LV-N region 104B and LV-P region 104C. It was observed that adjusting the remaining thickness of the threshold voltage tuning layer 144 can reduce the threshold voltage of the low-voltage ranges, such as the LV-N range 104B and LV-P range 104C, with respect to the high-voltage ranges, such as the HV-N range 104A and HV-N range 104D, by as much as 120 mV.In the illustrated embodiment, the threshold voltage tuning layer 144 in LV-N region 104B and / or LV-P region 104C has a thickness of less than or equal to approximately 1.5 nm after the threshold voltage tuning treatment 160. In some embodiments, the threshold voltage tuning layer 144 in LV-N region 104B and / or LV-P region 104C is completely removed, depending on the threshold voltage requirements of the LV-N region 104B and / or LV-P region 104C. Various etching parameters, such as...The etchant composition, etching temperature, etchant solution concentration, etching time, etching pressure, source power, RF bias, RF bias power, etchant flow rate, other suitable etching parameters, or combinations thereof, are adjusted to achieve the desired threshold voltage tuning (by adjusting the thickness of the threshold voltage tuning layer 144 in the low-voltage ranges relative to the thickness of the threshold voltage tuning layer 144 in the high-voltage ranges). In some embodiments, an etching temperature of approximately 400°C to approximately 500°C is achieved during the threshold voltage tuning treatment 160. In some embodiments, an etching pressure of approximately 2.67 kPa (20 Torr) to approximately 4.0 kPa (30 Torr) is achieved during the threshold voltage tuning treatment 160. In some versions, the threshold voltage tuning treatment 160 takes place in less than or approximately 100 seconds.The structured masking layer 150 is then removed by any suitable process.

[0037] In some embodiments, the surfaces of the threshold stress tuning layer 144 can be oxidized during processing when exposed to an oxygen environment, such that the threshold stress tuning layer 144 has an oxidized surface (layer) containing tantalum and oxygen (for example, TaO). In some embodiments, the threshold stress tuning treatment 160 uses the tungsten chloride-containing precursor, such as WCl5, to both remove the oxidized surface in the LV-N region 104B and the LV-P region 104C and to re-etch the threshold stress tuning layer 144 in the LV-N region 104B and the LV-P region 104C. In some embodiments, a tantalum chloride-containing precursor, such as tantalum pentachloride (TaCl5), is used in the threshold voltage tuning treatment 160 to remove the oxidized area in the LV-N region 104B and LV-P region 104C, and then the tungsten chloride-containing precursor, such asWCl5 is used to etch back the threshold voltage tuning layer 144 in the LV-N region 104B and the LV-P region 104C. In some embodiments, the threshold voltage tuning treatment 160 uses only a tantalum chloride-containing precursor, such as TaCl5, to remove only the oxidized area, such that the threshold voltage tuning layer 144 has no oxidized area (layer) in the LV-N region 104B and the LV-P region 104C, while the threshold voltage tuning layer 144 has an oxidized area (layer) in the HV-N region 104A and the HV-P region 104D.

[0038] With reference to Fig. In the illustrated embodiment, an n-type work function layer 172 is formed over the fin-based integrated circuit device 100. In this embodiment, the n-type work function layer 172 is not formed in every region of the fin-based integrated circuit device 100. For example, a structured masking layer 174 is formed over the fin-based integrated circuit device 100 such that the structured masking layer 174 covers the LV-P region 104C and exposes the HV-N region 104A, LV-N region 104B, and HV-P region 104D. In particular, the structured masking layer 174 has one or more openings 176 which expose the p-type output work layer 146 in the HV-N area 104A and HV-P area 104D and the threshold voltage tuning layer 144 in the LV-N area 104B.The structured masking layer 174 is formed by any suitable process, including deposition processes, lithography processes, and / or the etching process described here. In some embodiments, the structured masking layer 174 comprises any suitable masking material, such as silicon, amorphous silicon, semiconductor oxide (e.g., SiO2), semiconductor nitride (e.g., SiN), semiconductor oxynitride (e.g., SiON), and / or semiconductor carbide (e.g., SiC), another semiconductor material, and / or another dielectric material. In some embodiments, the structured masking layer 174 comprises a photoresist material.Continuing the example, in an ALD process, an n-type output work layer 172 is deposited above the p-type output work layer 146 and / or the threshold voltage tuning layer 144 in such a way that the n-type output work layer 172 has a substantially uniform thickness and partially fills the openings 130A, 130B, and 130D. In the illustrated embodiment, the n-type output work layer 172 is thus arranged on the n-type output work layer 146 in the HV-N region 104A and the HV-P region 104D, and it is arranged on the threshold voltage tuning layer 144 in the LV-N region 104B. In some versions, the n-type 172 work function layer has a thickness of approximately 2.5 nm to approximately 4.5 nm. The n-type 172 work function layer can be any suitable n-type work function material, such as...Ti, Al, Ag, Mn, Zr, TiAl, TiAlC, TaC, TaCN, TaSiN, TaAl, TaAlC, TiAlN, another n-type work function material, or combinations thereof. In the illustrated embodiment, the n-type work function layer 172 comprises titanium and aluminum, such as TaAlC, TaAl, TiAlC, TiAl, TaSiAl, TiSiAl, TaAlN, or TiAlN. Alternatively, the n-type work function layer 172 is deposited using another suitable deposition process, such as CVD, PVD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, spin coating, plating, another deposition process, or combinations thereof.

[0039] With reference to Fig. In step 2J, an adhesive layer 180 is formed over the fin-based integrated circuit device 100. In the illustrated embodiment, the adhesive layer 180 is not formed in every region of the fin-based integrated circuit device 100. For example, the structured masking layer 174 remains over the LV-P region 104B, with the n-type work function layer 172 being exposed in the HV-N region 104A, LV-N region 104B, and HV-P region 104D. The adhesive layer 180 is thus formed in the HV-N region 104A, LV-N region 104B, and HV-P region 104D. For example, in an ALD process, an adhesive layer 180 is conformally deposited on the n-type 172 exit work layer such that the adhesive layer 180 has a substantially uniform thickness and partially fills the openings 130A, 130B, and 130D. The structured masking layer 174 is then removed by any suitable process.In some embodiments, the adhesive layer 180 has a thickness of approximately 1.0 nm to approximately 1.5 nm. The adhesive layer 180 comprises a material that promotes adhesion between adjacent layers, such as the n-type exit work layer 172 and the subsequently formed layers of the gate structures 110A-110D (for example, the metal filler layers). For example, the adhesive layer 180 comprises a metal (for example, W, Al, Ta, Ti, Ni, Cu, Co, another suitable metal, or combinations thereof), metal oxides, metal nitrides, or combinations thereof. In the illustrated embodiment, the adhesive layer 180 comprises titanium and nitrogen, such as TiN. Alternatively, the adhesive layer 180 is deposited using another suitable deposition process, such as CVD, PVD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, rotational coating, plating, another deposition process or combinations thereof.

[0040] With reference to Fig. In 2K, a metal filler (or volume) layer 182 is formed over the fin-based integrated circuit device 100. For example, the metal filler layer 182 is conformally deposited in an ALD process on the adhesive layer 180 (in the HV-N range 104A, LV-N range 104B, and HV-P range 104D) and on the threshold voltage tuning layer 144 (in the LV-P range 104C) such that the metal filler layer 182 has a substantially uniform thickness and fills the openings 130A-130D. In some embodiments, the metal filler layer 182 has a thickness of approximately 150 nm to approximately 300 nm. The metal filler layer 182 comprises a suitable conductive material, such as Al, W, and / or Cu. In the illustrated embodiment, the metal filler layer 182 comprises W. The metal filler layer 182 may additionally or jointly comprise other metals, metal oxides, metal nitrides, other suitable materials or combinations thereof.In some embodiments, a blocking layer 184 is optionally formed over the fin-based integrated circuit device 100 prior to the formation of the metal filler layer 182, such that the metal filler layer 182 is arranged above the blocking layer 184. For example, the blocking layer 184 is conformally deposited in an ALD process on the adhesive layer 180 and the threshold voltage tuning layer 144 such that the blocking layer 184 has a substantially uniform thickness and partially fills the openings 130A-130D. In some embodiments, the blocking layer 184 has a thickness of approximately 2.5 nm to approximately 3.5 nm. The blocking layer 184 has a material that blocks and / or reduces the diffusion between the gate layers, such as the metal filler layer 182 and the n-type work function layer 172 and / or the p-type work function layer 146.In the illustrated embodiment, the blocking layer 184 comprises titanium and nitrogen, such as TiN. Alternatively, the metal filler layer 182 and / or the blocking layer 184 are formed using another suitable deposition process, such as CVD, PVD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, spin coating, plating, another deposition process, or combinations thereof.

[0041] With reference to Fig. In step 2L, a planarization process is performed to remove excess gate material from the fin-based integrated circuit device 100 such that the gate structures 110A-110D have metal gate stacks. For example, a CMP process is performed until a cover surface of the ILD layer 120 is reached (exposed). In the illustrated embodiment, the cover surfaces of the gate structures 110A-110D lie essentially in one plane with a cover surface of the ILD layer 120 after the CMP process. Accordingly, an n-type FinFET 190A, which has a gate structure 110A, is arranged in the HV-N region 104A, an n-type FinFET 190B, which has a gate structure 110B, is arranged in the LV-N region 104B, a p-type FinFET 190C, which has a gate structure 110C, is arranged in the LV-P region 104C, and a p-type FinFET 190D, which has a gate structure 110D, is arranged in the HV-P region 104D.According to the configuration, the n-type FinFET 190A and the p-type FinFET 190B are high-voltage FinFETs, and the n-type FinFET 190B and the p-type FinFET 190C are low-voltage FinFETs, so the n-type FinFET 190A and the p-type FinFET 190B have a higher threshold (operating) voltage than the n-type FinFET 190B and the p-type FinFET 190C. The gate structure 110A comprises an interface layer 112A, a gate dielectric layer 140A, a cover layer 142A, a threshold voltage tuning layer 144A, a p-type output function layer 146A, an n-type output function layer 172A, an adhesive layer 180A, a blocking layer 184A and a metal filler layer 182A.Gate structure 110B comprises an interface layer 112B, a gate dielectric layer 140B, a cover layer 142B, a threshold voltage tuning layer 144B, an n-type work function layer 172B, an adhesive layer 180B, a blocking layer 184B, and a metal filler layer 182B. Gate structure 110C comprises an interface layer 112C, a gate dielectric layer 140C, a cover layer 142C, a threshold voltage tuning layer 144C, a blocking layer 184C, and a metal filler layer 182C. The gate structure 110D comprises an interface layer 112D, a gate dielectric layer 140D, a cover layer 142D, a threshold voltage tuning layer 144D, a p-type work function layer 146D, an n-type work function layer 172D, an adhesive layer 180D, a blocking layer 184D, and a metal filler layer 182D. The thickness of the p-type work function layer 146D is greater than the thickness of the p-type work function layer 146A.The thickness of the threshold voltage tuning layer 144A and / or the threshold voltage tuning layer 144D is greater than the thickness of the threshold voltage tuning layer 144B and / or the threshold voltage tuning layer 144C. High-voltage FinFETs thus have threshold voltage tuning layers (here the threshold voltage tuning layers 144A, 144D) that have a better aluminum blocking capacity than the threshold voltage tuning layers of low-voltage FinFETs (here the threshold voltage tuning layers 144B, 144C), whereby aluminum from other gate layers (here the n-type work function layers 172A, 172D) is prevented from penetrating into other gate layers (such as the interface layers 112A, 112D; the gate dielectric layers 140A, 140D; and / or the cover layers 142A, 142D), such that the high-voltage FinFETs have higher threshold voltages than the low-voltage FinFETs.By modifying the aluminum blocking capacity of a threshold voltage tuning layer, devices with multiple threshold voltages can be obtained. Different embodiments can offer different advantages, and no specific advantage is necessarily required of any single embodiment.

[0042] Manufacturing can continue to complete the production of the fin-based integrated circuit device 100. For example, various contacts can be formed to facilitate the operation of FinFET devices 190A-190D. For example, one or more ILD layers similar to ILD layer 120 can be formed over the substrate 102 (in particular over ILD layer 120 and the gate structures 110A-110D). Contacts can then be formed in ILD layer 120 and / or in the ILD layers arranged over ILD layer 120. For example, the contacts are electrically connected to the gate structures 110A-110D of the FinFETs 190A-190D (especially the gate electrodes of the gate structures 110A-110D), and the contacts are electrically connected to the source / drain regions of the FinFETs 190A-190C (especially the epitaxial source / drain features 118A-118D).The contacts comprise a conductive material, such as a metal. Metals include aluminum, aluminum alloy (such as aluminum / silicon / copper alloy), copper, copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, metal silicide, other suitable metals, or combinations thereof. The metal silicide may include nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, or combinations thereof. In some embodiments, the ILD layers arranged above ILD layer 120 and the contacts (extending, for example, through ILD layer 120 and / or the other ILD layers) are part of an MLI feature arranged above substrate 102, as described above. The MLI feature may comprise a combination of metal layers and ILD layers configured with vertical interconnect features, such as...To form contacts and / or vias, and / or horizontal interconnection features, such as leads. The various conductivity features utilize materials similar to those used for the contacts. In some designs, a Damascene process and / or a dual-Damascene process are employed to create the MLI feature.

[0043] Sometimes, one or more of the gate layers of the gate structures 110A-110D can be altered during machining if they are exposed to environmental influences during transport of the fin-based integrated circuit device 100 between machining systems. For example, the surfaces of one or more of the gate layers of the gate structures 110A-110D can be oxidized when exposed to an oxygen environment, undesirably altering the threshold voltages associated with the gate structures 110A-110D.To minimize such processes, in some embodiments one or more of the gate layers of the gate structures 110A-110D can be processed "in-situ," which generally refers to performing various processes on the fin-based integrated circuit device 100 in the same IC processing system or IC processing tool, allowing the fin-based integrated circuit device 100 to remain under vacuum conditions during the various processes. Therefore, "in-situ" generally also refers to performing various processes on the fin-based integrated circuit device 100 without exposing the fin-based integrated circuit device 100 to environmental influences (for example, outside an IC processing system), such as oxygen.In some embodiments, the threshold voltage tuning treatment 160, the production of the n-type work function layer 172, the production of the adhesive layer 180 and / or the production of the blocking layer 184 are carried out in situ, thereby minimizing (or eliminating) the influence of oxygen and / or other environmental factors during processing.

[0044] Fig. Figure 3 is an incomplete graphical representation of a multi-chamber processing system 200 for an integrated circuit (IC) according to various embodiments of the present disclosure. In some embodiments, the multi-chamber IC processing system 200 is referred to as an IC cluster tool. The multi-chamber IC processing system 200 comprises a loading port 202, one or more loading lock chambers (for example, a loading lock chamber 204A and a loading lock chamber 204B), one or more process chambers (for example, a process chamber 210A, a process chamber 210B, a process chamber 210C, a process chamber 210D, and a process chamber 210E), and a wafer handling chamber 220. The wafers are transported between the process chambers 210A-210E in order to process the different gate layers in an in-situ procedure such that the wafers remain under vacuum conditions during processing in the multi-chamber IC processing system 200.In some embodiments, the various gate exchange processes on the fin-based integrated circuit device 100 in the multi-chamber IC processing system 100 are carried out such that the fin-based integrated circuit device 100 remains under vacuum conditions during the various gate exchange processes. Fig. For the sake of clarity, paragraph 3 has been simplified to better illustrate the inventive concept of the present disclosure. Additional features can be added to the multi-chamber IC machining system 200, and some of the features described below can be replaced, modified, or omitted in other embodiments of the multi-chamber IC machining system 200.

[0045] The loading chambers 204A and 204B are configured to receive a wafer (which, for example, has a fin-based integrated circuit device 100 fabricated on it) transferred from a loading port 202. The loading chambers 204A and 204B are configured to allow the transfer of wafers into and out of the multi-chamber IC processing system 200. In some embodiments, the multi-chamber IC processing system 200 is evacuated, and the loading chamber 204A and 204B can "pump out" the environment of wafers being introduced into the multi-chamber IC processing system 200 (for example, using a mechanical pump and / or a turbomolecular pump) such that the wafer environment is under vacuum. In some versions, the loading lock chambers 204A, 204B are designed to accommodate a single wafer or multiple wafers (for example, wafers loaded into a wafer cassette, container or carrier).In some configurations, the loading chambers 204A and 204B are separated from the wafer handling chamber 220 by a slide valve, allowing the wafer handling chamber 220 to remain under vacuum when loading chambers 204A and / or 204B are vented during operation. The wafer handling chamber 220 features an automated robot arm that can transport wafers along any horizontal, vertical, and / or rotary axis between loading chambers 204A, 204B, and / or any of the process chambers 210A-210E. The process chambers 210A-210E are equipped to perform a number of IC processing steps, such as ALD, CVD, PVD, etching, pretreatment / pre-impregnation, degassing, annealing, as well as a number of measurement processes, such as XPS analysis, AFM analysis, and / or other suitable processing or measurement operations.The wafers can thus remain in a vacuum during processing in the multi-chamber IC processing system 100, such that the wafers are not (or only minimally) exposed to environmental influences, such as oxygen, during the gate formation processes. The present disclosure considers that the multi-chamber IC processing system 200 may have more or fewer loading chambers, process chambers, wafer handling chambers, and / or other chambers, depending on the IC process requirements.

[0046] In some embodiments, process chamber 210A is configured to perform a threshold voltage tuning treatment, such as threshold voltage tuning treatment 160; process chambers 210B, 210C, and / or 210D are configured to perform an ALD process to form an n-type work function layer, such as n-type work function layer 172; and process chamber 210E is configured to perform an ALD process to form an adhesive layer, such as adhesive layer 180, and / or a blocking layer, such as blocking layer 184. For example, process chamber 210A is configured to receive one or more precursors to form a threshold voltage tuning layer containing tantalum and nitrogen, such as...to reduce the threshold voltage tuning layer 144 in the illustrated embodiment; process chamber 210B, process chamber 210C and / or process chamber 210D are configured to receive one or more precursors suitable for forming an n-type work function layer comprising titanium and aluminum; and process chamber 210E is configured to receive one or more precursors suitable for forming an adhesive layer and / or a blocking layer comprising titanium and nitrogen. In some embodiments, process chamber 210A is configured to receive a tungsten chloride-containing precursor, such as WCl5; process chamber 210B, process chamber 210C and / or process chamber 210D are configured to receive an aluminum-containing precursor, such as dimethylaluminium hydride (DMAH) or dimethylethylamylamine (DMEAA); and process chamber 210E is configured to receive a titanium-containing precursor, such asto accommodate titanium tetrachloride (TiCl4) and a nitrogen-containing precursor, such as ammonia (NH3). In some embodiments, process chamber 210A is configured to maintain a temperature of approximately 400°C to approximately 500°C. In some embodiments, process chamber 210A is configured to maintain a pressure of approximately 2.67 kPa (20 Torr) to approximately 4.0 kPa (30 Torr). In the present disclosure, embodiments are considered in which process chambers 210A-210E are configured to carry out other gate exchange processes, such as...The formation of a gate dielectric layer (for example, the high-k dielectric layer 140), the formation of a cover layer (for example, the cover layer 142), the formation of a threshold voltage tuning layer (for example, the threshold voltage tuning layer 144), the formation of a p-type work function layer (for example, the p-type work function layer 146), the treatment of one or more of the gate layers, and / or any other gate exchange process that can benefit from in-situ processing. In embodiments in which one of the process chambers 210A-210E is configured to form a threshold voltage tuning layer containing tantalum and nitrogen, the process chamber may be configured to receive a tantalum-containing precursor, such as pentakis dimethylamino tantalum (PDMAT), and a nitrogen-containing precursor, such as NH3.

[0047] The present disclosure provides many different embodiments. Herein, methods for tuning the threshold voltages of fin-type field-effect transistor devices are disclosed. One example method comprises forming a first opening in a first gate structure and a second opening in a second gate structure. The first gate structure is arranged over a first fin structure, and the second gate structure is arranged over a second fin structure. The method further comprises filling the first and second openings by forming a gate dielectric layer, forming a threshold-voltage tuning layer over the gate dielectric layer, etching back the threshold-voltage tuning layer in the second opening, forming a work function layer over the threshold-voltage tuning layer, and forming a metal filler layer over the work function layer.The threshold voltage tuning layer contains tantalum and nitrogen. A tungsten chloride-containing precursor is used for back-etching. In some embodiments, forming the threshold voltage tuning layer involves performing an atomic layer deposition process. In some embodiments, back-etching involves adjusting etching parameters to reduce a threshold voltage belonging to the second gate structure relative to a threshold voltage belonging to the first gate structure. In some embodiments, filling the first and second openings further involves forming a cover layer over the gate dielectric layer, with the cover layer being positioned between the gate dielectric layer and the threshold voltage tuning layer.

[0048] In some embodiments, the work function layer is formed after the threshold voltage tuning layer has been etched back. In such embodiments, the work function layer is a first-type work function layer, and the filling of the first and second openings further comprises forming a second-type work function layer over the threshold voltage tuning layer in the first and second openings before etching back the threshold voltage tuning layer, removing the second-type work function layer from the second opening, thereby exposing the threshold voltage tuning layer in the second opening for etching back, and forming the first-type work function layer over the second-type work function layer in the first opening and over the threshold voltage tuning layer in the second opening.In some embodiments, the work function layer is formed before the threshold voltage tuning layer is back-etched. In such embodiments, the work function layer is a first-type work function layer, and the filling of the first and second openings further comprises removing the first-type work function layer from the second opening, thereby exposing the threshold voltage tuning layer in the second opening for back-etching, and forming a second-type work function layer over the first-type work function layer in the first opening after back-etching.

[0049] Another example of the method involves forming a first opening in the first gate structure of a first fin-type field-effect transistor (FinFET), a second opening in the second gate structure of a second FinFET, a third opening in the third gate structure of a third FinFET, and a fourth opening in the fourth gate structure of a fourth FinFET. The method further includes partially filling the first, second, third, and fourth openings with a high-k dielectric layer. The method also includes partially filling the first, second, third, and fourth openings with a threshold tuning layer, the threshold tuning layer being placed above the high-k dielectric layer.The method further comprises partially filling the first opening, the second opening, the third opening, and the fourth opening with a first-type work function layer, wherein the first-type work function layer is arranged above the threshold voltage tuning layer. The method further comprises removing the first-type work function layer from the second opening and the third opening, thereby exposing the threshold voltage tuning layer in the second opening and the third opening.The method further comprises performing a threshold voltage tuning treatment on the threshold voltage tuning layer exposed in the second and third openings, such that the threshold voltage of the second and third FinFETs is lower than the threshold voltage of the first and fourth FinFETs, wherein the threshold voltage tuning treatment employs a tungsten chloride-containing precursor. The method further comprises partially filling the first, second, and fourth openings with a second-type work function layer, wherein the second-type work function layer is positioned above the threshold voltage tuning layer in the first, second, and fourth openings.The method further comprises filling the first, second, third, and fourth openings with a metal filler layer, wherein the metal filler layer is arranged above the second-type work function layer in the first, second, and fourth openings, and wherein the metal filler layer is further arranged above the threshold voltage tuning layer in the third opening. In some embodiments, the method further comprises partially filling the first, second, third, and fourth openings with a cover layer above the high-k dielectric layer prior to forming the threshold voltage tuning layer. In some embodiments, the method further comprises filling the first, second, and fourth openings with an adhesive layer above the second-type work function layer.

[0050] In some embodiments, the partial filling of the first, second, third, and fourth orifices with the threshold voltage tuning layer includes the formation of a tantalum- and nitrogen-containing layer. In some embodiments, the partial filling of the first, second, third, and fourth orifices with the threshold voltage tuning layer includes the execution of an atomic layer deposition process. In some embodiments, the threshold voltage tuning treatment includes reducing the thickness of the threshold voltage tuning layer in the second and third orifices. In some embodiments, the first-type work function layer has a p-type work function material, and the second-type work function layer has an n-type work function material.In some embodiments, the partial filling of the first, second, third, and fourth openings with the first-type exit work layer comprises forming the first-type exit work layer in a first thickness in the first and second openings, and forming the first-type exit work layer in a second thickness in the third and fourth openings. The second thickness is greater than the first thickness.

[0051] An example of an integrated circuit device features a first fin-type field-effect transistor (FinFET) with a first gate structure comprising a first high-k dielectric layer, a first threshold tuning layer arranged above the first high-k dielectric layer, a first p-type work function layer arranged above the first threshold tuning layer, a first n-type work function layer arranged above the first threshold tuning layer, and a first metal filler layer arranged above the first n-type work function layer.The integrated circuit further comprises a second FinFET with a second gate structure, comprising a second high-k dielectric layer, a second threshold tuning layer arranged above the second high-k dielectric layer, a second n-type work function layer arranged above the second threshold tuning layer, and a second metal filler layer arranged above the second threshold tuning layer. The integrated circuit further comprises a third FinFET with a third gate structure, comprising a third high-k dielectric layer, a third threshold tuning layer arranged above the third high-k dielectric layer, and a third metal filler layer arranged above the third threshold tuning layer.The integrated circuit further comprises a fourth FinFET with a fourth gate structure, which includes a fourth high-k dielectric layer, a fourth threshold tuning layer arranged above the fourth high-k dielectric layer, a second p-type work function layer arranged above the fourth threshold tuning layer, a third n-type work function layer arranged above the fourth threshold tuning layer, and a fourth metal filler layer arranged above the third n-type work function layer. The thickness of the second and third threshold tuning layers is less than the thickness of the first and fourth threshold tuning layers. The thickness of the second p-type work function layer is greater than the thickness of the first p-type work function layer.In some versions, the first threshold voltage tuning layer, the second threshold voltage tuning layer, the third threshold voltage tuning layer and the fourth threshold voltage tuning layer contain tantalum and nitrogen.

[0052] The integrated circuit further comprises a first high-k cover layer located between the first high-k dielectric layer and the first threshold voltage tuning layer, a second high-k cover layer located between the second high-k dielectric layer and the second threshold voltage tuning layer, a third high-k cover layer located between the third high-k dielectric layer and the third threshold voltage tuning layer, and a fourth high-k cover layer located between the fourth high-k dielectric layer and the fourth threshold voltage tuning layer. In some embodiments, the first p-type work function layer and the second p-type work function layer contain titanium and nitrogen.In some versions, the first, second, and third n-type exit work layers contain titanium and aluminum. In some versions, the first, second, third, and fourth metal fill layers contain tungsten.

Claims

[1] Procedure, encompassing: Forming a first opening (130A, 130B, 130C, 130D) in a first gate structure (110A, 110B, 110C, 110D) and a second opening (130A, 130B, 130C, 130D) in a second gate structure (110A, 110B, 110C, 110D), wherein the first gate structure (110A, 110B, 110C, 110D) is arranged over a first fin structure (106A, 106B, 106C, 106D) and the second gate structure (110A, 110B, 110C, 110D) is arranged over a second fin structure (106A, 106B, 106C, 106D); and Filling the first opening (130A, 130B, 130C, 130D) and the second opening (130A, 130B, 130C, 130D) using: Formation of a gate dielectric layer (140), Forming a threshold voltage tuning layer (144) over the gate dielectric layer (140), wherein the threshold voltage tuning layer (144) comprises tantalum and nitrogen, Etching back the threshold voltage tuning layer (144) in the second opening (130A, 130B, 130C, 130D) using a tungsten chloride-containing precursor, Forming an output work layer (146, 172) above the threshold voltage tuning layer (144), and Formation of a metal fill layer (182) over the work function layer (146, 172), wherein the re-etching of the threshold voltage tuning layer (144) includes tuning etching parameters to reduce a threshold voltage belonging to the second gate structure (110A, 110B, 110C, 110D) with respect to a threshold voltage belonging to the first gate structure (110A, 110B, 110C, 110D). [2] Method according to claim 1, wherein forming the threshold voltage tuning layer (144) comprises performing an atomic layer deposition process. [3] Method according to one of the preceding claims, further comprising forming the work function layer (146, 172) after etching back the threshold voltage tuning layer (144). [4] Method according to claim 3, wherein the work of exit layer (146, 172) is a work of exit layer of the first type and wherein filling the first opening (130A, 130B, 130C, 130D) and the second opening (130A, 130B, 130C, 130D) further comprises: Forming a work function layer (146, 172) of the second type over the threshold voltage tuning layer (144) in the first opening (130A, 130B, 130C, 130D) and the second opening (130A, 130B, 130C, 130D) before etching back the threshold voltage tuning layer (144); Removing the second-type work function layer (146, 172) from the second opening (130A, 130B, 130C, 130D), thereby exposing the threshold voltage tuning layer (144) in the second opening (130A, 130B, 130C, 130D) for back-etching; and Forming the output work layer (146, 172) of the first type over the output work layer (146, 172) of the second type in the first opening (130A, 130B, 130C, 130D) and over the threshold voltage tuning layer (144) in the second opening (130A, 130B, 130C, 130D). [5] Method according to one of claims 1 or 2, further comprising forming the work function layer (146, 172) prior to etching back the threshold voltage tuning layer (144). [6] Method according to claim 5, wherein the work of exit layer (146, 172) is a work of exit layer of the first type and wherein filling the first opening (130A, 130B, 130C, 130D) and the second opening (130A, 130B, 130C, 130D) further comprises: Removing the first-type work function layer (146, 172) from the second opening (130A, 130B, 130C, 130D), thereby exposing the threshold voltage tuning layer (144) in the second opening (130A, 130B, 130C, 130D) for back-etching; and Formation of a second type exit work layer (146, 172) over the first type exit work layer (146, 172) in the first opening (130A, 130B, 130C, 130D) after back-etching. [7] Method according to one of the preceding claims, wherein the filling of the first opening (130A, 130B, 130C, 130D) and the second opening (130A, 130B, 130C, 130D) further comprises forming a cover layer over the gate dielectric layer (140), wherein the cover layer is arranged between the gate dielectric layer (140) and the threshold voltage tuning layer (144). [8] Procedures, comprehensive: Forming a first opening (130A, 130B, 130C, 130D) in a first gate structure (110A, 110B, 110C, 110D) of a first fin-like field-effect transistor, hereinafter referred to as FinFET, a second opening (130A, 130B, 130C, 130D) in a second gate structure (110A, 110B, 110C, 110D) of a second FinFET, a third opening (130A, 130B, 130C, 130D) in a third gate structure (110A, 110B, 110C, 110D) of a third FinFET, and a fourth opening (130A, 130B, 130C, 130D) in a fourth gate structure (110A, 110B, 110C, 110D) of a fourth FinFET; Partial filling of the first opening, the second opening, the third opening and the fourth opening (130A, 130B, 130C, 130D) with a high-k dielectric layer (140); Partially filling the first opening, the second opening, the third opening and the fourth opening (130A, 130B, 130C, 130D) with a threshold voltage tuning layer (144), wherein the threshold voltage tuning layer (144) is arranged over the high-k dielectric layer (140); Partial filling of the first opening, the second opening, the third opening and the fourth opening (130A, 130B, 130C, 130D) with a work function layer (146, 172) of the first type, wherein the work function layer (146, 172) of the first type is arranged above the threshold voltage tuning layer (144); Removing the first type output work layer (146, 172) from the second opening and the third opening, thereby exposing the threshold voltage tuning layer (144) in the second opening and the third opening; Performing a threshold voltage tuning treatment on the threshold voltage tuning layer (144) exposed in the second opening and the third opening, such that a threshold voltage of the second FinFET and the third FinFET is lower than a threshold voltage of the first FinFET and the fourth FinFET, wherein the threshold voltage tuning treatment employs a tungsten chloride-containing precursor; Partially filling the first opening, the second opening and the fourth opening with a second-type work function layer (146, 172), wherein the second-type work function layer (146, 172) is arranged above the threshold voltage tuning layer (144) in the first opening, the second opening and the fourth opening; and Filling the first opening, the second opening, the third opening and the fourth opening (130A, 130B, 130C, 130D) with a metal filler layer (182), wherein the metal filler layer (182) is arranged above the second type output work layer (146, 172) in the first opening, the second opening and the fourth opening, and wherein the metal filler layer (182) is further arranged above the threshold voltage tuning layer (144) in the third opening. [9] Method according to claim 8, wherein the partial filling of the first opening, the second opening, the third opening and the fourth opening (130A, 130B, 130C, 130D) with the threshold voltage tuning layer (144) comprises forming a tantalum-and-nitrogen-containing layer. [10] Method according to claim 8 or 9, wherein the partial filling of the first opening, the second opening, the third opening and the fourth opening (130A, 130B, 130C, 130D) with the threshold voltage tuning layer (144) comprises performing an atomic layer deposition process. [11] Method according to any one of the preceding claims 8 to 10, wherein performing the threshold voltage tuning treatment comprises reducing the thickness of the threshold voltage tuning layer (144) in the second opening and the third opening. [12] Method according to any one of the preceding claims 8 to 11, further comprising partially filling the first opening, the second opening, the third opening and the fourth opening (130A, 130B, 130C, 130D) with a cover layer over the high-k dielectric layer (140) prior to forming the threshold voltage tuning layer (144). [13] Method according to any one of the preceding claims 8 to 12, further comprising partially filling the first opening, the second opening and the fourth opening with an adhesive layer over the exit work layer (146, 172) of the second type. [14] Method according to any one of the preceding claims 8 to 13, comprising partially filling the first opening, the second opening, the third opening and the fourth opening (130A, 130B, 130C, 130D) with the work-of-release layer (146, 172) of the first type: Forming the exit work layer (146, 172) of the first type of a first thickness in the first opening and the second opening; and Forming the exit work layer (146, 172) of the first type of a second thickness in the third opening and the fourth opening, wherein the second thickness is greater than the first thickness. [15] Method according to any one of the preceding claims 8 to 14, wherein the threshold voltage tuning treatment and the partial filling of the first opening, the second opening and the fourth opening with the work function layer (146, 172) of the second type are carried out in situ. [16] Integrated circuit device comprising: a first fin-like field-effect transistor, hereinafter referred to as FinFET, with a first gate structure (110A) comprising a first high-k dielectric layer (140), a first threshold voltage tuning layer (144) arranged above the first high-k dielectric layer (140), a first p-type work function layer (146, 172) arranged above the first threshold voltage tuning layer (144), a first n-type work function layer (146, 172) arranged above the first threshold voltage tuning layer (144), and a first metal filler layer (182) arranged above the first n-type work function layer (146, 172), a second FinFET with a second gate structure (110B) comprising a second high-k dielectric layer (140), a second threshold voltage tuning layer (144) arranged above the second high-k dielectric layer (140), a second n-type work function layer (146, 172) arranged above the second threshold voltage tuning layer (144), and a second metal fill layer (182) arranged above the second threshold voltage tuning layer (144), a third FinFET with a third gate structure (110C) comprising a third high-k dielectric layer (140), a third threshold voltage tuning layer (144) arranged above the third high-k dielectric layer (140), and a third metal fill layer (182) arranged above the third threshold voltage tuning layer (144), a fourth FinFET with a fourth gate structure (110D) comprising a fourth high-k dielectric layer (140), a fourth threshold voltage tuning layer (144) arranged above the fourth high-k dielectric layer (140), a second p-type work function layer (146, 172) arranged above the fourth threshold voltage tuning layer (144), a third n-type work function layer (146, 172) arranged above the fourth threshold voltage tuning layer (144), and a fourth metal fill layer (182) arranged above the third n-type work function layer (146, 172). wherein the thickness of the second threshold voltage tuning layer (144) and the third threshold voltage tuning layer (144) is smaller than the thickness of the first threshold voltage tuning layer (144) and the fourth threshold voltage tuning layer (144), such that the second FinFET and the third FinFET have lower threshold voltages than the first FinFET and the fourth FinFET, where the thickness of the second p-type work function layer (146, 172) is greater than the thickness of the first p-type work function layer (146, 172). [17] Integrated circuit device according to claim 16, wherein the first threshold voltage tuning layer, the second threshold voltage tuning layer, the third threshold voltage tuning layer and the fourth threshold voltage tuning layer (144) comprise tantalum and nitrogen. [18] Integrated circuit device according to claim 16 or 17, further comprising: a first high-k cover layer arranged between the first high-k dielectric layer and (140) the first threshold voltage tuning layer (144); a second high-k cover layer arranged between the second high-k dielectric layer (140) and the second threshold voltage tuning layer (144); a third high-k cover layer arranged between the third high-k dielectric layer (140) and the third threshold voltage tuning layer (144); and a fourth high-k cover layer, which is arranged between the fourth high-k dielectric layer (140) and the fourth threshold voltage tuning layer (144). [19] Integrated circuit device according to any one of the preceding claims 16 to 18, wherein: the first p-type work function layer (146, 172) and the second p-type work function layer (146, 172) contain titanium and nitrogen; the first n-type work function layer, the second n-type work function layer and the third n-type work function layer (146, 172) exhibit titanium and aluminum; and the first metal fill layer, the second metal fill layer, the third metal fill layer and the fourth metal fill layer (182) contain tungsten.

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