Semiconductor device and manufacturing process for it

Abstract

Semiconductor device comprising: a drift layer (1) formed from a semiconductor material of a first conductivity type; a MOSFET part (22) which is provided on a front surface of the drift layer (1) and has a semiconductor layer of a second conductivity type which forms a pn junction with the drift layer (1); a first buffer layer (8) provided on a back side of the drift layer (1), which has the first conductivity type, has a higher impurity concentration than the drift layer and a total amount of electrically active impurities per unit area of ​​1.0 × 10 12 cm -2 or less; and a second buffer layer (11) provided on a back side of the first buffer layer (8), which has the first conductivity type and has a higher impurity concentration than the first buffer layer (8), wherein the impurity concentration of the first buffer layer (8) 1.0 × 10 15 cm -3 or less, and a maximum concentration value of the impurity concentration distribution in one thickness direction of the second buffer layer (11) in a range of 3 × 10 16 cm -3 up to 6 × 10 16 cm -3 falls.

Description

Field of invention

[0001] The present invention relates to a semiconductor device. background

[0002] Conventionally, as disclosed, for example, in JP 2011-119542 A, an IGBT is known which is provided with two buffer layers having different impurity concentrations on a drift layer backside. The IGBT according to this publication has a buffer layer with a low impurity concentration located a distance from a p + -Collector layer of the IGBT and a buffer layer with a high impurity concentration located near the p + -collector layer is located.

[0003] One of the features of the technology referred to in this publication is that the total thickness and total impurity quantity of the low-impact buffer layer and the high-impact buffer layer are limited within a certain range. Paragraph 0022 of the publication describes a specific structure of a buffer layer 24, which is the low-impact buffer layer, containing an impurity concentration of 2 × 10 16 cm -3 , a thickness of 40 µm and a total impurity quantity of 8 × 10 13 cm -2 exhibits.

[0004] The buffer layer of low impurity concentration, which is located away from the p +The collector layer located at the top of the drift layer is, according to the preceding prior art, also referred to below as a "deep low-concentration buffer layer," in the sense that it is a buffer layer that is formed deep within the drift layer and has a relatively low impurity concentration. Meanwhile, the high-concentration buffer layer, according to the preceding prior art, which is located near the top of the drift layer, is referred to as a "deep low-concentration buffer layer." + -Collector layer, hereinafter also referred to as a "flat high-concentration buffer layer", in the sense that it is a buffer layer that is flat in the drift layer and has a relatively high impurity concentration.

[0005] If a shallow high-concentration buffer layer is not provided, the leakage current of the IGBT will increase significantly the lower the impurity concentration of the deep low-concentration buffer layer. If a shallow high-concentration buffer layer is provided, there is the advantage that the leakage current is reduced to a sufficiently low level, even if the impurity concentration of the deep low-concentration buffer layer is low.

[0006] On the other hand, if the impurity concentration in the deep low-concentration buffer layer is too high, there is a disadvantage: the electric field on the drift layer backside becomes too high in a safe operating area in the event of a short-circuit interruption. The safe operating area at the time of the short-circuit interruption is one of the performance characteristics of a switching element and is also called "SCSOA (Short Circuit Safe Operating Area)." Although the impurity concentration in the deep low-concentration buffer layer must be designed to fall within a suitable range, the aforementioned JP 2011-119542 A only discloses a concentration that is high to a certain degree and does not give sufficient consideration to the SCSOA.

[0007] The foregoing JP 2011-119542 A does not provide a specific description of dopants for the shallow high-concentration buffer layer and the deep low-concentration buffer layer, nor of a manufacturing process for them. As a result of intensive research, the inventor of the present invention found a preferred method for manufacturing a semiconductor device provided with a shallow high-concentration buffer layer and a deep low-concentration buffer layer.

[0008] One of the performance characteristics of a switching element is a safe, reverse bias operating area (RBSOA). As a result of intensive research, the inventor of the present invention found a preferred structure that ensures a good RBSOA.

[0009] Further semiconductor devices are known from DE 11 2010 004 241 T5 and JP 2009 - 176 772 A.

[0010] From DE 11 2014 003 712 T5, it is known to provide a plurality of trenches in a strip shape extending in a direction parallel to a front substrate surface to a predetermined depth in a depth direction from the front substrate surface. A gate electrode, with an intermediate gate insulating film, is provided within each trench. In mesa regions separated by the trenches, p-base regions are provided at an emitter potential across the entire surface layer on the side of the front substrate surface. Within the p-base regions, n + Etriitter zones are provided scattered at predetermined intervals along the length of the trenches. A p-collector layer and an n-collector layer are also provided. + -Buffer layers are in this order on the surface layer of the rear side.

[0011] Substrate surface provided. The thickness of the n +The buffer layer is essentially equal to the thickness of a n - -drift layer or greater than the thickness of the n - -Drift layer.

[0012] From DE 11 2012 004 985 T5, a semiconductor device is known with a vertical semiconductor element configured to carry an electric current between an upper electrode and a lower electrode. The semiconductor device includes a field-stop layer, a phosphorus / arsenic layer doped with phosphorus or arsenic, and a proton layer doped with protons. The phosphorus / arsenic layer extends from the back side of a semiconductor substrate to a predetermined depth. The proton layer is deeper than the phosphorus / arsenic layer. The impurity concentration of the proton layer reaches its peak within the phosphorus / arsenic layer and decreases gradually and continuously at a depth greater than that of the phosphorus / arsenic layer.

[0013] From DE 103 30 571 A1, a vertical power semiconductor device is known, e.g., a diode or an IGBT, in which a backside temperature or a cathode emitter and a backside metal layer covering it at least partially are formed on the back side of a substrate. The vertical power semiconductor device is characterized in that injection damping means are provided in the edge region of the device to reduce the charge carrier injection from the backside emitter or the cathode emitter into this edge region. Summary

[0014] The present invention has been implemented to solve the aforementioned problems, and it is an object of the present invention to provide a semiconductor device with improved SCSOA and a manufacturing method for it.

[0015] Another object of the present invention is to provide a preferred manufacturing method for manufacturing a semiconductor device that is provided with a shallow high-concentration buffer layer and a deep low-concentration buffer layer.

[0016] Another objective of the present invention is to provide a semiconductor device with an improved RBSOA.

[0017] This problem is solved by the features of the independent claims. The dependent claims contain advantageous embodiments of the invention.

[0018] Other and further tasks, features and advantages of the invention will become more apparent from the following description. Brief description of the drawings Fig. Figure 1 is a diagram representing a semiconductor device according to a first embodiment of the present invention; Fig. Figure 2 is a graph representing an impurity concentration distribution of the semiconductor device according to the first embodiment of the present invention; Fig. Figure 3 is a graph for describing operating processes and effects of the semiconductor device according to the first embodiment of the present invention; Fig. Figure 4 is a graph for describing operating processes and effects of the semiconductor device according to the first embodiment of the present invention; Fig. Figure 5 is a graph for describing operating processes and effects of the semiconductor device according to the first embodiment of the present invention; Fig. Figure 6 is a graph for describing operating processes and effects of the semiconductor device according to the first embodiment of the present invention; Fig. Figure 7 is a graph for describing operating processes and effects of the semiconductor device according to the first embodiment of the present invention; Fig. Figure 8 is a graph for describing operating processes and effects of the semiconductor device according to the first embodiment of the present invention; Fig. Figure 9 is a graph for describing operating processes and effects of the semiconductor device according to the first embodiment of the present invention; Fig. Figure 10 is a graph for describing operating processes and effects of the semiconductor device according to the first embodiment of the present invention; Fig. Figure 11 is a graph for describing operating processes and effects of the semiconductor device according to the first embodiment of the present invention; Fig. Figure 12 is a diagram describing a method for manufacturing the semiconductor device according to the first embodiment of the present invention; Fig. Figure 13 is a diagram describing a method for manufacturing the semiconductor device according to the first embodiment of the present invention; Fig. Figure 14 is a diagram describing a method for manufacturing the semiconductor device according to the first embodiment of the present invention; Fig. Figure 15 is a diagram describing a method for manufacturing the semiconductor device according to the first embodiment of the present invention; Fig. Figure 16 is a diagram describing a method for manufacturing the semiconductor device according to the first embodiment of the present invention; Fig. Figure 17 is a diagram describing a method for manufacturing the semiconductor device according to the first embodiment of the present invention; Fig. Figure 18 is a diagram describing a method for manufacturing the semiconductor device according to the first embodiment of the present invention; Fig. Figure 19 is a diagram describing a method for manufacturing the semiconductor device according to the first embodiment of the present invention; Fig. Figure 20 is a diagram describing a method for manufacturing the semiconductor device according to the first embodiment of the present invention; Fig. 21 is a diagram describing a method for manufacturing the semiconductor device according to the first embodiment of the present invention; Fig. Figure 22 is a diagram describing a method for manufacturing the semiconductor device according to the first embodiment of the present invention; Fig. Figure 23 is a diagram illustrating a semiconductor device according to a comparative example of the first embodiment of the present invention; Fig. Figure 24 is a graph representing an impurity concentration distribution of the semiconductor device according to the comparative example for the first embodiment of the present invention; Fig. Figure 25 is a diagram illustrating a semiconductor device according to a second embodiment of the present invention; and Fig. Figure 26 is a diagram illustrating a semiconductor device according to a modification of the second embodiment of the present invention. Description of the embodiments: First embodiment

[0019] Fig. Figure 1 is a diagram illustrating a semiconductor device 20 according to a first embodiment of the present invention. The semiconductor device 20 according to the first embodiment is an insulated-gate bipolar transistor (IGBT) provided with a trench gate. Fig. In Figure 1, the semiconductor device 20 is provided with a substrate 1. The substrate 1 consists of silicon and exhibits n-type conductivity. Since the substrate 1 functions as a drift layer 1 in the IGBT, the substrate 1 is subsequently also referred to as a "drift layer 1".

[0020] A MOSFET part 22 is provided on the drift layer 1 using a surface process. The MOSFET part 22 is equipped with a p-type base layer 2, n + -Type emitter layers 3, trench gates 4, one p +The p-type base layer 5, interlayer insulation layers 6, and an emitter electrode 7 are provided. The p-type base layer 2 is provided on a front face of the drift layer 1. The p-type base layer 2 is connected to the drift layer 1, so that they form a pn junction, which creates a depletion layer. A plurality of n + The -type emitter layer 3 is formed separately at a plurality of locations on a front surface of the p-type base layer 2. The trench gates 4 are designed such that they form their respective n + -Type emitter layers 3 penetrate. The p + -Type layer 5 is between the majority of n + -Type emitter layers 3 are provided on the front surface of the p-type base layer 2. The intermediate insulating layers 6 cover the surface sides of the n + -Type emitter layers 3 and the trench gates 4. The emitter electrode 7 covers surfaces of the intermediate insulation layers 6 and the p + -Type-Layer 5.

[0021] A first n-type buffer layer 8 and a second n-type buffer layer 11 are provided on the back side of the drift layer 1. The first n-type buffer layer 8 has a low impurity concentration and is an n-type buffer layer that extends to a considerable depth within the drift layer 1. The first n-type buffer layer 8 is produced by implanting protons into the back side of the drift layer 1 using an ion implanter. More precisely, the first n-type buffer layer 8 is formed by repeatedly implanting protons while varying an accelerating voltage, for example, up to 1500 keV, using a proton implanter. In the first embodiment, it is assumed that the first n-type buffer layer 8 is formed to a depth on the order of 30 µm from the back side of the drift layer 1 prior to ion implantation.

[0022] The second n-type buffer layer 11 is a layer that forms in a flat region on the back side of the drift layer 1 and has a higher impurity concentration than the first n-type buffer layer 8. The second n-type buffer layer 11 is formed after the formation of the first n-type buffer layer 8 and its activation by heat treatment through ion implantation of phosphorus or arsenic into the back side of the drift layer 1.

[0023] A p-type collector layer 9 is provided on one side of the second n-type buffer layer 11. A collector electrode 10 is also provided on one side of the collector layer 9.

[0024] Fig. Figure 2 is a graph representing an impurity concentration distribution of the semiconductor device 20 according to the first embodiment of the present invention. Fig. Figure 2 shows an impurity concentration profile on the back side of the drift layer 1 of the semiconductor device 20. The collector layer 9, which is closest to the back side, exhibits the highest impurity concentration. The second n-type buffer layer 11, which is closer to the drift layer 1 than the collector layer 9, has a maximum impurity concentration of approximately 4 × 10⁻⁶. 16 cm -3 The first n-type buffer layer 8, which is closer to the drift layer 1 than the second n-type buffer layer 11, exhibits a plurality of maximum concentration values, or more precisely, four maximum concentration values. Of the four maximum concentration values ​​of the first n-type buffer layer 8, the maximum concentration value closest to the second n-type buffer layer 11 is approximately 1.0 × 10 15 cm -3The remaining three maximum concentration values ​​decrease gradually as the distance from the second n-type buffer layer 11 increases.

[0025] It should be noted that the thicknesses of the first n-type buffer layer (8) and the second n-type buffer layer (11) are shown. As an example, it can be shown how, using a Fig. 10 and Fig. In the simulation shown in Figure 11, which is described below, it is determined that the proton implantation depth upon formation of the first n-type buffer layer 8 is on the order of 30 µm, and the thickness of the second n-type buffer layer 11 can be on the order of approximately 1 µm to several µm. The thickness of the first n-type buffer layer 8 has a value that is obtained by subtracting the total thickness of the second n-type buffer layer 11 and the collector layer 9 from 30 µm, which is the proton implantation depth.

[0026] The processes and effects of the semiconductor device 20 according to the first embodiment are described below. Fig. 3 to Fig. 11 are graphs for describing processes and effects of the semiconductor device 20 according to the first embodiment of the present invention.

[0027] This includes comparative examples that are in Fig. 23 and Fig. The 24 images shown are also used for a comparative description. Fig. Figure 23 is a diagram illustrating a semiconductor device 120 according to a comparative example of the first embodiment of the present invention. Fig. Figure 24 is a graph representing an impurity concentration distribution of the semiconductor device 120 according to the comparative example for the first embodiment of the present invention. The semiconductor device 120 according to the comparative example has a structure and an impurity concentration distribution similar to those of the device described in Figure 24. Fig. 1 semiconductor device 20 shown, except that it is not provided with the second n-type buffer layer 11.

[0028] The effect of forming the second n-type buffer layer 11 was verified using a device simulation. The device used for the simulation is an IGBT, and calculations were performed under conditions with a resistivity of approximately 67 Ω·cm, a wafer thickness of 110 µm, and a Q factor of 175 A / 1200 V.

[0029] Fig. Figure 3 represents the ratio between the total amount of electrically active impurities per unit area of ​​the first n-type buffer layer 8 and the leakage current when 1200 V is applied. It is observed that the leakage current is significantly reduced by the inclusion of the second n-type buffer layer 11 compared to the case containing only the first n-type buffer layer 8. This is because the second n-type buffer layer 11 reduces the supply of hole current from the collector layer into the silicon. Another reason is that when a voltage is applied, even if a depletion layer with a low concentration is extended to the inside of the first n-type buffer layer 8, the second n-type buffer layer 11, with its high concentration, acts to halt the depletion layer.

[0030] Fig. 4 to Fig. Figure 6 shows results from SCSOA tests performed using a simulation for an electric field, electron concentration, and hole concentration in Si. The simulation is run on the following four structures. In the first structure, the first n-type buffer layer 8 is designed to be relatively shallow, and the second n-type buffer layer 11 is included. In the second structure, the first n-type buffer layer 8 is designed to be relatively shallow, and the second n-type buffer layer 11 is omitted. In the third structure, the first n-type buffer layer 8 is designed to be relatively thick, and the second n-type buffer layer 11 is included. In the fourth structure, the first n-type buffer layer 8 is designed to be relatively thick, and the second n-type buffer layer 11 is omitted.One condition of the SCSOA is Vce = 800 V, Vge = 15 V, tw = 5 µs and the electric field, electron concentration and hole concentration are each measured when t = 4 µs.

[0031] Fig. Figure 4 represents a distribution of an electric field in a thickness direction, assuming that the front face of the semiconductor device 20 is the origin. The results for the four structures described above are each shown by characteristic curves Q1 to Q4. As can be seen from characteristic curves Q3 and Q4 in Fig. As is detected in section 4, when the impurity concentration of the first n-type buffer layer 8 increases, the electric field becomes strong at a position 80 µm thick from the surface, i.e., at the interface between the drift layer 1 and the first n-type buffer layer 8. In contrast, as can be seen from the characteristic curves Q1 and Q2 in Fig. 4 is detected when the impurity concentration of the first n-type buffer layer 8 decreases, causing the electric field to increase on the surface side of the drift layer 1, more precisely in the vicinity of a thickness of 5 µm to 6 µm from the surface.

[0032] Fig. Figure 5 represents an electron concentration in the thickness direction, assuming that the front surface of the semiconductor device 20 is the origin. Fig. Figure 6 represents a hole concentration in the thickness direction, assuming that the front face of the semiconductor device 20 is the origin. As can be seen from the characteristic curves Q1 to Q4 in Fig. 5, even when compared with a case in which the impurity concentration of the first n-type buffer layer 8 is high and a case in which it is low, the electron concentration in the drift layer 1, i.e., the substrate 1, does not change much. However, as in Fig. As shown in Figure 6, the hole concentration in drift layer 1 decreases according to characteristic curves Q3 and Q4, where the impurity concentration of the first n-type buffer layer 8 is high. This occurs because holes within the first n-type buffer layer 8 are quenched. As a consequence, a charge carrier deficiency arises on the back side of drift layer 1. This charge carrier deficiency causes the depletion layer between drift layer 1 and the first n-type buffer layer 8 to expand. Accordingly, the electric field increases, and positive feedback occurs, generating an excessively strong electric field.

[0033] It should be noted that when comparing a case in which the second n-type buffer layer 11 is provided with a case in which it is not provided, there is essentially no difference in the distribution of the electric field in the semiconductor device 20. This is because the second n-type buffer layer 11 can prevent hole quenching.

[0034] Fig. Figure 7 shows simulation results indicating a relationship between the total amount of electrically active impurities per unit area of ​​the first n-type buffer layer 8 and the maximum electric field in the semiconductor device 20 during an SCSOA test. As shown in Fig. Figure 7 shows a minimum value of the maximum of the electric field in the vicinity of the total amount of impurities of 6 × 10 11 cm -2The reasons for this trend are described. First, the electric field on the surface side of the semiconductor device 20 becomes higher the lower the impurity concentration of the first n-type buffer layer 8. Conversely, the electric field on the back side of the semiconductor device 20 becomes stronger the higher the impurity concentration of the first n-type buffer layer 8. Therefore, from the point of view of reducing the maximum of the electric field in the semiconductor device 20, the impurity concentration of the first n-type buffer layer 8 has a precisely suitable range.

[0035] According to the in Fig. In graph 7, it is possible to limit the total amount of electrically active impurities per unit area of ​​the first n-type buffer layer 8 to within a range of 4.5 × 10 11 cm -2 up to 1.0 × 10 12 cm -2It is possible to reduce the maximum of the electric field in the semiconductor device 20 and to meet a high SCSOA.

[0036] If the results in Fig. 3 and Fig. By combining the two n-type buffer layers, it is possible to obtain a high SCSOA while suppressing the leakage current by providing the second n-type buffer layer 11 and having the impurity concentration of the first n-type buffer layer 8 within a suitable range.

[0037] It should be noted that the formation of the first n-type buffer layer 8 offers the following advantages. First, compared to the second n-type buffer layer 11, the first n-type buffer layer 8 exhibits low sensitivity to foreign matter and damage on the back side during formation, suppresses leakage current fluctuations, and can improve quality. Furthermore, by halting the depletion layer at the time of power-off in the first n-type buffer layer 8, it can prevent charge carrier depletion and suppress oscillation at the time of power-off. Oscillation of a voltage or current can cause radiation interference. In particular, if the wafer is made thinner to improve performance, it is more likely that the depletion layer will reach the back side when a voltage is applied to the device.One preferred solution to these problems is to provide the first n-type buffer layer 8.

[0038] Fig. Figure 8 shows an example of an oscillation waveform corresponding to that of a shutdown. An arrow labeled S in Fig. 8 denotes a "voltage amplitude at the start of the shutdown oscillation". The voltage amplitude at the start of the shutdown oscillation corresponds to the difference between a minimum voltage value and a maximum voltage value when a voltage reaches a maximum value after shutdown, then decreases, and the voltage rises again due to oscillation.

[0039] Fig. Figure 9 shows a relationship between the total amount of electrically active impurities per unit area of ​​the first n-type buffer layer 8 and the maximum voltage oscillation width at the start of a shutdown oscillation. Since the growth of the depletion layer at the time of shutdown varies over time, its growth is confirmed using a simulation in a static case. If the impurity concentration of the first n-type buffer layer 8 is low, an oscillation is more likely to occur. If the impurity concentration of the first n-type buffer layer 8 is high, a voltage oscillation may be suppressed. More precisely, from Fig. It can be read that if the total amount of electrically active impurities per unit area is 4.5 × 10 11 cm -2 or increases in size, the oscillation of the voltage is suppressed.

[0040] Fig. Figure 10 is a diagram representing the electric field strength in the semiconductor device 20 when a nominal voltage Vce = 1200 V is applied. The total amount of impurities in the first n-type buffer layer 8 is specified as five different total amounts of impurities, and characteristic curves C1 to C5, showing their respective calculation results, are shown. The ratio between the five total amounts of impurities and the characteristic curves C1 to C5 is as follows: C1 is 1.6 × 10 11 cm -2 ; C2 is 3.1 × 10 11 cm -2 ; C3 is 4.5 × 10 11 cm -2 C4 is 5.9 × 10 11 cm -2 ; and C5 is 1.4 × 10 12 cm -2 Longitudinal lines, represented by dashed lines in Fig. Figure 10 shows a transition J1 between the drift layer 1 and the first n-type buffer layer 8, a transition J2 between the first n-type buffer layer 8 and the second n-type buffer layer 11, and a transition J3 between the second n-type buffer layer 11 and the collector layer 9. Since the impurity concentration in the first n-type buffer layer 8 is higher than in the drift layer 1, the depletion layer hardly spreads in the first n-type buffer layer 8.

[0041] Fig. Figure 11 is an enlarged view of an area with a thickness of 90 µm to 110 µm in Fig. 10. The one in Fig. The enlarged area 11 corresponds to the area from the first n-type buffer layer 8 to the collector layer 9. To prevent oscillation at the time of a switch-off, it is preferred to prevent the depletion layer from reaching the second n-type buffer layer 11 when a nominal voltage is applied in a static state, during a switching operation, or when a breakdown voltage is maintained in the OFF state. In this regard, according to Fig. 11 the depletion layer the second n-type buffer layer 11 not in the characteristic curves C3 to C5, in which a total amount of electrically active impurities per unit area is 4.5 × 10 11 cm -2 or larger. A total amount of impurities of 4.5 × 10 11 cm -2 coincides with a minimal total amount of impurities for suppressing an oscillation voltage at the time of a shutdown.

[0042] As described above, according to the first embodiment, in the semiconductor device 20, which is provided with the first and second n-type buffer layers 8 and 11, the total amount of electrically active impurities per unit area of ​​the first n-type buffer layer 8 is 1.0 × 10 12 cm -2 or less. Since the upper limit of the total amount of impurities in the first n-type buffer layer 8 is suitably determined so that it is able to reduce a maximum electric field in the semiconductor device 20, the SCSOA can be obtained to have a preferred characteristic. On the other hand, the lower limit of the total amount of electrically active impurities per unit area in the first n-type buffer layer 8 is preferably 4.5 × 10 11 cm -2or greater. In this way, the effect of suppressing an oscillation at the time of a shutdown is achieved. That is, from the results in Fig. 3, Fig. 7 and Fig. 9 is preferably the total amount of electrically active impurities per unit area of ​​the first n-type buffer layer 8 within a range of 4.5 × 10 11 cm -2 up to 1.0 × 10 12 cm -2 to define. In this way, it is possible to provide a wide SCSOA and a high shutdown oscillation suppression effect while suppressing leakage current.

[0043] It should be noted that the impurity concentration of the second n-type buffer layer 11 must be higher than that of the first n-type buffer layer 8. However, in order to achieve a higher leakage current suppression effect and a higher suppression effect for a maximum electric field in the semiconductor device 20, the impurity concentration of the second n-type buffer layer 11 also has a preferred range. The scale on the vertical axis of the Fig. The graph shown in the second graph is a logarithmic one, and in Fig. 2 The second n-type buffer layer 11 according to the first embodiment has a maximum value of an impurity concentration distribution of 3 × 10 16 cm -3 as an example. A maximum concentration value of the impurity concentration distribution in the thickness direction of the second n-type buffer layer 11 can be set such that it falls within a range of 3 × 10 16 cm -3 up to 6 × 10 16cm -3 as an example. Furthermore, the total amount of electrically active impurities per unit area of ​​the second n-type buffer layer 11 can also be specified such that it falls within a range of 7 × 10 11 cm -2 up to 1.4 × 10 12 cm -2 falls.

[0044] It should be noted that the following semiconductor device may also be provided as a modification of the semiconductor device 20 according to the first embodiment.

[0045] The semiconductor device 20 has been described in the first embodiment, in which the semiconductor material is silicon, the dopant of the first n-type buffer layer is 8 protons, and the dopant of the second n-type buffer layer is phosphorus or arsenic. However, the semiconductor material of the drift layer 1 can be silicon carbide, i.e., SiC. In this case, the dopant of the first n-type buffer layer can be 8 protons, and the dopant of the second n-type buffer layer can be nitrogen.

[0046] The first embodiment aims to provide an IGBT with a trench gate, but as a modification, the aim can be an IGBT with a planar gate. Furthermore, a MOSFET can be provided by omitting the collector layer 9.

[0047] Fig. 12 to Fig. Figure 22 are diagrams describing a method for manufacturing the semiconductor device 20 according to the first embodiment of the present invention. Fig. Figure 12 is a flowchart illustrating a method for manufacturing the semiconductor device 20 according to the first embodiment. A surface process for manufacturing a surface structure, i.e., the MOSFET part 22, is similar to a method for manufacturing a well-known IGBT and is not a new item. Therefore, a detailed description of the surface process is omitted.

[0048] (Step S100) In the Fig. In the flowchart shown in section 12, a semiconductor wafer is first prepared at the time of completion of the surface process, as shown in Fig. Figure 13 shows that the semiconductor wafer is configured by forming the MOSFET part 22 on the silicon substrate 1. It should be noted that at a predetermined stage after the completion of a process in Fig. In the backside process shown in section 12, the semiconductor device 20, which is formed into a chip, is provided by sawing the semiconductor wafer. At one point in Fig. 13. The wafer thickness is on the order of 700 µm and is essentially the same as that of a bare wafer.

[0049] (Step S102) Next, as in Fig. Figure 14 shows that the back side of the semiconductor wafer, i.e., the back side of the drift layer 1, is polished to a desired thickness using a grinder or wet sets. In the first embodiment, polishing is carried out until the wafer thickness reaches, for example, 110 µm.

[0050] Next, a "first buffer layer formation step" is performed. In this step, protons are ion-implanted onto the back side of the drift layer 1 to a first depth, and a heat treatment is applied. This forms the first n-type buffer layer 8, which distributes the impurity concentration in the thickness direction with a first concentration peak, as shown in Fig. 2 shown, exhibits.

[0051] (Step S104) We will first explain in more detail how in Fig. Figure 15 shows that protons are implanted from the rear side at an accelerating voltage of up to 1500 keV for several times. The range of the protons is 6 µm at 500 keV and on the order of 30 µm at 1500 keV. In the first buffer layer formation step, it is preferred to implant ions several times at an accelerating voltage of 1.5 × 10 6to perform implantations at eV or less. Although a broader impurity concentration gradient is formed by performing an activation anneal to spread the protons, it is preferred to perform implantations several times while varying the accelerating voltage to form an impurity concentration gradient closer to a Gaussian distribution.

[0052] Furthermore, in the first buffer layer formation step, it is preferred to set the proton implantation angle to 7 degrees or more and to 60 degrees or less. By increasing the ion implantation angle to a specific degree, it is possible to create a gentler impurity concentration gradient in the thickness direction of the first n-type buffer layer 8. This is described in more detail below. Fig. Figure 22 represents an impurity concentration profile when protons of 1.0 × 10 12 cm -2Protons are implanted into the semiconductor substrate at angles of 7 degrees and 60 degrees. Even if the proton implantation angle is set to a small angle, protons are spread by performing the activation anneal, so they provide a broad profile, but its full width at half the maximum is small and its impurity concentration gradient is intense. In this case, to obtain a profile similar to a Gaussian distribution, the implantation must be performed several times while varying the accelerating voltage. Although the range can be reduced by setting a large ion implantation angle, that is, by setting an ion implantation angle, for example, within a range of 7 to 60 degrees, a gentle impurity concentration gradient, such as that found in Fig. The impurity concentration distribution shown in Figure 22 for an ion implantation angle of 60 degrees can be generated more easily. As a consequence, advantages include a reduction in the number of implantations and a reduction in the work and time required to adjust the beam current when the accelerating voltage is changed. It should be noted that the implantation depth is a function of the implantation angle θ and is essentially determined by cos θ. The range when θ = 60 degrees is half that when θ = 7 degrees. If an ion implantation is performed several times by carrying out one implantation at 7 degrees and one at 60 degrees, it is possible to position the highest impurity concentration position of the first n-type buffer layer 8 in the vicinity of a depth of 30 µm and in the vicinity of a depth of 15 µm.This makes it possible to achieve a well-balanced growth of the depletion layer while maintaining the breakdown stress.

[0053] (Step S106) Next, furnace annealing is carried out at a temperature on the order of 350°C to 450°C. In this way, protons are activated and the first n-type buffer layer 8 is formed, as shown in Fig. 16 shown.

[0054] Next, a “second buffer layer formation step” is performed. In the second buffer layer formation step, V-group elements are ion-implanted into the back side of the first n-type buffer layer 8 to a second depth, which is shallower than the first depth, and a heat treatment is carried out. In this way, the second n-type buffer layer 11 is formed, as described in Fig. 2 shown, formed, which has a contaminant concentration distribution in the thickness direction with a second concentration maximum value which is higher than the first concentration maximum value.

[0055] (Step S108) More precisely, phosphorus is only implanted at an accelerating voltage of 1 MeV or less, as in Fig. Figure 17 shows that the second n-type buffer layer 11 is formed in a flat part on the back side of the drift layer 1, in other words, in a flat part of the back side of the first n-type buffer layer 8. It should be noted that arsenic can be implanted instead of phosphorus.

[0056] (Step S110) Then, activation is performed using laser annealing, and the second n-type buffer layer 11 is applied as in Fig. 18 shown, trained.

[0057] Therefore, it is preferred to perform furnace annealing in the first buffer layer formation step and laser annealing in the second buffer layer formation step.

[0058] (Step S112) Next, as in Fig. Figure 19 shows that boron is implanted into the back side of the second n-type buffer layer 11 to form the collector layer 9.

[0059] (Step S114) Next, laser annealing is performed, and collector layer 9 is formed as shown in Fig. 20 shown.

[0060] (Step S116) Then, as in Fig. Figure 21 shows the collector electrode 10 produced by sputtering. The material of the collector electrode 10 can be Al / Ti / Ni / Au or AlSi / Ti / Ni / Au or the like.

[0061] (Step S118) Finally, a heat treatment is performed to reduce the contact resistance between the n-type silicon substrate 1 and the collector electrode 10. It should be noted that, as a modification, the heat treatment for proton activation in step S106 can be omitted, and the heat treatment performed when forming the collector electrode 10 can also serve as such an omitted heat treatment.

[0062] At the same accelerating voltage, protons have a relatively long range, and are therefore suitable for forming the first n-type buffer layer 8 to a deep region of the back side of the drift layer 1. On the other hand, V-group elements have relatively short ranges, making it possible to accurately form a region with a high impurity concentration in a shallow region of the back side of the drift layer 1. By using dopants in different ways for different purposes, taking advantage of these characteristics, it is possible to form the first n-type buffer layer 8 and the second n-type buffer layer 11 to a desired depth and with a desired impurity concentration. Second embodiment

[0063] Fig. Figure 25 is a diagram illustrating a semiconductor device 50 according to a second embodiment of the present invention. In the first embodiment, the collector layer 9 is formed over the entire back side of the drift layer 1. In contrast, in the second embodiment, a p-type collector layer 9 is formed directly beneath a cell portion 62, and a p-type collector layer 14, which has a lower impurity concentration than the collector layer 9, is formed directly beneath a gate wiring portion 64 and a breakdown voltage retention portion 66. Apart from this, the semiconductor device 50 according to the second embodiment has a structure similar to that of the semiconductor device 20 according to the first embodiment. Therefore, it is assumed that the following description focuses on differences from the first embodiment.Identical or corresponding elements between the first embodiment and the second embodiment are assigned the same reference numerals, and their description is simplified or omitted.

[0064] As in Fig. As shown in Figure 25, the semiconductor device 50 is provided with the cell part 62 and a circumferential region 68, which is designed to surround the cell part 62 on the front face of the drift layer 1. The circumferential region 68 includes the gate wiring part 64 and the breakdown voltage retainer 66. The gate wiring part 64 is located next to the cell part 62 on the front face of the drift layer 1. The gate wiring part 64 is provided with gate wiring 13. The gate wiring 13 is connected to the trench gate 4 according to a generally known wiring method, the details of which are not shown. The breakdown voltage retainer 66 is also located next to the gate wiring part 64. The breakdown voltage retainer 66 is provided with a guard ring 12.It should be noted that when the semiconductor device 50 is viewed in a top view, the cell part 62 is provided in the center of the semiconductor chip, the gate wiring part 64 is provided around the cell part 62, and the breakdown voltage holding part 66 is provided further outside the gate wiring part 64.

[0065] Collector layer 9 is of a p-type and is located on the back side of the second n-type buffer layer 11 in an area directly below the cell part 62. Collector layer 14 is of a p-type and is located on the back side of the second n-type buffer layer 11 in an area directly below the gate wiring part 64 and in an area directly below the breakdown voltage holding part 66. The impurity concentration of collector layer 14 is lower than that of collector layer 9.

[0066] In a situation where a voltage exceeding a threshold voltage is applied to the gate and the IGBT is switched on, an electron current flows towards a collector region directly below cell part 62. Therefore, since the collector region directly below cell part 62 operates in ON mode, an equivalent ON voltage is applied, regardless of the presence or absence of the collector layer 14, which has a low impurity concentration and is located directly below the breakdown voltage hold-down region 66. However, in a test of a turn-off cut-off resistor such as the reverse bias safe operation area (RBSOA), the IGBT will enter temporary PNP operation when the gate voltage is cut off at the time of turn-off.For this reason, by placing the collector layer 14 with a low concentration directly below the breakdown voltage retention section 66, it is possible to prevent a hole current from flowing from the collector layer 14 directly below the breakdown voltage retention section 66 into the cell section 62. As a consequence, the cut-off resistance is improved.

[0067] Fig.Figure 26 is a diagram illustrating a semiconductor device 150 according to a modification of the second embodiment of the present invention. In the semiconductor device 150, the collector layer 9 is formed only in a region directly below the cell part 62. That is, the collector layer is not provided in regions directly below the gate wiring part 64 and the breakdown voltage holding part 66, and the collector electrode 10 is formed on the back side of the second n-type buffer layer 11 in the regions directly below the gate wiring part 64 and the breakdown voltage holding part 66.

[0068] Differences in the effects of semiconductor devices 50 and 150 are described. The turn-off cut-off resistance can be improved more by not forming the collector layer 9 in the region directly beneath the circumferential region 68, as in the case of semiconductor device 150, than by reducing the impurity concentration of the collector layer 14 directly beneath the breakdown voltage retention region 66. On the other hand, however, semiconductor device 150 also has a disadvantage: the breakdown voltage decreases when voltages in reverse directions are applied to the first and second n-type buffer layers 8 and 11 and the collector layer 9. More precisely, if energy stored in an inductive load begins to flow into a freewheeling diode during a switching operation, a voltage on the order of several tens of volts can be applied directly to the diode.In this case, a negative voltage is applied to the collector side of the IGBT, which is connected in parallel to the freewheeling diode. Therefore, a breakdown voltage of the pn junction on the back side may be required. To obtain such a breakdown voltage, the collector layer 14 in the semiconductor device 50 is formed, which has an impurity concentration high enough to maintain a reverse breakdown voltage directly below the breakdown voltage retention section 66.

[0069] It should be noted that the breakdown voltage retention region 66 is wider than the gate wiring region 64 in the plane direction of the semiconductor devices 50 and 150. Improving the structure of the collector layer directly beneath the breakdown voltage retention region 66 is more important for improving the RBSOA. Therefore, it is preferable to include collector layer 14, or to omit either collector layer 9 or 14, in the region directly beneath at least the breakdown voltage retention region 66. Both the gate wiring region 64 and the breakdown voltage retention region 66 are ineffective regions where no transistor is formed; that is, regions where the collector layer on the back side is not important.Therefore, the gate wiring part 64 and the breakdown voltage holding part 66 can together be treated as the circumferential region 68, and the collector layer 14 can be provided in the region directly below the circumferential region 68, as in the case of the semiconductor device 50, or the collector layer can not be provided in the region directly below the circumferential region 68, as in the case of the semiconductor device 150.

[0070] It should be noted that, when the semiconductor device 50 is manufactured according to the second embodiment, the boron implantation step in step S112 and the laser annealing step in step S114 can be modified in the manufacturing process of the first embodiment, as an example. More precisely, the impurity concentration of the collector layer between the area directly below the cell part 62, the areas directly below the gate wiring part 64, and the breakdown voltage holding part 66 can be changed using a photolithography technique.

[0071] It should be noted that the collector layer 14 according to the second embodiment can be used in a so-called longitudinal IGBT and a longitudinal MOSFET. It is also applicable in a generally known longitudinal IGBT and a longitudinal MOSFET, and applicable in both a trench gate and a planar gate, regardless of the presence or absence of the first n-type buffer layer 8 and the second n-type buffer layer 11 according to the first embodiment.

[0072] The features and advantages of the present invention can be summarized as follows. According to the first aspect of the present invention, a suitable upper limit for the impurity concentration of the first buffer layer is defined such that it is able to reduce a maximum electric field in the semiconductor device, and it is thereby possible to obtain the SCSOA with a preferred characteristic.

[0073] According to the second aspect of the present invention, a suitable dopant is selected according to the necessary buffer layer structure, and it is thereby easier to accurately form the first and second buffer layers in the deep region and the shallow region respectively on the drift layer back side.

[0074] According to the third aspect of the present invention, it is possible to improve the RBSOA by preventing the introduction of holes to the cell portion from outside the cell portion. Simultaneously, it is also possible to prevent a deterioration of the reverse breakdown voltage by providing a collector layer with a low impurity concentration in an area directly beneath the gate wiring portion.

[0075] In summary, a semiconductor device comprises a drift layer formed from a semiconductor material of a first conductivity type, a MOSFET part having a p-type base layer on a front face of the drift layer, a first n-type buffer layer on a back face of the drift layer, and a second n-type buffer layer on a back face of the first n-type buffer layer, which has a high impurity concentration. The first n-type buffer layer has a higher impurity concentration than the drift layer and has a total amount of electrically active impurities per unit area of ​​1.0 × 10⁻⁶. 12 cm -2 or less. Reference symbol list 1. Substrate, drift layer 2 p-type base layer 3 n+-type emitter layer 4 Trench Gate 5 p + -Type layer 6 intermediate layer insulation layer 7 Emitter electrode 8 n-type buffer layer 9 p-type collector layer 10 Collector electrode 11 n-type buffer layer 12 Protective ring 13 Gate wiring 14 p-type collector layer 20 Semiconductor device 22 MOSFET part 50 Semiconductor device 62 cell part 64 Gate wiring section 66 Breakdown voltage holding element 68 Scope 120 semiconductor device 150 semiconductor device

Claims

[1] Semiconductor device comprising: a drift layer (1) formed from a semiconductor material of a first conductivity type; a MOSFET part (22) which is provided on a front surface of the drift layer (1) and has a semiconductor layer of a second conductivity type which forms a pn junction with the drift layer (1); a first buffer layer (8) provided on a back side of the drift layer (1), which has the first conductivity type, has a higher impurity concentration than the drift layer and a total amount of electrically active impurities per unit area of ​​1.0 × 10 12 cm -2 or less; and a second buffer layer (11) provided on a back side of the first buffer layer (8), which has the first conductivity type and has a higher impurity concentration than the first buffer layer (8), wherein the impurity concentration of the first buffer layer (8) 1.0 × 10 15 cm -3 or less, and a maximum concentration value of the impurity concentration distribution in one thickness direction of the second buffer layer (11) in a range of 3 × 10 16 cm -3 up to 6 × 10 16 cm -3 falls. [2] Semiconductor device according to claim 1, wherein the total amount of electrically active impurities per unit area of ​​the first buffer layer (8) is 4.5 × 10 11 cm -2 or more. [3] Semiconductor device according to claim 1 or 2, wherein the semiconductor material is silicon, a dopant of the first buffer layer (8) protons are, and a dopant of the second buffer layer (11) is phosphorus or arsenic. [4] Semiconductor device according to claim 1 or 2, wherein the semiconductor material is silicon carbide, a dopant of the first buffer layer (8) protons are, and a dopant of the second buffer layer (11) is nitrogen. [5] Semiconductor device according to one of claims 1 to 4, further comprising a collector layer (9) which is provided on a back side of the second buffer layer (11) and which has the second conductivity type. [6] Semiconductor device according to claim 5, further comprising a circumferential region (68) which is provided around the MOSFET part (22) on the front surface of the drift layer (1), wherein the collector layer (9) is provided in an area directly below the MOSFET part (22) and in an area directly below the circumferential area (68) on the back side of the second buffer layer (11) and has the second conductivity type, and a contamination concentration of the collector layer (9) in the area directly below the circumferential area (68) is lower than a contamination concentration of the collector layer (9) in the area directly below the MOSFET part (22). [7] Semiconductor device according to claim 5, further comprising a circumferential region (68) which is provided around the MOSFET part (22) on the front surface of the drift layer (1), wherein the collector layer (9) has the second conductivity type, is provided in a region directly below the MOSFET part (22) on the back side of the second buffer layer (11) and is not provided in a region directly below the circumferential region (68) on the back side of the second buffer layer (11). [8] Semiconductor device comprising: a drift layer (1) formed from a semiconductor material of a first conductivity type; a cell part (62) that is provided on a front surface of the drift layer (1); a circumferential area (68) which is provided around the cell part (62) on the front surface of the drift layer (1); a first buffer layer (8) provided on a back side of the drift layer (1), which has the first conductivity type, has a higher impurity concentration than the drift layer and a total amount of electrically active impurities per unit area of ​​1.0 × 10 12 cm -2 or less; a second buffer layer (11) provided on the back side of the first buffer layer (8), which has the first conductivity type and has a higher impurity concentration than the first buffer layer (8); and a collector layer (9) which is provided to extend over an area directly below the cell part (62) and an area directly below the circumferential area (68) on a rear side of the buffer layer (8, 11) and has a second conductivity type, the impurity concentration of which in an area directly below the circumferential area (68) is lower than an impurity concentration in an area directly below the cell part (62), wherein the impurity concentration of the first buffer layer (8) 1.0 × 10 15 cm -3 or less, and a maximum concentration value of the impurity concentration distribution in one thickness direction of the second buffer layer (11) in a range of 3 × 10 16 cm -3 up to 6 × 10 16 cm -3 falls. [9] Semiconductor device according to claim 8, wherein the circumferential region (68) comprises a gate wiring part (64) which is provided next to the cell part (62) on the front surface of the drift layer (1), and a breakdown voltage holding part (66) which is further provided next to the gate wiring part (64), and the collector layer (9) is provided such that it extends over an area directly below the gate wiring part (64) and an area directly below the breakdown voltage holding part (66) on the back side of the buffer layer (8, 11), the impurity concentrations of which in an area directly below the gate wiring part (64) and in an area directly below the breakdown voltage holding part (66) are lower than an impurity concentration in an area directly below the cell part (62).

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