PARALLELIZATION METHOD AND PARALLELIZATION TOOL

Abstract

Parallelization method for automatically parallelizing a control program executed by a single-core processor and comprising several processing blocks (T1 to T5, T7 to T11) to generate a parallelized control program (21a1) from the several processing blocks and a non-control program (21a2) which, during its execution, monitors the parallelized control program (21a1) for failure, wherein the several processing blocks (T1 to T5, T7 to T11) are assigned to several cores (21c, 21d) of a multi-core processor (21), wherein a previous and a later processing block are related to each other by the fact that the processing of the later processing block depends on the preceding processing of the earlier processing block, wherein the execution order of each later and assigned previous processing block during processing by the several cores (21c,21d) is ensured by inserting respective associated store processing procedures and wait processing procedures into the parallelized control program (21a1), wherein, in a store processing procedure that is executed immediately after completion of an execution of the associated previous processing block, an associated termination state flag is modified to indicate the completion of the execution of the previous processing block; and wherein a wait processing procedure allows execution of an associated subsequent processing block only on the condition that the termination state flag of the associated previous processing block indicates that the execution of the previous processing block is complete, wherein the non-control program (21a2) is a synchronous monitoring processing procedure that monitors whether all termination state flags that are each associated with the previous processing blocks,indicate that the execution of the respective previous processing blocks is complete, and has a synchronous failover processing procedure that is executed if the synchronous monitoring processing procedure determines that not all termination state flags indicate that the execution of the respective previous processing blocks is complete.

Description

The present invention relates to a parallelization method and a parallelization tool for automatically fail-safe parallelizing a control program executed by a single core processor and including a plurality of processing blocks to generate a parallelized control program from the plurality of processing blocks and a non-control program that, when executed, monitors the parallelized control program for a failure.JP 2015-001 807 A (corresponding to US 2014 / 0 372 995 A1) discloses a parallelization compilation method as an exemplary parallelization method for generating programs of a multi-core processor from a program of a single-core processor.According to the parallelization compilation method, a serial program for an integrated system executed by a single core processor system is divided into a plurality of macro tasks (macro tasks), and then the macro tasks having a control dependency are combined into one macro task. Further, according to the parallelization compilation method, the macro tasks executable in parallel are extracted based on data dependency, and a parallel program is generated by static scheduling.In the parallelization method, it is proposed to assign normal processing to each core after parallelization analysis and insert synchronous processing for maintaining an order of processing execution. This synchronous processing includes a state setting for setting a variable indicating termination of the normal processing and waiting for waiting to start normal processing from its core until a variable is set in the other core.The variable is likely to unexpectedly change due to noise or the like. In the multi-core processor, when the variable is changed, the waiting processing continues in at least one core and causes a system block in which execution of the normal processing is prohibited.In order to prevent the system blockage, it may be proposed to insert into the parallel program fail-safe processing such as processing for restoring the unexpectedly changed variable to a previous state. In this case, the parallel program is control logic corresponding to the program of the single core processor and a logic group including fail-safe logic for preventing the system lock state. The parallel program generated as described above is not advantageous in that the control logic in the core for executing the parallel program requires complicated management and a processing load of the core increases upon execution of the control logic.Furthermore, DE 10 2010 042 574 A1 discloses a method for operating a microcontroller for an automobile.The present invention has an object to provide a parallelization method and a parallelization tool that simplify logic management and are capable of generating a parallelized program that is effective in keeping a processing load low at a time of execution of control logic.This object is achieved by the subject matters having the features according to the independent claims. FIG. 1 is a block diagram showing a general configuration of a parallelization tool according to an embodiment of the present invention; FIG. 2 is a block diagram showing a general configuration of an in-vehicle control device according to the embodiment; FIG. 3 is a flowchart showing a processing operation (processing operation) of a computer in the embodiment; FIG. 4 is a pictorial illustration of a parallel program in the embodiment; FIG. 5 is a flowchart showing a processing operation of the in-vehicle control device in the embodiment; FIG. 6 is a flowchart showing a processing operation of the in-vehicle control device in the embodiment; FIG. 7 is a flowchart showing a processing operation of the computer in the embodiment; and FIG. 8 is a flowchart showing a processing operation of an in-vehicle control device according to a modification.(Embodiment)The present invention will be described below with reference to an embodiment shown in the drawings.Referring to FIGS. 1 and 2, a computer 10 is provided to generate a parallel program 21 a 1 parallelized for a multi-core processor 20 having a first core 21 cand a second core 21 dcapable of executing multiple processing of a single-core processor having a single core in parallel. The processor is a microcomputer. The computer 10 according to the present embodiment further generates, in addition to the parallel program 21 a 1, a non-control program 21 a 2 different from the parallel program 21 a 1 executable by the first core 21 cand the second core 21 d. That is, the computer 10 generates a program 21 a 3 including the parallel program 21 a 1 and the non-control program 21 a 2.As disclosed in JP 2015-001 807 A, the parallel program 21 a 1 is generated by analyzing the single program and assigning the multiple processing to the first core 21 cand the second core 21 d. The detailed disclosure of JP 2015-001 807 A is incorporated herein by reference.In the following description, processing is referred to as a processing block, i.e., a task block (task block). In the present embodiment, as shown in FIG. 4, the multiple processing blocks are assumed to include a first processing block T 1 to a fifth processing block T 5 and a sixth processing block T 6 to an eleventh processing block T 11. The multiple processing blocks include prior processing and later processing assigned to different cores. The previous processing is first executed and the later processing is executed after completion of the previous processing. Later processing is processing that receives influence of the previous processing. Later processing uses, for example, data likely to be updated in the previous processing. For example, of the first processing block T 1 and the eighth processing block T 8, the first processing block T 1 is the previous processing and the previous processing block, respectively, and the eighth processing block T 8 is the later processing block. Of the third processing block T 3 and the eighth processing block T 8, the eighth processing block T 8 is the previous processing, and the third processing block T 3 is the later processing.The computer 10 and the in-vehicle control device 20 are configured as described below, as shown in FIG. 1. The computer 10 is a parallelization tool that performs parallelization procedures. The computer 10 is also a program generation tool (program generation tool) that generates the program 21 a 3 including the parallelization program 21 a 1 and the non-control program 21 a 2. The computer 10 is configured to include a display 11, an HDD 12, a CPU 13, a ROM 14, a RAM 15, an input device 16, a fetch part 17, and the like. The computer 10 is configured to retrieve storage contents stored in a storage medium 18. The storage medium 18 stores therein an automatic parallelization compiler 1. the computer 10 and the storage medium may be configured with reference to a personal computer 100 and a storage medium 180 disclosed in JP 2015-001 807 A.The automatic parallelization compiler 1 is a parallelization method. That is, the automatic parallelization compiler 1 is a program defining a parallelization procedure, i.e., the parallelization method. The computer 10 generates the program 21 a 3 including the parallel program 21 a 1 and the non-control program 21 a 2 by executing the automatic parallelization compiler 1.The automatic parallelization compiler 1 may be configured with reference to the disclosure of JP 2015-001 807 A. The automatic parallelization compiler 1 specifically includes procedures for inserting state setting processing (state setting processing), inserting wait processing, inserting synchronous monitoring processing, and inserting synchronous fail-safe processing.The insertion procedure of the state setting processing is for inserting the state setting processing(s) F 0 to F 2 and F 4 to F 6 into the parallel program 21 a 1 as shown in FIG. 4. The state setting processes F 0 to F 2 and F 4 to F 6 are processes for storing a termination state at the time of termination of the previous processing to maintain the sequence of execution between different cores, i.e., between the first core 21 cand the second core 21 d. That is, the insertion procedure of the state setting processing is provided to cause the first core 21 cand the second core 21 dto execute the state setting processing at the time of completion of the previous processing of the first core 21 cand the second core 21 d. The state setting processing is storage processing of the termination state. The insertion procedure of the state setting processing is a storage processing insertion procedure.Here, as a storage (storage) method of a termination state, state flags A 1, A 3, A 6, B 8, B 10, and B 11 are used. Each state flag indicates the termination state (uncompleted state) if "1" is set ("0" is set). As described above, the in-vehicle control device 20 is configured to set a state flag corresponding to each of the multiple previous processings. Setting the state flag is storing the termination state.The first state flag A 1 corresponds to the first processing block T 1. If the first processing block T 1 has been completed, "1" and "0", respectively, are set in the first state setting processing F 1. The third state flag A 3 corresponds to the third processing block T 3. If the third processing block T 3 has been completed, "1" and "0", respectively, are set in the second state setting processing F 2. The eighth state flag B 8 corresponds to the eighth processing block T 8. If the eighth processing block T 8 has been completed, "1" and "0", respectively, are set in the fifth state setting processing F 5. The tenth state flag B 10 corresponds to the tenth processing block T 10. If the tenth processing block T 10 has been completed, "1" and "0", respectively, are set in the sixth state setting processing F 6.A state flag AA indicates a state of the entire state flags of the first core 21c. If the state flag AA is set to "1" and "0", respectively, it indicates that all of the state flags A1 to A6 are in the terminated states and not in the terminated states, respectively. The state flag AA set to "1" is reset to "0" in the zeroth state setting processing F 0.A state flag BA indicates a state of the entire state flags of the second core 21 d. If the state flag BA is set to "1" and "0", respectively, it indicates that all of the state flags B8 to B11 are in the terminated states and not in the terminated states, respectively. The state flag BA set to "1" is reset to "0" in the fourth state setting processing F 4.The insertion procedure of the wait processing is for inserting wait processes W1, W2, W4, and W5 into the parallel program 21a1. The waiting processes W1, W2, W4, and W5 are for executing the later processing after waiting and setting the state flag to maintain the sequence of execution between the first core 21 cand the second core 21 d. That is, the insertion procedure of the wait processes W 1, W 2, W 4, and W 5 serves to allow the first core 21 cand the second core 21 dto execute the later processing on the condition that the state flag is set to "1" after waiting for the setting of the state flag. The insertion processing of the wait processing(s) is a wait processing insertion procedure. In the present embodiment, as shown in FIG. 4, the waiting processing is indicated as a "while" set ("so long" set), for example, while (B8=0) (so long (B8=0)) in the waiting processing W 1.The first waiting processing W 1 corresponds to an eighth state flag B 8. The first waiting processing W 1 is for executing the third processing block T 3, which is the later processing, on condition that the eighth state flag B 8 has been changed to "1" after repeatedly checking whether the eighth state flag B 8 is "0". The second waiting processing W 2 corresponds to a tenth state flag B 10. The second processing W 2 is to execute the fifth processing block T 5, which is the later processing, on condition that the tenth state flag B 10 has been changed to "1" after repeatedly checking whether the tenth state flag B 10 is "0".The fourth waiting processing W 4 corresponds to a first state flag A 1. The fourth waiting processing W 4 is for executing the eighth processing block T 8, which is the later processing, on condition that the first state flag A 1 has been changed to "1" after repeatedly checking whether the first state flag A 1 is "0". The fifth waiting processing W 5 corresponds to a third state flag A 3. The fifth waiting processing W 5 is for executing the tenth processing block T 10, which is the later processing, on condition that the third state flag A 3 has been changed to "1" after repeatedly checking whether the third state flag A 3 is "0".The insertion procedure of the synchronous monitoring processing is to insert the monitoring processing that monitors whether the state flag is set to "1" before the parallel program 21 a 1 is executed into the non-control program 21 a 2. That is, the insertion procedure of the synchronous monitoring processing is provided to execute the monitoring processing that monitors whether all of the state flags are set to "1" before execution of the parallel program 21 a 1. Thus, the insertion procedure of the synchronous monitoring processing serves to cause the first core 21 cand the second core 21 dto confirm that all of the state flags are set to "1" before execution of the parallel program 21 a 1. The insertion procedure of the synchronous monitoring processing is a monitoring processing insertion procedure. The non-control program 21 a 2 will be described in more detail later.The insertion procedure for inserting the synchronous fail-safe processing is to insert the synchronous fail-safe processing, which is executed when the synchronous monitoring processing detects that any one of the state flags is not set to "1", into the non-control program 21 a 2. That is, the synchronous fail-safe processing insertion procedure is for causing the first core 21c and the second core 21d to execute the synchronous fail-safe processing which is executed after detecting the synchronous monitoring processing that any of the state flags is not set to "1". The insertion procedure of the synchronous fail-safe processing is a fail-safe processing insertion procedure.The synchronous fail-safe processing includes, for example, a reset of a task (a task), a reset of the multi-core processor 21, and a reset of vehicle information such as a limp home operation mode or a vehicle operation state. A reset of a task is processing for executing the tasks that the first core 21 cand the second core 21 dexecute to the beginning. Resetting of the multi-core processor 21 is processing for resetting the RAM 21 band registers of the multi-core processor 21, The limp home operation mode is a mode for causing the first core 21 cand the second core 21 dto not execute the parallel program 21 a 1 but execute processing for driving the vehicle in a limp home mode. Resetting of the vehicle information is processing for resetting the vehicle information (variable(s)) to which the first core 21 cand the second core 21 d relate in executing the parallel program 21 a 1 or which the first core 21 cand the second core 21 ddescribe in executing the parallel program 21 a 1.In the present embodiment, the automatic parallelizing compiler 1 is provided as the synchronous processing for simultaneously ending the processing of the first core 21 cand the second core 21 d. The automatic parallelization compiler 1 has procedures for inserting the state setting processing and the waiting processing at the end of the parallel program 21 a 1. As an example, as shown in FIG. 4, the automatic parallelizing compiler 1 has procedures for including the state setting processing F 3 and the waiting processing W 3 as well as the state setting processing F 7 and the waiting processing W 6. Thus, the automatic parallelization compiler 1 generates the parallel program 21 a 1 that allows the first core 21 cand the second core 21 dto finish at the same time. The state setting processing F 3 and the waiting processing W 3, as well as the state setting processing F 7 and the waiting processing W 6, are processes for simultaneously ending the tasks of the first core 21 cand the second core 21 d.The state flag A 6 corresponds to the fifth processing block T 5. The state flag A6 is set to "1" and "0", respectively, in the state setting processing F3 if the fifth processing block T5 has been ended and has not been ended, respectively. The state flag B 11 corresponds to the eleventh processing block T 11. The state flag B 11 is set to "1" and "0", respectively, in the state setting processing F 7 if the eleventh processing block T 11 has been ended and has not been ended, respectively.The waiting processing W 3 corresponds to the state flag B 11. The waiting processing W 3 is finished on the condition that the state flag B 11 has been changed to "1" after repeatedly checking whether the state flag B 11 is "0". The waiting processing W 6 corresponds to the state flag A 6. The waiting processing W 6 is completed on the condition that the state flag A 6 has changed to "1" after repeatedly checking whether the state flag A 6 is "0".The computer 10 generates the parallel program 21a1 including control logic groups corresponding to the first core 21c and the second core 21d as shown in FIG. 4 by executing the automatic parallelizing compiler 1.Further, the computer 10 generates the non-control program 21 a 2 including the synchronous monitoring processing and the synchronous fail-safe processing, which is executed in task activation processing (task activation processing) shown in FIG. 4 by execution of the automatic parallelization compiler 1. The non-control program 21 a 2 thus includes a monitoring logic and a fail-safe logic. However, although the parallel program 21 a 1 includes multiple control logics, it does not include either the monitor logic or the fail-safe logic included in the non-control program 21 a 2.As shown in FIG. 2, the in-vehicle control device 20 is configured to include a multi-core processor 21, a communication part 22, a sensor part 23, and an input-output port (input-output port) 24. The multi-core processor 21 includes not only the first core 21 cand the second core 21 d, but also a ROM 21 aand a RAM 21 b, each of which is a storage medium. The in-vehicle control device 20 is used in, for example, an engine control device or a hybrid control device mounted on a vehicle. As an example, the in-vehicle control device 20 is assumed to be used in the engine control device. In this example, the parallel program 21 a 1 is, for example, a vehicle control program for engine control. The multi-core processor 21 is a multi-core processor. The core may be referred to as a processor element.The RAM 21 b, the communication part 22, the sensor part 23, and the input-output part 24 are provided similarly to a RAM 420, a communication part 430, a sensor part 450, and an input-output port 460 in JP 2015-001 807 A.The ROM 21 astores therein the program 21 a 3 executable by the first core 21 cand the second core 21 d. The program 21 a 3 includes the parallel program 21 a 1 generated by the parallelization method. The first core 21 cand the second core 21 dexecute the engine control by executing the parallel program 21 a 1. That is, the first core 21 cand the second core 21 dexecute the engine control by executing the control logic according to the parallel program 21 a 1.The program 21 a 3 further includes the non-control program 21 a 2 which has been generated by the parallelization method and is different from the parallel program 21 a 1. The first core 21 cand the second core 21 dexecute the non-control program 21 a 2.In the present embodiment, the multi-core processor 21 is assumed to be mounted in the in-vehicle control device 20. The present invention is not limited to this example, and the multi-core processor 21 may be mounted in any other devices, e.g., a personal computer, other than the in-vehicle control device 20.A processing operation (processing operation) of the computer 10 will be described next with reference to FIGS. 3 and 4. The CPU 13 executes processing shown by a flowchart in FIG. 3 when, for example, an execution command for the insertion processing is generated from an input device 16. The CPU 13 generates the program 21 a 3 including the parallel program 21 a 1 and the non-control program 21 a 2 from the single program by executing the automatic parallelization compiler 1. the CPU 13 executes the following steps S 11 to S 14 in the case of generating the parallel program 21 a 1 according to the procedure disclosed in JP 2015-001 807 A.In step S 11, the CPU 13 inserts the state setting processing. The CPU 13 executes the insertion procedure of the state setting processing in the automatic parallelization compiler 1. That is, the CPU 13 inserts the state setting processes F 0 to F 2 and F 4 to F 6 into the parallel program 21 a 1. In the present embodiment, as shown in FIG. 4, the CPU 13 inserts, for example, the first state setting processing F 1 and the eighth state setting processing F 8 following the first processing block T 1 and the eighth processing block T 8, respectively. The computer 10 thus includes a function block that introduces the state setting processing. Step S 11 thus corresponds to a Speicher(ungs)verarbeitungseinfügeteil. The CPU 13 may insert the third state setting processing F 3 and the seventh state setting processing F 7 into the parallel program 21 a 1 in step S 11.In the present embodiment, the CPU 13 is exemplified to insert the plurality of state setting processes F 0 to F 2 and F 4 to F 6 into the parallel program 21 a 1 in step S 11 as shown in FIG. 4. Alternatively, the CPU 13 may insert state setting processing into the parallel program 21 a 1.The CPU 13 inserts the waiting processing in step S 12. The CPU 13 executes the insertion procedure of the wait processing in the automatic parallelizing compiler 1. That is, the CPU 13 inserts the wait processes W 1, W 2, W 4, and W 5 into the parallel program 21 a 1. In the present embodiment, as shown in FIG. 4, the CPU 13 inserts, for example, the fourth waiting processing W 4 and the first waiting processing W 1 in advance of the eighth processing block T 8 and the third processing block T 3, respectively. The computer 10 thus comprises a function block which introduces the wait processing. Step S 12 thus corresponds to a wait processing insertion part. The CPU 13 may insert the third wait processing W 3 and the sixth wait processing W 6 into the parallel program 21 a 1 in step S 12.The CPU 13 inserts the synchronous monitoring processing in step S 13. The CPU 13 executes the insertion procedure of the synchronous monitoring processing in the automatic parallelizing compiler 1. That is, the CPU 13 inserts the synchronous monitoring processing into the non-control program 21 a 2. The computer 10 thus includes a function block that introduces synchronous monitoring processing. Step S 13 thus corresponds to a monitoring processing insertion part.The CPU 13 inserts the synchronous fail-safe processing in step S14. The CPU 13 executes the insertion procedure of the synchronous fail-safe processing in the automatic parallelizing compiler 1. That is, the CPU 13 inserts the synchronous fail-safe processing into the non-control program 21 a 2. The computer 10 thus includes a functional block that introduces synchronous fail-safe processing. Step S 14 thus corresponds to a fail-safe processing insertion part.As described above, the computer 10 generates the parallel program 21 a 1 and the non-control program 21 a 2 in the present embodiment by executing steps S 11 to S 14. An example of a generated parallel program 21a1 is shown in Fig. 1. In this example, the first processing block T 1, the second processing block T 2, the third processing block T 3, the fourth processing block T 4, and the fifth processing block T 5 are allocated to the first core 21 c. On the other hand, the seventh processing block T 7, the eighth processing block T 8, the ninth processing block T 9, the tenth processing block T 10, and the eleventh processing block T 11 are assigned to the second core 21 d.Further, in the parallel program 21 a 1, the state setting processing F 1 and the state setting processing F 5 are inserted following the first processing block T 1 and the eighth processing block T 8, respectively. Further, in the parallel program 21a1, the waiting processing W1 and the waiting processing W4 are inserted in advance of the third processing block T3 and the eighth processing block T8, respectively.The non-control program 21 a 2 includes the monitoring processing that monitors whether the state flags are all set to "1" and the synchronous fail-safe processing that is executed when any of the state flags is not set to "1.".The present invention is not limited to the above-described example. For example, the parallel program 21 a 1 and the non-control program 21 a 2 may be generated by executing steps S 11 to S 14 in addition to the parallelization method disclosed in JP 2015-001 807 A.Processing operations of the first core 21 cand the second core 21 dof the multi-core processor 21 will be described below in detail with reference to FIGS. 4, 5, and 6. The first core 21 cand the second core 21 dexecute task activation processing at every predetermined time and execute the assigned processing each assigned as shown in FIG. 4 after the task activation processing.The first core 21 cand the second core 21 dexecute the non-control program 21 a 2 in the task activation processing, i.e., before execution of the parallel program 21 a 1. The first core 21 cand the second core 21 dexecute processing shown as a flowchart in FIG. 5 in task activation processing. The non-control program 21 a 2 thus includes the processing(s) of steps S 21 to S 25.In some cases depending on the contents of the synchronous fail-safe processing, the first core 21 cand the second core 21 dmay execute the synchronous fail-safe processing without execution of the parallel program 21 a 1 when any of the state flags is "0" as a result of execution of the non-control program 21 a 2. For example, when any one of the state flags is "0" in the setting of the limp home operation mode, the first core 21 cand the second core 21 dexecute the state setting processing for the limp home running of the vehicle according to the limp home operation mode without executing the parallel program 21 a 1.In FIG. 6, which shows a timing chart of the processing operations of the first core 21 cand the second core 21 d, only the first state flag A 1 among the plurality of state flags is shown. Further, FIG. 6 shows an example that the first core 21 cand the second core 21 dstart execution of the task activation processing at time ti 0 (i.e., at time ti 0) and execute the tasks at time ti 1 without synchronous fail-safe processing, and execute the next activation processing at time ti 6 which is after a predetermined time period from the activation time ti 0. Further, in the example shown in FIG. 6, after starting the task activation processing at time ti 6, the first core 21 cand the second core 21 dexecute the synchronous fail-safe processing at time ti 7 and execute the task at time ti 8.Further, in the example shown in FIG. 6, the first state flag A 1 is assumed to be erroneously changed to "0" at time ti 3, and the waiting state of the waiting processing W 4 continues. Thus, the waiting processing W 1 continues to be fixed. That is, the system block arises in the first core 21 cin the first waiting processing W 1 starting at the time ti 5. The system block arises in the waiting processing W4 starting at the time ti4 in the second core 21d.In step S 21, the first core 21 cand the second core 21 dcheck whether the previously activated tasks have been completed. The first core 21c and the second core 21d check whether the previously activated tasks have been completed as shown at a time immediately after the time ti0 and the time ti6. Based on the test results, the first core 21 cand the second core 21 dexecute step S 25 and step S 22 if the task has been completed and has not been completed, respectively.For example, the first core 21 cand the second core 21 ddetermines that the previously activated task has been completed if the state flag B 11 and the state flag A 6 are set to "1". The first core 21 cand the second core 21 ddetermines that the previously activated task has not been completed if either of the state flag B 11 and the state flag A 6 is not set to "1.".The first core 21 cand the second core 21 dactivate tasks in step S 25. The first core 21 cand the second core 21 dstart execution of the parallel program 21 a 1 as shown at time ti 1 and time ti 8 after the task activation.The first core 21 cand the second core 21 dcheck whether any of the state flags is "0" in step S 22. The first core 21 cand the second core 21 dcheck whether any of the state flags A 1, A 3, B 8, and B 10 is "0". That is, the first core 21 cand the second core 21 dcheck whether any of the processing blocks has not been completed yet. The first core 21 cand the second core 21 dmay alternatively check whether any of the state flags including the state flag A 6 and the state flag B 11 is "0" in step S 22.In the case of determining that all of the state flags are set to "1", the first core 21 cand the second core 21 ddetermines that all of the processing blocks have been completed, and executes step S 23. In the case of determining that any of the state flags is "0", the first core 21 cand the second core 21 ddetermines that at least one of the processing blocks has not been completed, and executes step S 24. In the example of FIG. 6, the first core 21 cand the second core 21 ddetermines "YES" (at least one state flag is "0") in step S 22 executed in the task activation processing, which occurs from time ti 6 to time ti 8.The first core 21 cand the second core 21 dexecute the synchronous fail-safe processing. The first core 21 cand the second core 21 dexecute the synchronous fail-safe processing at time ti 7 which is within the activation processing between time ti 6 and time ti 8. For example, the first core 21 cand the second core 21 dresets the task in the synchronous fail-safe processing executed at time ti 7. The first core 21 cand the second core 21 dexecute the parallel program 21 a 1 as shown after time ti 8.The first core 21 cand the second core 21 dexecute fail-safe processing of a task activation time. This task activation time fail-safe processing is different from the fail-safe processing of the synchronous fail-safe processing, and is not limited to a particular processing. Each of the first core 21 cand the second core 21 dactuates the task in a similar manner to step S 25 after termination of step S 23.Since the non-control program 21 a 2 is executed in the task activation processing in the present embodiment, the non-control program 21 a 2 including steps S 21 and S 25 is provided. The present invention is not limited to this example. The non-control program 21 a 2 may be different as long as it includes steps S 22 and S 24.After completion of the task activation processing, each of the first core 21 cand the second core 21 dexecutes the processing of the program 21 aallocated to itself as shown in FIG. 4 in the order of higher priority. The first core 21 cexecutes the zeroth state setting processing F 0 at time ti 1 and sets the state flag AA to "0". The first core 21c resets the state flags A1, A3, and A6, i.e., sets these flags to "0". The second core 21 dalso executes the fourth state setting processing F 4 at time ti 1 and sets the state flag BA to "0". The second core 21d resets the state flags B8, B10, and B11, i.e., sets these flags to "0".Then, the first core 21 cexecutes the first processing block T 1. When the first core 21 cends the execution of the first processing block T 1, the first core 21 cexecutes the state setting processing F 1 and sets the first state flag A 1 to "1". After setting the first state flag A 1 to "1", the first core 21 cexecutes the second processing block T 2. In the present embodiment, it is assumed that the first state flag A 1 is reset by mistake, for example, by noise at time ti 3 as shown in FIG. 6. That is, the first state flag A 1 of the multi-core processor 21 is changed from "1" to "0".The second core 21 dexecutes the seventh processing block T 7 after setting the state flag BA to "0". When the second core 21 dends the execution of the seventh processing block T 7, the second core 21 dexecutes the wait processing W 4 at time ti 4 and loops until the first state flag A 1 is changed to "1".However, the first state flag A 1 is reset to "0" at time ti 3. The first state flag A1 remains "0" although the execution of the first processing block T1 has been completed. For this reason, the second core 21d loops and remains stuck until the first state flag A1 is set to "1" after the time ti4. When the first core 21 cends the execution of the second processing block T 2, the first core 21 cexecutes the wait processing W 1 at time ti 5 and loops until the eighth state flag B 8 is changed to "1". However, since the second core 21 dis locked in the waiting processing W 4 as described above, the first core 21 cmay not execute the third processing block T 3. Thus, the eighth state flag B8 continues to remain "0". The first core 21c loops in a locked state from time ti5 until the eighth state flag B8 is set to "1".Since both the first core 21 cand the second core 21 dare thus locked, the first core 21 and the second core 21 dexecute the next task activation processing after a predetermined time period as shown at time ti 6 without completing the task of this time. The first core 21 cand the second core 21 ddetermines NO (state flag is "0") in step S 21 in the current task activation processing, and executes step S 22. The first core 21 cand the second core 21 ddetermines YES (state flag is "1") in step S 22, and execute the synchronous fail-safe processing at time ti 7.After executing the task activation processing again, each of the first core 21 cand the second core 21 dexecutes the processing of the program 21 aof FIG. 4 assigned to itself in the order of higher priority after the time ti 8 in a similar manner to the above-described case. In the current task, i.e., after time ti8 in FIG. 6, it is assumed that the state flag is not reset by mistake and system blockage does not occur.The first core 21 csets the state flag A 6 to "1" in the state setting processing F 3. The first core 21 creceeds checking whether the state flag B 11 is "0" in the waiting processing W 3 until the state flag B 11 is set to "1". The second core 21 dsets the state flag B 11 to "1" in the state setting processing F 7. The second core 21 dreceeds checking whether the state flag A 6 is "0" in the waiting processing W 6 until the state flag A 6 is set to "1". Thus, the first core 21c and the second core 21d are capable of completing respective tasks at the same time, i.e., in parallel.As described above, the automatic parallelization compiler 1 generates the parallel program 21 a 1 that parallelizes multiple processing to be executed by the multiple cores 21 cand 21 dfrom the multiple processing of the single program that is parallelizable. The automatic parallelization compiler 1 inserts, into the parallel program 21 a 1, the state setting processing that stores the ending state of the previous processing after ending the previous processing and the waiting processing that allows the execution of the later processing on the condition that the ending state of the previous processing is stored, that is, the state flag is "1". The automatic parallelizing compiler 1 thus generates the parallel program 21 a 1 including the control logic corresponding to the single program executed by the single-core processor.The automatic parallelization compiler 1 further inserts the synchronous monitoring processing and the synchronous fail-safe processing into the non-control program 21 a 2 different from the parallel program 21 a 1. For this reason, the automatic parallelization compiler 1 can generate the non-control program 21 a 2 including the monitoring logic and the fail-safe logic separately from the parallel program 21 a 1. The automatic parallelizing compiler 1 can thus generate the non-control program 21 a 2 that allows the multiple cores 21 cand 21 dto execute the synchronous fail-safe processing when the state flag has inadvertently changed from "1" to "0".For this reason, the multiple cores 21 cand 21 dneed not to execute the non-control program 21 a 2 upon execution of the parallel program 21 a 1, and may separately execute the management of the control logic and the management of the monitoring logic and the fail-safe logic. Thus, the automatic parallelization compiler 1 can generate the parallel program 21 a 1 that enables simple logic management, compared to a case where the non-control program 21 a 2 is included in the parallel program 21 a 1.For example, in the case where the non-control program 21 a 2 is included in the parallel program 21 a 1, the management of the control logic and the management of the monitoring logic and the fail-safe logic are complicated. The parallel program 21 a 1 is likely to cause an erroneous change if the logics are not managed appropriately by the plurality of cores 21 cand 21 d. However, since the automatic parallelization compiler 1 generates the parallel program 21 a 1 that simplifies logic management, it is possible to protect it from the erroneous change.Further, it is possible to prevent the processing loads of the multiple cores 21 cand 21 drequired for executing the non-control program 21 a 2 from being included in the processing loads of the multiple cores 21 cand 21 drequired for executing the parallel program 21 a 1. Therefore, the automatic parallelization compiler 1 can generate the parallel program 21 a 1 that is effective in suppressing an increase in processing loads required for the plurality of cores 21 cand 21 dto execute the control logics. In some cases, in manufacturing the parallel program directly related to a controller, the in-vehicle control device 20 and the multi-core processor including the parallel program 21 a 1 may be entrusted to other or different manufacturers. In such cases, the automatic parallelization compiler 1 can separate the synchronous monitoring processing and the synchronous fail-safe processing that are not directly related to the engine control or the like, as the non-control program 21 a 2, from the parallel program 21 a 1 that is directly related to the engine control or the like. The automatic parallelization compiler 1 is thus effective in that the production of the parallel program 21 a 1 and the like can be instructed without including the non-control program 21 a 2. The automatic parallelization compiler 1 is also effective in that the production of the parallel program 21 a 1 and the like can be instructed without including the processing load required for execution of the non-control program 21 a 2 in the processing load required for execution of the parallel program 21 a 1.Further, since the computer 10 generates the parallel program 21 a 1 and the non-control program 21 a 2 by executing the automatic parallelizing compiler 1, the computer 10 can generate the parallel program 21 a 1 as the automatic parallelizing compiler 1 generates it. The computer 10 thus provides similar advantages to the automatic parallelizing compiler 1.As described above, the in-vehicle control device 20 includes the multi-core processor 21 as well as the parallel program 21 a 1 and the non-control program 21 a 2 generated as described above. In the multi-core processor 21, each of the cores 21 cand 21 dexecutes the parallel program 21 a 1 and the non-control program 21 a 2. For this reason, even if the state flag changes from "1" to "0" by mistake, the in-vehicle control device 20 can execute the fail-safe processing. The in-vehicle control device 20 is more effective in facilitating the management of the logic and prevents an increase in the processing load when the plurality of cores 21 cand 21 dexecute the control logic, compared with a case where the non-control program 21 a 2 is included in the parallel program 21 a 1.In the present embodiment, the non-control program 21 a 2 is exemplified to be executed at the task activation processing time. The present invention is not limited to this embodiment, but may be realized in the automatic parallelization compiler 1 and the computer 10 in which the monitoring processing and the synchronous fail-safe processing are inserted into programs different from the parallel program 21 a 1 and executable by two cores 21 cand 21 d. The program for inserting the monitoring program and the synchronous fail-safe processing may be a program executable by two cores 21 cand 21 d, and having a higher priority than that of the parallel program 21 a 1.Further, in the present embodiment, the multi-core processor 21 including two cores 21 cand 21 dis used. For this reason, the present embodiment is exemplified to generate the program 21 a 3 executable by two cores 21 cand 21 dcorresponding to two cores 21 cand 21 d. The present invention can be implemented even in an embodiment in which three or more cores are provided. In this case, the program 21 a 3 is generated to correspond to three or more cores, that is, to be executed in parallel by three or more cores.The present invention is not limited to the above-described embodiment, but can be realized with various modifications as described below. Each of the following modifications may be realized singly or in combination.(Modification)A modification will be described below with reference to FIGS. 7 and 8. The present modification is different from the embodiment described above with reference to FIGS. 1 to 6 in that the automatic parallelization compiler 1 includes a procedure for inserting specified processing into the non-control program 21 a 2. Similarly, the present modification is different from the above-described embodiment in that the computer 10 includes an insertion part of the specified processing. The present modification is different from the above-described embodiment in that each of the cores 21 cand 21 dexecutes the synchronous monitoring processing and the synchronous fail-safe processing with respect to each state flag.A processing operation of the computer 10 according to the modification will be described first. The CPU 13 executes processing shown as a flowchart in FIG. 7 when, for example, a command for executing the insertion processing is output from the input device 16. The CPU 13 generates the program 21 a 3 including the parallel program 21 a 1 and the non-control program 21 a 2 from the single program by executing the automatic parallelization compiler 1. the CPU 13 executes the following steps S 11 to S 14 and S 131 in generating the parallel program 21 a 1 based on the procedure disclosed in JP 2015-001 807 A.The CPU 13 executes a specified processing in step S 131 following step S 13. The CPU 13 inserts the specified processing into the non-control program 21 a 2 (specified processing insertion procedure, specified processing insertion part). Upon detecting that the state flag is not set to "1", the CPU 13 inserts the specified processing, which specifies that the state setting processing has not set the state flag to "1", into the non-control program 21 a 2. In the synchronous fail-safe processing insertion procedure, the CPU 13 inserts the synchronous fail-safe processing executed with respect to each state flag specified by the specified processing into the non-control program 21 a 2. That is, the CPU 13 according to the modification individually checks the plurality of state flags as to whether the respective state flag is set to "1". The CPU 13 generates the non-control program 21a2 which indicates the execution of the synchronous fail-safe processing for each state flag which is not set to "1".Processing operations of the first core 21 cand the second core 21 dwill be described next with reference to FIG. 8. The first core 21 cand the second core 21 dexecute processing shown in a flowchart of FIG. 8 at each task activation of a predetermined time. The processing shown in FIG. 8 is different from that of FIG. 5 in that the synchronous fail-safe processing executed in S4 in FIG. 5 is modified into steps S31 to S42.Upon determination of YES (at least one state flag is "0") in step S 22, the first core 21 cand the second core 21 dexecute step S 31.In step S31, it is checked whether the first state flag A1 is set to "1" (specified processing). Upon determining that the first state flag A 1 is set to "1", the second core 21 ddetermines that the first processing block T 1 has been ended and executes step S 33.Upon determining that the first state flag A 1 is not set to "1", the second core 21 ddetermines that the first processing block T 1 has not been completed yet, and executes step S 32. That is, the second core 21 dspecifies that the state setting processing whose state has not been set to "1" yet is the first state setting processing F 1.Thus, the second core 21 dspecifies the processing block whose processing has not been completed yet. In this case, the second core 21 dspecifies that the processing of the first processing block T 1 has not been completed by the first core 21 c.The second core 21d executes the synchronous fail-safe processing corresponding to the first state flag A1 in step S32. The second core 21d executes the synchronous fail-safe processing corresponding to the first state flag A1, i.e., the synchronous fail-safe processing suitable for a case where the first processing block T1 has not been completed yet. The second core 21 dexecutes steps S 33 to S 36 in a similar manner by changing the state flag concerned.In step S37, it is checked whether the eighth state flag B8 is set to "1" (specified processing). Upon determining that the eighth state flag B 8 is set to "1", the first core 21 cdetermines that the eighth processing block T 8 has been completed and executes step S 39.Upon determining that the eighth state flag B 8 is not set to "1", the first core 21 cdetermines that the eighth processing block T 8 has not been completed yet, and executes step S 38. That is, the first core 21 cspecifies that the state setting processing whose state has not been set to "1" yet is the fifth state setting processing F 5.Thus, the first core 21 cspecifies the processing block whose processing has not been completed yet. In this case, the first core 21 cspecifies that the processing of the eighth processing block T 8 by the second core 21 dhas not been completed yet.The first core 21c executes the synchronous fail-safe processing corresponding to the eighth state flag B8 in step S38. The first core 21c executes the synchronous fail-safe processing corresponding to the eighth state flag B8, i.e., the synchronous fail-safe processing suitable for a case where the eighth processing block T8 has not been completed yet. The first core 21c similarly executes steps S39 to S42 by changing the state flag concerned.The automatic parallelization compiler 1, the computer 10, and the in-vehicle control device 20 according to the modification thus provide the same advantages as provided by the above-described embodiment. Further, the automatic parallelization compiler 1, the computer 10, and the in-vehicle control device 20 cause the first core 21 cand the second core 21 dto execute the synchronous fail-safe processing suitable for the processing block whose processing has not been completed yet. Further, the in-vehicle control device 20 executes the synchronous fail-safe processing suitable for the processing block whose processing has not been completed yet.

Claims

A parallelization method for automatically fail-safe parallelizing a control program executed by a single core processor and comprising a plurality of processing blocks (T1 to T5, T7 to T11) to generate a parallelized control program (21a1) from the plurality of processing blocks and a non-control program (21a2) which, when executed, monitors the parallelized control program (21a1) for a failure, wherein the plurality of processing blocks (T1 to T5, T7 to T11) are assigned to a plurality of cores (21c, 21d) of a multi-core processor (21), wherein a previous and a later processing block are assigned to each other by the processing of the later processing block depending on the previous processing of the earlier processing block, wherein the execution order of a later and assigned previous processing block is ensured in processing by the plurality of cores (21c, 21d) by inserting respective assigned storage processing procedures and wait processing procedures into the parallelized control program (21a1), wherein in a storage processing procedure executed immediately after completion of execution of the assigned previous processing block, a respective assigned completion state flag is changed to indicate completion of execution of the previous processing block; A wait processing procedure allowing execution of an associated later processing block only on condition that the completion state flag of the associated previous processing block indicates that the execution of the previous processing block is completed, wherein the non-control program (21a2) comprises a synchronous monitoring processing procedure monitoring whether all the completion state flags associated with the previous processing blocks respectively indicate that the execution of the respective previous processing blocks is completed and a synchronous fail-safe processing procedure executed when the synchronous monitoring processing procedure determines that not all the completion state flags indicate that the execution of the respective previous processing blocks is completed.A parallelization tool configured to perform the parallelization method according to claim 1.

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