SOI semiconductor structure and method for fabricating an SOI semiconductor structure

Abstract

SOI semiconductor structure (WF) encompassing - a first semiconductor disk (WF1) designed as a semiconductor layer (HLS) with a first front surface (VF1) and a first back surface (RF1), - a second semiconductor disk (WF2) designed as a substrate layer with a second front surface (VF2) and a second back surface (RF2), wherein an oxide layer is arranged on the first front surface (VF1) and / or the second front surface (VF2), - an insulating layer (OXS) produced by bonding the two semiconductor disks (WF1, WF2) via the first and second front surfaces (VF1, VF2) forming a joining surface (BF), wherein the first back surface (RF1) forms a front (VS) of the SOI semiconductor structure (WF) and the second back surface (RF2) forms a back (RS) of the SOI semiconductor structure (WF), - a buried lower surface (UF) formed between the insulating layer (OXS) and the semiconductor layer (HLS) of the first semiconductor disk (WF1), - a three-dimensional Hall sensor structure (HSENS) formed in the semiconductor layer (HLS) comprising a sensor area consisting of a monolithic semiconductor body (HLK) and an integrated circuit (IS), wherein the semiconductor body (HLK) is of a second conductivity type and extends from the buried bottom surface (UF) to the front surface (VS), - on the front surface (VS) at least three spaced-apart first metallic connection contacts (K11, K12, K13) and on the buried lower surface (UF) at least three spaced-apart second connection contacts (K21, K22, K23) wherein the respective second connection contacts (K21, K22, K23) comprise a highly doped polysilicon of a second conductivity type or metal, - highly doped semiconductor contact areas (HG11, HG12, HG13) of a second conductivity type for each first connection contact (K11, K12, K13), wherein the first connection contacts (K11, K12, K13) are each formed on a highly doped semiconductor contact area (HG11, HG12, HG13), and - highly doped semiconductor contact area (HG21, HG22, HG23) of a second conductivity type for each second connection contact (K21, K22, K23), which is formed under a highly doped semiconductor contact area (HG21, HG22, HG23), wherein - in a projection perpendicular to the front face (VS), at least the part of the first connection contacts (K11, K12, K13) formed on the highly doped semiconductor contact areas (HG11, HG12, HG13) is offset from at least the part of the second connection contacts (K21, K22, K23) formed on the highly doped semiconductor contact areas (HG21, HG22, HG23), and - the first connection contacts (K11, K12, K13) and the second connection contacts (K21, K22, K23) each have multiple rotational symmetry with respect to a symmetry axis perpendicular to the front (VS) and the bottom surface (UF) of the semiconductor body (HLK).

Description

[0001] The invention relates to an SOI semiconductor structure and a method for producing an SOI semiconductor structure.

[0002] From EP 2 806 283 B1, a semiconductor body with a sensor area is known, wherein a three-dimensional Hall sensor arrangement is formed in the sensor area. Another 3D Hall sensor is known from DE 10 2016 109 883 B4.

[0003] Further Hall sensor elements are known from US 2012 / 0 169 329 A1 and DE 10 2009 027 338 A1.

[0004] A CMOS-compatible photodetector is known from DE 60 2005 001 401 T2.

[0005] Against this background, the object of the invention is to provide a device that further develops the state of the art.

[0006] The problem is solved by an SOI semiconductor structure with the features of claim 1 and a method with the features of claim 11. Advantageous embodiments of the invention are the subject of dependent claims.

[0007] In a first object of the invention, an SOI semiconductor structure is provided with a second semiconductor disk formed as a substrate layer on a rear side and a semiconductor layer of a second conductivity type formed on a front side by a first semiconductor disk.

[0008] An insulating layer is arranged between the substrate layer and the semiconductor layer.

[0009] The semiconductor layer contains a three-dimensional Hall sensor structure with a sensor area consisting of a monolithic semiconductor body and an integrated circuit.

[0010] The semiconductor body extends from a buried lower surface to the front surface, with at least three spaced-apart first metallic terminal contacts on the front surface and at least three spaced-apart second metallic terminal contacts on the lower surface.

[0011] In a projection perpendicular to the front side, at least the part of the first connection contacts formed on the highly doped connection areas is offset from at least the part of the second connection contacts formed on the highly doped connection areas.

[0012] Each first terminal contact and each second terminal contact is at least partially formed on a first or second highly doped semiconductor contact area of ​​a second conductivity type.

[0013] The first and second connection contacts each exhibit multiple, in particular threefold, rotational symmetry with respect to a symmetry axis perpendicular to the front and lower surfaces of the semiconductor body.

[0014] It is understood that the first connection contacts are therefore offset from the second connection contacts, since the corresponding first highly doped semiconductor contact areas are offset from the corresponding second.

[0015] The underside of the semiconductor body is formed on the insulating layer.

[0016] It should be noted that the term SOI semiconductor structure refers to a structure produced by a semiconductor bonding process. In this process, a first semiconductor wafer with an oxide layer is bonded to a second semiconductor wafer. Preferably, both semiconductor wafers consist of the same semiconductor material, particularly silicon, to prevent stress caused by differing coefficients of thermal expansion during temperature changes.

[0017] It should be noted that the term "three-dimensional Hall sensor structure" refers to a Hall sensor which has a continuous extent in all three spatial directions within the semiconductor body and by means of the Hall sensor structure all three components of a magnetic field can be determined.

[0018] It is understood that the formation of the highly doped semiconductor contact areas is preferably carried out by means of an implantation step, whereby the dose is above 10E15 N / cm². 3 lies.

[0019] Furthermore, it is understood that the insulating intermediate layer consists entirely or predominantly of silicon dioxide.

[0020] One advantage of the device is that the SOI semiconductor structure allows for the integration of a three-dimensional Hall sensor, spatially formed in the semiconductor layer in three dimensions, together with an integrated circuit. In particular, the integrated circuit is electrically connected to the Hall sensor structure. This enables the cost-effective and reliable production of highly sensitive Hall sensors.

[0021] In a further development, the semiconductor body is electrically isolated from the rest of the semiconductor layer by means of a circumferential trench structure. It is understood that the trench structure, also referred to as a trench, is spaced apart from the first and second connection contacts. It is also understood that while the semiconductor body or sensor structure is electrically isolated from the rest of the semiconductor layer, the first and second connection contacts are preferably connected to the integrated circuit by means of conductive traces.

[0022] The depth of the trench structure extends to the insulating intermediate layer. Alternatively, the intermediate layer may comprise several insulating intermediate layers, for example, a combination of SiO2 and Si3N4 layers. Preferably, the trench structure has a continuous SiO2 layer around its entire side walls. A doped polysilicon layer is preferably formed between the side walls, the polysilicon being expediently connected to a reference potential.

[0023] Preferably, the semiconductor body or sensor area is hexagonal. In a further development, the semiconductor body has a different shape, e.g., a square shape or a polygon.

[0024] In a further development, the semiconductor body in the sensor area has a thickness of between 2 µm and 30 µm. Most preferably, the semiconductor body in the sensor area has a thickness of up to 100 µm. Preferably, the thickness of the semiconductor body is constant, at least within the sensor area. In particular, the surface on the front of the semiconductor body is almost completely or completely parallel and planar to the surface on the underside, at least in the area of ​​the sensor region. It should be noted that "almost completely" is understood to mean a value above 90%.

[0025] In one embodiment, the thickness-to-length ratio of the semiconductor body in the sensor area comprises a range between 0.6 and 1.4 or between 0.8 and 1.2. Preferably, the sensor area is isotropic, i.e., the thickness-to-length ratio is 1.0. Investigations have shown that this allows all three components of a magnetic field to be easily determined. In particular, the three components can be determined simultaneously.

[0026] In another training course, the second connection contacts each comprise a highly doped polysilicon of a second conductivity type.

[0027] In one embodiment, the second connection contacts are electrically connected from the front, and in an alternative embodiment, the second connection contacts are electrically connected from the back.

[0028] It is understood that during the measurements, one of the first connection contacts forms a contact pair with one of the second connection contacts, i.e., a current is either applied or a voltage is tapped at the two terminals of the contact pair.

[0029] In a further development, the semiconductor layer outside the sensor area has a smaller thickness than inside the sensor area, with the thickness of the semiconductor layer outside the sensor area being in a range between 0.1 µm and 10 µm or in a range between 0.5 µm and 2 µm.

[0030] Preferably, an integrated circuit is formed in the semiconductor layer outside the sensor area, wherein the integrated circuit is electrically connected to the Hall sensor structure. A small substrate thickness is particularly advantageous for the formation of an integrated circuit using CMOS transistors in order to reduce parasitic capacitances.

[0031] In another embodiment, the semiconductor layer outside the sensor area has regions of a first conductivity type. This is particularly desirable in the area of ​​the integrated circuit.

[0032] In further training, the first conductivity type is a p-type and the second conductivity type is an n-type or vice versa.

[0033] In a second document, a method for manufacturing an SOI semiconductor structure with a three-dimensionally designed Hall sensor structure is provided.

[0034] In a first process section, a multitude of process steps are carried out on a first semiconductor disk, having a semiconductor layer of a second conductivity type with a first front surface and a first back surface.

[0035] Through numerous process steps, at least three second highly doped semiconductor contact areas of the second conductivity type, each assigned to one of the second connection contacts, are produced on the first front surface by means of implantation.

[0036] In a second process section, the first front surface of the first semiconductor disk is joined to a second front surface of a second semiconductor disk designed as a substrate disk.

[0037] After joining, an insulating layer is formed between the first semiconductor disk and the second semiconductor disk.

[0038] By joining the two components, the first back surface of the first semiconductor disk becomes the front surface of the SOI semiconductor disk, and the second back surface of the second semiconductor disk becomes the back surface of the SOI semiconductor disk.

[0039] After joining, the first front surface of the first semiconductor wafer becomes a buried lower surface above the insulating layer.

[0040] In a third process section, the front side of the SOI semiconductor disk, and thus the semiconductor layer, is thinned.

[0041] Furthermore, in the third process section, the first highly doped semiconductor contact areas are created by implantation on the thinned front side of the SOI semiconductor disk, and the first connection contacts are formed on each of these first semiconductor contact areas.

[0042] In a further development step, a trench structure completely enclosing the sensor area is formed in a fourth process section on the front side. It is understood that the semiconductor body or sensor structure is electrically isolated from the rest of the semiconductor layer; however, the first and second connection contacts are preferably connected to the integrated circuit via conductor tracks.

[0043] In another advanced training course, during the first process section for connecting the highly doped semiconductor contact areas of the second conductivity type, contact areas are deposited and structured as doped polysilicon.

[0044] In one embodiment, the structured polysilicon is covered by a dielectric during the first process stage. Preferably, the dielectric comprises silicon dioxide and / or silicon nitride.

[0045] In a further training course, an oxide is formed as an insulating layer in the second process section.

[0046] In one embodiment, the semiconductor layer in the third process section is formed in two different thicknesses, with the sensor area having a greater thickness than the area surrounding the sensor area. Preferably, a masking process and a CMP process are carried out for this purpose. Alternatively, the thickness of the semiconductor layer is the same over the entire extent.

[0047] In another embodiment, in the third process section, a semiconductor layer with a thickness between 2 µm and 30 µm is formed in the sensor area using a CMP process. Most preferably, the semiconductor body in the sensor area has a thickness of up to 100 µm.

[0048] In a further training course, trench etching is carried out outside the sensor area in the third process section.

[0049] In another training course, the second buried connection contacts are connected from the front of the semiconductor layer in the third process section area and in the fourth process section area.

[0050] In one embodiment, the second connection contacts are connected from the back of the carrier substrate in the third process section area and / or in the fourth process section area.

[0051] In a further training course, the first connection contacts and the second connection contacts are electrically connected in a fifth process section.

[0052] The invention is explained in more detail below with reference to the drawings. Similar parts are labelled with identical designations. The illustrated embodiments are highly schematic; that is, the distances and the lateral and vertical extents are not to scale and, unless otherwise indicated, do not exhibit any derivable geometric relationships to one another. This shows Fig. 1. A cross-sectional view of a semi-finished product for the fabrication of an SOI semiconductor structure, Fig. 2 a cross-sectional view of a first embodiment of an SOI semiconductor structure with a sensor area, Fig. 3 A top view of the upper surface of the sensor area is shown in the Fig. 2, Fig. 4 A cross-sectional view of the SOI semiconductor structure showing two different thicknesses of a semiconductor region, Fig. 5 A cross-sectional view of the SOI semiconductor structure showing a connection of buried terminal contacts from the rear.

[0053] The illustration of Fig. Figure 1 shows a cross-sectional view of an SOI semiconductor structure WF. The SOI semiconductor structure WF comprises a first semiconductor wafer WF1 joined or bonded to a second semiconductor wafer WF2. Bonding the two semiconductor wafers WF1 and WF2 creates an insulating layer OXS made of silicon dioxide between them. Preferably, semiconductor wafers WF1 and WF2 are silicon wafers.

[0054] The first semiconductor disk WF1 has a semiconductor layer HLS of a second conductivity type with a first front surface VF1 and a first back surface RF1.

[0055] The second semiconductor disk WF2, with a second front surface VF2 and a second back surface RF2, comprises a substrate layer. The substrate layer is designed as a support layer.

[0056] The two front surfaces VF1 and VF2 of the two semiconductor wafers WF1 and WF2, preferably each covered with silicon dioxide, are joined together by a material-bonding and force-locking connection along a bonding surface BF, also called a bonding surface. The bonding surface BF extends within the insulating layer OXS, the insulating layer consisting essentially, i.e., more than 50%, of silicon dioxide.

[0057] Prior to the joining process, the first front surface VF1 forms a surface on the first semiconductor disk WF1, wherein, prior to the joining process, three highly doped second semiconductor contact areas HG21, HG22 and HG23 of a second conductivity type are created on the surface of the first semiconductor disk WF1 in a multitude of process steps, preferably by means of implantation.

[0058] Subsequently, a second terminal contact K21, K22 and K23 is formed on each of the second semiconductor contact areas HG21, HG22 and HG23. Preferably, the second terminal contacts K21, K22 and K23 are made of doped polysilicon or metal.

[0059] It should be noted that the second semiconductor contact area HG23 and the second connection contact K23 are shown in a subsequent top view for the sake of clarity.

[0060] In the illustration of the Fig. Figure 2 shows a cross-sectional view of a first embodiment of an SOI semiconductor structure with a sensor area. The following only highlights the differences compared to the figure of the Fig. 1 explained.

[0061] By joining, the first back surface RF1 of the first semiconductor disk WF1 becomes a front surface VS of the semiconductor layer HLS, wherein the semiconductor layer HLS of the first semiconductor disk WF1 is thinned from a thickness D of several hundred µm to a thickness D in the range between 2 µm and 30 µm preferably by a CMP process.

[0062] The second back surface RF2 of the second semiconductor disk WF2 becomes the back surface RS of the SOI semiconductor structure WF.

[0063] The semiconductor surface of the first front surface VF1 of the first semiconductor disk WF1 becomes, after joining, a buried lower surface above the insulating layer OXS.

[0064] After joining, highly doped first semiconductor contact areas HG11, HG12, HG13 are created by implantation in subsequent process steps and then first connection contacts K11, K12, K13 are formed on the first semiconductor contact areas HG11, HG12, HG13.

[0065] To form a sensor area for a three-dimensional Hall sensor structure HSENS, a semiconductor body HLK is electrically isolated from the remaining semiconductor layer HLS by means of a circumferential groove structure TR, wherein in the sensor area the ratio of the thickness D of the semiconductor layer HLS or of the semiconductor body HLK to a length L of the semiconductor body HLK comprises a range between 0.6 and 1.4 or a range between 0.8 and 1.2. Preferably, the ratio is 1. The lateral extent of the sensor area results from the length L of the semiconductor body HLK between two first connection contacts K11, K12 and K13.

[0066] In further process steps, the second connection contacts K21, K22 and K23 are electrically connected from the front side VS.

[0067] The semiconductor layer HLS outside the sensor area, i.e., the remaining semiconductor layer HLS, has the same thickness D as the layer within the sensor area. An integrated circuit (not shown) is formed within a region of this remaining semiconductor layer HLS. The integrated circuit is electrically connected to the terminals K11, K12, K13, K21, K22, and K23 via conductive traces (not shown).

[0068] One advantage is that by means of a monolithic design of the integrated circuit and the Hall sensor structure HSENS in the semiconductor layer HLS, a simple and cost-effective manufacturing process is achieved.

[0069] In the illustration of the Fig. Figure 3 is a top view of a front face VS of the sensor area shown in the Fig. 2 is shown. The following only highlights the differences from the illustration of the Fig. 2 explained.

[0070] The semiconductor body HLK, and thus the sensor area, is electrically insulated from the other areas of the semiconductor layer HLS by means of the circumferential trench structure TR, which is square in shape for clarity. Preferably, the semiconductor body HLK is hexagonal or polygonal in shape.

[0071] The second semiconductor contact areas HG21, HG22 and HG23 - shown with dashed lines - exhibit multiple, in particular threefold, symmetry with respect to a symmetry axis SA.

[0072] The first semiconductor contact areas HG11, HG12 and HG13 formed on the front side VS also exhibit multiple, in particular threefold, symmetry with respect to the symmetry axis SA.

[0073] The first semiconductor contact areas HG11, HG12 and HG13 on the front surface VS are offset from the second semiconductor contact areas HG21, HG22 and HG23 on the buried lower surface OS.

[0074] In the illustration of the Fig. Figure 4 shows a cross-sectional view of the SOI semiconductor structure WF in a version with two different thicknesses D of the semiconductor layer HLS. The following only highlights the differences compared to the figure of Fig. 2 explained.

[0075] The thickness of the semiconductor layer HLS outside the sensor area, i.e., in the remaining semiconductor layer HLS, is significantly less than the thickness of the semiconductor layer HLS within the sensor area. The thickness of the semiconductor body HLK decreases immediately outside the sensor area, so that the trench structure TR is already implemented in the region with a low thickness.

[0076] One advantage is that by creating a trench structure with a shallower depth, reliability is increased and manufacturing costs are reduced.

[0077] Within the remaining semiconductor layer HLS, which has a thickness of, for example, 0.5 µm, an integrated circuit IS with a large number of CMOS transistors is formed. Here, the individual transistors or other components, or groups of transistors or groups of components, can be arranged in distinct areas within the trench structure.

[0078] The integrated circuit IS is connected to the Hall sensor structure HSENS - not shown.

[0079] In the illustration of the Fig. Figure 5 shows a cross-sectional view of the SOI semiconductor structure WF with a connection of buried terminal contacts K21, K22, and K23 from the rear side RS. The following only highlights the differences from the figure of Fig. 4 explained.

[0080] Below the sensor structure, the back side RS is etched free down to the insulating layer OXS. Using a masking process, the second connection contacts K21, K22, and K23 – the latter not shown – are then contacted from the back side; that is, the second connection contacts K21, K22, and K23 are brought out in the etched area and can thus be easily connected electrically.

Claims

[1] SOI semiconductor structure (WF) comprising - a first semiconductor wafer (WF1) formed as a semiconductor layer (HLS) with a first front surface (VF1) and a first rear surface (RF1), - a second semiconductor wafer (WF2) formed as a substrate layer having a second front surface (VF2) and a second rear surface (RF2), wherein an oxide layer is arranged on the first front surface (VF1) and / or the second front surface (VF2), - an insulating layer (OXS) produced by bonding the two semiconductor wafers (WF1, WF2) via the first and second front surfaces (VF1, VF2) forming a joining surface (BF), wherein the first rear surface (RF1) forms a front side (VS) of the SOI semiconductor structure (WF) and the second rear surface (RF2) forms a rear side (RS) of the SOI semiconductor structure (WF), - a buried lower surface (UF) formed between the insulating layer (OXS) and the semiconductor layer (HLS) of the first semiconductor wafer (WF1), - a three-dimensional Hall sensor structure (HSENS) formed in the semiconductor layer (HLS) with a sensor region consisting of a monolithic semiconductor body (HLK) and an integrated circuit (IS), wherein the semiconductor body (HLK) is of a second conductivity type and extends from the buried lower surface (UF) to the front side (VS), - at least three first metallic connecting contacts (K11, K12, K13) spaced apart from one another are formed on the front side (VS) and at least three second connecting contacts (K21, K22, K23) spaced apart from one another are formed on the buried lower surface (UF), wherein the respective second connecting contacts (K21, K22, K23) comprise a highly doped polysilicon of a second conductivity type or metal, - highly doped semiconductor contact regions (HG11, HG12, HG13) of a second conductivity type for each first connection contact (K11, K12, K13), wherein the first connection contacts (K11, K12, K13) are each formed on a highly doped semiconductor contact region (HG11, HG12, HG13), and - highly doped semiconductor contact region (HG21, HG22, HG23) of a second conductivity type for a respective second connection contact (K21, K22, K23), which is formed in each case under a highly doped semiconductor contact region (HG21, HG22, HG23), wherein - in a projection perpendicular to the front side (VS), at least the part of the first connection contacts (K11, K12, K13) formed on the highly doped semiconductor contact regions (HG11, HG12, HG13) is offset from at least the part of the second connection contacts (K21, K22, K23) formed on the highly doped semiconductor contact regions (HG21, HG22, HG23), and - the first connection contacts (K11, K12, K13) and the second connection contacts (K21, K22, K23) each have a multiple rotational symmetry with respect to an axis of symmetry perpendicular to the front side (VS) and to the lower surface (UF) of the semiconductor body (HLK). [2] SOI semiconductor structure (WF) according to claim 1, according to which the semiconductor body (HLK) is electrically insulated from the remaining semiconductor layer (HLS) by means of a circumferential trench structure (TR). [3] SOI semiconductor structure (WF) according to claim 1 or claim 2, wherein the semiconductor body (HLK) has a thickness of between 2 µm and 30 µm. [4] SOI semiconductor structure (WF) according to one of claims 1 to 3, according to which the ratio of thickness (D) to length (L) of the semiconductor body (HLK) comprises a range between 0.6 to 1.4 or a range between 0.8 to 1.2, wherein the thickness (D) denotes the distance between the buried lower surface (UF) and the front side (VS) and the length (L) denotes the lateral distance between the first connection contacts (K11, K12, K13). [5] SOI semiconductor structure (WF) according to one of claims 1 to 4, according to which the second connection contacts (K21, K22, K23) are electrically connected from the front side (VS) of the SOI semiconductor structure (WF). [6] SOI semiconductor structure (WF) according to one of claims 1 to 4, according to which the second connection contacts (K21, K22, K23) are electrically connected from the rear side (RS) of the SOI semiconductor structure (WF). [7] SOI semiconductor structure (WF) according to one of claims 1 to 6, according to which the semiconductor layer (HLS) outside the monolithic semiconductor body (HLK) has a smaller thickness (D) than the monolithic semiconductor body (HLK), wherein the thickness (D) of the semiconductor layer (HLS) outside the monolithic semiconductor body (HLK) is in a range between 0.1 µm and 10 µm, preferably in a range between 0.5 µm and 2 µm. [8] SOI semiconductor structure (WF) according to one of claims 1 to 7, according to which the integrated circuit (IS) is electrically connected to the first and second connection contacts (K11, K12, K13, K21, K22, K23) by means of conductor tracks. [9] SOI semiconductor structure (WF) according to one of claims 1 to 8, according to which the semiconductor layer (HLS) outside the monolithic semiconductor body (HLK) has regions of a first conductivity type. [10] SOI semiconductor structure (WF) according to one of claims 1 to 9, wherein a first conductivity type is p and the second conductivity type is n or vice versa. [11] Method for producing an SOI semiconductor structure (WF) with a three-dimensional Hall sensor structure (HSENS) according to one of claims 1 to 10, and with the following method steps: - in a first process section, in a first semiconductor wafer (WF1) comprising a semiconductor layer (HLS) with a first front surface (VF1) and a first rear surface (RF1) and of a second conductivity type, at least three second highly doped semiconductor contact regions (HG21, HG22, HG23) of the second conductivity type, each associated with one of the second connection contacts (K21, K22, K23), are produced by implantation in a plurality of process steps on the first front surface (VF1), - in a second process section, the first front surface (VF1) and / or the second front surface (VF2) is formed with an oxide layer, the first front surface (VF1) of the first semiconductor wafer (WF1) is joined to a second front surface (VF2) of a second semiconductor wafer (WF2) formed as a substrate layer in such a way that the first rear surface (RF1) of the first semiconductor wafer (WF1) becomes a front surface (VS) of the SOI semiconductor wafer (WF) and the second rear surface (RF2) of the second semiconductor wafer (WF2) becomes the rear surface (RS) of the SOI semiconductor wafer (WF), and after joining, on the one hand, an insulating layer (OXS) is formed between the first semiconductor wafer (WF1) and the second semiconductor wafer (WF2), and on the other hand, the first front surface (VF1) between the semiconductor layer (HLS) of the first semiconductor wafer (WF1) and the insulating layer (OXS) becomes a buried lower surface (UF), - in a third process section, a front side (VS) of the SOI semiconductor structure (WF) is thinned and highly doped first semiconductor contact regions (HG11, HG12, HG13) are produced by implantation and first connection contacts (K11, K12, K31) are formed on the first semiconductor contact regions (HG11, HG12, HG13), and - in a fourth process section region on the front side (VS), a trench structure is formed which completely encloses a monolithic semiconductor body (HLK) formed by the semiconductor layer (HLS) as a sensor region to form the three-dimensional Hall sensor structure (HSENS). [12] Method for producing an SOI semiconductor structure (WF) with a three-dimensional Hall sensor structure (HSENS) according to claim 11, in which a doped polysilicon is deposited and structured during the first process section region for connecting the highly doped second semiconductor contact regions (HG21, HG22, HG23) contact regions (K21, K22, K23). [13] Method for producing an SOI semiconductor structure (WF) with a three-dimensional Hall sensor structure (HSENS) according to claim 12, in which the structured polysilicon is covered by means of a dielectric during the first process section region. [14] Method for producing an SOI semiconductor structure (WF) with a three-dimensional Hall sensor structure (HSENS) according to one of claims 11 to 13, in which an oxide is formed as an insulating layer (OXS) in the second process section region. [15] Method for producing an SOI semiconductor structure (WF) with a three-dimensional Hall sensor structure (HSENS) according to one of claims 11 to 14, in which in the third process section region the semiconductor layer (HLS) is formed in the region of the semiconductor body (HLK) with a greater thickness (D) than the thickness (D) of the region of the semiconductor layer (HLS) surrounding the semiconductor body (HLK). [16] Method for producing an SOI semiconductor structure (WF) with a three-dimensional Hall sensor structure (HSENS) according to one of claims 11 to 14, in which the semiconductor layer (HLS) is formed with a thickness (D) between 2 µm and 30 µm, preferably less than 100 µm, in the third process section region by means of a CMP process. [17] Method for producing an SOI semiconductor structure (WF) with a three-dimensional Hall sensor structure (HSENS) according to one of claims 11 to 14 or 16, in which the semiconductor layer (HLS) is formed with a uniform thickness (D) in the third process section region. [18] Method for producing an SOI semiconductor structure (WF) with a three-dimensional Hall sensor structure (HSENS) according to one of claims 11 to 17, in which in a further process section the second connection contacts (K21, K22, K23) are connected from the front side (VS) of the SOI semiconductor structure (WF). [19] Method for producing an SOI semiconductor structure (WF) with a three-dimensional Hall sensor structure (HSENS) according to one of claims 11 to 17, in which in a further process section the second connection contacts (K21, K22, K23) are connected from the rear side (RS) of the SOI semiconductor structure (WF). [20] Method for producing an SOI semiconductor structure (WF) with a three-dimensional Hall sensor structure (HSENS) according to one of claims 11 to 19, in which in a fifth process section the first connection contacts (K11, K12, K13) and the second connection contacts (K21, K22, K23) are electrically connected to the integrated circuit (IS).

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