Thin film transistor, gate driver comprising the same, and display device comprising the gate driver

Abstract

Thin film transistor, comprising: a first oxide semiconductor layer (131) comprising indium (In), gallium (Ga), zinc (Zn), tin (Sn) and oxygen (O); and a second oxide semiconductor layer (132) comprising indium (In), gallium (Ga), zinc (Zn) and oxygen (O), where a content ratio, hereinafter referred to as Ga / In, of Ga to In in the second oxide semiconductor layer (132) is higher than the content ratio Ga / In of Ga to In in the first oxide semiconductor layer (131), and a content ratio, hereinafter referred to as Zn / In, of Zn to In in the second oxide semiconductor layer (132) is higher than the content ratio Zn / In of Zn to In in the first oxide semiconductor layer (131), wherein in the first oxide semiconductor layer (131) a content ratio, hereinafter referred to as In / Sn, of In to Sn satisfies 2.5 ≤ In / Sn ≤ 5, a content ratio, hereinafter referred to as Ga / Sn, of Ga to Sn satisfies 1 ≤ Ga / Sn ≤ 2, and a content ratio, hereinafter referred to as Zn / Sn, of Zn to Sn satisfies 2.5 ≤ Zn / Sn ≤ 5, and wherein a content of Sn of the second oxide semiconductor layer (132) is lower than a content of Sn of the first oxide semiconductor layer (131) or the second oxide semiconductor layer (132) does not contain Sn, wherein a Zn content of the second oxide semiconductor layer (132) is higher than a Zn content of the first oxide semiconductor layer (131), and wherein in the second oxide semiconductor layer (132) the content ratio of Ga to In 2 ≤ Ga / In ≤ 4, and the content ratio of Zn to In 2 ≤ Zn / In ≤ 8.

Description

BACKGROUNDField of the InventionThe present disclosure relates to a thin film transistor (TFT), a gate driver including the same, and a display device including the gate driver.Discussion of the Prior ArtUS 2013 / 0 161 608 A1 describes a semiconductor device including an oxide layer; a first oxide semiconductor layer formed over the oxide layer; a second oxide semiconductor layer formed over the first oxide semiconductor layer; a gate insulating layer formed over the second oxide semiconductor layer; and a gate electrode that is in contact with the gate insulating layer and formed in a region overlapping with the second oxide semiconductor layer. In an example, the second oxide semiconductor layer is an In-Sn-Ga-Zn-based oxide, and may have an atomic ratio of In:Ga:Zn=3:1:2 or 2:1:3. In an example, the first oxide semiconductor layer is an In-Ga-Zn-based oxide having an atomic ratio of In:Ga:Zn=1:1:1 or 1:3:2.JP 2010-118 407 A describes a thin film transistor including an oxide sintered body made of an oxide semiconductor in which the atomic ratio of each element of an indium element (In), a gallium element (Ga), a zinc element (Zn), and a tin element (Sn) relative to the whole (In+Ga+Zn+Sn) satisfies the following relations: 0.18<In / (In+Ga+Zn+Sn)<0.79; 0.00010<Ga / (In+Ga+Zn+Sn)<0.27; 0.060< Zn / (In+Ga+Zn+Sn)<0.49; and 0.12<Sn / (In+Ga+Zn+Sn)<0.40. According to an example, an atomic ratio of each element satisfies the following relations: 0.18<In / (In+Ga+ Zn+Sn)<0.62; 0.0001<Ga / (In+Ga+ Zn+Sn)<0.27; 0.090< Zn / (In+Ga+ Zn+Sn)<0.49; 0.12<Sn / (In+Ga+ Zn+Sn)<0.40.US 2011 / 0 140 100 A discloses a thin film transistor having an oxide semiconductor layer disposed between a source electrode and a drain electrode.US 2014 / 0 239 298 A1 describes a semiconductor device manufactured by imparting stable electrical characteristics to a transistor using an oxide semiconductor layer for a channel.As the information-oriented society advances, demands for display devices for displaying an image are increasing. Consequently, various display devices such as liquid crystal display (LCD) devices, plasma display panel (PDP) devices, and emissive display devices have been recently used. Examples of light emitting display devices include organic light emitting display devices using an organic light emitting diode (OLED) as a light emitting element and light emitting diode display devices using a light emitting photodiode as a light emitting element.Flat panel display devices each include a display panel, a gate driver, a data driver, and a timing controller. The display panel includes a plurality of data lines, a plurality of gate lines, and a plurality of pixels each provided in a plurality of regions defined by intersections of the data lines and the gate lines. When a gate signal is supplied to a gate line using a TFT as a switching element, a data voltage is supplied to each of the pixels via a data line. Each of the pixels emits light having a certain brightness with the data voltage.Recently, flat panel display devices for displaying an image having a high resolution corresponding to an ultra high resolution (UHD) have been brought out, and flat panel display devices for displaying an image having a high resolution corresponding to an 8K UHD have been developed. The UHD denotes a resolution of 3840×160 and the 8K UHD denotes a resolution of 7680×4320.Flat panel display devices having high resolution such as the UHD or the 8K UHD require high-speed driving, and thus a one-line scan time, which is a time for which the gate signal is supplied to a gate line, is shortened. The one-line scanning time corresponds to a data voltage supply period of each pixel. Therefore, when the one-line scanning time is shortened, a desired data voltage is not charged in each pixel, resulting in deterioration of the image quality. In order to solve such a problem, a TFT having high electron mobility should be used as the switching element.In a case where a TFT having an oxide-based semiconductor layer is used as a switching element, manufacturing cost is reduced, and electron mobility is low compared to a case where a TFT having a polysilicon-based semiconductor layer is used as a switching element. Therefore, high-resolution flat panel display devices requiring high-speed driving require the TFT having the oxide-based semiconductor layer.However, the oxide-based semiconductor layer of the TFT applied to the high resolution flat panel display devices requiring high speed driving should be implemented as a short channel due to pixels per inch (PPI) as well as high electron mobility. In the related art, a TFT based on a semiconductor layer including indium gallium zinc oxide (IGZO) is used, and due to this, it is difficult to ensure high electron mobility. Also, when the semiconductor layer including IGZO is used as a single layer, a threshold voltage is rapidly shifted due to a channel length change of a channel. For this reason, it is difficult to implement a short channel in a state of maintaining a desired threshold voltage value.FIG. 1 is a graph showing a drain-source current with respect to a gate-source voltage when a channel length varies in a TFT having an IGZO-based semiconductor layer.FIG. 1 shows an experiment result obtained by measuring a drain-source current with respect to a gate-source voltage under a condition where a channel length of a TFT having an IGZO-based semiconductor layer that is a single layer is changed to 4 μm to 10. As shown in FIG. 1, it can be seen that in a case where the channel length is shortened to 4 μm or less, the threshold voltage is shifted negatively by about -5 V, compared to a case where the channel length is 5 μm to 10 μm. Accordingly, when the channel length is shortened to 4 μm or less, it is difficult to secure a desired driving characteristicWhen power, pressure, and temperature of a manufacturing device are set to a certain range in a process of depositing the IGZO-based semiconductor layer, which is a single layer, a problem in which a threshold voltage is shifted negatively in a short channel as in FIG. 1 is solved. In this case, however, a degree of freedom considered for other factors such as film uniformity is considerably reduced due to conditions such as the performance, pressure and temperature of the manufacturing apparatus.Therefore, high-resolution flat panel display devices requiring high-speed driving require a TFT having an oxide semiconductor layer without limiting the degree of freedom of a manufacturing device.SUMMARYAccordingly, the present disclosure is directed to providing a TFT, a gate driver including the same, and a display device including the gate driver, which substantially avoid one or more problems caused by limitations and disadvantages of the related art.An aspect of the present disclosure is directed to providing a TFT including an oxide semiconductor layer that can be deposited on high-resolution flat panel display devices requiring high-speed driving, a gate driver including the TFT, and a display device including the gate driver.The invention is set out in claim 1. Advantageous embodiments are specified in the dependent claims. Additional advantages and features of the disclosure will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following, or may be learned by practice of the disclosure. The objects and other advantages of the disclosure may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.To achieve these and other advantages, and in accordance with the purpose of the disclosure, as embodied and broadly described herein, a thin film transistor (TFT) is provided that includes a first oxide semiconductor layer including indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O), and a second oxide semiconductor layer including indium (In), gallium (Ga), zinc (Zn), and oxygen (O). The first and / or second oxide semiconductor layers may include IGZTO. A content ratio (Ga / In) of gallium (Ga) to indium (In) of the second oxide semiconductor layer is higher than a content ratio (Ga / In) of Ga to In the first oxide semiconductor layer, and a content ratio (Zn / In) of zinc (Zn) to In the second oxide semiconductor layer is higher than a content ratio (Zn / In) of Zn to In the first oxide semiconductor layer. A content ratio (Zn / In) of Zn to In the second oxide semiconductor layer may be less than 5. A thickness of the second oxide semiconductor layer may be thicker than one third of a thickness of the first oxide semiconductor layer and thinner than five thirds of the thickness of the first oxide semiconductor layer. A gate electrode of the TFT may be disposed closer to the first oxide semiconductor layer than the second oxide semiconductor layer. The first oxide semiconductor layer may overlap the gate electrode with a gate insulating layer interposed therebetween. An inclination angle of a side surface of the first oxide semiconductor layer may be an acute angle. An inclination angle of a side surface of the second oxide semiconductor layer may be 90 degrees or an acute angle. The angles may be formed by controlling the temperature of the first substrate such that the etch rate of the second semiconductor layer is higher than that of the first semiconductor layer. The first oxide semiconductor layer may be a main channel layer. The second oxide semiconductor layer may be a Vth shift prevention layer.The gate electrode may be disposed below the first oxide semiconductor layer. The second oxide semiconductor layer may be disposed on the first oxide semiconductor layer. A source electrode of the TFT contacting a side of the first oxide semiconductor layer and a side of the second oxide semiconductor layer may be provided. A drain electrode of the TFT contacting another side of the first oxide semiconductor layer and another side of the second oxide semiconductor layer may be provided. A length of the first oxide semiconductor layer in a direction in which the source electrode and the drain electrode are separated from each other may be longer than a length of the second oxide semiconductor layer in the direction in which the source electrode and the drain electrode are separated from each other.The gate electrode may be disposed on the first oxide semiconductor layer. The second oxide semiconductor layer may be disposed below the first oxide semiconductor layer. A source electrode of the TFT contacting one side of the first oxide semiconductor layer through a first contact hole passing through an interlayer insulating layer covering the first and second semiconductor layers and the gate electrode may be provided. A drain electrode of the TFT contacting another side of the first oxide semiconductor layer through a second contact hole passing through the interlayer insulating layer may be provided. The source electrode may contact one side of the second oxide semiconductor layer through the first contact hole additionally passing through the first oxide semiconductor layer. The drain electrode may contact another side of the second oxide semiconductor layer through the second contact hole additionally passing through the first oxide semiconductor layer.A content of Ga of the second oxide semiconductor layer may be higher than a content of Ga of the first oxide semiconductor layer. A content of Zn of the second oxide semiconductor layer may be higher than a content of Zn of the first oxide semiconductor layer. A content of In the second oxide semiconductor layer may be lower than a content of In the first oxide semiconductor layer. In the second oxide semiconductor layer, a content ratio of Ga to In may satisfy 2≤Ga / In≤4. A content ratio of Zn to In may satisfy 2≤ Zn / In≤8.The second oxide semiconductor layer may further include tin (Sn). A content ratio (In / Sn) of In to Sn of the second oxide semiconductor layer may be equal to or higher than a content ratio (In / Sn) of In to Sn of the first oxide semiconductor layer. A content of Sn of the second oxide semiconductor layer may be lower than a content of Sn of the first oxide semiconductor layer. In the first oxide semiconductor layer, a content ratio of In to Sn may satisfy 2.5≤In / Sn≤5. A content ratio of Ga to Sn may satisfy 1≤Ga / Sn≤2. A content ratio of Zn to Sn may satisfy 2.5≤ Zn / Sn≤5. In the second oxide semiconductor layer, a content ratio of Sn to In satisfies 0.1≤Sn / In≤0.5.In another aspect of the present disclosure, a gate driver is provided that includes multiple stages for outputting gate signals. The plurality of stages each include a TFT according to an embodiment of the present disclosure.In another aspect of the present disclosure, there is provided a display device including a display panel including a plurality of data lines, a plurality of gate lines, and a plurality of pixels each provided in a plurality of regions defined by intersections of the plurality of data lines and the plurality of gate lines. The plurality of pixels each include a TFT according to an embodiment of the present disclosure, and / or the display device includes a gate driver for outputting gate signals to the plurality of gate lines, the gate driver including a plurality of stages each including a TFT according to an embodiment of the present disclosure.It is to be understood that both the foregoing general description and the following detailed description of the present disclosure are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed.BRIEF DESCRIPTION OF THE DRAWINGSThe accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the disclosure and together with the description serve to explain the principle of the disclosure. In the drawings: FIG. 1 is a graph showing a drain-source current with respect to a gate-source voltage when a channel length varies in a TFT having an IGZO-based semiconductor layer; FIG. 2 is a perspective view illustrating a display device according to an embodiment of the present disclosure; FIG. 3 is a plan view illustrating a first substrate, a gate driver, a source driver integrated circuit (IC), a flexible film, a circuit board, and a timing controller illustrated in FIG. 2 ; FIG. 4 is a circuit diagram illustrating a pixel of FIG. 3 ; FIG. 5 is a circuit diagram illustrating a portion of the gate driver of FIG. 3 ; FIG. 6 is a plan view illustrating a TFT according to an embodiment of the present disclosure; FIG. 7 is a cross-sectional view illustrating an example taken along line I-I' of FIG. 6; FIG. 8 is an exemplary diagram for describing an oxide semiconductor layer of a TFT according to an embodiment of the present disclosure; FIG. 9 is a graph showing a drain-source current with respect to a gate-source voltage when a channel length varies, in a TFT according to an embodiment of the present disclosure; FIG. 10 is a graph showing a variation of an etching rate with respect to a variation of each of a gallium (Ga) content and a zinc (Zn) content of a second oxide semiconductor layer;FIGS. 11A and 11B are enlarged cross-sectional views illustrating embodiments of a region A of FIG. 7 ; FIG. 12 is a graph showing an etching rate of each of a first oxide semiconductor layer and a second oxide semiconductor layer with respect to a temperature of a first substrate in a process of depositing the first oxide semiconductor layer and the second oxide semiconductor layer; FIG. 13 shows images of cross-sectional areas of a first oxide semiconductor layer and a second oxide semiconductor layer with respect to a temperature of a first substrate in a process of depositing the first oxide semiconductor layer and the second oxide semiconductor layer;FIGS. 14A to 14C show material characteristic analysis images of a second oxide semiconductor layer with respect to variation of a Zn content; FIG. 15 is a graph showing a PBTS threshold voltage shift value and a NBTIS threshold voltage shift value of a TFT with respect to a thickness variation of a second oxide semiconductor layer when a thickness of a first oxide semiconductor layer is 300 Å; FIG. 16 is a flowchart illustrating a method of manufacturing a TFT according to an embodiment of the present disclosure;FIGS. 17A to 17E are cross-sectional views for describing a method of manufacturing a TFT according to an embodiment of the present disclosure; FIG. 18 is a plan view illustrating a TFT according to another embodiment of the present disclosure; FIG. 19 is a cross-sectional view illustrating an example taken along line II-II' of FIG. 8; FIG. 20 is a plan view illustrating a TFT according to another embodiment of the present disclosure; FIG. 21 is a cross-sectional view illustrating an example taken along line III-III' of FIG. 20 ; and FIG. 22 is a cross-sectional view illustrating another example taken along line III-III' of FIG. 20.DETAILED DESCRIPTION OF THE DISCLOSUREReference will now be made in detail to the exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.In the description, like reference numerals refer to like elements. When it is determined in the following description that the detailed description of the relevant known function or configuration unnecessarily obscures the important point of the present disclosure, the detailed description will be omitted. A name of each of the elements used herein is selected in consideration of the convenience of description of the specification, and may be different from a name of an actual product.Advantages and features of the present disclosure and implementation methods thereof will be made apparent by the following embodiments described with reference to the accompanying drawings. However, the present disclosure may be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Further, the present disclosure is defined only by the scopes of the claims.A shape, a size, a ratio, an angle, and a number disclosed in the drawings to describe embodiments of the present disclosure are merely an example, and thus the present disclosure is not limited to the illustrated details. Like reference numerals refer to like elements throughout. In the following description, when it is determined that the detailed description of the relevant known function or configuration unnecessarily obscures the important point of the present disclosure, the detailed description is omitted.In constructing an element, the element is designed to have an error range, although there is no explicit description.Features of various embodiments of the present disclosure may be partially or wholly interconnected or combined with each other and may cooperate and be technically controlled in various ways as those skilled in the art can sufficiently understand. The embodiments of the present disclosure may be carried out independently of each other or may be carried out together in a co-dependent relationship.Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.An example in which a display device according to an embodiment of the present disclosure is a light emitting display device will be described below, but embodiments of the present disclosure are not limited thereto. The display device according to an embodiment of the present disclosure may be implemented as a liquid crystal display (LCD) device, a light emitting display device, a field emission display device, and an electrophoresis display device. Examples of the light emitting display device include organic light emitting display devices using an organic light emitting diode (OLED) as a light emitting element and light emitting diode display devices using a micro light emitting diode as a light emitting element.FIG. 2 is a perspective view illustrating a display device according to an embodiment of the present disclosure. FIG. 3 is a plan view illustrating a first substrate, a gate driver, a source driver integrated circuit (IC), a flexible film, a circuit board, and a timing controller illustrated in FIG. 2.Referring to FIGS. 2 and 3, an organic light emitting display device 1000 according to an embodiment of the present disclosure may include a display panel 1100, a gate driver 1200, a data driver, a flexible film 1400, a circuit board 1500, and a timing controller 1600.The display panel 1100 may include a first substrate 1110 and a second substrate 1120. The first substrate 1110 and the second substrate 1120 may each be plastic, glass, or the like. For example, when the first substrate 1110 is plastic, the first substrate 1110 may be formed of polyimide, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polycarbonate (PC), and / or the like. When the first substrate 1110 is formed of resin, the organic light emitting display device 1000 may be implemented as a flexible display device that may be bent or curved. The second substrate 1120 may be one of glass, a plastic film, and an encapsulation film.The first substrate 1110 may be a TFT substrate on which a plurality of TFTs are provided. A plurality of gate lines, a plurality of data lines, and a plurality of pixels P may be provided on a surface of the first substrate 1110 facing the second substrate 1120. The pixels P may be respectively provided in a plurality of regions defined by an intersection structure of the gate lines and the data lines. The display panel 1100 may be divided into a display area DA where the pixels P are provided to display an image and a non-display area NDA that does not display an image, as in FIG. 3. The gate lines, the data lines, and the pixels P may be provided in the display region DA. The gate driver 1200, a plurality of pads, and a plurality of connection lines connecting the data lines to the pads may be provided in the non-display area NDA.Each of the pixels P may include, as a switching element, at least one transistor that is turned on by a gate signal of a corresponding gate line and transmits a data voltage of a corresponding data line to an element of a corresponding pixel. The transistor may be a TFT.For example, as in FIG. 4, each of the pixels P may include an organic light emitting diode OLED, a driving transistor DT, a plurality of switching transistors ST 1 and ST 2, and a capacitor Cst. The plurality of switching transistors ST 1 and ST 2 may include first and second switching transistors ST 1 and ST 2. In FIG. 4, for convenience of description, only one pixel P including a j-th (where j is an integer equal to or greater than two) data line Dj, a q-th (where q is an integer equal to or greater than two) reference voltage line Rq, a k-th (where k is an integer equal to or greater than two) gate line Gk, and a k-th initialization line SEk is illustrated.The organic light emitting diode OLED may emit light with a current supplied through the driving transistor DT. An anode electrode of the organic light emitting diode OLED may be connected to a source electrode of the driving transistor DT, and a cathode electrode may be connected to a first source voltage line VSSL through which a first source voltage is supplied. The first source voltage line VSSL may be a low-level voltage line through which a low-level source voltage is supplied.The organic light emitting diode OLED may include an anode electrode, a hole transport layer, an organic light emitting layer, an electron transport layer, and a cathode electrode. In the organic light emitting diode OLED, when a voltage is applied to the anode electrode and the cathode electrode, a hole and an electron may move to the organic light emitting layer through the hole transport layer and the electron transport layer, respectively, and may be combined in the organic light emitting layer to emit light.The driver transistor DT may be arranged between the organic light emitting diode OLED and a second source voltage line VDDL, via which a second source voltage is supplied. The driving transistor DT may control a current flowing from the second source voltage line VDDL to the organic light emitting diode OLED based on a voltage difference between the source electrode and a gate electrode thereof. The gate electrode of the driving transistor DT may be connected to a first electrode of the first switching transistor ST 1, the drain electrode may be connected to the second source voltage line VDDL, and a source electrode may be connected to the anode electrode of the organic light emitting diode OLED. The second source voltage line VDDL may be a high-level voltage line through which a high-level source voltage is supplied.The first switching transistor ST 1 may be turned on by a k-th gate signal of the k-th gate line Gk, and may supply a data voltage of the j-th data line Dj to the gate electrode of the driving transistor DT. A gate electrode of the first switching transistor ST 1 may be connected to the k-th gate line Gk, a source electrode may be connected to the gate electrode of the driving transistor DT, and a drain electrode may be connected to the j-th data line Dj.The second switching transistor ST 2 may be turned on by a k-th initialization signal of the k-th initialization line SEk, and may connect the q-th reference voltage line Rq to the source electrode of the driving transistor DT. A gate electrode of the second switching transistor ST 2 may be connected to the k-th initialization line SEk, a first electrode may be connected to the q-th reference voltage line Rq, and a second electrode may be connected to the source electrode of the driving transistor DT.The capacitor Cst may be provided between the gate electrode and the source electrode of the driving transistor DT. The capacitor Cst may store a differential voltage between a gate voltage and a source voltage of the driving transistor DT.One electrode of the capacitor Cst may be connected to the gate electrode of the driving transistor DT and the source electrode of the first switching transistor ST 1, and the other electrode may be connected to the source electrode of the driving transistor DT, the drain electrode of the second switching transistor ST 2, and the anode electrode of the organic light emitting diode OLED.In FIG. 4, the driving transistor DT, the first switching transistor ST 1, and the second switching transistor ST 2 of each of the pixels P may be a TFT, respectively. Also, in FIG. 4, an example is illustrated in which the driving transistor DT, the first switching transistor ST 1, and the second switching transistor ST 2 of each of the pixels P are each implemented as an N-type semiconductor transistor having an N-type semiconductor characteristic, but embodiments of the present disclosure are not limited thereto. In other embodiments, the driving transistor DT, the first switching transistor ST 1, and the second switching transistor ST 2 of each of the pixels P are each implemented as a P-type semiconductor transistor having a P-type semiconductor characteristic.The gate driver 1200 may supply gate signals to the gate lines according to a gate drive signal input from the timing controller 1600. The gate driver 1200 may be provided as a gate driver in panel (GIP) type in the non-display area NDA outside one side or both sides of the display area DA of the display panel 1100. In this case, the gate driver 1200 may include a plurality of transistors to output the gate signals to the gate lines according to the gate driving signal. Here, each of the plurality of transistors may be a TFT.For example, as in FIG. 5, the gate driver 1200 may include a plurality of stages STT 1 that are dependently connected to each other, and the stages STT 1 may sequentially output the gate signals to the gate lines.The stages STT 1 may include, as in FIG. 3, a pull-up node NQ, a pull-down node NQB, a pull-up transistor TU that is turned on when the pull-up node NQ is charged with a gate high voltage, a pull-down transistor TD that is turned on when the pull-down node NQB is charged with the gate high voltage, and a node controller NC for controlling charging or discharging of the pull-up node NQ and the pull-down node NQB.The node controller NC may be connected to a start signal line through which a start signal or a transmission signal of a front end stage is input and a clock line through which one of the gate clock signals is input. The node controller NC may control the charging or discharging of the pull-up node NQ and the pull-down node NQB according to the start signal or the transmission signal of the front-end stage input via the start signal line and a gate clock signal input through the clock line. In order to stably control an output of the stage STT 1 when the pull-up node NQ is charged with the gate high voltage, the node controller NC may discharge the pull-down node NQB to a gate low voltage, and when the pull-up node NQB is charged with the gate high voltage, the node controller NC may discharge the pull-up node NQ to the gate low voltage. For this purpose, the node controller NC may include a plurality of transistors.When the stage STT 1 is pulled up ("pulled up"), namely, when the pull-up node NQ is charged with the gate high voltage, the pull-up transistor TU may be turned on and may output a gate clock signal of a clock line CL to an output terminal OT. When the stage STT 1 is pulled down ("pulled down"), namely, when the pull-down node NQB is charged with the gate high voltage, the pull-down transistor TD may be turned on and may discharge the output terminal OT to a gate low voltage of a gate low voltage terminal VLT.In FIG. 5, the pull-up transistor TU, the pull-down transistor TD, and the plurality of transistors of the node controller NC of each of the stages STT 1 included in the gate driver 1200 may be each implemented as a TFT. Also illustrated in FIG. 5 is an example in which the pull-up transistor TU, the pull-down transistor TD, and the plurality of transistors of the node controllers NC of each of the stages STT 1 included in the gate driver 1200 are each implemented as an N-type semiconductor transistor having the N-type semiconductor characteristic, but embodiments of the present disclosure. In other embodiments, the pull-up transistor TU, the pull-down transistor TD, and the plurality of transistors of the node controllers NC of each of the stages STT 1 included in the gate driver 1200 are each implemented as a P-type semiconductor transistor having the P-type semiconductor characteristic.The gate driver 1200 may be implemented as a driver chip such as an integrated circuit (IC). In this case, the gate driver 1200 may be mounted on a gate flexible film according to a chip-on-film (COF) type, and the gate flexible film may be mounted on the first substrate 1110 of the display panel 1100.The data driver may include at least one source driver IC 1300. The source driver IC 1300 may receive digital video data and a source driver signal from the timing controller 1600. The source driver IC 1300 may convert the digital video data into analog data voltages according to the source driver signal, and may supply the data voltages to the data lines, respectively.In a case where the source driver IC 1300 is implemented as a driver chip such as an IC, the source driver IC 1300 may be mounted on the flexible film 1400 as in FIGS. 1 and 2. A plurality of lines connecting the pads to the source driver IC 1300 and a plurality of lines connecting the pads to lines of the circuit board 1500 may be provided on the flexible film 1400. The flexible film 1400 may be mounted on the pads, such as data pads provided in the non-display area NDA of the display panel 110 using an anisotropic conductive film, and thus the pads may be connected to the lines of the flexible film 1400. Alternatively, the source driver IC 1300 may be directly attached to pads of the first substrate 1110 of the display panel 1100 according to a chip-on-glass (COG) type or a chip-on-plastic (COP) type.The flexible film 1400 may be provided in multiple, and the circuit board 1500 may be attached to the flexible films 1400. A plurality of circuits each implemented as driver chips may be mounted on the circuit board 1500. The timing controller 1600 may be mounted on the circuit board 1500. The circuit board 1500 may be a printed circuit board (PCB) or a flexible circuit board (FPCB).The timing controller 1600 may receive the digital video data and a timing signal from an external system board via a cable of the circuit board 1500. The timing controller 1600 may generate the gate drive signal for controlling an operation timing of the gate driver 1200 and the source drive signal for controlling the source driver IC 1300 provided in multiple based on the timing signal. The timing controller 1600 may provide the gate drive signal to the gate driver 1200 and may provide the source drive signal to the source driver ICs 1300.As described above, in the display device according to an embodiment of the present disclosure, each of the pixels P may include at least one TFT as a switching element, and in a case where the gate driver 1200 is implemented as the GIP, the gate driver 1200 may include a plurality of transistors to sequentially output the gate signals to the gate lines. Therefore, in display devices that require high-speed driving due to high resolution, electron mobility of each of the plurality of transistors included in the gate driver 1200 should increase in order for the gate driver 1200 to stably output the gate signals.Hereinafter, a TFT including an oxide semiconductor layer that can be applied to the transistors of the gate driver 1200 and the transistors of the pixels P of the display device that requires high-speed driving due to high resolution will be described in detail according to an embodiment of the present disclosure.FIG. 6 is a plan view illustrating a TFT 100 according to an embodiment of the present disclosure. FIG. 7 is a cross-sectional view illustrating an example taken along the line I-I' of FIG. 6.FIGS. 6 and 7 illustrate an example in which a TFT according to an embodiment of the present disclosure is implemented in an inverted staggered structure using a channel etch-back (BCE) process. The inverted staggered structure may include a lower gate structure, wherein a gate electrode is provided under an active layer.Referring to FIGS. 6 and 7, the TFT 100 according to an embodiment of the present disclosure may include a gate electrode 110, an oxide semiconductor layer 130, a source electrode 140, and a drain electrode 150.The TFT 100 may be provided on a first substrate 1110. The first substrate 1110 may be formed of plastic, glass, and / or the like.A buffer layer 300 may be provided on the first substrate 1110 to protect the TFT 100 from water penetrating through the first substrate 1110. The buffer layer 300 may include a plurality of inorganic layers that are alternately stacked. For example, the buffer layer 300 may be formed of a multilayer in which one or more inorganic layers of silicon oxide (SiOx), silicon nitride (SiNx), and SiON are alternately stacked. The buffer layer 300 may be omitted.The gate electrode 110 may be provided on the buffer layer 300. The gate electrode 110 may be provided to have an area wider than that of the oxide semiconductor layer 130 to block light incident on the oxide semiconductor layer 130 from the first substrate 1110, and thus the gate electrode 110 may cover the oxide semiconductor layer 130. Therefore, the oxide semiconductor layer 130 can be protected from the light incident from the first substrate 1110. The gate electrode 110 may be formed of a single layer or a multilayer including one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.A gate insulation layer 120 may be provided on the gate electrode 110. The gate insulating layer 120 may be formed of an inorganic layer, and may be formed of, for example, SiOx, SiNx, or a multilayer thereof.The oxide semiconductor layer 130 may be provided on the gate insulating layer 120. The oxide semiconductor layer 130 may be disposed to overlap the gate electrode 110 with the gate insulating layer 120 therebetween.The oxide semiconductor layer 130 may include a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132. The second oxide semiconductor layer 132 may have a lower conductivity than the first oxide semiconductor layer 131, and may have a larger band gap than the first oxide semiconductor layer 131. The first oxide semiconductor layer 131 may be a main channel layer through which an electron moves, and thus may be disposed near the gate electrode 110. Therefore, the first oxide semiconductor layer 131 may be defined as a layer disposed closer to the gate electrode 110 than the second oxide semiconductor layer 132, and the second oxide semiconductor layer 132 may be defined as a layer farther from the gate electrode 110 than the first oxide semiconductor layer 131. For example, in a case where the TFT 100 is implemented in the inverted staggered structure, as in FIGS. 6 and 7, since the gate electrode 110 is disposed below the oxide semiconductor layer 130, the first oxide semiconductor layer 131 may be disposed on the gate insulating layer 120, and the second oxide semiconductor layer 132 may be disposed on the first oxide semiconductor layer 131.The source electrode 140 may directly contact a side of the second oxide semiconductor layer 132 and a side of the first oxide semiconductor layer 131 that is the main channel layer. Specifically, the source electrode 140 may directly contact a side surface of the first oxide semiconductor layer 131 and a side surface and a part of a top surface of the second oxide semiconductor layer 132. Also, the drain electrode 150 may directly contact the other side of the first oxide semiconductor layer 131 and the other side of the second oxide semiconductor layer 132. Specifically, the drain electrode 150 may directly contact the other side surface of the first oxide semiconductor layer 131 and the other side surface and a part of the upper surface of the second oxide semiconductor layer 132. The source electrode 140 and the drain electrode 150 may each be formed of a single layer or a multilayer including one of Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu, or an alloy thereof.A passivation layer 160 may be provided on the oxide semiconductor layer 130, the source electrode 140, and the drain electrode 150. The passivation layer 160 may be formed of an inorganic layer, and may be formed of, for example, SiOx, SiNx, or a multilayer thereof.The first oxide semiconductor layer 131 may be made of indium gallium zinc tin oxide (IGZTO) in place of indium gallium zinc oxide (IGZO) to increase electron mobility. More specifically, an electron mobility of the first oxide semiconductor layer 131 may be set to 15 cm 2 / V·s or more, and in order to satisfy a bias temperature stress (PBTS) characteristic and a bias temperature illumination stress (NBTIS) characteristic, an indium gallium zinc tin (IGZT) content should satisfy the following conditions. In the first oxide semiconductor layer 131, a content ratio of indium (In) to tin (Sn) may be 2.5≤In / Sn≤5, a content ratio of gallium (Ga) to Sn may be 1≤Ga / Sn≤2, and a content ratio of zinc (Zn) to Sn may be 2.5≤ Zn / Sn≤5. A condition that satisfies the PBTS characteristic and the NBTIS characteristic may represent a case where a threshold voltage shift value is within a range of -5 V to 2 V. Here, a content of each element is represented as atomic percent.However, when the oxide semiconductor layer 130 is formed of a single IGZTO-based layer, a threshold voltage may be shifted based on a variation of a channel length, and due to this, it is difficult to implement a short channel in a state of maintaining a desired threshold voltage value. That is, when the oxide semiconductor layer 130 is formed of a single layer based on IGZTO, it is difficult to implement a short channel and ensure a desired driving characteristic due to an influence of a channel length variation (CLV). The CLV may indicate a degree by which a threshold voltage is shifted based on a variation in channel length.Therefore, in order to prevent a threshold voltage from being shifted in a case where the oxide semiconductor layer 130 is implemented as a short channel, the oxide semiconductor layer 130 may further include the second oxide semiconductor layer 132 including indium gallium zinc oxide (IGZO). For example, the second oxide semiconductor layer 132 may be made of IGZO or IGZTO. In a case where the second oxide semiconductor layer 132 is formed of IGZTO, a composition ratio of IGZT of the second oxide semiconductor layer 132 may be different from that of IGZT of the first oxide semiconductor layer 131.In a case where the oxide semiconductor layer 130 includes the first oxide semiconductor layer 131 including IGZTO and the second oxide semiconductor layer 133 including IGZO or IGZTO at a composition ratio different from that of the first oxide semiconductor layer 131, the oxide semiconductor layer 130 may have a heterojunction structure as in FIG. 8. Here, a depletion region caused by a built-in potential is formed in a transition portion between the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 due to a Fermi energy level difference between thin layers, and the built-in potential causes band bending in the transition portion. The oxide semiconductor layer 130 can control a total charge density because it has the depletion region, thereby preventing a threshold voltage from being shifted based on a channel length. That is, in an embodiment of the present disclosure, since the second oxide semiconductor layer 132 is provided, an increase in charge density in the oxide semiconductor layer 130 formed of a highly mobile thin layer is effectively controlled, thereby preventing a shift in threshold voltage based on a variation in channel length of the oxide semiconductor layer 130. As a result, in an embodiment of the present disclosure, electron mobility increases, and moreover, a device characteristic of a TFT is ensured.Moreover, a bonding force between Sn and oxygen is stronger than a bonding force between In and oxygen. Therefore, in a case where the second oxide semiconductor layer 132 is formed of IGZTO, chemical resistance increases, and moreover, oxygen vacancies are reduced compared to a case where the second oxide semiconductor layer 132 is formed of IGZO. Therefore, the PBTS characteristic and the NBTIS characteristic of the TFT including the second oxide semiconductor layer 132 formed of IGZTO are improved, and the reliability of the TFT is improved.FIG. 9 is a graph showing a drain-source current with respect to a gate-source voltage when a channel length varies, in a TFT according to an embodiment of the present disclosure. FIG. 9 shows an experiment result obtained by measuring a drain-source current with respect to a gate-source voltage while changing a channel length to 4 μm to 10 μm in the TFT including the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132. For example, the experiment result of FIG. 9 can be obtained by performing an experiment under a condition in which a drain-source voltage Vds was set to 10 V, a composition ratio of IGZT of the first oxide semiconductor layer 131 was set to 4:1:4:1, and a composition ratio of IGZT of the second oxide semiconductor layer 132 was set to 4:12:16:1. That is, in FIG. 9, an example in which the second oxide semiconductor layer 132 is formed of IGZTO is shown.Referring to FIG. 9, it can be seen that in the TFT according to an embodiment of the present disclosure, a threshold voltage is hardly shifted with respect to variation of a channel length. That is, in the TFT according to an embodiment of the present disclosure, a short channel is implemented and a desired threshold voltage is maintained, thereby ensuring a desired device characteristic of the TFT.Moreover, as in FIG. 9, when a channel of the oxide semiconductor layer 130 has a width of 4 μm and a length of 4 μm, the electron mobility may be about 23 cm 2 / V×s. The electron mobility has a high numerical value, as compared with a case where, with the same channel width and channel length, an electron mobility of a TFT including an IGZO-based semiconductor layer is about 10 cm 2 / V·s as in FIG. 1.Moreover, the second oxide semiconductor layer 132 cannot function as a channel, but may cover and protect the first oxide semiconductor layer 131 in order for the first oxide semiconductor layer 131 to function as a channel stably. For this purpose, a content ratio (Ga / Sn) of Ga to Sn of the second oxide semiconductor layer 132 may be higher than a content ratio (Ga / Sn) of Ga to Sn of the first oxide semiconductor layer 131. The second oxide semiconductor layer 132 may be formed of IGZO, and may not include Sn. In this case, the second oxide semiconductor layer 132 may have a lower conductivity than the first oxide semiconductor layer 131 and have a larger band gap than the first oxide semiconductor layer 131.FIG. 10 is a graph showing an etching rate with respect to a variation of each of a Ga content and a Zn content of a second oxide semiconductor layer.FIG. 10 shows a result obtained by measuring an etching rate under the same condition while sequentially changing a composition ratio of IGZT of the second oxide semiconductor layer 132 to 4:1:4:1, 4:4:4:1, 4:8:4:1, 4:12:4:1, 4:8:1, 4:8:12:1, and 4:12:16:1. As in FIG. 10, when only a content of Ga in the second oxide semiconductor layer 132 increases, an etching rate of the second oxide semiconductor layer 132 is decreased. For this reason, a time required for etching the second oxide semiconductor layer 132 increases.As in FIG. 10, as a Zn content in the second oxide semiconductor layer 132 increases, an etching rate of the second oxide semiconductor layer 132 increases. Therefore, in order to prevent an etching rate of the second oxide semiconductor layer 132 from increasing, a content of Zn should increase along with a content of Ga. Therefore, a content ratio (Ga / In) of Ga to In the second oxide semiconductor layer 132 may be higher than a content ratio (Ga / In) of Ga to In the first oxide semiconductor layer 131. Also, a content ratio (Zn / In) of Zn to In the second oxide semiconductor layer 132 may be higher than a content ratio (Zn / In) of Zn to In the first oxide semiconductor layer 131.In order to check a device characteristic with respect to a content variation of each of Ga and Zn of the second oxide semiconductor layer 132, a composition ratio of IGZT of the first oxide semiconductor layer 131 was set to 4:1:4:1 as in Table 1, and a CLV and electron mobility were measured while varying a content of each of Ga and Zn of the second oxide semiconductor layer 132. In Table 1, the CLV denotes a difference between a threshold voltage when a channel length is 4 μm and a threshold voltage when a channel length is 12 μm. When the CLV is small, it means that variation of a threshold voltage with respect to variation of a channel length is small. Table 1] Table 1]Second Oxide Semiconductor Layer (In:Ga:Zn:Sn)4:4:4:14:8:4:14:12:4:14:8:8:14:8:12:14:12:16:1CLV (L=12-4 μm)1.340.540.340.370.380.21Mobility (L=4 μm)33.321.923.620.525.220.7Referring to Table 1, as a content of Ga of the second oxide semiconductor layer 132 increases, a CLV value is decreased. Also, when a content of Ga and a content of Zn increase to adjust an etching rate, the CLV value is decreased, and an electron mobility of 20 cm 2 / V×s is ensured.However, when a content of Zn in the second oxide semiconductor layer 132 continuously increases, the PBTS characteristic and the NBTIS characteristic of the TFT 100 are deteriorated, and a Zn content should be designed in consideration of the deterioration. A condition that satisfies the PBTS characteristic and the NBTIS characteristic may represent a case where a threshold voltage shift value is within a range of -5 V to 2 V. This will be described in detail below with reference to Figs. 14A to 14C.As described above, since the second oxide semiconductor layer 132 is formed of IGZO or IGZTO at a composition ratio different from that of the first oxide semiconductor layer 131, a threshold voltage is prevented from being shifted even when the oxide semiconductor layer 130 is implemented as a short channel, the second oxide semiconductor layer 132 covers and protects the first oxide semiconductor layer 131 to stably function as a channel, and an etching rate of the second oxide semiconductor layer 132 is increased. In this case, when the second oxide semiconductor layer 132 is formed of IGZTO, a composition ratio of IGZT of the second oxide semiconductor layer 132 should satisfy the following conditions. In the second oxide semiconductor layer 132, a content ratio of Sn to In may be 0.1≤Sn / In≤0.5, a content ratio of Ga to In may be 2≤Ga / In≤4, and a content ratio of Zn to In may be 2≤ Zn / In≤8. Further, when the second oxide semiconductor layer 132 is formed of IGZO, a composition ratio of IGZ of the second oxide semiconductor layer 132 should satisfy the following conditions. In the second oxide semiconductor layer 132, a content ratio of Ga to In may be 2≤Ga / In≤4, and a content ratio of Zn to In may be 2≤ Zn / In≤8. Here, a content of each element is represented as atomic percent.In addition, a content ratio of In to Sn of the second oxide semiconductor layer 132 may be substantially equal to or higher than a content ratio of In to Sn of the first oxide semiconductor layer 131. Also, a content ratio of Ga to Sn of the second oxide semiconductor layer 132 may be higher than a content ratio of Ga to Sn of the first oxide semiconductor layer 131. Also, a content ratio of Zn to Sn of the second oxide semiconductor layer 132 may be higher than a content ratio of Zn to Sn of the first oxide semiconductor layer 131.In addition, a content of In the second oxide semiconductor layer 132 may be lower than a content of In the first oxide semiconductor layer 131. Also, a content of Ga of the second oxide semiconductor layer 132 may be higher than a content of Zn of the second oxide semiconductor layer 132. Also, a content of Ga of the second oxide semiconductor layer 132 may be higher than a content of Zn of the first oxide semiconductor layer 131. Also, a content of Sn of the second oxide semiconductor layer 132 may be lower than a content of Sn of the first oxide semiconductor layer 131.FIGS. 11A and 11B are enlarged cross-sectional views illustrating embodiments of a region A of FIG. 7.Referring to FIGS. 11A and 11B, an inclination of each of the side surfaces of the first oxide semiconductor layer 131 may be formed at a first angle "θ 1" that is an acute angle. An inclination of each of the side surfaces of the second oxide semiconductor layer 132 may be formed at a second angle "θ 2" that is a right angle as in FIG. 11A, or may be formed at a third angle "θ 3" that is an acute angle as in FIG. 11B.Specifically, the oxide semiconductor layer 130 may include the first oxide semiconductor layer 131 including IGZTO and the second oxide semiconductor layer 132 including IGZO or IGZTO at a composition ratio different from that of the first oxide semiconductor layer 131. Therefore, as in FIG. 12, an etching rate of the first oxide semiconductor layer 131 and an etching rate of the second oxide semiconductor layer 132 vary differently with respect to a temperature of the first substrate 1110 in a process of depositing the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132. In FIG. 12, the etching rate of the first oxide semiconductor layer 131 and the etching rate of the second oxide semiconductor layer 132 with respect to the temperature of the first substrate 1110 in the process of depositing the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 are shown in a state in which a composition ratio of IGZT of the first oxide semiconductor layer 131 is 4:1:4:1 and a composition ratio of IGZT of the second oxide semiconductor layer 132 is 4:12:16:1.As in FIG. 12, when the temperature of the first substrate 1110 is lower than 200° C. in the process of depositing the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132, the etching rate (Å / s) of the first oxide semiconductor layer 131 is higher than that of the second oxide semiconductor layer 132. In a case where the first oxide semiconductor layer 131 is disposed below the second oxide semiconductor layer 132 as in FIG. 7, when the etching rate of the first oxide semiconductor layer 131 is higher than that of the second oxide semiconductor layer 132, the inclination of each of the side surfaces of the second oxide semiconductor layer 132 may be formed at an obtuse angle at a room temperature of 100° C. and 150° C. of FIG. 13. In this case, even when the source electrode 140 and the drain electrode 150 are provided to cover the side surfaces of the first oxide semiconductor layer 131 and the side surfaces of the second oxide semiconductor layer 132, a void may be formed in a boundary between the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132. Therefore, an etchant for etching the source electrode 140 and the drain electrode 150 may enter the void, and the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 may be additionally etched by the etchant entering the void. For this reason, the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 may be formed to have an undesirable channel length or channel width.However, as in FIG. 12, when the temperature of the first substrate 1110 is equal to or higher than 200° C., in the process of depositing the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132, the etching rate (Å / s) of the first oxide semiconductor layer 131 is substantially equal to or less than that of the second oxide semiconductor layer 132. In this case, the inclination of each of the side surfaces of the second oxide semiconductor layer 132 may be formed at an acute angle or a right angle as at 200 C and 250 C of FIG. 13. In this case, even when the source electrode 140 and the drain electrode 150 are provided to cover the side surfaces of the first oxide semiconductor layer 131 and the side surfaces of the second oxide semiconductor layer 132, a void is not formed in the boundary between the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132. Therefore, the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 are prevented from being additionally etched by an etchant penetrating into the void. Accordingly, the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 are formed to have a desired channel length or channel width.FIGS. 14A to 14C show material characteristic analysis images of the second oxide semiconductor layer with respect to variation of a Zn content.In FIGS. 14A to 14C, an example in which the second oxide semiconductor layer 132 is formed of IGZTO is shown. In this case, FIG. 14A shows a material characteristic analysis image of the second oxide semiconductor layer 132 when a composition ratio of IGZT of the second oxide semiconductor layer 132 is 4:12:12:1. FIG. 14B shows a material characteristic analysis image of the second oxide semiconductor layer 132 when a composition ratio of IGZT of the second oxide semiconductor layer 132 is 4:12:16:1. FIG. 14C shows a material characteristic analysis image of the second oxide semiconductor layer 132 when a composition ratio of IGZT of the second oxide semiconductor layer 132 is 4:12:20:1. Each of the material characteristic analysis images shown in Figs. 14A to 14C has a pattern of transmission electron microscope fast Fourier transform (TEM-FFT).As in FIG. 14A, when a composition ratio of IGZT of the second oxide semiconductor layer 132 is 4:12:12:1, only a crystal axis (a dotted line) in one direction is shown at a material characteristic analysis measurement point of the second oxide semiconductor layer 132. Also in FIG. 14B, when a composition ratio of IGZT of the second oxide semiconductor layer 132 is 4:12:16:1, only a crystal axis (a dotted line) in one direction is shown at a material characteristic analysis measurement point of the second oxide semiconductor layer 132. In FIG. 14C, when a composition ratio of IGZT of the second oxide semiconductor layer 132 is 4:12:20:1, crystal axes (dotted lines) in three directions are shown at a material characteristic analysis measurement point of the second oxide semiconductor layer 132.In a case where the crystal axes (dotted lines) in the three directions are shown in the second oxide semiconductor layer 132 as in FIG. 14C, the case where structural phase segregation occurs in a material characteristic analysis measurement point of the second oxide semiconductor layer 132 is illustrated. That is, the case where deformation occurs in the second oxide semiconductor layer 132 at the stoichiometry is illustrated, and in this case, the PBTS characteristic and NBTIS characteristic of the TFT 100 may be deteriorated. Therefore, a content ratio (Zn / In) of Zn to In the second oxide semiconductor layer 132 may be lower than 5.Moreover, the first oxide semiconductor layer 131 may be provided such that only a crystal axis in one direction is shown at a material characteristic analysis measurement point, as in the second oxide semiconductor layer 132 shown in FIG. 14A. In this case, a crystal axis shown in the first oxide semiconductor layer 131 may be parallel to a crystal axis shown in the second oxide semiconductor layer 132.FIG. 15 is a graph showing a PBTS threshold voltage shift value and a NBTIS threshold voltage shift value of a TFT with respect to a thickness variation of the second oxide semiconductor layer when a thickness of the first oxide semiconductor layer is 300 Å.FIG. 15 shows a PBTS threshold voltage shift value "PBTSΔVth" and a NBTIS threshold voltage shift value "NBTISΔVth" of the TFT 100 when a thickness of the first oxide semiconductor layer 131 is set to 300 Å and a thickness of the second oxide semiconductor layer 132 is changed to 100 Å, 200 Å, 300 Å, 400 Å and 500 Å. Also, FIG. 15 shows a PBTS threshold voltage shift value "PBTSΔVth" and a NBTIS threshold voltage shift value "NBTISΔVth" of the TFT 100 when the first oxide semiconductor layer 131 is formed of IGZTO, the second oxide semiconductor layer 132 is formed of IGZTO, a composition ratio of IGZT of the first oxide semiconductor layer 131 is 4:1:4:1, and a composition ratio of IGZT of the second oxide semiconductor layer 132 is 4:12:16:1.The first oxide semiconductor layer 131 may be formed to have a thickness of 100 Å or more based on thin film deposition uniformity and electron mobility characteristics, and based on a process time, the first oxide semiconductor layer 131 may be formed to have a thickness of 1,000 Å or less. Therefore, a thickness of the first oxide semiconductor layer 131 may be previously set to 100 Å to 1000 Å based on a shift of a threshold voltage and an oxygen or hydrogen concentration of an upper or lower insulation layer contacting the first oxide semiconductor layer 131. In FIG. 15, an experiment was performed under a condition where the thickness of the first oxide semiconductor layer 131 is 300 Å.Referring to FIG. 15, a BTS threshold voltage shift value "BTSΔVth" may be in a range of -5 V to 2 V based on a positive shift of a threshold voltage of the TFT 100 provided in the display device. The BTS threshold voltage shift value "BTSΔVth" includes a PBTS threshold voltage shift value "PBTSΔVth" and a NBTIS threshold voltage shift value "NBTISΔVth".As in FIG. 15, when a thickness of the second oxide semiconductor layer 132 is 100 Å, the BTS threshold voltage shift value "BTSΔVth" of the TFT 100 is outside a range of -5 V to 2 V. Even when a thickness of the second oxide semiconductor layer 132 is 500 Å, the BTS threshold voltage shift value "BTSΔVth" of the TFT 100 is outside a range of -5 V to 2 V. On the other hand, when a thickness of the second oxide semiconductor layer 132 is 200 Å, 300 Å, or 400 Å, the BTS threshold voltage shift value "BTSΔVth" of the TFT 100 is within a range of -5 V to 2 V.Therefore, based on the BTS threshold voltage shift value "BTSΔVth" of the TFT 100, when a thickness of the first oxide semiconductor layer 131 is 300 Å, a thickness of the second oxide semiconductor layer 132 may be 200 Å, 300 Å, or 400 Å. That is, the thickness of the second oxide semiconductor layer 132 may be thicker than one third (1 / 3) of the thickness of the first oxide semiconductor layer 131 and thinner than five thirds (5 / 3) of the thickness of the first oxide semiconductor layer 131.FIG. 16 is a flowchart illustrating a method of manufacturing a TFT according to an embodiment of the present disclosure. FIGS. 17A to 17E are cross-sectional views for describing a method of manufacturing a TFT according to an embodiment of the present disclosure.Hereinafter, a method of manufacturing a TFT according to an embodiment of the present disclosure will be described in detail with reference to FIGS. 16 and 17A to 17E.First, as in FIG. 17A, a gate electrode 110 may be formed on a first substrate 1110, and a gate insulation layer 120 may be formed on the gate electrode 110. (S 101 in FIG. 16 )Specifically, a first metal layer may be formed on the first substrate 1110 by a sputtering process. Subsequently, a photoresist pattern may be formed on the first metal layer, and then, by patterning the first metal layer through a mask process for etching the first metal layer, the gate electrode 110 may be formed. The gate electrode 110 may be formed of a single layer or a multilayer including one of Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu, or an alloy thereof.Alternatively, a buffer layer 300 may be formed on the first substrate 1110 to protect a TFT 100 from water entering through the first substrate 1110, and the gate electrode 110 may be formed on the buffer layer 300. In this case, the buffer layer 300 may include a plurality of inorganic layers that are alternately stacked. For example, the buffer layer 300 may be formed of a multilayer in which one or more inorganic layers of SiOx, SiNx, and SiON are alternately stacked. The buffer layer 300 may be formed by a plasma enhanced chemical vapor deposition (PECVD) process.Subsequently, the gate insulation layer 120 may be formed on the gate electrode 110. The gate insulating layer 120 may be formed of an inorganic layer, and may be formed of, for example, SiOx, SiNx, or a multilayer thereof. The gate insulation layer 120 may be formed by a PECVD process.Second, as in FIG. 17B, a first semiconductor material layer 131' and a second semiconductor material layer 132' may be formed on the gate insulating layer 120, and a photoresist pattern 133 may be formed on the second semiconductor layer 132'. (S 102 of FIG. 16 )Specifically, the first semiconductor material layer 131' may be formed on the gate insulation layer 120. The first semiconductor material layer 131' may be formed of IGZTO to increase electron mobility.Subsequently, the second semiconductor material layer 132' may be formed on the first semiconductor material layer 131'. The second semiconductor material layer 132' may include IGZO to prevent a threshold voltage from being rapidly shifted due to a variation in channel length. The second semiconductor material layer 132' may be formed of IGZO or IGZTO. When the second semiconductor material layer 132' is formed of IGZTO, the second semiconductor material layer 132' may have a composition ratio different from that of the first semiconductor material layer 131'. The first semiconductor material layer 131' and the second semiconductor material layer 132' may be continuously deposited in the same facility. Also, the first semiconductor material layer 131' and the second semiconductor material layer 132' may be deposited in a state where a temperature of the first substrate 1110 is maintained at 200° C. or more.Subsequently, a photoresist pattern 133 may be formed on the second semiconductor material layer 132'.Third, as in FIG. 17C, a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132 may be formed by etching the first semiconductor material layer 131' and the second semiconductor material layer 132' simultaneously, and the photoresist pattern 133 may be removed. (S 103 of FIG. 16 )Specifically, as described above with reference to FIGS. 12 and 13, in a case where the first semiconductor material layer 131' and the second semiconductor material layer 132' are etched in a state where a temperature of the first substrate 1110 is lower than 200° C. in a process of depositing the first semiconductor material layer 131' and the second semiconductor material layer 132', since an etching rate of the first semiconductor material layer 131' is higher than that of the second semiconductor material layer 132', a slope of a side surface of the second oxide semiconductor layer 132 can be formed at an obtuse angle. In this case, even if a source electrode 140 and a drain electrode 150 are provided to cover a side surface of the first oxide semiconductor layer 131 and the side surface of the second oxide semiconductor layer 132, a void may be formed in a boundary between the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132. Therefore, an etchant for etching the source electrode 140 and the drain electrode 150 may enter the void, and the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 may be additionally etched by the etchant entering the void. For this reason, the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 may be formed to have an undesirable channel length or channel width.However, as in FIG. 12, in a case where the first semiconductor material layer 131' and the second semiconductor material layer 132' are etched under a condition where the temperature of the first substrate 1110 is maintained at 200° C. or more in a process of depositing the first semiconductor material layer 131' and the second semiconductor material layer 132', since an etching rate of the first semiconductor material layer 131' is equal to or less than that of the second semiconductor material layer 132', the inclination of the side surface of the second oxide semiconductor layer 132 can be formed at an acute angle. In this case, even when the source electrode 140 and the drain electrode 150 are provided to cover the side surface of the first oxide semiconductor layer 131 and the side surface of the second oxide semiconductor layer 132, no void is formed in the boundary between the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132. Therefore, the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 are prevented from being additionally etched by an etchant penetrating into the void. Accordingly, the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 are formed to have a desired channel length or channel width.The first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 may be formed by simultaneously etching the first semiconductor material layer 131' and the second semiconductor material layer 132' with an etchant such as oxalic acid that may simultaneously etch the first semiconductor material layer 131 and the second semiconductor material layer 132'. Thereafter, the photoresist pattern 133 may be removed by a stripping process.Fourth, as in FIG. 17D, the source electrode 140 and the drain electrode 150 may be formed. (S 104 of FIG. 16 )The source electrode 140 may directly contact a side of the second oxide semiconductor layer 132 and a side of the first oxide semiconductor layer 131 that is a main channel layer. Specifically, the source electrode 140 may directly contact a side surface of the first oxide semiconductor layer 131 and a side surface and a part of a top surface of the second oxide semiconductor layer 132. Also, the drain electrode 150 may directly contact the other side of the first oxide semiconductor layer 131 and the other side of the second oxide semiconductor layer 132. Specifically, the drain electrode 150 may directly contact the other side surface of the first oxide semiconductor layer 131 and the other side surface and a part of the upper surface of the second oxide semiconductor layer 132. The source electrode 140 and the drain electrode 150 may each be formed of a single layer or a multilayer including one of Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu, or an alloy thereof.Fifth, as in FIG. 17E, a passivation layer 160 may be provided on the oxide semiconductor layer 130, the source electrode 140, and the drain electrode 150 (S 105 in FIG. 16 ).The passivation layer 160 may be formed of an inorganic layer, and may be formed of, for example, SiOx, SiNx, or a multilayer thereof.FIG. 18 is a plan view illustrating a TFT according to another embodiment of the present disclosure. FIG. 19 is a cross-sectional view showing an example taken along the line II-II' of FIG. 18.Except that a length of a first oxide semiconductor layer 131 in a first direction (an X-axis direction) is set longer than a length of a second oxide semiconductor layer 132 in the first direction (the X-axis direction), descriptions of FIGS. 18 and 19 are substantially the same as the descriptions given above with reference to FIGS. 6 and 7, and thus overlapping description is omitted.In FIGS. 18 and 19, the first oxide semiconductor layer 131 may have an area wider than that of the second oxide semiconductor layer 132, and thus a contact area between each of a source electrode 140 and a drain electrode 150 and the first oxide semiconductor layer 131, which is a main channel layer, is increased. Therefore, in another embodiment of the present disclosure illustrated in FIGS. 18 and 19, contact resistance is reduced.FIG. 20 is a plan view illustrating a TFT 100 according to another embodiment of the present disclosure. FIG. 21 is a cross-sectional view illustrating an example taken along the line III-III' of FIG. 20.In FIGS. 20 and 21, the TFT 100 according to another embodiment of the present disclosure is illustrated as being provided in a coplanar structure. The coplanar structure may include a top gate structure wherein a gate electrode is provided on an active layer.Referring to FIGS. 20 and 21, the TFT 100 according to another embodiment of the present disclosure may include a gate electrode 110, an oxide semiconductor layer 130, a source electrode 140, and a drain electrode 150.The TFT 100 may be provided on a first substrate 1110. The first substrate 1110 may be formed of plastic, glass, and / or the like.A buffer layer 300 may be provided on the first substrate 1110 to protect the TFT 100 from water entering through the first substrate 1110. The buffer layer 300 may include a plurality of inorganic layers that are alternately stacked. For example, the buffer layer 300 may be formed of a multilayer in which one or more inorganic layers of SiOx, SiNx, and SiON are alternately stacked. The buffer layer 300 may be omitted.An oxide semiconductor layer 130 may be formed on the buffer layer 300. The oxide semiconductor layer 130 may include a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132. The first oxide semiconductor layer 131 may be a main channel layer through which an electron moves, and thus may be disposed near the gate electrode 110. Therefore, the first oxide semiconductor layer 131 may be defined as a layer disposed closer to the gate electrode 110 than the second oxide semiconductor layer 132, and the second oxide semiconductor layer 132 may be defined as a layer farther from the gate electrode 110 than the first oxide semiconductor layer 131. For example, in a case where the TFT 100 is implemented in the coplanar structure, as in FIGS. 20 and 21, since the gate electrode 110 is disposed on the oxide semiconductor layer 130, the second oxide semiconductor layer 132 may be disposed on the first substrate 1110 or the buffer layer 300 of the first substrate 1110, and the first oxide semiconductor layer 131 may be disposed on the second oxide semiconductor layer 132.A light blocking layer may be formed under the oxide semiconductor layer 130 to block light incident from the first substrate 1110 on the oxide semiconductor layer 130.A gate insulation layer 120 may be provided on the oxide semiconductor layer 130. The gate insulating layer 120 may be formed of an inorganic layer, and may be formed of, for example, SiOx, SiNx, or a multilayer thereof.The gate electrode 110 may be formed on the gate insulation layer 120. The gate electrode 110 may be disposed to overlap the oxide semiconductor layer 130 with the gate insulating layer 120 therebetween. The gate electrode 110 may be formed of a single layer or a multilayer including one of Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu, or an alloy thereof.In FIG. 21, an example in which the gate insulating layer 120 is disposed only between the gate electrode 110 and the oxide semiconductor layer 130 is shown, but embodiments of the present disclosure are not limited thereto. In other embodiments, the gate insulation layer 120 may be formed to cover the first substrate 1110 and the oxide semiconductor layer 130.An interlayer insulating layer 170 may be formed on the gate electrode 110 and the oxide semiconductor layer 130. The interlayer insulating layer 170 may be formed of an inorganic layer, and may be formed of, for example, SiOx, SiNx, or a multilayer thereof.A first contact hole CT 1 that passes through the interlayer insulating layer 170 and exposes one side of the first oxide semiconductor layer 131, and a second contact hole CT 2 that passes through the interlayer insulating layer 170 and exposes the other side of the first oxide semiconductor layer 131 may be formed in the interlayer insulating layer 170.The source electrode 140 and the drain electrode 150 may be formed on the interlayer insulating layer 170. The source electrode 140 may contact one side of the first oxide semiconductor layer 131 through the first contact hole CT 1. The drain electrode 150 may contact the other side of the first oxide semiconductor layer 131 through the second contact hole CT 2.A passivation layer 160 may be formed on the source electrode 140 and the drain electrode 150. The passivation layer 160 may be formed of an inorganic layer, and may be formed of, for example, SiOx, SiNx, or a multilayer thereof.The first oxide semiconductor layer 131 may be formed of IGZTO instead of IGZO to increase electron mobility.In addition, the second oxide semiconductor layer 132 may be formed of IGZTO. Specifically, a composition ratio of IGZT of the second oxide semiconductor layer 132 may be different from that of IGZT of the first oxide semiconductor layer 131, so that a threshold voltage is prevented from being shifted even when the oxide semiconductor layer 130 is implemented as a short channel, the second oxide semiconductor layer 132 covers and protects the first oxide semiconductor layer 131 to stably function as a channel, and an etching rate of the second oxide semiconductor layer 132 increases.A composition ratio of IGZT of the first oxide semiconductor layer 131 and a composition ratio of IGZT of the second oxide semiconductor layer 132 are substantially the same as described above with reference to FIGS. 6 to 13, and thus overlapping description is omitted.FIG. 22 is a cross-sectional view illustrating another example taken along line III-III' of FIG. 20.Except that a source electrode 140 and a drain electrode 150 are connected to a second oxide semiconductor layer 132 and a first oxide semiconductor layer 131, a description of FIG. 22 is substantially the same as the description given above with reference to FIGS. 20 and 21, and thus overlapping description is omitted.Referring to FIG. 22, each of the first and second contact holes CT 1 and CT 2 may pass through a first oxide semiconductor layer 131 and an interlayer insulating layer 170, and may expose a second oxide semiconductor layer 132. Therefore, the source electrode 140 may be connected to the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 through the first contact hole CT 1, and the drain electrode 150 may be connected to the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 through the second contact hole CT 2.As described above, according to the embodiments of the present disclosure, the first oxide semiconductor layer corresponding to a main channel layer may be formed of IGZTO, and the second oxide semiconductor layer may be formed of IGZO. As a result, according to the embodiments of the present disclosure, electron mobility increases, and moreover, a threshold voltage is prevented from being shifted based on a channel length. Accordingly, the embodiments of the present disclosure may be applied to flat panel display devices that require high-speed driving due to high resolution.Moreover, according to the embodiments of the present disclosure, an inclination of a side surface of the first oxide semiconductor layer may be formed to have an acute angle, and an inclination of a side surface of the second oxide semiconductor layer may be formed to have a right angle or an acute angle. When the source electrode and the drain electrode cover the side surface of the first oxide semiconductor layer and the side surface of the second oxide semiconductor layer, a void is not formed in a boundary between the first oxide semiconductor layer and the second oxide semiconductor layer. Therefore, according to the embodiments of the present disclosure, the first oxide semiconductor layer and the second oxide semiconductor layer are prevented from being additionally etched by an etchant penetrating into the void. Accordingly, the first oxide semiconductor layer and the second oxide semiconductor layer according to the embodiments of the present disclosure may be formed to have a desired channel length or channel width.In order to prevent a PBTS characteristic and a NBTIS characteristic of a TFT from being deteriorated, according to the embodiments of the present disclosure, the second oxide semiconductor layer may be formed such that a content ratio (Zn / In) of Zn to In the second oxide semiconductor layer is less than 5.Further, in the embodiments of the present disclosure, based on a positive shift and a negative shift of a threshold voltage of a TFT, a thickness of the second oxide semiconductor layer may be thicker than one third (1 / 3) of a thickness of the first oxide semiconductor layer and thinner than five thirds (5 / 3) of the thickness of the first oxide semiconductor layer.As described above, the oxide semiconductor layer according to the embodiments of the present disclosure may include the first oxide semiconductor layer that corresponds to a main channel layer and includes IGZTO and the second oxide semiconductor layer including IGZO. The second oxide semiconductor layer may include IGZO or IGZTO. When the second oxide semiconductor layer includes IGZTO, a composition ratio of IGZTO of the second oxide semiconductor layer may be different from that of IGZTO of the first oxide semiconductor layer. As a result, according to the embodiments of the present disclosure, electron mobility increases, and moreover, a threshold voltage is prevented from being shifted based on a channel length. Accordingly, the embodiments of the present disclosure may be applied to flat panel display devices that require high-speed driving due to high resolution.Moreover, according to the embodiments of the present disclosure, an inclination of a side surface of the first oxide semiconductor layer may be formed to have an acute angle, and an inclination of a side surface of the second oxide semiconductor layer may be formed to have a right angle or an acute angle. When the source electrode and the drain electrode cover the side surface of the first oxide semiconductor layer and the side surface of the second oxide semiconductor layer, a void is not formed in a boundary between the first oxide semiconductor layer and the second oxide semiconductor layer. Therefore, according to the embodiments of the present disclosure, the first oxide semiconductor layer and the second oxide semiconductor layer are prevented from being additionally etched by an etchant penetrating into the void. Accordingly, the first oxide semiconductor layer and the second oxide semiconductor layer according to the embodiments of the present disclosure may be formed to have a desired channel length or channel width.In order to prevent a PBTS characteristic and a NBTIS characteristic of a TFT from being deteriorated, according to the embodiments of the present disclosure, the second oxide semiconductor layer may be formed such that a content ratio (Zn / In) of Zn to In the second oxide semiconductor layer is less than 5.

Claims

A thin film transistor comprising: a first oxide semiconductor layer (131) including indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O); and a second oxide semiconductor layer (132) including indium (In), gallium (Ga), zinc (Zn), and oxygen (O), wherein a content ratio, hereinafter referred to as Ga / In, of Ga to In in the second oxide semiconductor layer (132) is higher than the content ratio Ga / In of Ga to In the first oxide semiconductor layer (131), and a content ratio, hereinafter referred to as Zn / In, of Zn to In the second oxide semiconductor layer (132) is higher than the content ratio Zn / In of Zn to In the first oxide semiconductor layer (131), wherein, in the first oxide semiconductor layer (131), a content ratio, referred to as In / Sn hereinafter, of In to Sn satisfies 2.5≤In / Sn≤5; a content ratio, referred to as Ga / Sn hereinafter, of Ga to Sn satisfies 1≤Ga / Sn≤2; and a content ratio, referred to as Zn / Sn hereinafter, of Zn to Sn satisfies 2.5≤ Zn / Sn≤5; and wherein a content of Sn of the second oxide semiconductor layer (132) is lower than a content of Sn of the first oxide semiconductor layer (131) or the second oxide semiconductor layer (132) does not include Sn, wherein a content of Zn of the second oxide semiconductor layer (132) is higher than a content of Zn of the first oxide semiconductor layer (131), and wherein, in the second oxide semiconductor layer (132), the content ratio of Ga to In satisfies 2≤Ga / In≤4, and the content ratio of Zn to In satisfies 2≤ Zn / In≤8.The thin film transistor according to claim 1, wherein the content ratio Zn / In of Zn to In in the second oxide semiconductor layer (132) is lower than 5.The thin film transistor according to claim 1 or 2, wherein a thickness of the second oxide semiconductor layer (132) is thicker than one third of a thickness of the first oxide semiconductor layer (131) and thinner than five thirds of the thickness of the first oxide semiconductor layer (131).The thin film transistor according to any one of the preceding claims, further comprising a gate electrode (110) disposed closer to the first oxide semiconductor layer (131) than to the second oxide semiconductor layer (132).The thin film transistor according to claim 4, wherein an inclination angle of a side surface of the first oxide semiconductor layer (131) is an acute angle, and an inclination angle of a side surface of the second oxide semiconductor layer (132) is an acute angle.The thin film transistor according to claim 4, wherein the gate electrode (110) is disposed on the first oxide semiconductor layer (131), and the first oxide semiconductor layer (131) is disposed on the second oxide semiconductor layer (132).The thin film transistor according to claim 6, further comprising: a source electrode (140) contacting one side of the first oxide semiconductor layer (131) through a first contact hole (CT1) passing through an interlayer insulating film covering the first and second oxide semiconductor layers (131; 132) and the gate electrode (110); and a drain electrode (150) contacting another side of the first oxide semiconductor layer (131) through a second contact hole (CT2) passing through the interlayer insulating film.The thin film transistor according to claim 7, wherein the source electrode (140) contacts one side of the second oxide semiconductor layer (132) through the first contact hole (CT1) additionally passing through the first oxide semiconductor layer (131), and the drain electrode (150) contacts another side of the second oxide semiconductor layer (132) through the second contact hole (CT2) additionally passing through the first oxide semiconductor layer (131).The thin film transistor according to any one of the preceding claims, wherein the second oxide semiconductor layer (132) further comprises tin (Sn).The thin film transistor according to claim 9, wherein the content ratio In / Sn of In to Sn of the second oxide semiconductor layer (132) is equal to or higher than the content ratio In / Sn of In to Sn of the first oxide semiconductor layer, and / or wherein a content of In the second oxide semiconductor layer (132) is lower than a content of In the first oxide semiconductor layer (131), and / or wherein a content of Sn of the second oxide semiconductor layer (132) is lower than a content of Sn of the first oxide semiconductor layer (131).The thin film transistor according to claim 9 or 10, wherein in the second oxide semiconductor layer (132), a content ratio, hereinafter referred to as Sn / In, of Sn to In satisfies 0.1 ≤ Sn / In ≤ 0.5.The thin film transistor according to any one of the preceding claims, wherein a content of Ga of the second oxide semiconductor layer (132) is higher than a content of Ga of the first oxide semiconductor layer (131).A gate driver comprising a plurality of stages (STT1) outputting gate signals, wherein the plurality of stages (STT1) each comprise a thin film transistor according to any one of the preceding claims.A display device (1000) comprising a display panel (1100) including a plurality of data lines, a plurality of gate lines, a plurality of pixels (P) each provided in a plurality of regions (DA) defined by intersections of the plurality of data lines and the plurality of gate lines, and a gate driver (1200) for outputting gate signals to the plurality of gate lines, characterized in that each of the plurality of pixels (P) and / or the gate driver (1200) includes a thin film transistor according to any one of the preceding claims 1 to 13.

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