Semiconductor device

Abstract

Semiconductor device (10) comprising: a semiconductor substrate (12), an upper main electrode (14) provided above the semiconductor substrate (12), a scanning anode electrode (50) provided above the semiconductor substrate (12), a resistive layer (52) provided above the semiconductor substrate (12) having a higher resistance than the scanning anode electrode (50), and a lower main electrode (16) provided below the semiconductor substrate (12), wherein the semiconductor substrate (12) comprises a switching element (82) and a scanning diode (80), the switching element (82) being connected between the upper main electrode (14) and the lower main electrode (16), the scanning diode (80) having a first anode region (60) of a P-type connected to the scanning anode electrode (50) via the resistive layer (52), and a first cathode region (62) of an N-type connected to is connected to the lower main electrode (16), hasand the first anode region (60) is in direct contact with the resistive layer (52).

Description

TECHNICAL FIELD The technology disclosed here relates to a semiconductor device. BACKGROUND Japanese patent application JP 2016-149715A discloses a semiconductor device in which a switching element and a protection diode are integrated into a common semiconductor substrate. A cathode electrode of the protection diode is connected to a terminal of the switching element. An anode electrode of the protection diode is connected to an external circuit. The potential of the anode electrode of the protection diode varies depending on the potential of one terminal of the switching element. The technique described in Japanese patent application JP 2016-149715A determines whether a freewheeling diode connected in parallel to the switching element is switched on or off according to the potential of the anode electrode in the protection diode. When the freewheeling diode is switched off, the external circuit allows the switching element to be switched on. DE 43 00 100 A1 further discloses a semiconductor device with a switching device and an avalanche device for protecting the switching device by generating an avalanche breakdown current when an overvoltage is applied to the switching device, wherein the avalanche device shares a drift layer with the switching device, so that the avalanche breakdown voltage from the avalanche device follows changes in the breakdown voltages from the switching device that are based on variations in the thickness or impurity concentration of the drift layer or the temperature. From WO 2016 027 563 A1, a current interruption device is known which comprises: a semiconductor substrate with a switching element formed therein; a first electrode formed on the surface of the semiconductor substrate; a second electrode formed on the surface and insulated from the first electrode; a resistive film formed on the surface and connecting the first electrode and the second electrode; a terminal; a connecting wire connecting the first electrode and the terminal; and a control element that switches on the switching element when a voltage between both ends of a current path including the resistive film exceeds a threshold value, the switching element being connected to the first electrode and / or the second electrode. SUMMARY Similar to the protection diode described in Japanese Patent Publication JP 2016-149715A, when the cathode electrode of the diode is connected to a terminal of the switching element, the potential of the diode's anode electrode varies depending on the potential of the terminal. This type of diode can be used to determine the operating state of the switching element based on the potential of the terminal, even in a method different from the one described in Japanese Patent Publication JP 2016-149715A (i.e., determining the on-state of the freewheeling diode). Hereinafter, this type of diode will be referred to as a sampling or measuring diode. When the scanning diode and the switching element are mounted on a single semiconductor substrate, an upper main electrode and a measuring / scanning anode electrode can be located on the upper surface of the semiconductor substrate, and a lower main electrode can be located on the lower surface. A P-type anode layer of the scanning diode is connected to a measuring / scanning anode electrode, while an N-type cathode layer of the scanning diode is connected to a lower main electrode. The switching element is connected between the upper and lower main electrodes. That is, the switching element and the scanning diode are connected together at the lower main electrode. In other words, the lower main electrode serves as a terminal for the switching element and also as a cathode electrode for the scanning diode.Since both the upper main electrode and the scanning anode electrode are positioned above the semiconductor substrate, there is a parasitic capacitance between the upper main electrode and the scanning anode electrode. Fig. 6 shows a circuit diagram of the semiconductor device. In more detail, Fig. 6 shows a switching element 100, a scanning diode 110, an upper main electrode 120, a lower main electrode 130, a scanning anode electrode 140, and a parasitic capacitor 150. Although Fig. 6 shows the switching element 100 configured as an insulated-gate bipolar transistor (IGBT), the switching element 100 could be a different switching element, such as a metal-oxide-semiconductor field-effect transistor (MOSFET), a bipolar transistor, or the like. The switching element 100 is connected between the upper main electrode 120 and the lower main electrode 130, as shown in Fig. 6. A cathode layer of the scanning diode 110 is connected to the lower main electrode 130, with an anode layer of the scanning diode 110 being connected to the scanning anode electrode 140. The parasitic capacitance 150 is present between the scanning anode electrode 140 and the upper main electrode 120.In the semiconductor device shown in Fig. 6, when the potential of the upper main electrode 120 is higher than the potential of the lower main electrode 130, the potential of the scanning anode electrode 140 is increased due to the coupling capacitance of the parasitic capacitance 150. Consequently, a forward voltage is applied to the scanning diode 110. A current then flows through the scanning diode 110 in the forward direction. At this time, holes are injected into the semiconductor substrate from the scanning anode electrode 140. Subsequently, when the potential of the upper main electrode 120 decreases to a potential lower than that of the lower main electrode 130, the potential of the scanning anode electrode 140 decreases. As a result, the voltage applied to the scanning diode 110 switches from a forward voltage to a reverse voltage.The holes present in the semiconductor substrate then flow towards the scanning anode electrode 140, thus allowing a reverse current to flow through the scanning diode 110. This reverse current is generally called a recovery current. A high recovery current flowing through the scanning diode 110 indicates a high load on the diode. Consequently, it is an object of the present invention to provide a technique for suppressing a recovery current of a scanning diode. This object is achieved by the features of the independent claim. Advantageous embodiments are disclosed in the dependent claims. A semiconductor device according to the invention comprises: a semiconductor substrate, an upper main electrode provided above the semiconductor substrate, a scanning anode electrode provided above the semiconductor substrate, a resistive layer provided above the semiconductor substrate which has a higher resistance than the scanning anode electrode, and a lower main electrode provided below the semiconductor substrate. The semiconductor substrate includes a switching element and a scanning diode. The switching element is connected between the upper main electrode and the lower main electrode. The scanning diode has a first anode region of a P-type, which is connected to the scanning anode electrode via the resistive layer, and a first cathode region of an N-type, which is connected to the lower main electrode. The first anode region is in direct contact with the resistive layer. In this semiconductor device, the first anode region of the scanning diode is connected to the upper main electrode via a resistive layer with high resistance. Therefore, when a forward voltage is applied to the scanning diode, the current flowing through it is small. Consequently, few holes are injected into the semiconductor substrate from the scanning anode electrode when the forward voltage is applied. Subsequently, when the voltage applied to the scanning diode is switched to the reverse voltage, the holes in the semiconductor substrate are discharged into the scanning anode electrode. Therefore, a recovery current flows through the scanning diode.Since there are few holes injected from the scanning anode electrode to the semiconductor substrate when the forward voltage is applied, there are also few holes discharged from the semiconductor substrate to the scanning anode electrode when the reverse voltage is applied. Consequently, the recovery current flowing through the scanning diode is low. In this way, the recovery current at the scanning diode can be suppressed according to the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a top view of a semiconductor device according to one embodiment. Fig. 2 is a cross-sectional view of the semiconductor device along line II-II of Fig. 1, not according to the invention. Fig. 3 is a cross-sectional view of the semiconductor device along line III-III of Fig. 1. Fig. 4 is a circuit diagram of the semiconductor device according to one embodiment. Fig. 5 is a cross-sectional view of the semiconductor device according to the invention, corresponding to Fig. 2. Fig. 6 is a circuit diagram of the semiconductor device, which has a scanning diode 110. DETAILED DESCRIPTION A semiconductor device 10, shown in Figs. 1, 2 to 3, has a semiconductor substrate 12. The semiconductor substrate 12 is a silicon substrate. As shown in Fig. 1, the semiconductor substrate 12 contains an element region 18 and a measurement / scanning region 70. One area of ​​the element region 18 is much larger than one area of ​​the scanning region 70. The scanning region 70 is located adjacent to the element region 18. IGBTs and freewheeling diodes are provided at the element region 18, which will be described in detail later. A scanning diode is also provided at the scanning region 70.It should be noted that in the following description, a Z-direction is defined as a thickness direction of the semiconductor substrate 12, an X-direction is defined as a direction parallel to an upper surface of the semiconductor substrate 12 (a direction perpendicular to the Z-direction), and a Y-direction is defined as a direction perpendicular to both the Z-direction and the X-direction. As shown in Fig. 2 (not according to the invention), an upper surface of the semiconductor substrate 12 at the scanning region 70 is covered with an insulating interlayer film 36. A measuring or scanning anode electrode 50, a resistive layer 52, and a wiring layer 54 are provided above the insulating interlayer film 36. The resistive layer 52 is composed of polysilicon doped with impurities. The resistive layer 52 has a specific resistance that is higher than that of both the scanning anode electrode 50 and the wiring layer 52. The resistive layer 52 is provided on the insulating interlayer film 36. The scanning anode electrode 50 is made of Al (aluminum) or AlSi (an alloy of aluminum and silicon). The scanning anode electrode 50 is positioned on the resistive layer 52. An upper surface of the scanning anode electrode 50 serves as a bonding pad. The scanning anode electrode 50 covers an upper surface of a central section of the resistive layer 52. Thus, the central section of the resistive layer 52 is positioned beneath the scanning anode electrode 50 (i.e., the bonding pad), with an outer peripheral section of the resistive layer 52 extending beyond the scanning anode electrode 50. That is, the resistive layer 52 has its central section positioned beneath the bonding pad, and the outer peripheral section extends to the outer edge of the bonding pad. The wiring layer 52 is composed of Al or AlSi. The wiring layer 52 is provided on the insulating interlayer film 36. As shown in Fig. 1, the wiring section 54 extends circularly around the scanning anode electrode 50. A space is provided between the wiring section 54 and the scanning anode electrode 50. As shown in Fig. 2 (not according to the invention), a section of the wiring layer 54 is provided above the outer peripheral section of the resistive layer 52. Contact holes 37a and 37b are provided in the insulating interlayer film 36, which is provided beneath the wiring layer 54. The wiring layer 54 is in contact with the resistive layer 52 at contact hole 37a. The wiring layer 54 is in contact with the upper surface of the semiconductor substrate 12 within contact hole 37b. The resistive layer 52 and the wiring layer 54 configure a current path that connects the scanning anode electrode 50 to the semiconductor substrate 12 (more precisely, an anode region 60, which will be described later). As mentioned above, the resistance of the resistive layer 52 is higher than the resistance of either the scanning anode electrode 50 or the wiring layer 54. Therefore, in the current path leading from the bonding pad to the semiconductor substrate 12, the resistance of the resistive layer is higher than the resistance of either the scanning anode electrode 50 or the wiring layer 54. As shown in Fig. 1, one end of a wire 17 is connected to a top surface of the scanning anode electrode 50 (i.e., the bonding pad). Although not shown, the other end of the wire 17 is connected to an external circuit. As shown in Figs. 1, 2 to 3, an upper main electrode 14 is provided above the element region 18. The upper main electrode 14 is made of Al or AlSi. The upper main electrode is in contact with the upper surface of the semiconductor substrate 12 within the element region 18. The upper main electrode 14 is separated from the wiring layer 54. As shown in Figures 2 and 3 (not according to the invention), a lower main electrode 16 is provided on a lower surface of the semiconductor substrate 12. The lower main electrode 16 is in contact with a substantially entire region of the lower surface of the semiconductor substrate 12. As shown in Fig. 2, which is not according to the invention, the anode region 60, a drift region 27, a cathode region 62 and a lower region 64 of the P type are provided at the scanning region 70. The anode region 60 is a P-type region. The anode region 60 is located on an area that constitutes the top surface of the semiconductor substrate 12. The anode region 60 is in contact with the wiring layer 54 within the contact holes 37b. The anode region 60 is connected to the outer peripheral section of the resistive layer 52 via the wiring layer 54 (i.e., a section not covered by the scanning anode electrode 50). The anode region 60 is connected to the scanning anode electrode 50 via the wiring section 54 and the resistive layer 52. The anode region 60 is not located directly beneath the scanning anode electrode 50 (i.e., the bonding pad). Drift region 27 is an N-type region. It is located beneath anode region 60. Furthermore, drift region 27 extends across the area on the upper surface of the semiconductor substrate 12 beneath the scanning anode electrode 50. The resistance of the resistive layer 52 is higher than the resistance of drift region 28, which is evident when no conductivity modulation phenomenon occurs. The cathode region 62 is an N-type region with a higher concentration of N-type impurities than the drift region 27. The cathode region 62 is located below the drift region 27 and directly below the anode region 60. The cathode region 62 is situated on a region of the lower surface of the semiconductor substrate 12. The cathode region 62 is in contact with the lower main electrode 16. The lower P-type region 64 is a region of a P-type. The lower P-type region 64 is located below the drift region 27 and directly below the scanning anode electrode 50. The lower P-type region 64 is in contact with the lower main electrode 16. The scanning diode is provided at the scanning region 70 by the anode region 60, the drift region 27 and the cathode region 62. As shown in Fig. 3, the element region 18 contains an IGBT region 20, where the IGBTs are located, and a diode region 40, where freewheeling diodes are located. The IGBT region 20 and the diode region 40 are adjacent to each other. Within the element region 18, the IGBT region 20 and the diode region 40 are arranged alternately and repeatingly in the X direction. A plurality of grooves 38 are provided on the lower surface of the semiconductor substrate 12 at the element region 18. The plurality of grooves 38 extend parallel along the Y-direction on the upper surface of the semiconductor substrate 12. As shown in the cross-sectional view of Fig. 3, each groove 38 extends from the upper surface of the semiconductor substrate 12 along the Z-direction. The plurality of grooves 38 are provided in each of the IGBT regions 20 and the diode regions 40. The inner surface of each groove 38 is covered with an insulating gate film 32. A gate electrode 34 is provided in each groove 38. Each gate electrode 34 is insulated from the semiconductor substrate 12 by the respective insulating gate film 32. An upper surface of each gate electrode 34 is covered with the insulating interlayer film 36. Each gate electrode 34 is isolated from the upper main electrode 14 by the insulating intermediate film 36.Each gate electrode 34 at the IGBT region is connected to a gate wiring (not shown). Each gate electrode 34 at the diode region 40 may be connected to the gate wiring or may be a dummy electrode connected to the upper main electrode 14 or similar. Emitter regions 22 and a P-type region 24 are provided in each region inserted between the two trenches 38. The emitter regions 22 and the P-type region 24 are located in the IGBT region 20 and the diode region 40. Each emitter region 22 is an N-type region. The emitter regions 22 are located in areas on the upper surface of the semiconductor substrate 12. Each emitter region 22 is in contact with the lower main electrode 14. The emitter region 22 is in contact with the insulating gate film 32 at the upper end of each trench 38. The P-type region 24 has high-concentration regions 24a and a low-concentration region 24b. Each of the high-concentration regions 24a has a higher P-type foreign matter concentration than the low-concentration region 24b. Each high-concentration region 24a is located in an area on the upper surface of the semiconductor substrate 12. Each high-concentration region 24a is in contact with the upper main electrode 14.The low-concentration region 24b is located below the high-concentration region 24a and the emitter regions 22. The low-concentration region 24b is in contact with the insulating gate film 32 below the emitter regions 22. A section of the P-type region 24 in the IGBT region 20 acts as a body region of the IGBT. Meanwhile, a section of the P-type region 24 in the diode region acts as an anode region of the freewheeling diode. It is noted that while Fig. 3 shows that the emitter regions 22 are located at the diode region 40, no emitter region 22 can be located at the diode region 40. Drift region 27 is located beneath P-type region 24 in IGBT regions 20 and diode region 40. This means that drift region 27 extends across sampling region 70, IGBT regions 20, and diode region 40. Drift region 27 is in contact with the insulating gate film 32 beneath P-type regions 24. Drift region 27 is separated from emitter regions 22 by P-type region 24. A collector region 30 is provided below the drift region 27 in each IGBT region 20. The collector region 30 is a P-type region. The collector region 30 is located in a region on the lower surface of the semiconductor substrate 12. The collector region 30 is in contact with the lower main electrode 16. The collector region 30 is separated from the P-type region 24 by the drift region 27. A cathode region 44 is provided below the drift regions 27 in each diode region 40. The cathode region 30 is a P-type region with a higher N-type impurity concentration than the drift region 27. The cathode region 44 is located in a region on the lower surface of the semiconductor substrate 12. The cathode region 44 is in contact with the lower main electrode 16. In IGBT region 20, each of the IGBTs is constituted by the emitter regions 22, the P-type region 24 (i.e., body region), the drift region 27, the collector region 30, the gate electrodes 34, the insulating gate films 32, and similar components. When the semiconductor device 10 is operated as the IGBT, the upper main electrode acts as an emitter electrode, and the lower main electrode 16 acts as a collector electrode. In diode region 40, the freewheeling diode is constituted by the P-type region 24 (i.e., the anode region), the drift region 27, the cathode region 44, and similar components. When the semiconductor device 10 is operated as the freewheeling diode, the upper main electrode 14 acts as an anode electrode, and the lower main electrode 16 acts as a cathode electrode. Fig. 4 shows an internal circuit of the semiconductor device 10. Referring to Fig. 4, IGBT 82 denotes each of the IGBTs arranged at IGBT region 20, freewheeling diode 84 denotes each of the freewheeling diodes provided in diode region 40, and scanning diode 80 denotes a scanning diode provided at scanning region 70. A collector of IGBT 82 is connected to the lower main electrode 14, and an emitter of IGBT 82 is connected to the upper main electrode 16. An anode of freewheeling diode 84 is connected to the upper main electrode 14, and a cathode of freewheeling diode 84 is connected to the lower main electrode 16. That is, freewheeling diode 84 is connected in antiparallel to IGBT 82. A cathode of scanning diode 80 is connected to the lower main electrode 16. Meanwhile, one anode of the scanning diode 80 is connected to the scanning anode electrode 50.The scanning anode electrode 50 is connected to an external circuit 90 via the wire 17 (see Fig. 1) or similar. The external circuit 90 controls the potential of the gate electrode of the IGBT 82 according to the potential of the scanning anode electrode 50. The potential of the scanning anode electrode 50 varies depending on the potential of the lower main electrode 16. The potential of the lower main electrode 16 varies depending on the operating states of the IGBT 82 and the freewheeling diode 84, and similar components. Consequently, the external circuit 90 detects the potential of the scanning anode electrode 50, thereby enabling appropriate control of the IGBT 82. Furthermore, as shown in Fig. 1 and Fig. 2, the scanning anode electrode 50 and the wiring layer 54 are located close to the upper main electrode 14. Therefore, a relatively large parasitic capacitance exists between the scanning anode electrode 50 and the upper main electrode 14. Refer to Fig.In 4, the parasitic capacity is named by a capacity of 86. The voltage between the upper main electrode 14 and the lower main electrode 16 varies depending on the operating states of the IGBT 82 and the freewheeling diode 84, or on the operating state of a circuit connected to the upper main electrode 14 and the lower main electrode 16. Furthermore, if the potential of the upper main electrode 14 rises to a potential higher than that of the lower main electrode 16, the potential of the scanning anode electrode 50 increases due to the coupling capacitance via the parasitic capacitance 86. Consequently, the potential of the scanning anode electrode 50 becomes higher than that of the lower main electrode 16. Therefore, a forward current flows through the scanning diode 80. At this time, holes are injected from the anode regions 60 into the drift region 27.Consequently, when the potential of the upper main electrode 14 is reduced to a potential lower than that of the lower main electrode 16, the voltage applied to the freewheeling diode 84 switches from the forward voltage to the reverse voltage, allowing a recovery current to flow through the freewheeling diode 84. Furthermore, when the potential of the upper main electrode 14 is reduced to a potential lower than that of the lower main electrode 16, the potential of the scanning anode electrode 50 is reduced due to the coupling capacitance via the parasitic capacitance 86. Consequently, the potential of the scanning anode electrode 50 becomes lower than that of the lower main electrode 16. Therefore, the voltage applied to the scanning diode 80 switches from the forward voltage to the reverse voltage. As a result, a recovery current flows through the scanning diode 80.When a high recovery current flows through the sampling diode 80, a high load is applied to the sampling diode 80. Nevertheless, in the semiconductor device 10 of the present non-inventive embodiment, the scanning anode electrode 50 is connected to the anode region 60 via the resistive layer 52, which has a high resistance. Consequently, when the forward voltage is applied, hardly any current flows through the scanning diode 80. This means that the forward voltage drop across the scanning diode 80 is large. As a result, a few holes are injected from the anode region 60 into the drift region 27 when the forward voltage is applied to the scanning diode 80. Subsequently, when the reverse voltage is applied to the scanning diode 80, the holes present in the drift region 27 are discharged to the scanning anode electrode 50, thereby allowing a recovery current to flow through the scanning diode 80.Since few holes are injected into the drift region 27 when the forward voltage is applied, few holes are discharged from the drift layer 27 when the reverse voltage is applied. Consequently, in the semiconductor device 10 of the present non-inventive embodiment, hardly any recovery current flows through the scanning diode 80. As a result, the load on the scanning diode 80 is reduced, thereby improving its availability. In the semiconductor device 10 of the present non-inventive embodiment, the resistance of the resistive layer 52 is higher than the resistance of the drift region 27. Therefore, the drop in the forward voltage of the scanning diode 80 across the resistive layer 52 can be effectively increased. For this reason, the recovery current at the scanning diode 80 can be suppressed more effectively. In the aforementioned non-inventive embodiment, the anode region 60 is not located beneath the scanning anode electrode 50 (i.e., the bonding pad). Consequently, the shock caused during wire bonding is hardly exerted on the anode regions 60. Therefore, the occurrence of defects or similar issues in the anode regions 60 can be prevented. As a result, leakage current or similar issues in the scanning diode 80 can be suppressed. Furthermore, the resistive layer 52, which is composed of polysilicon, is located beneath the scanning anode electrode 50 (i.e., the bonding pad). By providing the polysilicon layer beneath the bonding pad in this way, the semiconductor substrate 12 can be protected by the polysilicon layer during wire bonding. Therefore, damage to the semiconductor substrate 12 during wire bonding can be reduced. In a manufacturing process of the semiconductor device 10 in the aforementioned non-inventive embodiment, the resistive layer 52 and the insulating interlayer film 36 are formed to embed the resistive layer 52 in the insulating interlayer film 36. Then, contact holes, including contact holes 37a and 37b, are formed. Subsequently, the scanning anode electrode 50, the wiring layer 54, and the upper main electrode 14 can be formed. The contact holes are formed by etching the insulating interlayer film. At this time, etching is stopped at the resistive layer 52 when it is present, and at the semiconductor substrate 12 when it is not present.Consequently, the contact holes (for example, contact holes 37a) leading to the resistive layer 52 and the contact holes (for example, compact holes 37b) leading to the semiconductor substrate 12 can be formed simultaneously. As a result, the scanning anode electrode 50, the wiring layer 54, and the upper main electrode can then be formed simultaneously. Therefore, the semiconductor device 10 of the present non-inventive embodiment can be manufactured with essentially the same efficiency as a conventional semiconductor device. It should be noted that in the aforementioned non-inventive embodiments, the resistive layer 52 is connected to the anode region 60 via the wiring layer 54. However, as shown in Fig. 5, according to the invention, the resistive layer 52 is in direct contact with the anode region 60. In this case, the resistive layer 52 can be composed of polysilicon. When the resistive layer 52 is composed of polysilicon, as shown in Fig. 5, holes are permitted to flow from the anode region 60 to the resistive layer 52 when a reverse voltage is applied. The carrier lifetime of polysilicon is short. For this reason, many holes recombine with electrons to disappear as they pass through the resistive layer 52. Consequently, the recovery current can also be reduced. In the aforementioned embodiment, the IGBTs are provided at element region 18. Alternatively, other switching elements, such as MOSFETs, can be provided at element region 18 instead of the IGBTs. In the aforementioned embodiment, the entire upper surface of the scanning anode electrode 50 serves as the bonding pad. Alternatively, a section of the upper surface of the scanning anode electrode 50 can serve as the bonding pad. In the aforementioned non-inventive embodiment, the wiring layer 54 surrounds a periphery of the scanning anode electrode 50. However, as long as the resistive layer 52 is present in the current path between the scanning anode electrode 50 and the anode region 60, the arrangement of the scanning anode electrode 50, the resistive layer 52, and the wiring layer 54 can be appropriately modified. As mentioned above, the wiring layer 54 is not present according to the invention. A relationship between components of the aforementioned embodiments and components of the claims is described below. The anode region 60 in the embodiment is an example of a first anode region as described in the claims. The cathode region 62 in the embodiment is an example of a first cathode region as described in the claims. The P-type region 24 in the diode region 40 of the embodiment is an example of a second anode region as described in the claims. The cathode region 44 in the embodiment is an example of a second cathode region as described in the claims. In a semiconductor device disclosed herein by way of example, the scanning anode electrode may have a bonding pad configured such that a wire is bonded to the bonding pad. The resistive layer may have a first section connected to the scanning anode electrode beneath the bonding pad and a second section extending outward from the bonding pad. The first anode region may not be located beneath the bonding pad and may be connected to the scanning anode electrode via the second section. With this configuration, a shock caused during wire bonding can hardly be applied to the first anode region, making it possible to avoid the occurrence of defects in the first anode region. In a configuration where the resistive layer is located under the bonding pad, the resistive layer can be composed of polysilicon. By placing high-resistance polysilicon under the bonding pad, any defect due to impact during wire bonding can be suppressed. According to the invention, the first anode region is in direct contact with the resistive layer. In this configuration, the resistive layer can be composed of polysilicon. The carrier lifetime of polysilicon is short. With this configuration, when the reverse voltage is applied to the scanning diode, holes discharged from the semiconductor substrate into the scanning anode electrode are allowed to pass through the resistive layer formed by polysilicon. Consequently, the holes recombine with electrons and disappear into the resistive layer. This also suppresses the recovery current. In a semiconductor device disclosed herein as an example, the semiconductor substrate may have an N-type drift region located between the first anode region and the first cathode region. The drift region may have a lower N-type impurity concentration than the first cathode region. The resistive layer may have a higher resistance than the drift region. This configuration also allows the recovery current of the scanning diode to be suppressed. In a semiconductor device disclosed herein as an example, the semiconductor substrate may include a freewheeling diode. The freewheeling diode may have a second anode region of the P type connected to the upper main electrode and a second cathode region of the N type connected to the lower main electrode.

Claims

Semiconductor device (10) comprising: a semiconductor substrate (12), an upper main electrode (14) provided above the semiconductor substrate (12), a scanning anode electrode (50) provided above the semiconductor substrate (12), a resistive layer (52) provided above the semiconductor substrate (12) having a higher resistance than the scanning anode electrode (50), and a lower main electrode (16) provided below the semiconductor substrate (12), wherein the semiconductor substrate (12) comprises a switching element (82) and a scanning diode (80), the switching element (82) being connected between the upper main electrode (14) and the lower main electrode (16), the scanning diode (80) having a first anode region (60) of a P-type connected to the scanning anode electrode (50) via the resistive layer (52), and a first cathode region (62) of an N-type connected to is connected to the lower main electrode (16), hasand the first anode region (60) is in direct contact with the resistive layer (52). Semiconductor device (10) according to claim 1, wherein the scanning anode electrode (50) has a bonding pad configured to allow a wire to be bonded to the bonding pad, the resistive layer (52) has a first section connected to the scanning anode electrode (50) below the bonding pad and a second section extending outwards from the bonding pad, and the first anode region (60) is not provided below the bonding pad and is connected to the scanning anode electrode (50) via the second section. Semiconductor device (10) according to claim 1 or 2, wherein the resistive layer (52) is formed of polysilicon. Semiconductor device (10) according to one of claims 1 to 3, wherein the semiconductor substrate (12) has an N-type drift region (27) provided between the first anode region (60) and the first cathode region (62), wherein the drift region (27) has a lower N-type foreign substance concentration than the first cathode region (62), and the resistive layer (52) has a resistance that is higher than the resistance of the drift region (27). Semiconductor device (10) according to one of claims 1 to 4, wherein the semiconductor substrate (12) further comprises a freewheeling diode (84), and the freewheeling diode (84) comprises a second anode region (24) of the P type connected to the upper main electrode (14) and a second cathode region (44) of the N type connected to the lower main electrode (16).

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