Semiconductor transistor component
By using a p-conductive layer with high hole concentration in group III nitride transistors, the normally-off behavior is achieved, ensuring reliable blocking performance and stable switching.
Patent Information
- Application Number
- DE102018115224
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2018-06-25
- Publication Date
- 2025-07-03
- Estimated Expiration
- 2038-06-25
AI Technical Summary
Existing group III nitride-based transistors struggle to achieve reliable normally-off behavior due to low hole concentrations in p-GaN layers, leading to unsatisfactory blocking performance.
Incorporating a p-conductive layer with a second material system having a volume hole concentration above 1×10^18 cm^-3, such as metal halides like CuI or AgI, to enhance the blocking capability of the transistor.
The enhanced p-conductive layer ensures high threshold voltages and stable switching by effectively depleting the channel of electrons, making the transistor intrinsically safe against component failures.
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Abstract
Description
[0001] The invention relates to a normally-off semiconductor transistor component or semiconductor transistor component module in the Al system x Ga y In 1-x-y N, with 0 ≤ x,y ≤ 1, x+y ≤ 1.
[0002] Group III nitride-based transistors are used for high-frequency applications up to 100 GHz and as power components, particularly for switching power supplies. On the system side, transistors that are normally off and do not allow current to pass in the event of a defect are preferred. However, in the group III nitride system, this problem has so far remained unsatisfactorily solved. Currently, the active layer beneath the gate contact is either partially or completely removed locally, a p-GaN layer is applied, or the normally off behavior is realized using a more complex electronic circuit.
[0003] US 2017 / 0 317 184 A1 discloses a semiconductor transistor component with a group II nitride material system having a gate contact, which comprises a p-type conductive layer in a second material system having a volume hole concentration above 1×10 18 cm -3 contains.
[0004] Shibata, D. [et al.] (1.7 KV / 1.0 mWcm2 Normally-off Vertical GaN Transistor on GaN Substrate with Regrown p-GaN / AlGaN / GaN Semipolar Gate Structure. In: Proceeding 2016 IEEE International Device Meeting, 2016, 10.1.1-10.1.3) disclose a vertical GaN transistor with normally-off function on a GaN bulk substrate with a low specific on-resistance of 1.0 mΩ*cm 2and a high reverse breakdown voltage of 1.7 kV. P-GaN / AlGaN / GaN trilayers are epitaxially grown over V-shaped grooves formed above the drift layer. The channel utilizes a so-called semipolar surface with reduced substrate concentration at the AlGaN interface, enabling high threshold voltages of 2.5 V and stable switching.
[0005] US 2009 / 0 159 929 A1 discloses a heterostructure device comprising a semiconductor multilayer structure having a first region, a second region, and a third region. The first region is coupled to a supply electrode, and the second region is coupled to a drain electrode. The third region is disposed between the first region and the second region. The third region provides a switchable electrically conductive path from the supply electrode to the drain electrode. The third region contains iodine ions.
[0006] Furthermore, Lee, EW [et al.] (Layer-transferred Mos2 / GaN PN diodes. In: Appl.Phys.Lett, 2015, 103595-1-103505-4) discloses the electrical and optical characterization of two-dimensional / three-dimensional p-mol pybdenum disulfide / n-gallium nitride heterojunction diodes. The devices were fabricated on high-quality, large-area p-MoS2 grown by chemical vapor deposition on sapphire substrates. The fabricated devices were transferred onto GaN / sapphire substrates, and the transferred films were characterized by X-ray diffraction (XRD) and atomic force microscopy.
[0007] In principle, the concept of the p-type GaN layer is simple: here the electrons in the channel are displaced by the field of the layer below the gate and this can be switched by applying a voltage.
[0008] However, the hole concentrations in p-GaN are below 10 18 cm -3quite low and the blocking behavior of the components realized with it is often unsatisfactory.
[0009] This is now achieved according to the invention for a semiconductor transistor component (1, 2) with a first material system of group III nitrides (10, 11, 20, 21, 22) with a gate contact (17, 27) containing a p-conductive layer with a second material system (15, 23) having a volume hole concentration above 1×10 18 cm -3 and metal halides as a second material system (15, 23).
[0010] In these material systems, many compounds have hole concentrations well above 10 19 cm -3 In principle, values slightly above those of GaN:Mg are sufficient for the inventive function.
[0011] These materials can be easily fabricated, for example, through vapor deposition, sputtering, or vapor conversion (for example, Cu is converted to Cu by iodine vapor). In principle, many processes are possible, and these compounds can even be partially deposited from solutions.
[0012] By selecting the material and its composition, the band gap energy and the band offset relative to the GaN bands can be adjusted for many of these materials. This allows the electrical behavior of this layer to be influenced under a metallic gate contact or directly as a gate contact.
[0013] A further development of the invention provides that the component (1, 2) is characterized by the design of the component (1) as a horizontal field-effect transistor or the design of the component (2) as a vertical transistor structure. This involves a horizontal or vertical alignment to the substrate, i.e., parallel to it or perpendicular to it.
[0014] A component module is proposed, comprising at least one component (1, 2).
[0015] Materials that are not suitable according to the invention include p-conducting oxides and chalcopyrites that achieve sufficiently high hole concentrations. Values of ≥ 10 19 cm -3 In addition to these two groups of materials, the invention also includes p-conducting metal halides such as CuI or AGI or alloys thereof. Among the oxides, particularly, but not exclusively, ZnRh2O4, CuAlO2, SrCu2O2, SrCrO3, and GuxCr are of interest. 1-x MgO2, La 0.5 Sr0.5 CrO3, Ca3Co4O9, CuScO 2+x , ZnRhO4, CuY 1-x Ca x O3, AgCoO2, Mg x Cr 2-x O3, CuGaO2. Ag(In,Ga,Al)O2, Ag x (In, Ga, Al) 2-x O3 and alloys of these materials. Also included are p-type compounds in the system (Cu,Ag)(Al,In,Ga)(S,Se,O)2.
[0016] Two exemplary embodiments and the description of the associated figures of field effect transistors according to the invention are listed below.
[0017] Fig. Figure 1 shows a schematic cross-section of a possible design of the component (1) as a horizontal field-effect transistor. This is a component with current flow parallel to the substrate on which the layer sequence was grown. In the group III nitride system, this is currently the most common embodiment. 10 is the buffer, which can contain several layers that can also be compensated by a dopant such as C. 11 is a layer in the AlGaInN system. Due to the differences in the piezo fields of layers 10 and 11, a two-dimensional electron gas 12 is formed at the interface between the two in the GaN. This two-dimensional electron gas 12 acts as a current-conducting channel and is essential for the function of the transistor.
[0018] The structure now contains two contacts 13 and 14 for source and drain. A voltage is applied between these contacts, allowing current to flow, symbolized by the horizontal arrow 18. If a gate consisting of the usually metallic gate contact 16 and the second material 15 is then applied, the positive charge of layer 15 causes a depletion of electrons in the area below. The resistance in the channel increases, and in the best case, the current flows only at a rate several orders of magnitude lower. Contact 16 serves to apply a potential between the gate and source and to reduce the positive charge in layer 15, thereby reducing the electron depletion below layer 15 and increasing the current.
[0019] If no voltage is applied to contact 16, the current is so low that the transistor is considered to be pinched off. This makes it intrinsically safe against the failure of other components. The gate contact (17) is considered to be the entirety of the actual contact 16 and the second layer 15. In principle, additional thin layers, such as SiO2 or SiN, can be added for insulation. "Thin" means between 2 and 50 nm thickness for these optional additional layers.
[0020] Fig. Figure 2 shows a schematic cross-section of a possible design of the component (2) as a vertical transistor structure. This is a component with current flow perpendicular to the substrate on which the layer sequence was grown.
[0021] If the substrate has not been removed, the current flow can pass through it, or alternatively be discharged above it through a lateral contact, as shown, for example, in Yuhao Zhang, Daniel Piedra, Min Sun, Jonas Hennig, Armin Dadgar, Lili Yu, and Tomas Palacios, High-Performance 500 V Quasi- and Fully-Vertical GaN-on-Si pn Diodes, IEEE Electron Device Letters 38, 248 (2017). Fig. 2, 20 is the buffer, which in the embodiment shown is highly conductive and has a drain contact 25 at the bottom.
[0022] On top of the buffer is a low n-type conductivity layer 21 with ideally high charge carrier mobility and high crystal quality. Above this is the highly electron-conductivity layer 22, on which the source contact 24 sits.
[0023] To regulate the vertical current flow between source and drain, indicated by arrow 28, gate contacts 27 are now attached, consisting of the contacting layer 26 and the layer 23 according to the invention. Due to the positive charge of the layers 23, the layer 21 between these contacts becomes depleted of electrons and the resistance in the channel increases, so that the current flow decreases. As long as the distance between the layers 23 and the thickness of the layer 21 are not too thick, this layer is completely depleted of charge carriers and blocking. The possible thickness depends on the charge carrier concentration and the space charge zone forming in these layers 21 and 23. If a voltage is applied between gate contact 27 and source, the charge in layer 23 can be depleted and the channel in layer 21 becomes more conductive, whereby the current between source contact 24 and drain contact 25 increases.
[0024] The layers according to the invention can also be used in other component types, such as MOSFETs, MESFETs, or in layers with a different sequence, as long as the channel is electron-conducting and its conductivity can be modified accordingly by a p-type layer or the capture of charge carriers. Additional layers, which can be conductive or insulating, can also be inserted between the layer according to the invention and the component structure, as well as a metallic gate contact.
Claims
[1] Semiconductor transistor component (1, 2) with a first material system of group III nitrides (10, 11, 20, 21, 22) with a gate contact (17, 27) containing a p-conductive layer with a second material system (15, 23) having a volume hole concentration above 1×10 18 cm -3 and metal halides as a second material system (15, 23). [2] Semiconductor transistor component (1, 2) according to claim 1, characterized by the design of the component (1) as a horizontal field-effect transistor. [3] Semiconductor transistor component (1, 2) according to claim 1, characterized by the design of the component (2) as a vertical transistor structure. [4] Semiconductor transistor component module comprising at least one semiconductor transistor component (1, 2) according to one of the preceding claims.
Citation Information
Patent Citations
Heterostructure device and associated method
US20090159929A1
Method of Forming a High Electron Mobility Transistor
US20170317184A1