WRITING ASSISTANT FOR A STORAGE DEVICE AND METHOD FOR CONTROLLING IT

Abstract

Semiconductor memory device (200, 400, 700) comprising: a matrix (202, 800) of memory cells (204, 302, 804, 814, 816) arranged in a plurality of rows and columns (300), each memory cell (204, 302, 814, 816) having a plurality of bit cell transistors (308); and a plurality (802) of write assist circuits (100, 206, 208, 510, 808) comprising one or more write assist circuits (100, 206, 208, 510, 808) in each column (300) of the matrix (202, 800) of memory cells (204, 302, 804, 814, 816), wherein each write assist circuit (100, 206, 208, 808) is configured to provide a core voltage (VDDAI, 112, 210) for memory cells (204, 302, 804, 814, 816) in the same column (300) and to lower the core voltage (VDDAI, 112, 210) during a write operation, and wherein the one or more Write assistant circuits (100, 206, 208, 510, 808) comprising: a first pair of transistors (102, 104) connected between a pull-up voltage (VDD, 110) and a core voltage bus (VDDAI, 112, 210), the first pair of transistors (102, 104) being configured to connect the core voltage bus (VDDAI, 112, 210) to the pull-up voltage (VDD, 110) during the write operation; and a second pair of transistors (106, 108) connected between a pull-down voltage (VSS, 116) and the core voltage bus (VDDAI, 112, 210), the second pair of transistors (106, 108) each having a gate terminal receiving an enable signal (LCV_Enb, 118, 214, 518) that causes the second pair of transistors (106, 108) to connect the core voltage bus (VDDAI, 112, 210) to the pull-down voltage (VSS, 116) during the write operation;wherein the matrix (202, 800) of memory cells (204, 302, 804, 814, 816) and the plurality (802) of write assist circuits (100, 206, 208, 510, 808) have a common semiconductor layout (400, 700) having a repeating structure of gate regions and active regions, wherein each of the plurality (802) of write assist circuits (100, 206, 208, 510, 808) uses a layout area (808) of the common semiconductor layout (400, 700) that corresponds to an area for three adjacent memory cells (204, 302, 804, 814, 816) in a column (300) of the matrix (202, 800) of memory cells (204, 302, 804, 814, 816) corresponds.;

Description

background

[0001] Numerous electronic devices, such as office computers, laptops, tablets, and smartphones, use integrated and / or discrete semiconductor memory devices to store information. These semiconductor memory devices are divided into volatile and non-volatile memory devices. Volatile memory loses stored information when power is removed, while non-volatile memory retains its stored information even when power is removed. Volatile memory includes random-access memory (RAM), which is further subdivided into the subcategories of static random-access memory (SRAM) and dynamic random-access memory (DRAM).

[0002] A typical DRAM memory cell has only one transistor and one capacitor, allowing for a high level of integration for storing large amounts of information. However, DRAM requires regular refreshing, and its low speed mostly limits it to computer main memory. In contrast, an SRAM cell design, such as a 4-transistor (4T) or 6-transistor (6T) design, uses more transistors to make the SRAM cell bistable, meaning the SRAM cell maintains a binary output state indefinitely as long as sufficient power is supplied. While SRAM has a lower level of integration than DRAM, SRAM can operate at higher speeds and with lower power dissipation than DRAM, so SRAMs are mostly used for computer cache memory. Other SRAM applications include embedded memory and memory for network devices.SRAM is often preferred over DRAM when greater speed is required, and an even faster SRAM is desirable.

[0003] It is not uncommon for SRAM transistors, such as SRAM transistors that are part of a memory cell array, to be implemented on the same integrated circuit as other transistor types, such as those used for logic and / or I / O circuits. However, the design rules for SRAM transistors are usually different from (e.g., more stringent than) the design rules used for typical logic or I / O transistors. Because SRAM design rules are more stringent, SRAM transistors are usually smaller than logic or I / O transistors. A typical logic or I / O transistor therefore occupies more space on an integrated circuit than a typical SRAM transistor.And when SRAM transistors are implemented on the same integrated circuit as logic or I / O transistors, which have different design rules, the logic or I / O transistors are usually separated from the SRAM transistors on the integrated circuit by a buffer area, which requires additional space on the integrated circuit.

[0004] US 2006 / 0 262 628 A1 describes a voltage supply for columns of memory cells that lowers a supply voltage during a write operation. Short description of the drawings

[0005] Aspects of the present invention can best be understood from the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with common industry practice, various elements are not drawn to scale. Rather, for clarity of discussion, the dimensions of the various elements may be exaggerated or reduced as desired. The present invention relates to an apparatus according to claim 1, a circuit according to claim 10, and a method according to claim 17. Fig. Figure 1A shows an example of a lower CVVD voltage (LCV) write assist circuit using SRAM bitcell transistors. Fig. Figure 1B is a signal waveform diagram showing an example operation of the LCV write assist circuit of Fig. 1A shows. Fig. Figure 2 is an example layout of an SRAM with an LCV write assist circuit that is part of the SRAM matrix. Fig. Figure 3A is a circuit diagram of an example column of the SRAM matrix of Fig. 2. Fig. Figure 3B is a signal waveform diagram showing an example operation of the LCV write assist circuit of Fig. 3A shows. Fig. Figure 4 is a layout diagram of another SRAM embodiment with an LCV write assist circuit. Fig. Figure 5 shows an example of a masking circuit that can be used with the SRAM matrix layout of Fig. 4 can be used. Fig. Figure 6 is a diagram illustrating an example operation of the SRAM embodiment of the Fig. 4 and Fig. 5 shows. The Fig. 7 and Fig. 8 show an exemplary LCV write assist circuit configured in an SRAM semiconductor layout. Fig. Figure 9 shows an example of a common semiconductor layout used for bit cell and LCV write assist circuits in an SRAM array. Fig. Figure 10 shows an example of a six-transistor (6T) SRAM memory bit cell layout. Fig. 11 is a flow diagram of an exemplary method for manufacturing and controlling a semiconductor memory device. Detailed description

[0006] The following description provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to facilitate the present invention. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and may also include embodiments in which additional elements may be fabricated between the first and second elements such that the first and second elements are not in direct contact. Furthermore, in the present invention, reference numerals and / or letters may be repeated in the various examples.This repetition is for simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structure to one or more other elements or structures illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the component in use or operation, in addition to the orientation illustrated in the figures. The component may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0008] In certain memory devices, such as SRAM, a reduced supply voltage, i.e., a lower CVVD (LCV) voltage compared to a nominal supply voltage generated by a supply voltage circuit, shortens the cycle time of a data write operation, thus achieving a higher write speed. As long as the reduced supply voltage is not reduced so much that signal integrity, noise margins, etc., are compromised, thereby compromising the integrity of a data write operation, the shorter transition between logic low and logic high voltage values ​​associated with the reduced supply voltage range takes correspondingly less time. However, many LCV write assist circuits significantly increase the overall silicon area of ​​the integrated circuit.

[0009] Fig. 1A shows an example of an LCV write assist circuit 100 using SRAM bitcell transistors. The LCV write assist circuit 100 includes four SRAM transistors 102, 104, 106, and 108 that function to lower the SRAM core voltage (VDDAI) during write operations, as shown in the example signal waveform diagram 150 shown in Fig. 1B. The transistors 102, 104, 106, and 108 that form the LCV write assist circuit 100 are SRAM bitcell transistors that have the same semiconductor layout as the bitcells of the SRAM array (see, for example, Fig. 7 and Fig. 8). The LCV write assist circuit 100 can therefore be implemented in the SRAM array, resulting in an area-efficient layout design.

[0010] The LCV write assist circuit 100 includes two upper SRAM transistors 102 and 104 and two lower SRAM transistors 106 and 108. The two upper SRAM transistors 102 and 104 each have a first power-carrying terminal connected to an SRAM pull-up voltage (Vdd) 110 and a second power-carrying terminal connected to an SRAM core voltage bus (VDDAI) 112. Gate terminals of the two upper SRAM transistors 102 and 104 are each connected to a shutdown pin (SD pin) 114 of the SRAM. The two lower SRAM transistors 106 and 108 each have a first power-carrying terminal connected to the SRAM core voltage bus (VDDAI) 112 and a second power-carrying terminal connected to an SRAM pull-down voltage (Vss) 116. The pull-down voltage (Vss) 116 may be, for example, a ground potential.Gate terminals of the two lower SRAM transistors 106 and 108 are each coupled to an LCV enable signal 118. The SRAM core voltage bus (VDDAI) 112 is provided for one or more memory cells in the SRAM array. For example, the LCV write assist circuits 100 can be used to provide a separate core voltage bus (VDDAI) 112 for each bit cell column in an SRAM array, as described later with reference to the circuits shown in FIGS. Fig. The examples shown in Figures 2 to 5 explain this in more detail.

[0011] The operation of the LCV write assistant circuit 100 is shown in Fig. 1B. As shown, the LCV write assist circuit 100 functions as a voltage divider to pull down the SRAM core voltage (VDDAI) 112 during write operations. Specifically, the power-down signal (SD signal) 114 at the gate terminals of the upper SRAM transistors 102 and 104 is pulled low during normal operation, such that Vdd 110 is electrically connected to the VDDAI 112 via the live terminals of the upper SRAM transistors 102 and 104. The LCV enable signal 118 is normally logic high and transitions to a logic low state during a write operation. When the LCV enable signal 118 is in a logic high state, the lower SRAM transistors 106 and 108 are turned off, and the SRAM core voltage (VDDAI) 112 is substantially equal to Vdd.When the LCV enable signal 118 transitions to a logic low state during a write operation, the lower SRAM transistors 106 and 108 turn on, creating a voltage divider between Vdd and Vss (a voltage divider is created because Vdd is applied across the series-connected upper and lower transistors, with the output VDDAI voltage created by the connection between the series pairs). Thus, during a write operation, the SRAM core voltage (VDDAI) 112 is equal to the difference between Vdd and the voltage drop (ΔV) across the upper and lower SRAM transistors 102, 104, 106, and 108.

[0012] The resulting voltage drop ΔV of the SRAM core voltage (VDDAI) 112 during write operations depends on the size of the SRAM transistors 102, 104, 106, and 108. For a typical SRAM bitcell transistor layout, this results in a voltage drop ΔV of approximately 10 to 15% (although it should be understood that other values ​​are within the scope of the invention). In some embodiments, the voltage drop ΔV during write assist should be large enough to achieve a desired increase in bitcell switching speed, but it should not be so large that the core voltage (VDDAI) is reduced below the minimum required for reliable bitcell operation.

[0013] In the illustrated embodiments, the shutdown signal (SD signal) 114 is used to drive the gates of the upper SRAM transistors 102 and 104 in the LCV write assist circuit 100. The shutdown signal 114 remains in a logic low state during normal SRAM operations and transitions to a logic high state during a device shutdown mode. When the device shutdown mode is initiated, the SD signal 114 causes the upper SRAM transistors 102 and 104 to turn off, thereby turning off the current (Vdd) to the VDDAI 112 and thus to the SRAM array. Turning off the current to the VDDAI 112 in this manner may provide the additional benefit of reducing leakage during the shutdown mode. However, in other embodiments, the gate terminals of the upper SRAM transistors 102 and 104 may instead be driven to a logic low state.

[0014] Fig. 2 is an exemplary layout diagram of an SRAM 200 with an LCV write assist circuit that is part of an SRAM array 202. The layout diagram for the SRAM array 202 is shown in the dashed box of Fig. 2. The SRAM matrix 202 is a matrix of memory bit cells 204 (CELL[o] to CELL[n]) arranged in n rows and n columns, each sharing a common semiconductor layout (see Fig. 7 to 10). However, it should be understood that other SRAM array configurations are possible, such as an n-row, m-column array. One or more LCV write assist circuits are located in each column of the SRAM array 202. In the illustrated example, each column of the SRAM array 202 includes two LCV write assist circuits (labeled LCV_CELL), namely an upper write assist circuit 206 and a lower write assist circuit 208. Each column of the SRAM array 202 also includes a core voltage bus (VDDAI bus) 210 that provides the core operating voltage for each of the memory bit cells in the column. For example, a VDDAI 210 is provided on a column-by-column basis, and there is no Vdd connection that provides a core operating voltage directly to the entire array of memory bit cells 204. That is, the VDDAI bus in each column is independent of the VDDAI buses in other columns (i.e., VDDAI is not lowered across columns of matrix 204).

[0015] The core voltage bus (VDDAI bus) 210 runs in each column of the SRAM array 202 from the upper write assist circuit 206 to the lower write assist circuit 208. The core voltage (VDDAI) provided to each memory bit cell in a column is controlled by the upper and lower write assist circuits 206 and 208 such that VDDAI is decreased during write operations, for example, as described above with reference to the Fig. 1A and Fig. 1B. In the illustrated embodiment, two write assist circuits 206 and 208 are provided for each column to provide sufficient current on the VDDAI bus 210 to overcome the resistance and leakage across the entire column of bit cells. However, it should be appreciated that other embodiments may use more or fewer write assist circuits for each column of the SRAM array 202. For example, in one embodiment, four upper write assist circuits and four lower write assist circuits may be used for each bit cell column to provide sufficient column-by-column VDDAI current for a large bit cell array 204.

[0016] In Fig. Also shown in Figure 2 are wordline signals 212 (WLDR V0 through WLDR Vn) for each row of the memory bitcell array 204 and an LCV enable signal 214 (LCV_Enb). The wordline signals 212 are used to select a particular row of the bitcell array 204 for a write operation. The LCV enable signal 214 is coupled to the LCV write assist circuits 206 and 208 in each column of the SRAM array 202 via a multiplexer (not shown), which is used to selectively couple the LCV enable signal 214 to one or more particular columns at a given time. In the illustrated embodiment, the LCV enable signal 214 is coupled to the upper and lower write assist circuits 206 and 208 of each column via a MUX-4 device that selectively couples the LCV enable signal 214 to one of four outputs at a given time, resulting in Fig. 2 by four lines extending from each of the LCV enable signal blocks 214 and connecting to the LCV write assist circuits 206 and 208. Connections between the four multiplexer outputs for the LCV enable signal 214 and a specific LCV write assist circuit 206 and 208 are shown in Fig. 2 by connection node 216. In the illustrated example, each multiplexer output is connected to the LCV write assist circuits 206 and 208 in every fifth column of the matrix 202. When selected by the MUX-4 for output to the LCV write assist circuits 206 and 208 in a particular column, the LCV enable signal 214 causes the core operating voltage 210 (VDDAI) in that column to be reduced during write operations, such as in the Fig. 3A and Fig. 3B is shown.

[0017] Those skilled in the art will appreciate that the illustrated MUX-4 configuration results in multiple bits (i.e., one bit in every fifth column of the matrix 202) being written simultaneously. For example, in a typical SRAM configuration, 32, 64, 128, or more bits are written during one and the same write cycle using the MUX-4 configuration. It will also be appreciated that the Fig. 2 may be used in other embodiments using a MUX-x design (such as MUX-1, -2, -4, or -8). In these embodiments, the LCV_Enb signal bus would be LCV ENB <o:x>.

[0018] In some embodiments, the LCV write assist circuits 206 and 208 are arranged directly adjacent to the memory bit cells 204 without a buffer area therebetween (such as in Fig. 9). The space saving can be achieved by implementing both LCV write assist circuits 206 and 208 and the memory bit cells 204 using SRAM transistors and therefore no buffer area is required.

[0019] Fig. 3A is a circuit diagram showing an example of a column 300 of the SRAM matrix 200 of Fig. 2. The SRAM array column 300 includes an upper LCV write assist circuit 206 at an upper end of the column, a lower LCV write assist circuit 208 at a lower end of the column, and a column of memory bit cells 302 between the upper and lower LCV write assist circuits 206 and 208. The memory bit cells 302 in the column 300 each receive a core voltage from a common VDDAI bus 210, which is fed via the upper and lower LCV write assist circuits 206 and 208. For simplicity, the illustrated example shows only two memory bit cells 302 in the column 300. However, it should be appreciated that a memory bit cell column 300 typically includes many more memory bit cells, each connected to the core voltage bus (VDDAI).

[0020] The memory bit cells 302 operate in a conventional manner to store data bits, with write access to the memory bit cells 302 being controlled using wordline (WL) and bitline (BL) signals, as shown. In the illustrated example, the memory bit cells 302 are six-transistor (6T) cells comprising two pass-gate transistors 304 and 306 and four bit cell transistors 308 configured in a latch structure (however, it should be understood that other types of SRAMs / memories are within the scope of the invention). The data latch of each SRAM cell 302 can be used to store a single bit. The wordline and bitline signals are used to control the operations of reading and writing a bit from / to the SRAM cell 302.

[0021] During a write operation, a bit line 310 and an inverse bit line 312 may be set to opposite logic values ​​corresponding to the data to be written to SRAM cell 302. When SRAM cell 302 is selected, a logic high state may be applied to a word line (WL) 212, thereby selecting the data latch to proceed to the write operation. In response to a logic high pulse applied to word line 212, storage nodes 314 and 316 of the data latch are connected to bit lines 310 and 312, thereby writing the logic values ​​on bit lines 310 and 312 to the respective storage nodes 314 and 316 of memory cell 302.

[0022] The upper and lower LCV write assist circuits 206 and 208 utilize the same semiconductor layout as the memory cells 302. In this manner, the LCV write assist circuits 206 and 208 may be included in the same SRAM array column 300 as the memory bit cells 302. An example of a common semiconductor layout that may be utilized by the LCV write assist circuits 206 and 208 and the memory cells 302 is described below with reference to Fig. 7 to 10 described.

[0023] The operation of the LCV write assist circuits 206 and 208 for lowering the SRAM core voltage (VDDAI) in column 300 during write operations is described in Fig. 3B. The LCV write assist circuits 206 and 208 are both connected to the VDDAI bus 210 and function as voltage divider circuits to lower the VDDAI voltage during write operations. The SD signal 114 is pulled low during normal device operation, as described above with reference to Fig. 1B, causing the upper SRAM transistors 102 and 104 of the LCV write assist circuits 206 and 208 to connect Vdd 110 to the VDDAI bus 210. The LCV enable signal 118 transitions to a logic low state during write operations in the SRAM column 300, turning on the lower SRAM transistors 106 and 108 of the LCV write assist circuits 206 and 208. This creates a voltage divider between the Vdd 110 and the Vss 116 in each of the LCV write assist circuits 206 and 208, and the voltage on the VDDAI bus 112 is lowered by the voltage drop ΔV across the SRAM transistors 102, 104, 106, and 108, as shown in Fig. 3B is shown.

[0024] Fig. 4 is an exemplary layout diagram of another SRAM embodiment 400 with an LCV write assist circuit. This example 400 is similar to the embodiment described above with reference to Fig. 2, except that the LCV enable signal is provided to the LCV write assist circuits 206 and 208 on a column-by-column basis. In this embodiment, a bit write operation is utilized, so the LCV enable signal 214 is applied to the desired columns at a given time and hidden from the other columns. Thus, the LCV enable signal 214 can be selectively applied to one or more desired columns at a given time to lower the voltage on the VDDAI bus 210.

[0025] In each column of the SRAM matrix, the LCV enable signal 214 is coupled to the two LCV write assist circuits 206 and 208 via a masking circuit (not shown) configured to mask the LCV enable signal 214 except during desired write operations. An example of a masking circuit 500 that can be used with the SRAM matrix layout 400 is shown in Fig. 5 shown.

[0026] The masking circuit 500 in Fig. 5 is illustrated for simplicity as a circuit connected to only one LCV write assist circuit 510, but it could instead be connected to multiple LCV write assist circuits in the same SRAM array column. The masking circuit 500 is a logic circuit configured to receive the LCV enable signal 214 and a bit write enable signal (BWE) 512 and, depending on the logic state of the bit write enable signal 512, either pass or block the LCV enable signal 214. In particular, the illustrated embodiment utilizes a NOR gate 514 connected in series with a logic inverter 516. In operation, an output 518 of the illustrated masking circuit 500 is in a logic low state only when both the bit write enable signal 512 and the LCV enable signal 214 are in a logic low state.When either the bit write enable signal 512 or the LCV enable signal 214 is in a logic high state, the mask circuit output 518 is also in a logic high state. Thus, a logic high state on the bit write enable signal 512 prevents the LCV enable signal 214 from lowering the VDDAI bus voltage 210 in the LCV write assist circuit 510.

[0027] Fig. 6 is a diagram illustrating an exemplary operation of the SRAM embodiment 400 of the Fig. 4 and Fig. 5 shows. As explained above, the Fig. 5 is used to select a single column of the matrix 400 for a write operation based on a bit write enable signal (BWE) 512 and an LCV enable signal 214. In the Fig. In the example shown in Figure 6, a first column 610 (column[o]) of the matrix is ​​selected for a write operation.

[0028] It should be clear that the example given in the Fig. 4 to 6 is a MUX-4 design, which means that each bit (Bit[o] to Bit[n]) is chosen from four columns of cells. In the Fig. 6, the first column of each bit is selected with the LCV enable signal 214. That is, the address LCV_Enb <o>is used to select the first column in each bit (i.e., column[o] of bit[o], column[4] of bit[1], etc.). The bit write enable signal (BWE) 512 can be used to write to a column of a particular bit while not writing to other bits. In the illustrated example, the bit write enable signal (BWE) 512 is set to perform a write operation to bit[o] but prevent writing to bit[1]. Specifically, BWE[o] is set to 1 to enable writing to bit[o], and BWE[1] is set to 0 to prevent writing to bit[1]. The LCV enable signal 214 can be used to select a particular column in the enabled bit (e.g., column[o] of bit[o] in the illustrated example).

[0029] The Fig. Figures 7 to 10 show an example of a common semiconductor layout that can be used by both memory bit cells and an LCV write assist circuit in an SRAM array. Fig. 7 and Fig. 8 show an example of how the LCV write assistant circuit 510 described with reference to Fig. 5, can be implemented in an SRAM semiconductor layout 700. Fig. Figure 9 is an expanded illustration of the SRAM semiconductor layout 700, showing how the semiconductor layout for the bit cells and the LCV write assist circuit will be shared throughout the SRAM array. Fig. Figure 10 shows an example of a six-transistor (6T) SRAM memory bitcell layout to further explain how the bitcells and the LCV write assist circuit can be implemented using a common SRAM transistor layout.

[0030] Let us first come to Fig. 7. The exemplary semiconductor layout 700 includes a plurality of intersecting gate (poly) regions 710 and fin-shaped active regions (fin regions) 720 used to fabricate SRAM fin field-effect transistors (FinFETs). Transistors are fabricated at crosspoints of a boundary region 710 and an active region 720. A non-limiting example of a FinFET structure for an SRAM device is disclosed in commonly assigned U.S. application Ser. No. 2013 / 0292777. However, it should be understood that the present invention is not limited to any particular transistor structure.

[0031] In the illustrated example, the SRAM semiconductor layout 700 is used to fabricate the four transistors 102, 104, 106, and 108 of the LCV write assist circuit 510. Corresponding reference numerals 102, 104, 106, and 108 are used to illustrate the coupling points of the active gate regions in the SRAM semiconductor layout 700 in which each of the four transistors 102, 104, 106, and 108 of the LCV write assist circuit is implemented. As shown, contact regions are used to connect the transistor gate regions to either the SD signal 114 or the LVC_Enb signal 118 and to connect the source and drain regions to either VDDAI 112, VDD 110, or VSS 116. As shown, the VDD 110, VSS 116 and VDDAI 112 lines may be provided, for example, by vertical connections to metal grid lines 785, 790 and 795, respectively, in one or more layers of the semiconductor.Similarly, the SD signal 114 and the LVC_Enb signal 118 may be provided by vertical connections to signal lines in one or more layers of the semiconductor. As an example, FIG. Fig. 8 signal lines 796 and 798 arranged on a metal 1 layer and a metal 0 layer of the semiconductor, respectively, to provide the SD signal 114 and the LVC_Enb signal 118. The signal lines 796 and 798 may be connected to the transistor gate regions 114 and 118, for example, by interlayer vias.

[0032] Fig. 9 shows an expanded representation of the SRAM semiconductor layout 700. As in Fig. 9, one and the same semiconductor layout 700 is used for an SRAM bitcell array 800 and for a plurality of LCV write assist circuits 802. The SRAM semiconductor layout 700 has a repeating structure of gate (poly) regions and active (fin) regions, and this structure of poly and fin regions is shared by the SRAM bitcell array 800 and the LCV write assist circuits 802. Specifically, in the illustrated example, the structure of gate (poly) regions and active (fin) regions repeats every two rows in the vertical direction and every two columns in the horizontal direction. The illustrated example shows a bit cell 804 in a bit cell column 806 receiving its core voltage (VDDAI) 112 from a VDDAI grid line 795 controlled by an LCV write assist circuit 808 in the same SRAM bit cell column 806.As shown, the bit cell 804 utilizes the same semiconductor layout 700 (i.e., the same repeating structure of poly and bit regions) used for the LCV write assist circuit 808.

[0033] In the illustrated example, each LCV write assist circuit 808 has a layout area corresponding to a layout area of ​​three adjacent SRAM bit cells 804 in a bit cell column 806. For example, for the Fig. In the LCV write assist circuit shown in Figure 7, the four transistors 102, 104, 106, and 108 are formed by PMOS regions in a layout area corresponding to three SRAM bit cells fabricated in three adjacent rows. Specifically, transistor 102 is formed by a PMOS region in the corresponding layout area of ​​an upper bit cell, transistors 104 and 106 are formed by two PMOS regions in the corresponding layout area of ​​a middle bit cell, and transistor 108 is formed by a PMOS region in the corresponding layout area of ​​a lower bit cell.

[0034] The Fig. The example shown in Figure 9 shows only one LCV write assist circuit in each SRAM bit cell column for simplicity. However, in other examples, multiple LCV write assist circuits may be used in each SRAM bit cell column. For example, LCV write assist circuits may be located at the top and bottom of each SRAM bit cell column, as shown in Figures Fig. 2 and Fig. 4 is shown.

[0035] In Fig. 9, for the sake of simplicity, a bit cell 804 in the matrix 800 is placed in the center. However, it should be clear that a bit cell matrix 800 has several bit cells in each column and can have many more rows and columns than in Fig. 9. It should also be clear that although only one row of LCV write assist circuits 802 in Fig. 9, an SRAM array may have more than one row of LCV write assist circuits, as described above with reference to Fig. 2 and Fig. 4 has been explained.

[0036] Fig. Figure 10 shows an example of a six-transistor (6T) SRAM memory bitcell layout to further explain how the bitcells and the LCV write assist circuit can be implemented using a common SRAM transistor layout 700. In particular, Fig. 10 shows an exemplary SRAM transistor layout for two bit cells 810 and 812 in a column of the matrix 800 shown in Fig. 9. Schematics 814 and 816 of the two 6T SRAM bit cells 810 and 812 are shown to the right of the exemplary layout 700. The operation of the exemplary 6T SRAM memory bit cells is described above with reference to Fig. 3A has been described.

[0037] To assist in explaining the transistor layouts 810 and 812 for the two 6T SRAM memory bit cells 814 and 816, Fig. 10 corresponding reference symbols A 1 to F 1 and A 2 to F 2 for the SRAM transistors in circuit diagrams 814 and 816 and for the coupling points of the active gate regions in bit cells 810 and 812, each of the SRAM transistors being implemented in the SRAM semiconductor layout 700. For example, circuit diagram 814 shows a PMOS transistor labeled A 1 and the bit cell layout 810 shows that this transistor is located at the coupling point between the poly and fin regions, which is also labeled A 1 is designated.

[0038] If you compare the Fig. 7 and Fig. 10, it can be seen that the LCV write assistant circuit 510 in Fig. 7 using the same poly / fin area layout used to implement the two exemplary 6T SRAM memory bit cells 814 and 816 in Fig. 10. In particular, the same arrangement of gate (poly) and active (fin) regions is used throughout the SRAM semiconductor layout 700, namely for the array of SRAM memory bit cells and the LCV write assist circuit 510. As in Fig. 9, certain active (fin) areas may also be shared across the one or more LCV write assist circuits and the memory bit cells in a column of the SRAM semiconductor layout 700.

[0039] Fig. 11 is a flow diagram of an exemplary method 900 for manufacturing and controlling a semiconductor device. It will be appreciated that the method of Fig. 11 can be used for many different structures. However, for better understanding, the procedure for the structures of the Fig. 1 to 10. In step 910, a matrix of memory cells (e.g., 200, 400) is divided into a plurality of rows and columns, each memory cell (e.g., 302) having a plurality of bit cell transistors (e.g., 308). The matrix of memory cells has a common semiconductor layout, which, for example, has been described above with reference to Fig. 7 to 10. In step 920, a plurality of write assist circuits (e.g., 206, 208) are arranged such that one or more write assist circuits are included in each column of the array of memory cells, each write assist circuit comprising a plurality of transistors (e.g., 102, 104, 106, 108). The plurality of write assist circuits share the same common semiconductor layout as the array of memory cells. For example, each of the plurality of write assist circuits may share a layout area of ​​the common semiconductor layout corresponding to an area for three adjacent memory cells in a column of the array of memory cells.In one embodiment, the plurality of write assist circuits may each include four PMOS transistors fabricated using four PMOS regions in three rows of the layout area, with one of the four PMOS transistors fabricated in a top row, two of the four PMOS transistors fabricated in a middle row, and another of the four PMOS transistors fabricated in a bottom row. Each write assist circuit (e.g., 206, 208) is configured to provide a core voltage (e.g., 210) to memory cells (e.g., 302) in the same column and to lower the core voltage (e.g., 210) during a write operation. In step 930, a core voltage (e.g., 210) is provided to memory cells (e.g., 302) in a column of the array of memory cells (e.g., 200, 400). Then, in step 940, the one or more write assist circuits (e.g.,206, 208) the core voltage during a write operation in the column.

[0040] In one embodiment, a semiconductor memory device comprises a matrix of memory cells arranged in a plurality of rows and columns, each memory cell comprising a plurality of bitcell transistors. The semiconductor memory device further comprises a plurality of write assist circuits, including one or more write assist circuits in each column of the matrix of memory cells, each write assist circuit configured to provide a core voltage for memory cells in the same column and to lower the core voltage during a write operation.The matrix of memory cells and the plurality of write assist circuits have a common semiconductor layout having a repeating structure of gate regions and active regions, wherein each of the plurality of write assist circuits uses a layout area of ​​the common semiconductor layout corresponding to an area for three adjacent memory cells in a column of the matrix of memory cells.

[0041] In one embodiment, a write assist circuit for a semiconductor memory element has a core voltage bus configured to provide power for memory cells in the semiconductor memory element. The write assist circuit has a first pair of transistors connected between a pull-up voltage and the core voltage bus, and a second pair of transistors connected between a pull-down voltage and the core voltage bus, wherein each of the second pair of transistors has a gate terminal that receives an activation signal that causes the second pair of transistors to connect the core voltage bus to the pull-down voltage during write operations.The write assist circuit and the memory cells have a common semiconductor layout having a repeating structure of gate regions and active regions, wherein the write assist circuit uses a layout area of ​​the common semiconductor layout corresponding to an area for three adjacent memory cells.

[0042] In one embodiment, a method for controlling a semiconductor memory device having an array of memory cells arranged in a plurality of rows and columns and one or more write assist circuits in each column of the array of memory cells comprises the steps of: providing a core voltage to memory cells in a column of the array of memory cells;and causing the one or more write assist circuits in the column to lower the core voltage during a write operation, wherein the one or more write assist circuits and the memory cells have a common SRAM (Static Random Access Memory) semiconductor layout having a repeating structure of gate regions and active regions, wherein the one or more write assist circuits utilize a layout area of ​​the common semiconductor layout corresponding to an area for three adjacent memory cells in the column of the matrix of memory cells;< / o> < / o:x>

Claims

[1] Semiconductor memory device (200, 400, 700) comprising: a matrix (202, 800) of memory cells (204, 302, 804, 814, 816) arranged in a plurality of rows and columns (300), each memory cell (204, 302, 814, 816) having a plurality of bit cell transistors (308); and a plurality (802) of write assist circuits (100, 206, 208, 510, 808) comprising one or more write assist circuits (100, 206, 208, 510, 808) in each column (300) of the matrix (202, 800) of memory cells (204, 302, 804, 814, 816), wherein each write assist circuit (100, 206, 208, 808) is configured to provide a core voltage (VDDAI, 112, 210) for memory cells (204, 302, 804, 814, 816) in the same column (300) and to lower the core voltage (VDDAI, 112, 210) during a write operation, and wherein the one or more Write assistant circuits (100, 206, 208, 510, 808) comprising: a first pair of transistors (102, 104) connected between a pull-up voltage (VDD, 110) and a core voltage bus (VDDAI, 112, 210), the first pair of transistors (102, 104) being configured to connect the core voltage bus (VDDAI, 112, 210) to the pull-up voltage (VDD, 110) during the write operation; and a second pair of transistors (106, 108) connected between a pull-down voltage (VSS, 116) and the core voltage bus (VDDAI, 112, 210), the second pair of transistors (106, 108) each having a gate terminal receiving an enable signal (LCV_Enb, 118, 214, 518) that causes the second pair of transistors (106, 108) to connect the core voltage bus (VDDAI, 112, 210) to the pull-down voltage (VSS, 116) during the write operation;wherein the matrix (202, 800) of memory cells (204, 302, 804, 814, 816) and the plurality (802) of write assist circuits (100, 206, 208, 510, 808) have a common semiconductor layout (400, 700) having a repeating structure of gate regions and active regions, wherein each of the plurality (802) of write assist circuits (100, 206, 208, 510, 808) uses a layout area (808) of the common semiconductor layout (400, 700) that corresponds to an area for three adjacent memory cells (204, 302, 804, 814, 816) in a column (300) of the matrix (202, 800) of memory cells (204, 302, 804, 814, 816) corresponds.; [2] The semiconductor memory device (200, 400, 700) of claim 1, wherein the plurality (802) of write assist circuits (100, 206, 208, 510, 808) each comprise four PMOS transistors (102, 104, 106, 108) fabricated using four PMOS regions in three rows of the layout area, one of the four PMOS transistors (102, 104, 106, 108) being fabricated in an upper row, two of the four PMOS transistors (102, 104, 106, 108) being fabricated in a middle row, and another of the four PMOS transistors (102, 104, 106, 108) being fabricated in a lower row. [3] The semiconductor memory device (200, 400, 700) according to claim 1 or 2, wherein the plurality of bit cell transistors (308) and the plurality (802) of write assist circuits (100, 206, 208, 510, 808) are each fabricated using common design rules for SRAM (Statistical Random Access Memory) transistors. [4] The semiconductor memory device (200, 400, 700) according to any one of the preceding claims, wherein the plurality (802) of write assist circuits (100, 206, 208, 510, 808) are arranged adjacent to the matrix (202, 800) of memory cells (204, 302, 804, 814, 816) such that there is no buffer area between the matrix (202, 800) of memory cells (204, 302, 804, 814, 816) and the plurality (802) of write assist circuits (100, 206, 208, 510, 808). [5] The semiconductor memory device (200, 400, 700) of any preceding claim, wherein a common fin structure (720) is shared across the one or more write assist circuits (100, 206, 208, 510, 808) and the bit cell transistors (308) in each column (300) of the array (202, 800) of memory cells (204, 302, 804, 814, 816). [6] Semiconductor memory device (200, 400, 700) according to one of the preceding claims, wherein during the write operation a voltage divider is created between the pull-up voltage (VDD, 110) and the pull-down voltage (VSS, 116), which voltage divider comprises the first pair of transistors (102, 104) and the second pair of transistors (106, 108), the first pair of transistors (102, 104) and the second pair of transistors (106, 108) being connected in series and the core voltage (VDDAI, 112, 210) being created by the voltage divider. [7] The semiconductor memory device (200, 400, 700) of any preceding claim, wherein the first pair of transistors (102, 104) each has a gate terminal receiving a shutdown signal (SD, 114), the shutdown signal (SD, 114) causing the first pair of transistors (102, 104) to disconnect the core voltage bus (VDDAI, 112, 210) from the pull-up voltage (VDD, 110) during a shutdown operation. [8] Semiconductor memory device (200, 400, 700) according to one of the preceding claims, wherein the activation signal (LCV_Enb, 118, 214, 518) is coupled by a multiplexer to the one or more write assist circuits (100, 206, 208, 510, 808) in a particular column (300) during the write operation. [9] Semiconductor memory device (200, 400, 700) according to one of the preceding claims, wherein the activation signal (LCV_Enb, 118, 214, 518) is coupled to each column (300) of the matrix (202, 800) of memory cells (204, 302, 804, 814, 816) via a masking circuit arranged to mask the activation signal (LCV_Enb, 118, 214, 518) from the column (300) except during the write operation. [10] Write assistant circuit (100, 206, 208, 510, 808) for a semiconductor memory device (200, 400, 700) comprising: a core voltage bus (VDDAI, 112, 210) configured to provide power to memory cells (204, 302, 804, 814, 816) in the semiconductor memory device (200, 400, 700); a first pair of transistors (102, 104) connected between a pull-up voltage (VDD, 110) and the core voltage bus (VDDAI, 112, 210), wherein the first pair of transistors (102, 104) is configured to connect the core voltage bus (VDDAI, 112, 210) to the pull-up voltage (VDD, 110) during a write operation to the memory cells (204, 302, 804, 814, 816); and a second pair of transistors (106, 108) connected between a pull-down voltage (VSS, 116) and the core voltage bus (VDDAI, 112, 210), wherein the second pair of transistors (106, 108) each has a gate terminal receiving an activation signal (LCV_Enb, 118, 214, 518) that causes the second pair of transistors (106, 108) to connect the core voltage bus (VDDAI, 112, 210) to the pull-down voltage (VSS, 116) during the write operation to the memory cells (204, 302, 804, 814, 816), wherein the write assist circuit (100, 206, 208, 510, 808) and the memory cells (204, 302, 804, 814, 816) have a common semiconductor layout (400, 700) having a repeating structure of gate regions and active regions, wherein the write assist circuit (100, 206, 208, 510, 808) uses a layout area (808) of the common semiconductor layout (400, 700) which corresponds to an area for three adjacent memory cells (204, 302, 804, 814, 816). [11] The write assist circuit (100, 206, 208, 510, 808) of claim 10, wherein the write assist circuit (100, 206, 208, 510, 808) comprises four PMOS transistors (102, 104, 106, 108) fabricated using four PMOS regions in three rows of the layout area, wherein one of the four PMOS transistors (102, 104, 106, 108) is fabricated in an upper row, two of the four PMOS transistors (102, 104, 106, 108) are fabricated in a middle row, and another of the four PMOS transistors (102, 104, 106, 108) is fabricated in a lower row. [12] The write assist circuit (100, 206, 208, 510, 808) according to claim 10 or 11, wherein the write assist circuit (100, 206, 208, 510, 808) is arranged adjacent to a column (300) of memory cells (204, 302, 804, 814, 816) in the semiconductor memory device (200, 400, 700) such that there is no buffer region between the write assist circuit (100, 206, 208, 510, 808) and the column (300) of memory cells (204, 302, 804, 814, 816). [13] The write assist circuit (100, 206, 208, 510, 808) of any one of claims 10 to 12, wherein the first (102, 104) and second pairs of transistors (106, 108) in the write assist circuit (100, 206, 208, 510, 808) and the memory cells (204, 302, 804, 814, 816) are each fabricated using common design rules for SRAM (Statistical Random Access Memory) transistors. [14] The write assist circuit (100, 206, 208, 510, 808) of any one of claims 10 to 13, wherein a first common fin structure (720) is shared across the first pair of transistors (102, 104) and the memory cells (204, 302, 804, 814, 816) and a second common fin structure (720) is shared across the second pair of transistors (106, 108) and the memory cells (204, 302, 804, 814, 816). [15] The write assist circuit (100, 206, 208, 510, 808) of any one of claims 10 to 14, wherein the first pair of transistors (102, 104) each has a gate terminal that receives a shutdown signal (SD, 114), the shutdown signal (SD, 114) causing the first pair of transistors (102, 104) to disconnect the core voltage bus (VDDAI, 112, 210) from the pull-up voltage (VDD, 110) during a shutdown operation. [16] The write assist circuit (100, 206, 208, 510, 808) of any one of claims 10 to 15, wherein the core voltage bus (VDDAI, 112, 210) is configured to provide power to a column (300) of memory cells (204, 302, 804, 814, 816) in a matrix (202, 800) of memory cells (204, 302, 804, 814, 816) in the semiconductor memory device (200, 400, 700). [17] A method for controlling a semiconductor device (200, 400, 700) comprising a matrix (202, 800) of memory cells (204, 302, 804, 814, 816) arranged in a plurality of rows and columns (300), and one or more write assist circuits (100, 206, 208, 510, 808) in each column (300) of the matrix (202, 800) of memory cells (204, 302, 804, 814, 816), the method comprising the following steps: Providing (930) a core voltage (VDDAI, 112, 210) for memory cells (204, 302, 804, 814, 816) in a column (300) of the matrix (202, 800) of memory cells (204, 302, 804, 814, 816); and Causing (940) the one or more write assist circuits (100, 206, 208, 510, 808) in the column (300) to lower the core voltage (VDDAI, 112, 210) during a write operation, wherein lowering the core voltage (VDDAI, 112, 210) during the write operation comprises: Connecting a pull-up voltage (VDD, 110) to a core voltage bus (VDDAI, 112, 210) by means of a first pair of transistors (102, 104); Receiving an activation signal (LCV_Enb, 118, 214, 518) at a gate of a second pair of transistors (106, 108); and Connecting a pull-down voltage (VSS, 116) to the core voltage bus (VDDAI, 112, 210) by means of the second pair of transistors (106, 108); wherein the one or more write assist circuits (100, 206, 208, 510, 808) and the memory cells (204, 302, 804, 814, 816) have a common SRAM semiconductor layout (400, 700) having a repeating structure of gate regions and active regions, and the one or more write assistant circuits (100, 206, 208, 510, 808) each use a layout area (808) of the common SRAM semiconductor layout (400, 700) which corresponds to an area for three adjacent memory cells (204, 302, 804, 814, 816) in the column (300) of the matrix (202, 800) of memory cells (204, 302, 804, 814, 816). [18] The method of claim 17, wherein the one or more write assist circuits (100, 206, 208, 510, 808) each comprise four PMOS transistors (102, 104, 106, 108) fabricated using four PMOS regions in three rows of the layout area, wherein one of the four PMOS transistors (102, 104, 106, 108) is fabricated in an upper row, two of the four PMOS transistors (102, 104, 106, 108) are fabricated in a middle row, and another of the four PMOS transistors (102, 104, 106, 108) is fabricated in a lower row. [19] The method of claim 17 or 18, wherein the one or more write assist circuits (100, 206, 208, 510, 808) and the array (202, 800) of memory cells (204, 302, 804, 814, 816) are each fabricated using common design rules for SRAM transistors. [20] A method according to any one of claims 17 to 19, further comprising: Providing the enable signal (LCV_Enb, 118, 214, 518) that causes the one or more write assist circuits (100, 206, 208, 510, 808) to connect a core voltage bus (VDDAI, 112, 210) to a pull-down voltage (VSS, 116) during the write operation.

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