Integrated circuit device with improved layout

Abstract

Integrated circuit device, comprising: a component layer (50, 52, 54, 56) which has components (52) spaced apart according to a predetermined component pitch (A); a first metal compound layer (M0) arranged above the component layer (50, 52, 54, 56) and bonded to the component layer; and a second metal compound layer (M1) arranged above the first metal compound layer (M0) and connected to the first metal compound layer via a first via layer (VIA0), wherein the second metal compound layer (M1) comprises metal conductors (62, 206a, 206b, 120a, 120b, 306, 310, 404a, 404b) spaced apart according to a predetermined metal conductor pitch (B), where the ratio of the predetermined metal conductor pitch (B) to the predetermined component pitch (A) is less than 1, where the predetermined component pitch (A) is a pitch of polysilicon conductors of the component layer, and wherein the metal conductors (62, 206a, 206b, 120a, 120b, 306, 310, 404a, 404b) of the second metal compound layer (M1) and the polysilicon conductors of the component layer extend in a first direction; wherein the integrated circuit device comprises a first instance of a device corresponding to a first cell with a first cell layout (204a), and the integrated circuit device further comprises a second instance of a device corresponding to a second cell with a second cell layout (204b), wherein the first cell and the second cell have the same layout on the component layer (50, 52, 54, 56); wherein the first cell has a first metal conductor in the second metal compound layer (M1) and the second cell has a second metal conductor corresponding to the first metal conductor in the second metal compound layer; and wherein the first cell layout and the second cell layout have a common, identically positioned feature, the first metal conductor in a second direction perpendicular to the first direction has a first distance to the common, identically positioned feature in the first cell layout, the second metal conductor in the second direction has a second distance to the common, identically positioned feature in the second cell layout, and a difference between the first distance and the second distance is greater than zero and less than the predetermined metal conductor pitch (B).

Description

GENERAL STATE OF THE ART

[0001] In modern integrated circuits, the shape of connection pins on transistors and other active devices, such as input / output (I / O) pins, is restricted to a rectangular shape. Furthermore, polysilicon traces and connection pins must be arranged on predetermined paths. The typical approach is to place all connection pins on the metal-I (M1) interconnect layer and adjust the pitch of the M1 traces to match the pitch of the polysilicon traces on the device layer. This means a one-to-one (1:1) ratio of M1 trace pitch to polysilicon trace pitch. This approach increases the M1 pitch to match the polysilicon trace pitch and also reduces the amount of routing resources available in the M1 interconnect layer.Furthermore, this approach limits the possibility of arranging component cells directly under power lines formed in the M1 interconnect layer, since both the power lines and all connection pins are located in the M1 layer.

[0002] US 2015 / 0028495A1 describes a system-on-chip comprising a layer with gate lines arranged at a pitch of 96 nm. Several metal compound layers are arranged above the gate line layer. The metal lines of the M1 metal compound layer extend in the same direction as the gate lines, are connected to the gate lines, and have the same pitch of 96 nm. The metal lines of other metal compound layers, such as M2, M3, and M5, each have pitches smaller than 96 nm.

[0003] US 2013 / 0207199A1 describes a variety of cell layouts, wherein in a first cell layout a metal conductor of a met2 metal compound layer is arranged in a top view above a gate electrode conductor, and wherein in a second cell layout a metal conductor of the met2 metal compound layer is arranged in a top view between two gate electrode conductors.

[0004] US 2008 / 0222587A1 describes a method for defining a multi-structured cell layout for use in an integrated circuit design. A layout of one cell layer comprises several layout features, where the layout features are linearly shaped and uniformly aligned. The layout is divided into several sub-layouts for the cell layer. Each layout feature is assigned to one of the sub-layouts. Furthermore, the layout is divided such that each sub-layout can be fabricated. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of the present disclosure are best understood through the following detailed description when read in conjunction with the accompanying drawings. It should be noted that various features are not necessarily drawn to scale. Rather, the dimensions of the various features may be arbitrarily increased or decreased for the sake of clarity of discussion. Fig. Figure 1 illustrates a layout view of the M1 and M0 layers of a component cell for an integrated circuit device according to some embodiments. Fig. Figure 2 is a cross-sectional view of a section of a component cell in which the ratio of M1 conductor pitch to polysilicon conductor pitch is set to 2:3, according to some embodiments. Fig. Figure 3 illustrates features of a cell layout used to design a VIA0 boundary for pin connection optimization, according to some embodiments. Fig. 4A and Fig. Figure 4B illustrates cells arranged at multiple cell locations in a design of an integrated circuit, according to some embodiments. Fig. Figure 5 illustrates alternative positions for an M1 line for different cell layouts of the same component cell according to some embodiments. Fig. Figure 6 illustrates the use of different cell layouts of the same component cell according to some embodiments. Fig. Figure 7 illustrates the different positions of an M1 conductor in different cell layouts of the same component cell according to some embodiments. Fig. Figure 8 is a flowchart illustrating a process for manufacturing an integrated circuit device. DETAILED DESCRIPTION OF EXAMPLES OF EXECUTION

[0006] The following disclosure describes various embodiments for implementing different features of the subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples.

[0007] For example, the formation of a first feature above or on top of a second feature in the following description may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, so that the first and second features may not be in direct contact. Additionally, reference numerals and / or letters may be repeated in the various examples in this disclosure. This repetition is for the sake of simplicity and clarity and does not in itself imply any relationship between the various embodiments and / or configurations discussed.

[0008] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and the like may be used herein to simplify the description and to describe the relationship of one element or feature to other element(s) or feature(s), as illustrated in the figures. These spatially relative terms serve to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the figures. The device may be arranged differently (rotated 90 degrees or with other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0009] The present disclosure provides various embodiments of an integrated circuit structure as well as methods for its fabrication and design. In some embodiments, the integrated circuit structure design increases the M1 routing resources and maximizes the connection pin points. In certain embodiments, when the improved design is used, multiple component cell layouts are employed in the design process to ensure that the M1 trace connection pins lie on M1 traces when the component cell is located at a cell site.

[0010] In certain embodiments, the ratio of M1 trace pitch to polysilicon trace pitch is reduced to less than a 1:1 ratio. In some embodiments, the ratio of M1 pitch to polysilicon trace pitch is 2:3, 3:5, 1:2, or another X:Y ratio, where X is an integer less than an integer Y. In certain embodiments, the ratio is selected, and then the VIA0 boundary, e.g., the VIA0 pin boundary, is designed according to the selected ratio, particularly to maximize the number of pin connection points. In certain embodiments, multiple cell libraries can be used to ensure that all M1 traces and polysilicon traces lie on their respective paths. In certain embodiments, the M0 layer is used for pin connection, which consumes M0 routing resources and frees up M1 routing resources.This allows cells to be easily arranged under an M1 current band.

[0011] Fig. 1 ( Fig. 1) illustrates a layout view of the M1 and M0 layers of a component cell for an integrated circuit device. Fig. Figure 1 shows a single cell 12. In cell 12, the routing resources extending from left to right are located in the M0 layer, and the routing resources extending from bottom to top are located in the M1 layer. More precisely, the cell's connection pins are implemented in the M0 layer. These connection pins could, for example, be input pins. Also implemented in the M0 layer are internal wires 16a and 16b, one of which (wire 16a) is shown lying beneath a power ribbon 18 implemented in the M1 layer. Wire 16a is connected to the power ribbon 18 via a conductive via. In certain embodiments, M1 resources such as M1 output pin 20 connect active components such as NMOS and PMOS transistors of a CMOS cell via M0 output pins 22. Overall, the M0 output pins 22 and the M1 output pins 20 can be considered output pins.

[0012] Fig. 2 ( Fig. 2) is a cross-sectional view of a section of a cell and illustrates an embodiment in which the ratio of M1 pitch to polysilicon pitch is 2:3. A pair of transistor devices are formed on a substrate 50 as shown in Fig. Figure 2 shows the transistor devices having polysilicon gates 52, drain regions 54, and source regions 56. The pitch of the polysilicon conductors forming gates 52 is shown in Fig. 2 labeled with “A”. At least one connection pin 58 is formed in the M0 layer and connected to the polysilicon layer by a contact 60 (e.g., a tungsten (W) contact) formed between the M0 layer and the polysilicon layer. It should be understood that in some embodiments, a cell will have additional pins formed in the M0 layer, which are connected to underlying components (e.g., the gates, source regions, and drain regions) by respective conductive vias or contacts. M1 traces 62 are formed in the M1 layer and connected to the M0 pins via conductive vias 64 formed between them. This layer of vias 64 is referred to as the Via0 layer. The pitch of the M1 traces is in Fig. 2 is labeled "B". As can be seen, the pitch of the M1 lines 62 is smaller than the pitch of the polysilicon lines 52. In the illustrated example, the M1 pitch is two-thirds of the polysilicon line pitch. The M0 layer is used for pin connection. This arrangement—when the M0 layer is used for pin connection and the M1-to-polysilicon line pitch ratio is less than one to one—increases the M1 routing resources compared to a one-to-one M1 line pitch-to-polysilicon line pitch arrangement. It should be understood that pins, such as I / O pins, are defined for the circuitry reflected in a cell. An input pin can be connected to a polysilicon conductor via VIA0, and an output pin in the M1 layer can be connected to a PMOS or NMOS device via M0 wires or be located in the M0 layer.

[0013] In some embodiments, the VIA boundary is designed to maximize the pin connection points. In some embodiments, the VIA0 boundary is designed to maximize the pin connection points. This concept is in Fig. 3 ( Fig. 3) illustrated. In Fig. Figure 3 shows the M1 traces with dashed lines 100a to 100h. The cell boundary is shown at 102. An M0 trace is shown at 104. At an advanced knot, the wire end-to-wire distance between the two M0 wires is equal to the M0_cut width. During processing, a long wire is produced and then cut into two partial wires. Thus, the M0_cut width is the minimum distance between two pins of adjacent cells. The width of the cut of the M0 trace at its ends is shown in Fig. 3 is shown by reference numeral 106 and labeled M0_cut width. The maximum possible length of an M0 trace for a component cell is labeled Max_M0_length and extends between two M0 cuts. A via connection 108 (VIA0) between an M1 trace (not shown) on the M1 track 100a and the M0 trace 104 is shown in Fig. Figure 3 shows the width of any VIA0 connecting an M0 conductor and an M1 conductor, labeled VIA0_width. The M0 boundary (M0_UMG), defined as the distance from the edge of a VIA0 108 connecting the M0 conductor and the outermost M1 conductor (either an M1 conductor on track 100a or track 100h) to the end of the M0 conductor, is labeled reference 110. In other words, the M0 boundary is the distance from the outermost possible edge of an M0 conductor to the edge of the nearest possible VIA0 108. The maximum possible length of the M0 conductor (Max_M0_Length) can be defined by Equation 1 as follows, where X is the number of polysilicon conductor tracks per cell: Max_M0_Length = X * Poly_Pitch - M0_Cutting Width.

[0014] It should be understood that X is the cell width divided by the polysilicon conduction pitch, meaning that X * Poly_Pitch is the cell width. Therefore, the Max_M0_Length is the cell width minus the M0_Cut width. Assuming a 2:3 ratio of M1 conduction pitch to polysilicon conduction pitch as an example, for the same cell area there are five polysilicon conduction paths for all eight M1 conduction paths, and X equals 5. Therefore, for this example, the maximum possible length of an M0 conductor for such a cell is five times the polysilicon conduction pitch minus M0_Cut width.

[0015] The maximum pitch between the M1 lines is in Fig. Figure 3 is shown with reference numeral 112 and labeled Max_M1_PitchLength. This value, Max_M1_PitchLength, is defined by equation 2: Max_M1_Pitchla¨nge=M1_Pitch∗(int(Max_M0_L¨nge / M1_Pitch)−For_M0_Boundary). The variable `For_M0_Umgrenzung` is a small integer such as 0, 1, or 2, representing the number of unused M1 lanes. That is, `For_M0_Umgrenzung` equal to 0 means that all M1 lanes are used, `For_M0_Umgrenzung` equal to 1 means that one M1 lane is unused, and so on. `M1_Pitch` is the average distance between two adjacent M1 lanes (i.e., the distance between adjacent M1 lanes is 100).

[0016] The variable For_M0_Umgrenzung is set to 0 to define an M0_UMG value where the number of connection points is maximized. Using equations 1 and 2, the value of M0_UMG is defined by equation 3: M0_Umg<=(Max_M0_Length−Max_M1_Pitch length−VIA0_Width) / 2.

[0017] As should be obvious, a cell is a layout of a component. If a non-1:1 ratio of M1 trace pitch to polysilicon trace pitch is used for the cell, it may be necessary to have multiple cell layouts for a single component to ensure that the cell's M1 traces are aligned with the M1 traces. This is because the M1 trace pitch is not the same as the polysilicon trace pitch, and the cells may be located at different cell sites on the design area. In a physical design of an integrated circuit, the design is divided into rows, and a row is subdivided into sites. A site is a rectangle with a height equal to the cell height. The cell width is typically a multiple of the polysilicon pitch. Cells are arranged with a cell boundary oriented toward the side edge.As a result, the position of a cell may be laterally offset relative to the predefined M1 traces, meaning that if only one cell layout is used, the M1 trace of some cells may not lie on an M1 trace. Having more than one cell (i.e., more than one cell layout) for each component allows cells to be modified or selected during the design process to ensure that the M1 pins for each cell location lie on the M1 traces. This concept is discussed in the following. Fig. 4A and Fig. 4B ( Fig. 4A and Fig. 4B) illustrates.

[0018] Fig. Figure 4A illustrates a partial view of a layout design for an integrated circuit having multiple rows of cell locations, with each row having multiple locations. Parts of two rows 210 and 220 are shown in Fig. 4A is shown. The cell edges must be aligned with the cell locations. The cell locations are shown by lines 208a to 208j. Row 210 comprises a first cell 200a, whose left edge is aligned with cell location 208a, and a second cell 200b (partially shown), whose left edge is aligned with cell location 208g. Row 220 comprises a third cell 200c, whose left edge is aligned with cell location 208d. M1 traces 202a to 202n are shown extending over the layout area shown. Fig. Figure 4A shows that the same cell layout 204a is used for each of the cells 200a, 200b, and 200c. This cell layout 204a includes an M1 conductor 206a, which is arranged with respect to the cell boundary. As can be seen in row 210, the cells 200a and 200b are oriented with respect to the M1 conductor tracks such that the M1 conductors 206a each lie on M1 conductor tracks, in particular M1 conductor tracks 202d and 202m for cells 200a and 200b. However, if the same cell layout 204a is used in row 220, particularly for cell 200c, and the ratio of M1 conductor pitch to polysilicon conductor pitch is not 1:1, the M1 conductor 206a is not on an M1 conductor track, i.e., it lies between M1 conductor tracks 202h and 202i, which violates design rules. In particular, it is evident that the position of cell 200c with respect to the M1 conductor tracks 202 results in the M1 conductor 206a of cell layout 204a being between, and not on, M1 conductor tracks.M1 lines 202h and 202i, is located.

[0019] With reference to Fig. Figure 4B shows that in row 220, a different cell layout 204b is used than cell layout 204a for cell 200c. Compared to cell layout 204a, the difference is that cell layout 204b has the M1 line 206b in a different position relative to the cell boundary (or any other common reference feature, e.g., an M0 line), such that the M1 line 206b now lies on an M1 trace, in particular on M1 trace 202i. In some embodiments, the M0 line position can also differ between two cell layouts for the same component.

[0020] Assuming an M1 conductor pitch to polysilicon conductor pitch ratio of X:Y, the number of cell layouts required is at least the least common multiple of X and Y divided by Y. For example, if the pitch ratio is 2:3, the number of cell layouts required is at least 2 (i.e., (2*3) / 3). If the pitch ratio is instead 3:5, the number of cell layouts required is at least 3 (i.e., (3*5) / 5). It should be understood that additional cell layouts may be required due to other rule constraints.

[0021] Several different cell layouts for a given component are developed by offsetting the center of the M1 wire in the different cell layouts by a specified amount. The offset of any two layouts of a cell can be different. The minimum of the M1 offsets of any two layouts is referred to here as the minimum offset. The minimum offset is, for example, equal to the M1 pitch divided by the number of layouts required. If the ratio of M1 wire pitch to polysilicon wire pitch is, for example, 2:3, then the offset between layouts is ½ * M1 pitch, since the 2:3 ratio dictates that a maximum of two layouts are required. As another example, if the ratio of M1 wire pitch to polysilicon wire pitch is 3:5, then the offset between layouts is 1 / 3 * M1 pitch, since the 3:5 ratio dictates that a maximum of three layouts are required.

[0022] This concept is in Fig. 5 ( Fig. 5) illustrates which of the layouts discussed above consist of Fig. 3 used. As in Fig. As can be seen in Figure 5, the pitch between M1 conductors is shown as A. In a first layout, M1 conductor 120a is positioned such that, for a first cell location, it lies directly on top of M1 conductor 100a. However, for the 2:3 ratio discussed above, another cell location may be offset by an amount equal to ½ * M1 pitch relative to these M1 conductors. Therefore, a second cell layout is required, which includes M1 conductor 120b that is offset laterally by ½ * M1 pitch from the position of M1 conductor 120a in the first cell layout. This second cell layout is used when the component cell is to be located at a cell site position where using the first cell layout (i.e., the layout that has the M1 trace 120a) would cause the M1 trace to miss the M1 trace. Therefore, at this cell site position, the second layout (i.e.,the layout which has the M1 conductor 120b arranged as illustrated) is used. This method ensures that the M1 conductor lies in the center of the M1 conductor path.

[0023] This concept, i.e., when multiple cell layouts corresponding to a component cell are available for use when a non-1:1 ratio of M1 conductor to polysilicon conductor is used, is defined by Fig. 6 ( Fig. 6) further illustrated. As in Fig. As shown in Figure 6, a region of an integrated circuit design is traversed by predefined M1 traces 300a, 300b, 300c, 300d, and 300e. The M1 trace pitch to polysilicon trace pitch is set to 2:3 for this example. Fig. Figure 6 shows four possible locations 302a, 302b, 302c, 303d for polysilicon conductors in relation to the M1 conductor paths 300a, 300b, 300c, 300d and 300e. As shown from Fig. As can be seen in Figure 6, the path positions with respect to the boundaries of sites 302 are repeated every two sites. That is, for sites 302a and 302c, the M1 conductor paths 300 (i.e., 300a and 300d) are located in the center of site 302, while for sites 302b and 302d, the M1 conductor paths 300 (i.e., 300b, 300c, and 300e) are located closer to the lateral edges of sites 302b and 302d. As shown in Fig. As shown in Figure 6, if a cell is to be located in a first cell location position 302b, a first cell layout 304 is used, which has an M1 line 306 aligned near a lateral edge of the cell layout 304, such that the M1 line 306 lies on an M1 conductor track 300 (in this case, M1 conductor track 300b). If a cell is to be located in a second cell location position 302c, a second cell layout 308 is used, which has an M1 line 310 aligned at a center of the cell layout 308, such that the M1 line 310 lies on an M1 track 300 (in this case, M1 track 300d).In summary, for a 2:3 ratio of M1 conductor pitch to polysilicon conductor pitch, a cell layout with two different layouts for the M1 conductor orientation is provided, and in some embodiments, the cell layout M1 orientation is selected depending on where the cell is to be positioned in relation to the M1 conductor paths.

[0024] Fig. 7 ( Fig. Figure 7 shows two different cell layouts, 400A and 400B, for comparison purposes. In some embodiments, the cell layouts on the M0 layer, which has left-to-right extending M0 traces 402, are identical. Pins in the M0 layer are shown without cross-hatching, whereas inner wires in the M0 layer are shown with cross-hatching. The cells are oriented differently with respect to their alignment with the M1 traces 408. Assuming a fixed reference point in the device, such as features in the M0 layer (e.g., an M0 pin) or device layer (e.g., polysilicon gate trace), the position of the M1 trace 404a in cell 400A is therefore offset from the position of the M1 trace 404b in cell 400B. This offset is referred to as the M1 offset.The offset is clearly visible by comparing the position of the vias 406a in the VIA0 layer in cell 400A with the position of the vias 406b in the VIA0 layer in cell 400B. The offset is particularly evident where the vias 406a and 406b are connected to the M0 lines 402, especially to the M0 pins 402a and 402b, in cell layouts 400A and 400B.

[0025] Fig. 8 ( Fig. 8) A Method 500 illustrates the design and fabrication of an integrated circuit according to a generated integrated circuit design when the M1 trace pitch is smaller than the pitch of the polysilicon traces. For example, the pitch ratio in some embodiments could be 2:3, 3:5, or 1:2, as discussed above. In Step 502, multiple cell layouts for a device or devices are generated and stored as standard cells. That is, these cell layouts can correspond to basic devices, such as NAND gates, NOR gates, inverters, or other basic devices that can be used to fabricate a larger, more complex circuit. Multiple cell layouts for each device are stored in the cell library.Assuming a 2:3 pitch ratio implementation, for example, two different cell layouts with different M1 trace positions, offset from each other by ½ * M1 pitch, are stored for a given device. In some embodiments, the two cell layouts may be identical (i.e., on the device and M0 layers) except for the offset M1 trace positions and the Via0 connection to these M1 traces. In other embodiments, design requirements or constraints may dictate that the cell layouts also differ on the M0 layer.

[0026] In step 504, a location (i.e., a rectangular area with a height equal to the cell height and a width equal to the polysilicon pitch) is selected on a design area for arranging the component cell. Referring again to Fig. For example, in 4B a location within the 210 or 220 series is selected for the component cell.

[0027] In step 506, one of the several cell layouts for the component (which are generated and saved in step 502) is selected for this cell location, ensuring that the M1 trace(s) lies on M1 trace(s).

[0028] Step 508 creates the routing layout. This involves creating the layout of metal segments and vias for connecting multiple pins of cells. The routing layout can be developed using software such as the INNOVUS™ Implementation System from Cadence Design Systems Inc. of San Jose, California, on a PC, workstation, or other processing environment. In fact, this software tool (or another) can be used in some embodiments to perform steps 502 through 510. Fig. 8 can be used.

[0029] In step 510, the design (cell layout and routing) is saved in LEF / DEF format, and in certain implementations, in a database or other data storage. Layout Exchange Format (LEF) defines the elements of an IC process technology and its associated cell model library. Design Exchange Format (DEF) defines the elements of an IC design that are relevant for a physical layout, including netlist and design dependencies. That is, the LEF format can be used to represent cells, and the DEF format can be used to represent arrangement and routing.

[0030] Finally, in step 512, this stored design (i.e., the design stored in step 510) is then used in a fabrication process for an integrated circuit. The stored design is used, for example, to create the masks used in the fabrication process. These masks are then used in the fabrication of the various layers that make up the integrated circuit on a wafer.

[0031] In some embodiments, selecting a non-1:1 ratio of M1 trace pitch to polysilicon lead pitch, such as a 2:3 ratio, allows the use of an M0 pin that would otherwise be located on M1, thus saving routing resources. For example, in some embodiments, a 2:3 ratio for a 7 nm or 7 nm+ generation integrated circuit structure can save 40% of M0 metal resources and 50% of M1 metal resources. In some embodiments, the techniques described herein are applied to, but not limited to, a 7 nm (package size) generation as well as lower generations, such as 5 nm and 3 nm.In some embodiments, the generation is a 7-nm+ (N7+) generation, such as that of the current applicant, which is a 7-nm generation with some layers processed using EUVL. This improves yields and reduces fabrication cycle times, while simultaneously resulting in improved power consumption and a 15-20% area scaling compared to the first-generation 7-nm process. The 7-nm+ generation can feature reduced-size logic and routing areas compared to the standard 7-nm generation. Therefore, the techniques described herein can be particularly beneficial in the design and fabrication of N7+ generation integrated circuits.

[0032] The teachings of this disclosure can be implemented in the form of methods and an apparatus for implementing these methods. These embodiments can also be implemented in the form of program code executed on tangible media, such as Secure Digital (“SD”) cards, USB flash drives, floppy disks, CD-ROMs, DVD-ROMs, Blu-ray Discs, hard disks, or any other non-volatile, machine-readable storage medium, wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine becomes the apparatus for implementing the teachings of this disclosure.The teachings of the present disclosure can, for example, also be implemented in the form of program code, whether stored in a storage medium, loaded into a machine and / or executed by it, or transmitted via a transmission medium such as electrical wiring or cables, optical fibers, or electromagnetic radiation. When the program code is loaded into a machine, such as a computer, and executed by it, the machine becomes a device for implementing the embodiment. When implemented in a general-purpose computer, portions of the program code are combined with the processor to provide a unique device that operates analogously to certain logic circuits.

[0033] A computer system can be used to implement embodiments disclosed herein. Although other application-specific alternatives may be used, it should be understood that embodiments disclosed herein may be implemented in hardware, software, or a combination thereof by one or more compatible processing systems, unless otherwise specified.

[0034] The computer system, as described in one example, comprises elements connected via communication channels (e.g., a bus), including one or more general-purpose or specialized computers. Elements of the computer system may also include one or more input devices (such as a mouse, keyboard, microphone, stylus, etc.) and one or more output devices, such as a suitable display, speakers, actuators, etc., depending on the specific application.

[0035] The computer system also includes a reader for computer-readable storage media, which is connected to a computer-readable storage medium, for example, a storage / data storage device or removable storage / data storage media; such devices or media being further identified separately as storage device and data storage, which, according to a particular application, may include hard disk variants, floppy disk / compact disc variants, digital versatile disc ("DVD") variants, smart cards, read-only storage, random access storage, cache storage, etc. It may also include one or more suitable communication devices, for example, a modem, DSL, an infrared or other suitable transceiver, etc., to provide cross-device communication, directly or via one or more suitable private or public networks, which may include, but are not limited to, those already discussed.

[0036] A working memory also includes elements of an operating system (“OS”) and other programs, such as application programs, mobile code, data, etc., for implementing implementation elements that can be loaded or stored in it during use. The specific OS may vary according to a particular device, features, or other aspects specific to a given application (e.g., variants of Windows, Mac, Linux, Unix, or Palm OS, a proprietary OS, etc.). Various programming languages ​​or other tools may also be used, such as C++, Java, Visual Basic, etc.

[0037] One or more elements of the computer system may be implemented in hardware, software, or another suitable combination. When implemented in software (e.g., as an application program, object, downloadable, servlet, etc., in whole or in part), an element of the computer system may be temporarily or permanently transferred from local or remote storage to working memory (or cache, etc.) for execution, or some other suitable mechanism may be used, and elements may be implemented in compiled or interpreted form. Furthermore, input, intermediate, or output data, or functional elements, may reside temporarily or permanently in storage media, a cache, or more persistent, volatile, or non-volatile memory (e.g., the storage device or data storage), depending on a particular application.

[0038] As described herein, certain embodiments employ an integrated circuit layout in which the ratio of M1 lead pitch to polysilicon lead pitch is not 1:1, and in particular, is a ratio in which the M1 lead pitch is smaller than the polysilicon lead pitch. In some embodiments, this approach to cell layout, by shifting the connection pins to the M0 layer, frees up M1 interconnect layer resources. This, in turn, advantageously allows device cells to be arranged directly under current bands in the M1 interconnect layer.In some embodiments, the manufacturing processes are adapted such that multiple cell layouts are available for a given component, enabling the selection of a cell layout that ensures the M1 traces lie on predefined M1 tracks when using a non-1:1 ratio of M1 trace pitch to polysilicon trace pitch. In certain embodiments, the selection of a given cell layout can be integrated and automated within the existing design and manufacturing process.

[0039] The invention is defined by the main claim and the dependent claims. The subclaims describe further embodiments of the invention.

Claims

[1] Integrated circuit device comprising: a component layer (50, 52, 54, 56) which has components (52) spaced apart according to a predetermined component pitch (A); a first metal compound layer (M0) arranged above the component layer (50, 52, 54, 56) and bonded to the component layer; and a second metal compound layer (M1) arranged above the first metal compound layer (M0) and connected to the first metal compound layer via a first via layer (VIA0), wherein the second metal compound layer (M1) comprises metal conductors (62, 206a, 206b, 120a, 120b, 306, 310, 404a, 404b) spaced apart according to a predetermined metal conductor pitch (B), where the ratio of the predetermined metal conductor pitch (B) to the predetermined component pitch (A) is less than 1, where the predetermined component pitch (A) is a pitch of polysilicon conductors of the component layer, and wherein the metal conductors (62, 206a, 206b, 120a, 120b, 306, 310, 404a, 404b) of the second metal compound layer (M1) and the polysilicon conductors of the component layer extend in a first direction; wherein the integrated circuit device comprises a first instance of a device corresponding to a first cell with a first cell layout (204a), and the integrated circuit device further comprises a second instance of a device corresponding to a second cell with a second cell layout (204b), wherein the first cell and the second cell have the same layout on the component layer (50, 52, 54, 56); wherein the first cell has a first metal conductor in the second metal compound layer (M1) and the second cell has a second metal conductor corresponding to the first metal conductor in the second metal compound layer; and wherein the first cell layout and the second cell layout have a common, identically positioned feature, the first metal conductor in a second direction perpendicular to the first direction has a first distance to the common, identically positioned feature in the first cell layout, the second metal conductor in the second direction has a second distance to the common, identically positioned feature in the second cell layout, and a difference between the first distance and the second distance is greater than zero and less than the predetermined metal conductor pitch (B). [2] Integrated circuit device according to claim 1, wherein the ratio X:Y is, where X and Y are integer values. [3] Integrated circuit device according to claim 2, wherein X is equal to 2 and Y is equal to 3. [4] Integrated circuit device according to claim 2, wherein X is equal to 3 and Y is equal to 5. [5] Integrated circuit device according to claim 3 or 4, wherein the difference between the first distance and the second distance is equal to the predetermined metal conductor pitch divided by X. [6] Integrated circuit device according to one of the preceding claims, wherein the first cell comprises at least one cell connection pin in the first metal compound layer (M0) and at least one cell connection pin in the second metal compound layer (M1). [7] Integrated circuit device according to claim 6, further comprising a current band formed in the second metal compound layer (M1), wherein the cell is arranged under the current band. [8] Integrated circuit device according to claim 6 or 7, wherein the first cell corresponds to the equation M0_Umg ≤ (Max_M0_Length - Max_M1_Distance - VIA0_Width) / 2, wherein: Max_M0_Länge represents the maximum possible length of a conductor in the first metal compound layer (M0) in the first cell; Max_M1_Abstand represents the maximum possible distance between two conductors in the second metal compound layer (M1) in the first cell; VIA0_width represents the width of a via that connects a conductor in the first metal interconnect layer (M0) to a conductor in the second metal interconnect layer (M1); and M0_Umg represents a distance from an outermost edge of the conductor in the first metal interconnect layer (M0) to an edge of the nearest possible via that connects the conductor in the first metal interconnect layer to the conductor in the second metal interconnect layer (M1). [9] Integrated circuit device according to one of the preceding claims, wherein the first cell and the second cell each correspond to a NAND device, or the first cell and the second cell each correspond to a NOR device, or the first cell and the second cell each correspond to an inverter. [10] Integrated circuit device according to any of the preceding claims, wherein the integrated circuit device has predetermined track positions (100a - 100h, 202a - 202n, 300a - 300e) for the metal conductors (62, 206a, 206b, 120a, 120b, 306, 310, 404a, 404b) in the second metal compound layer (M1), and wherein the first metal conductor (62, 206a, 206b, 120a, 120b, 306, 310, 404a, 404b) of the first cell and the second metal conductor of the second cell are shifted in the second direction so that they are each aligned at one of the predetermined track positions (100a - 100h, 202a - 202n, 300a - 300e). [11] Integrated circuit device comprising: a first instance of a device that is manufactured at a first position (302a, 302c) according to a first cell layout (204a); and a second instance of a device manufactured at a second position (302b, 302d) according to a second cell layout (204b); wherein the cell layouts (204a, 204b) comprise a component layer (50, 52, 54, 56), a first metal compound layer (M0) arranged above and connected to the component layer, and a second metal compound layer (M1) arranged above the first metal compound layer and connected to the first metal compound layer via a first via layer (VIA0), where in the cell layouts (204a, 204b) the ratio of a predefined metal conduction pitch (B) in the second metal compound layer (M1) to a predefined polysilicon conduction pitch in the component layer (50, 52, 54, 56) is less than 1, wherein the first and second cell layouts (204a, 204b) differ with respect to a relative position of at least one metal conductor (62, 206a, 206b, 120a, 120b, 306, 310, 404a, 404b) in the second metal compound layer (M1) with respect to a common feature in the cell layouts; wherein the positions of the at least one metal conductor (62, 206a, 206b, 120a, 120b, 306, 310, 404a, 404b) in the second metal compound layer in the first and second cell layouts (204a, 204b) are laterally offset from each other by more than zero and less than the predefined metal conductor pitch with respect to the common feature in the cell layouts; and where: the first cell layout and the second cell layout each correspond to a NAND device, or the first cell layout and the second cell layout each correspond to a NOR element, or The first cell layout and the second cell layout each correspond to an inverter. [12] Integrated circuit device according to claim 11, wherein the ratio of the predefined metal conductor pitch (B) in the second metal compound layer (M1) to the predefined polysilicon conductor pitch in the component layer (50, 52, 54, 56) is 2:3 or 3:

5. [13] Integrated circuit device according to claim 11 or 12, wherein the cell layouts (204a, 204b) comprise at least one connection pin in the second metal compound layer (M1) and at least one connection pin in the first metal compound layer (M0). [14] Integrated circuit device according to one of claims 11 to 13, wherein the cell layouts (204a, 204b) of the equation M0_Umg≤(Max_M0_L¨nge−Max_M1_Abstand−VIA0_Breite) / 2 correspond to where: Max_M0_Länge represents a maximum possible length of a conductor in the first metal compound layer (M0) in the cell layouts (204a, 204b); Max_M1_Abstand represents a maximum possible distance between two conductors in the second metal interconnect layer (M1) in the cell layouts (204a, 204b); VIA0_width represents the width of a via that connects a conductor in the first metal interconnect layer (M0) to a conductor in the second metal interconnect layer (M1); and M0_Umg represents a distance from an outermost edge of the conductor in the first metal interconnect layer (M0) to an edge of the nearest possible via that connects the conductor in the first metal interconnect layer to the conductor in the second metal interconnect layer (M1). [15] Method (500) for manufacturing an integrated circuit device, comprising: Selecting (504) a first location in a design of an integrated circuit from several cells for a device in which the cells have different cell layouts (204a, 204b); Select (506) one of the cells for the device for the first location; Create (508) a routing layout after selecting one of the cells; Save (510) the routing layout; and Manufacture (512) the integrated circuit device using the stored layout, wherein each cell comprises a component layer (50, 52, 54, 56), a first metal compound layer (M0) arranged above and connected to the component layer, and a second metal compound layer (M1) arranged above the first metal compound layer and connected to the first metal compound layer via a first via layer (VIA0), where in the cell the ratio of a predefined metal conduction pitch (B) in the second metal compound layer (M1) to a predefined polysilicon conduction pitch in the component layer (50, 52, 54, 56) is less than 1; wherein the multiple cells for the device comprise a first and a second cell, wherein the first and the second cell differ with respect to the relative position of at least one metal conductor (62, 206a, 206b, 120a, 120b, 306, 310, 404a, 404b) in the second metal compound layer (M1) with respect to a common feature in the cells; wherein the positions of the at least one metal conductor (62, 206a, 206b, 120a, 120b, 306, 310, 404a, 404b) in the second metal compound layer in the first cell and the second cell are laterally offset from each other by more than zero and less than the predefined metal conductor pitch with respect to the common feature in the cells; and where the first cell and the second cell have the same layout on the component layer (50, 52, 54, 56). [16] Method (500) according to claim 15, further comprising the step of selecting another of the cells for a second location which differs from the first location. [17] Method (500) according to claim 15 or 16, wherein the ratio is X:Y, where X and Y are integer values. [18] Method (500) according to any one of claims 15 to 17, wherein each cell corresponds to the equation M0_Umg ≤ (Max_M0_Length - Max_M1_Distance - VIA0_Width) / 2, wherein: Max_M0_Länge represents the maximum possible length of a conductor in the first metal compound layer (M0) in the cell; Max_M1_Abstand represents the maximum possible distance between two conductors in the second metal compound layer (M1) in the cell; VIA0_width represents the width of a via that connects a conductor in the first metal interconnect layer (M0) to a conductor in the second metal interconnect layer (M1); and M0_Umg represents a distance from an outermost edge of the conductor in the first metal interconnect layer (M0) to an edge of the nearest possible via that connects the conductor in the first metal interconnect layer to the conductor in the second metal interconnect layer (M1).

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