Capacitorless voltage regulator and semiconductor device incorporating the same

Abstract

Voltage regulator, comprising: a voltage converter (110; 110a) configured to generate an output supply voltage (VDD_OUT) based on an input supply voltage (VDD_IN) and an input reference voltage (VBREF) and to provide the output supply voltage (VDD_OUT) to an external functional circuit (200), wherein the voltage converter (110; 110a) has an output terminal (TOUT) configured to output the output supply voltage (VDD_OUT); and a sink (120) connected to the output terminal (TOUT), the sink (120) being configured to generate a sink current (ISINK) in response to a sink enable signal (SINK_EN) while the external functional circuit (200) is not driven, and being configured to block generation of the sink current (ISINK) in response to an operation enable signal (OP_EN) while the external functional circuit (200) is driven, wherein the sink current (ISINK) corresponds to a load current (ILOAD) consumed while the external functional circuit (200) is driven.

Description

BACKGROUND1. Field of TechnologyEmbodiments relate generally to semiconductor devices, and more particularly to voltage regulators that generate supply voltages that are provided to semiconductor integrated circuits and that operate without external capacitors, semiconductor devices that include these voltage regulators, and methods for generating supply voltages.2. DESCRIPTION OF THE RELATED ARTTypically, a semiconductor device includes a semiconductor integrated circuit that performs a certain function and a power supply circuit for supplying power to the semiconductor integrated circuit. For example, a semiconductor memory device may include a memory cell array in which data is stored and a voltage regulator that sends an operating voltage to the memory cell array. The voltage regulator is driven by an external capacitor or an output capacitor which is connected to an output terminal of the voltage regulator and has a relatively high capacitance. Even if a load current flowing through a load is suddenly changed, due to the external capacitor, a supply voltage output from the voltage regulator may not be suddenly changed, and the voltage regulator may stably supply the supply voltage. However, the voltage regulator occupies a considerable part of the space in the semiconductor device because of the external capacitor. In order to reduce the size of a semiconductor device, various research projects are made by researchers with respect to a technique of a capacitorless (or capless) voltage regulator that operates without an external capacitor.German laid-open specification DE 10 2005 029 110 A1 describes a digital circuit unit in which a circuit block, a detection unit which monitors a change in a current consumption by the at least one circuit block, has a current consumption unit and a control unit on a chip, wherein the control unit controls the current consumption unit such that the current consumption unit is activated upon a change in the current consumption of the circuit block and receives current, wherein the detection unit monitors the load change and is capable of predicting the future current consumption.U.S. Pat. No. 5,987,615 A describes a parasitic load compensation circuit with a controllable additional load.German laid-open specification DE 10 2011 051 033 A1 describes the use of auxiliary currents for voltage regulation, e.g. digital circuits.Document WO 02 / 093 340 A1 describes a system of a wide band power control with control circuitry for current control using a sink.SUMMARYA voltage regulator includes: a voltage converter configured to generate an output supply voltage based on an input supply voltage and an input reference voltage, and provide the output supply voltage to an external functional circuit, the voltage converter including an output terminal configured to output the output supply voltage; and a drain connected to the output terminal, the drain configured to generate a drain current while the external functional circuit is not driven in response to a drain enable signal, and configured to block generation of the drain current while the external functional circuit is driven in response to an operation enable signal, the drain current corresponding to a load current consumed while the external functional circuit is driven.A semiconductor device includes: an external function circuit configured to operate based on an output supply voltage; a voltage regulator configured to generate the output supply voltage based on an input supply voltage and an input reference voltage, generate a sink current in response to a sink enable signal while the external function circuit is not driven, and block generation of the sink current while the external function circuit is driven in response to an operation enable signal; and a controller configured to control the external function circuit and the voltage regulator, wherein the sink current corresponds to a load current consumed while the external function circuit is driven.An unclaimed method for generating a supply voltage includes: generating an output supply voltage based on an input supply voltage and an input reference voltage and providing the output supply voltage to an external function circuit; generating a sink current in response to a sink enable signal while the external function circuit is not driven; and blocking generation of the sink current in response to an operation enable signal while the external function circuit is driven, wherein the sink current corresponds to a load current consumed while the external function circuit is driven.BRIEF DESCRIPTION OF THE DRAWINGSThe above and other features and advantages of embodiments of the inventive ideas will become more apparent by detailed description of embodiments of the inventive ideas with reference to the accompanying drawings. The accompanying drawings are intended to depict embodiments of the inventive ideas and should not be taken as limiting the intended scope of the claims. The accompanying drawings are not to be taken as true to scale unless expressly so indicated. FIG. 1 is a block diagram illustrating a voltage regulator according to at least some embodiments for the inventive ideas. FIG. 2 is a timing diagram for describing an operation of a voltage regulator according to at least some embodiments of the inventive ideas. FIG. 3 is a circuit diagram illustrating an example of a voltage converter included in a voltage regulator according to at least some embodiments of the inventive ideas. FIG. 4 is a block diagram illustrating an example of a sink logic circuit included in the voltage regulator of FIG. 1. FIG. 5 is a block diagram illustrating a voltage regulator according to at least some embodiments for the inventive ideas. FIG. 6 is a time chart for describing an operation of a high voltage limiter included in the voltage regulator of FIG. 5. FIG. 7 is a block diagram illustrating an example of a sink logic circuit included in the voltage regulator of FIG. 5. FIG. 8 is a block diagram illustrating a voltage regulator according to at least some embodiments for the inventive ideas. FIG. 9 is a time chart for describing an operation of a clock generator included in the voltage regulator of FIG. 8. FIG. 10 is a block diagram illustrating a voltage regulator according to at least some embodiments for the inventive ideas. FIG. 11 is a block diagram illustrating a semiconductor device according to at least some embodiments of the inventive ideas. FIGS. 12, 13 and 14 are flowcharts illustrating a method of generating a supply voltage according to at least some embodiments of the inventive ideas.DETAILED DESCRIPTION OF THE EMBODIMENTSAs is conventional in the art of inventive ideas, embodiments are described by means of function blocks, units and / or modules and are illustrated in the drawings. Those skilled in the art will appreciate that these blocks, units, and / or modules may be implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wirings, and the like, which may be formed using semiconductor-based fabrication methods or other fabrication techniques. In the case where the blocks, units, and / or modules are implemented by microprocessors or the like, they may be implemented using software (e.g., microcode) to perform various functions discussed herein, and may optionally be driven by firmware and / or software. Alternatively, the blocks, units, and / or modules may each be implemented by dedicated hardware or as a combination of dedicated hardware to perform some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) to perform other functions. Likewise, the blocks, units, and / or modules of the embodiments may each be physically separated into two or more interacting and discrete blocks, units, and / or modules without departing from the inventive concepts. Further, the blocks, units, and / or modules of the embodiments may be physically combined into multiple complex blocks, units, and / or modules without departing from the scope of the inventive concepts.FIG. 1 is a block diagram illustrating a voltage regulator according to at least some embodiments for the inventive ideas.As shown in FIG. 1, a voltage regulator 100 includes a voltage converter 110 and a drain 120.The voltage converter 110 generates an output supply voltage VDD_OUT based on an input supply voltage VDD_IN and an input reference voltage VBREF. The voltage converter 110 has an output terminal TOUT, which outputs the output supply voltage VDD_OUT. The voltage converter 110 may be configured to generate a stable supply voltage (e.g., stably generate the output supply voltage VDD_OUT). A configuration of the voltage converter 110 will be described in detail with reference to FIG. 3.The output supply voltage VDD_OUT is provided to an external function circuit 200 arranged or placed outside the voltage regulator 100. In other words, the functional circuit 200 may operate or be driven on the basis of the output supply voltage VDD_OUT. Although not illustrated in FIG. 1, a drive clock signal may be additionally provided to the functional circuit 200, and the functional circuit 200 may operate or be driven based on the drive clock signal. While the functional circuit 200 operates or is driven on the basis of the output supply voltage VDD_OUT and / or the drive clock signal, a load current ILOAD may additionally be consumed.In some embodiments, the functional circuit 200 may be any semiconductor integrated circuit that performs specific or alternatively predetermined functions. For example, the function circuit 200 may include a data storage circuit including, for example, a memory cell array, a display control circuit, any signal processing circuit such as an image signal processing circuit, or the like.The drain 120 is connected to the output terminal TOUT via an output node NOUT. The sink 120 generates a sink current ISINKin response to a sink enable signal SINK_EN, while the function circuit 200 is not driven. The sink current ISINKcorresponds to the load current ILOADthat needs to be consumed while the function circuit 200 is driven. The sink 120 inhibits generation of the sink current ISINK, while the function circuit 200 is driven, in response to an operation enable signal OP_EN. In other words, the depression 120 and the function circuit 200 can be complementarily actuated. While function circuit 200 is disabled (e.g., not driven), drain 120 may be enabled to generate drain current ISINK. While function circuit 200 is enabled (e.g., driven), drain 120 may be disabled and may not generate drain current ISINK.According to at least some exemplary embodiments of the inventive ideas, the intensity of the load current ILOADmay be predefined. For example, the magnitude of the load current ILOADmay be determined before the functional circuit 200 is mass produced (e.g., at a time when the functional circuit 200 is designed or trial copies of the functional circuit 200 are produced). The voltage regulator 100 including the drain 120 may be manufactured such that the drain current ISINKcorresponding to the load current ILOADis generated based on the predetermined magnitude of the load current ILOAD.In some embodiments, sink 120 may include a current generator 130 and a sink logic circuit 140.The current generator 130 may be connected to the output terminal TOUT via the output node NOUT. The current generator 130 may generate the sink current ISINKin response to a first control signal CS 1. The current generator 130 may include a plurality of current level controllers 130 a, 130 b, 130 c,..., 130 n. The plurality of current level controllers 130 a, 130 b, 130 c,..., 130 nmay be connected in parallel between the output terminal TOUT (e.g., the output node NOUT) and the ground voltage. The plurality of current level controllers 130 a, 130 b, 130 c,..., 130 nmay be selectively turned on in response to the first control signal CS 1. In FIG. 1 and the following drawings, an inverted triangle (e.g., V) connected to an electrode of a transistor or an end of a resistor may represent the ground voltage (e.g., GND or VSS voltage).Each of the plurality of current level controllers 130 a, 130 b, 130 c,..., 130 nmay each include one of a plurality of resistors R 1, R 2, R 3,..., RNand each one of a plurality of transistors T 1, T 2, T 3,..., TN. For example, the first current level controller 130 amay include the first resistor R 1 and the first transistor T 1, the second current level controller 130 bmay include the second resistor R 2 and the second transistor T 2, the third current level controller 130 cmay include the third resistor R 3 and the third transistor T 3, and the Nth current level controller 130 nmay include the Nth resistor RN and the Tth transistor Tn, where N is a natural number. Each of the plurality of resistors R 1, R 2, R 3,..., RN may be connected to the output terminal TOUT via the output node NOUT. Each of the plurality of transistors T 1, T 2, T 3,..., TN may be connected between each of the plurality of resistors R 1, R 2, R 3,..., RN and the ground voltage. Each of the plurality of transistors T 1, T 2, T 3,..., TN may include a control electrode that receives the first control signal CS 1.The sink logic circuit 140 may generate the first control signal CS 1 based on a first clock signal CLK 1, the sink enable signal SINK_EN, and the operation enable signal OP_EN. For example, the operation enable signal OP_EN may be provided from the function circuit 200. A configuration of the sink logic circuit 140 will be described in detail with reference to FIG. 4.In some embodiments, the first control signal CS 1 may be an N-bit control signal. For example, first to N-th bits of the first control signal CS 1 may be applied to the control electrodes of the plurality of transistors T 1, T 2, T 3,..., TN, respectively. For example, the N bits of the N-bit control signal CS 1 may be provided to the current generator 130 via N signal lines connected between the sink logic circuit 140 and the N transistors T 1-TN, such that the N bits of the N-bit control signal CS 1 may be used to independently control the current level controllers 130 a, 130 b, 130 c,..., 130 n. The number of the turned-on current level controllers of the plurality of current level controllers 130 a, 130 b, 130 c,..., 130 n(e.g., the number of the turned-on transistors of the plurality of transistors T 1, T 2, T 3,..., TN) may be adjusted or controlled based on the first control signal CS 1, and thus the magnitude of the sink current ISINKmay be adjusted or controlled. For example, the magnitude of the sink current ISINKmay increase (or decrease) as the number of turned-on current level controllers increases (or decreases).In some embodiments, resistance values of the plurality of resistors R 1, R 2, R 3,..., RN may be substantially the same as or different from each other among each other.FIG. 2 is a timing diagram for describing an operation of a voltage regulator according to at least some embodiments of the inventive ideas.As shown in FIGS. 1 and 2, before a time t 1, the voltage converter 110 generates the output supply voltage VDD_OUT having a target power level VDDT.At time t 1, the sink enable signal SINK_EN is activated by transitioning from a low logic level to a high logic level, and the sink 120 is enabled. When function circuit 200 is to be driven or used, drain 120 is enabled to generate drain current ISINKbefore function circuit 200 is enabled to perform specific or alternatively predetermined functions.A level of the sink current ISINKincreases stepwise (e.g., stepwise, gradually, step by step, or stepwise) from a zero level ISNto a target level ISTin response to activation of the sink enable signal SINK_EN(e.g., in response to a rising edge of the sink enable signal SINK_EN). In this case, a change or variation in the level of the output power supply voltage VDD_OUT may be reduced or minimized by stepwise increase in the level of the sink current ISINK.The zero level ISNmay be indicative of no sink current ISINKbeing generated, and the target level ISTmay correspond to the load current ILOAD. For example, the zero level ISNmay be about 0 mA and the target level ISTmay correspond to an operating level ILO, i.e., a level of the load current ILOADwhen the functional circuit 200 is actually operating or driven.Since the function circuit 200 is not actually operating or is not actually driven at time t 1, the operation enable signal OP_EN is disabled to maintain a logic low level and the load current ILOADhas an open circuit level ILN. In other words, the open circuit level ILN means that the function circuit 200 does not actually operate or is not actually driven. Unlike the zero level ISN, the open circuit level ILN may not be about 0 mA because a leakage current is generated from the function circuit 200 even when the function circuit 200 does not actually operate or is not actually driven.At a time t 2, based on the output supply voltage VDD_OUT, the function circuit 200 is enabled and actually operates or is actually driven, the operation enable signal OP_EN is activated by transitioning from a low logic level to a high logic level, and a level of the load current ILO AD immediately (e.g., immediately, immediately, or momentarily) increases from the open circuit level ILN to the operation level ILO. The level of the sink current ISINK decreases immediately from the target level IST to the zero level ISN in response to activation of the operation enable signal OP_EN (e.g., in response to a rising edge of the operation enable signal OP_EN). In other words, once the function circuit 200 actually starts to operate or is driven at time t 2, the load current ILOADis changed (e.g., increased) drastically or suddenly, and at the same time the sink current ISINKis also changed (e.g., decreased) drastically or suddenly. In addition, a level of the output power supply voltage VDD_OUT may slightly change or fluctuate according to the level change of the load current ILOAD and the sink current ISINK.In some embodiments, the magnitude of the sink current ISINKmay be substantially equal to the magnitude of the load current ILOAD. For example, the amount of change of the sink current ISINKand the amount of change of the load current ILOADin accordance with an assertion of the function circuit 200 may be substantially the same. For example, a difference between the target level ISTand the zero level ISNof the sink current ISINKmay be substantially equal to a difference between the operating level ILOand the open circuit level ILNof the load current ILOAD. In other words, an increment of the load current ILOADand a decrement of the sink current ISINKmay be substantially equal to each other, and thus the magnitude of the total current flowing through the output terminal TOUTor the output node NOUTmay not be substantially changed or substantially maintained.In other embodiments, the magnitude of the sink current ISINKmay be proportional to the magnitude of the load current ILOAD.At a time t 3, the functional circuit 200 is disabled and does not operate or is not driven, the operation enable signal OP_EN is disabled by transitioning from the high logic level to the low logic level, and the level of the load current ILO AD immediately decreases from the operating level ILO to the open circuit level ILN. The level of the sink current ISINK instantaneously rises from the zero level ISNto the target level ISTin response to deactivation of the operation enable signal OP_EN(e.g., in response to a falling edge of the operation enable signal OP_EN). In other words, when the function circuit 200 stops operating or is no longer driven at the time t 3, the load current ILOADis changed (e.g., decreased) drastically or suddenly, and at the same time, the decrease current ISINKis also changed (e.g., increased) drastically or suddenly. In addition, the level of the output power supply voltage VDD_OUT may slightly change or fluctuate according to the level change of the load current ILOAD and the sink current ISINK.An operation at a time t 4 and an operation at a time t 5 may be substantially the same as the operation at the time t 2 and the operation at the time t 3, respectively.At time t 6, the sink enable signal SINK_EN is disabled by transitioning from the high logic level to the low logic level, and the sink 120 is disabled. When it is no longer necessary to drive or drive the function circuit 200, the sink 120 is disabled after the function circuit 200 is disabled.The level of the sink current ISINK decreases stepwise from the target level IST to the zero level ISN in response to deactivation of the sink enable signal SINK_EN (e.g., in response to a falling edge of the sink enable signal SINK_EN). In this case, a change or variation in the level of the output power supply voltage VDD_OUT may be reduced or minimized by stepwise lowering of the level of the sink current ISINK.In some embodiments, an operation for determining whether to drive the function circuit 200 and / or whether to no longer drive the function circuit 200, e.g., an operation for determining activation / deactivation of the sink enable signal SINK_EN, may be performed by an external controller (e.g., a controller 50 in FIG. 11 ).The voltage regulator 100 according to at least some embodiments for the inventive ideas may be implemented as a capacitorless or capless voltage regulator in which no external capacitor and no output capacitor connected to the output terminal TOUTor the output node NOUTare used, and may include the drain 120 for stabilizing the output supply voltage VDD_OUT. The sink 120 may be enabled in advance before the function circuit 200 actually operates or is driven, and may generate the sink current ISINKcorresponding to the load current ILOAD voraussichtlich to be consumed while the function circuit 200 is actually driven, step by step. When the function circuit 200 is enabled and actually operates or is driven, and when the load current ILOADis actually consumed by the function circuit 200, the sink 120 may block generation of the sink current ISINK. Accordingly, the magnitude of the total current flowing through the output terminal TOUTor the output node NOUTmay not be substantially changed or substantially maintained, the level change of the output supply voltage VDD_OUTmay be minimized or reduced, and the output supply voltage VDD_OUTmay be generated at a relatively stable level.FIG. 3 is a circuit diagram illustrating an example of a voltage converter included in a voltage regulator according to at least some embodiments of the inventive ideas.As shown in FIG. 3, a voltage converter 110 amay include an error amplifier 112, a pass circuit 114, a feedback circuit 116, and the output terminal TOUT.In some exemplary embodiments, the voltage converter 110 acan be implemented as a linear regulator. The linear regulator has a linear relationship between an input voltage and an output voltage. Unlike a switching regulator, an output voltage of the linear regulator is controlled without switching operations. The linear regulator can have a relatively simple structure and reduced noise. For example, the voltage converter 110 amay be a low drop (LDO) regulator.The error amplifier 112 may compare the input reference voltage VBREFwith a feedback voltage VFBto generate a pass control signal PS. The error amplifier 112 may include a first input terminal receiving the input reference voltage VBREF, a second input terminal connected to a feedback node NF and receiving the feedback voltage VFB, and an output terminal outputting the pass control signal PS.In some embodiments, the input reference voltage VBREFmay be provided from outside the voltage regulator (e.g., from an external reference voltage generator). In other embodiments, not shown in FIGS. 1 and 3, the voltage converter 110 aor the voltage regulator (e.g., the voltage regulator 100 of FIG. 1 ) may include a reference voltage generator that generates the input reference voltage VBREF. For example, the input reference voltage VBREFmay be a bandgap reference voltage.The gating circuit 114 may generate the output supply voltage VDD_OUT in response to the input supply voltage VDD_IN and the pass control signal PS. The pass circuit 114 may include a pass transistor PT. The pass transistor PT may include a first electrode receiving the input supply voltage VDD_IN, a control electrode receiving the pass control signal PS, and a second electrode connected to the output terminal TOUT and outputting the output supply voltage VDD_OUT.The feedback circuit 116 may generate the feedback voltage VFBbased on the output supply voltage VDD_OUT(e.g., by retrieving the output supply voltage VDD_OUTfrom the output terminal TOUT). The feedback circuit 116 may include a plurality of resistors RF 1 and RF 2. The resistor RF 1 may be connected between the output terminal TOUT and the feedback node NF, and the resistor RF 2 may be connected between the feedback node NF and the ground voltage.In the voltage regulator 100 according to at least some embodiments for the inventive ideas, the output terminal TOUTof the voltage regulator 110 amay not be connected to an external capacitor having a relatively large capacitance (e.g., more than about 2 μF), and only a parasitic capacitance (e.g., less than about 5 nF) caused by other elements (e.g., the pass transistor PTand / or the resistors RF 1 and RF 2) may be present at the output terminal TOUT. When the output supply voltage VDD_OUT is generated using only the voltage converter 110 a, the output supply voltage VDD_OUT may be changed drastically or suddenly because the load current ILOAD is changed drastically or suddenly. For example, a functional circuit (e.g., functional circuit 200 in FIG. 1 ) may be damaged or destroyed when the level of output supply voltage VDD_OUT becomes excessively high, and malfunction of the functional circuit may be caused when the level of output supply voltage VDD_OUT becomes too low. As described with reference to FIGS. 1 and 2, when the output power supply voltage VDD_OUT is generated using the voltage converter 110 awith the drain 120 connected to the output terminal TOUT, the level change of the output power supply voltage VDD_OUT can be minimized or reduced, and the output power supply voltage VDD_OUT can be generated at a relatively stable level.Although not illustrated in FIG. 3, the voltage converter included in the voltage regulator 100 according to at least some embodiments of the inventive ideas may be implemented as any linear regulator such as a shunt regulator, a series regulator, or the like.FIG. 4 is a block diagram illustrating an example of a sink logic circuit included in the voltage regulator of FIG. 1.As shown in FIG. 4, sink logic circuit 140 amay include counter 142 and output circuit 144.The counter 142 may generate a count signal CNT based on the first clock signal CLK 1 and the sink enable signal SINK_EN. A value of the count signal CNT may become larger or smaller in a series of steps.In some embodiments, in response to the first clock signal CLK 1 and the assertion of the sink enable signal SINK_EN (e.g., at a time t 1 in FIG. 2 ), the counter 142 may increase a value of the count signal CNT from a minimum value (e.g., zero) to a maximum value in a series of steps. After the value of the count signal CNT has increased to reach the maximum value, the counter 142 may maintain the value of the count signal CNT at the maximum value while maintaining the activation of the sink enable signal SINK_EN.In some embodiments, in response to the first clock signal CLK 1 and the deactivation of the sink enable signal SINK_EN (e.g., at a time t 6 in FIG. 2 ), the counter 142 may decrease the value of the count signal CNT from the maximum value to the minimum value in a series of steps.In some embodiments, the first clock signal CLK 1 may be provided from outside the voltage regulator (e.g., from an external oscillator). In other embodiments, not shown in FIGS. 1 and 4, the sink logic circuit 140 aor the voltage regulator (e.g., the voltage regulator 100 of FIG. 1 ) may include an oscillator that generates the first clock signal CLK 1.The output circuit 144 may generate the first clock signal CLK 1 based on the count signal CNT and the operation enable signal OP_EN.In some embodiments, the output circuit 144 may generate the first control signal CS 1 in response to the count signal CNT such that at least a portion of the plurality of current level controllers is turned on based on the first control signal CS 1 (e.g., the plurality of current level controllers 130 a, 130 b, 130 c,..., 130 nin FIG. 1 are selectively turned on). For example, as described with reference to FIG. 1, the first control signal CS 1 may be an N-bit control signal. The output circuit 144 may control or adjust bits of the first control signal CS 1 in response to the count signal CNT such that the number of the current level controllers turned on corresponds to the value of the count signal CNT. For example, if the value of the count signal CNT is the minimum value (e.g., zero), then the output circuit 144 may adjust the bits of the first control signal CS 1 such that all current level controllers are turned off based on the first control signal CS 1. When the value of the count signal CNT is "1", the output circuit 144 may set the bits of the first control signal CS 1 so that only a current level controller based on the first control signal CS 1 is turned on. When the value of the count signal CNT is "2", the output circuit 144 may set the bits of the first control signal CS 1 so that only two current level controllers are turned on based on the first control signal CS 1. When the value of the count signal CNT is the maximum value (e.g., "N"), the output circuit 144 may set the bits of the first control signal CS 1 so that all current level controllers are turned on based on the first control signal CS 1. For example, if each of the transistors T 1, T 2, T 3,..., TN included in the current level controllers 130 a, 130 b, 130 c,..., 130 nis an n-type metal oxide semiconductor (NMOS) transistor, and if the value of the count signal CNT is the maximum value, then all bits of the first control signal CS 1 may be set to have "1" (e.g., a logic low level).In some embodiments, the output circuit 144 may generate the first control signal CS 1 in response to activation of the operation enable signal OP_EN such that each of the plurality of current level controllers is turned off based on the first control signal CS 1. For example, as described with reference to FIG. 1, the first control signal CS 1 may be an N-bit control signal. When the operation enable signal OP_EN is activated (e.g., at a time t 2 in FIG. 2 ), the output circuit 144 may set the bits of the first control signal CS 1 so that all current level controllers are turned off based on the first control signal CS 1 (e.g., generation of the sink current ISINK is blocked), even if the value of the count signal CNT is not the minimum value. For example, if each of the transistors T 1, T 2, T 3,..., TN included in the current level controllers 130 a, 130 b, 130 c,..., 130 nis an NMOS transistor, and if the operation enable signal OP_EN is activated, then all bits of the first control signal CS 1 may be set to have "0" (e.g., a logic low level). In other words, in an operation for controlling or adjusting the first control signal CS 1, a priority of the operation enable signal OP_EN may be higher than a priority of the count signal CNT.When the operation enable signal OP_EN is disabled (e.g., at a time t 3 in FIG. 2 ), the output circuit 144 may generate the first control signal CS 1 in response to the count signal CNT such that at least a portion of the plurality of current level controllers is turned on based on the first control signal CS 1.FIG. 5 is a block diagram illustrating a voltage regulator according to at least some embodiments for the inventive ideas.As shown in FIG. 5, a voltage regulator 100 aincludes a voltage converter 110, a drain 120, and a high voltage limiter 160.The voltage regulator 100 aof FIG. 5 may be substantially the same as the voltage regulator 100 of FIG. 1, except that the voltage regulator 100 aincludes further the high voltage limiter 160. Thus, repeated explanation is omitted.The high voltage limiter 160 may be connected to the output terminal TOUT via the output node NOUT. The high voltage limiter 160 may generate a second control signal CS 2 that is activated when a level of the output supply voltage VDD_OUT is higher than a first reference level. The second control signal CS 2 may be provided to the sink logic circuit 140 included in the sink 120, and the sink 120 may also control generation of the sink current ISINK based on the second control signal CS 2.In some embodiments, the high voltage limiter 160 may include a first voltage divider 162 and a first comparator 164.The first voltage divider 162 may be connected between the output terminal TOUT(e.g., the output node NOUT) and the ground voltage and may generate a first voltage V 1 corresponding to the output supply voltage VDD_OUT.The first voltage divider 162 may include a plurality of resistors R 11, R 12, and R 13. The resistor R 11 may be connected between the output terminal TOUT (e.g., the output node NOUT) and a node N 1. The resistors R 12 and R 13 may be connected in series between the node N 1 and the ground voltage. The number and the resistance values of the resistors R 11, R 12, and R 13 may be changed at least in accordance with some embodiments of the inventive ideas.The first comparator 164 may compare the first voltage V 1 with a first reference voltage VREF 1 to generate the second control signal CS 2. The first comparator 164 may include a first input terminal connected to the node N 1 and receiving the first voltage V 1, a second input terminal receiving the first reference voltage VREF 1, and an output terminal outputting the second control signal CS 2.In some embodiments, the first reference voltage VREF 1 may be provided from outside the voltage regulator 100 a(e.g., from an external reference voltage generator). In other embodiments, not shown in FIG. 5, the high voltage limiter 160 or the voltage regulator 100 amay include a reference voltage generator generating the first reference voltage VREF 1.In some embodiments, the first reference voltage VREF 1 and the input reference voltage VBREF may be substantially the same as or different from each other.FIG. 6 is a time chart for describing an operation of a high voltage limiter included in the voltage regulator of FIG. 5. In FIG. 6, VDD_OUT' represents an output supply voltage in an example where the high voltage limiter 160 is not included in the voltage regulator, and VDD_OUT represents an output supply voltage in an example where the high voltage limiter 160 is included in the voltage regulator 100 a(e.g., in an example of FIG. 5 ).As shown in FIGS. 5 and 6, in the example where the high voltage limiter 160 is not included in the voltage regulator, a level of the output supply voltage VDD_OUT' may be changed drastically or suddenly with respect to the target power level VDDT and may become higher than a first reference level VTH 1. In other words, the output power supply voltage VDD_OUT' may overshoot, and the function circuit 200 may be damaged or destroyed when the level of the output power supply voltage VDD_OUT' exceeds the upper limit.In the example where the high voltage limiter 160 is included in the voltage regulator 100 a, the high voltage limiter 160 may activate the second control signal CS 2 when the level of the output supply voltage VDD_OUT is higher than the first reference level VTH 1. While the second control signal CS 2 is activated (e.g., while the second control signal CS 2 is at a high logic level), the drain 120 may generate the drain current ISINKat the maximum magnitude to decrease the level of the output supply voltage VDD_OUT.When the level of the output power supply voltage VDD_OUT is at most as high as the first reference level VTH 1, the high voltage limiter 160 may deactivate the second control signal CS 2.FIG. 7 is a block diagram illustrating an example of a sink logic circuit included in the voltage regulator of FIG. 5.As shown in FIG. 7, sink logic circuit 140 bmay include counter 142 and output circuit 146.The counter 142 of FIG. 7 may be substantially the same as the counter 142 of FIG. 4, and the output circuit 146 of FIG. 7 may be substantially the same as the output circuit 144 of FIG. 4, except that the output circuit 146 further operates based on the second control signal CS 2. Thus, repeated explanation is omitted.The output circuit 146 may generate the first control signal CS 1 based on the count signal CNT, the operation enable signal OP_EN, and the second control signal CS 2.In some embodiments, the output circuit 146 may generate the first control signal CS 1 in response to activation of the second control signal CS 2 such that each of the plurality of current level controllers is turned on based on the first control signal CS 1 (e.g., each of the plurality of current level controllers 130 a, 130 b, 130 c,..., 130 nin FIG. 1 ). For example, as described with reference to FIG. 1, the first control signal CS 1 may be an N-bit control signal. While the second control signal CS 2 is activated (e.g., during a period in which the second control signal CS 2 is at the high logic level in FIG. 6 ), the output circuit 146 may set the bits of the first control signal CS 1 so that all the current level controllers are turned on based on the first control signal CS 1 (e.g., the sink current ISINK having the maximum magnitude is generated) even if the value of the count signal CNT is not the maximum value or even if the operation enable signal OP_EN is activated. In other words, during an operation for controlling or adjusting the first control signal CS 1, a priority of the second control signal CS 2 may be higher than the priority of the operation enable signal OP_EN and the priority of the count signal CNT.While the second control signal CS 2 is deactivated (e.g., during a period in which the second control signal CS 2 is at the low logic level in FIG. 6 ), the output circuit 146 may generate the first control signal CS 1 again in response to the count signal CNT and the operation enable signal OP_EN.FIG. 8 is a block diagram illustrating a voltage regulator according to at least some embodiments for the inventive ideas.As shown in FIG. 8, a voltage regulator 100 bincludes a voltage converter 110, a sink 120, and a clock generator 180.The voltage regulator 100 bof FIG. 8 may be substantially the same as the voltage regulator 100 of FIG. 1, except that the voltage regulator 100 bfurther includes the clock generator 180. Thus, repeated explanation is omitted.The clock generator 180 may be connected to the output terminal TOUT via the output node NOUT. The clock generator 180 may generate a driving clock signal DCLK provided to the functional circuit 200 based on a second clock signal CLK 2 and a third control signal CS 3 that is activated when a level of the output supply voltage VDD_OUT is lower than a second reference level. The function circuit 200 may operate or be driven based on the output supply voltage VDD_OUT and the drive clock signal DCLK.In some embodiments, the second clock signal CLK 2 may be provided from outside the voltage regulator 100 b(e.g., from an external oscillator). In other embodiments, not shown in FIG. 8, the clock generator 180 or the voltage regulator 100 bmay include an oscillator generating the second clock signal CLK 2.In some embodiments, the clock generator 180 may include a second voltage divider 182, a second comparator 184, and an AND gate 186.The second voltage divider 182 may be connected between the output terminal TOUT(e.g., the output node NOUT) and the ground voltage and may generate a second voltage V 2 corresponding to the output supply voltage VDD_OUT.The second voltage divider 182 may include a plurality of resistors R 21, R 22, and R 23. The resistors R 21 and R 22 may be connected in series between the output terminal TOUT (e.g., the output node NOUT) and a node N 1. The resistor R 23 may be connected between the node N 2 and the ground voltage. The number and the resistance values of the resistors R 21, R 22, and R 23 may be changed at least according to some embodiments of the inventive ideas.The second comparator 184 may compare the second voltage V 2 with a second reference voltage VREF 2 to generate the third control signal CS 3. The second comparator 184 may have a first input terminal connected to the node N 2 and receiving the second voltage V 2, a second input terminal receiving the second reference voltage VREF 2, and an output terminal outputting the third control signal CS 3.In some embodiments, the second reference voltage VREF 2 may be provided from outside the voltage regulator 100 b(e.g., from an external reference voltage generator). In other embodiments, not shown in FIG. 8, the clock generator 180 or the voltage regulator 100 bmay include a reference voltage generator generating the second reference voltage VREF 2.The AND gate 186 may generate the driving clock signal DCLK based on the second clock signal CLK 2 and the third control signal CS 3.The sink logic circuit 140 of FIG. 8 may be substantially the same as the sink logic circuit 140 aof FIG. 4.In some embodiments, the second reference voltage VREF 2 and the input reference voltage VBREF (or the first reference voltage VREF 1 in FIG. 5 ) may be substantially the same as or different from each other. In some embodiments, the second reference voltage VREF 2 and the first clock signal CLK 1 may be substantially the same as or different from each other.FIG. 9 is a time chart for describing an operation of a clock generator included in the voltage regulator of FIG. 8.As shown in FIGS. 8 and 9, the level of the output power supply voltage VDD_OUT' may be changed drastically or suddenly with respect to the target power level VDDT and may become lower than a second reference level VTH2. In other words, the output power supply voltage VDD_OUT may be under-shoot, and malfunction of the function circuit 200 may be caused when the level of the output power supply voltage VDD_OUT falls below the lower limit. At least according to some embodiments of the inventive ideas, the second reference level VTH 2 may be different from the first reference level VTH 1 in FIG. 6.The clock generator 180 may activate the third control signal CS 3 when the level of the output supply voltage VDD_OUT is lower than the second reference level VTH 2. While the third control signal CS 3 is activated (e.g., while the third control signal CS 3 is at a low logic level), the clock generator 180 may block generation of the drive clock signal DCLK. For example, the AND gate 186 may perform an AND operation on the second clock signal CLK 2 and the third control signal CS 3 to generate the drive clock signal DCLK. Since the third control signal CS 3 has the low logic level, the drive clock signal DCLK output from the AND gate 186 may have a low logic level based on the low logic level of the third control signal CS 3 regardless of the level of the second control signal CS 2. In other words, the clock generator 180 may perform a clock pause function to prevent the drive clock signal DCLK from jumping back and forth, and the function circuit 200 may not operate or be driven while the generation of the drive clock signal DCLK is blocked.When the level of the output power supply voltage VDD_OUT is at least as high as the second reference level VTH 2, the clock generator 180 may deactivate the third control signal CS 3 and may generate the drive clock signal DCLK again.FIG. 10 is a block diagram illustrating a voltage regulator according to at least some embodiments for the inventive ideas.As shown in FIG. 10, a voltage regulator 100 cincludes a voltage converter 110, a drain 120, a high voltage limiter 160, and a clock generator 180.The voltage regulator 100 cof FIG. 10 may be substantially the same as the voltage regulator 100 of FIG. 1, except that the voltage regulator 100 cfurther includes the high voltage limiter 160 and the clock generator 180. The high voltage limiter 160 and the clock generator 180 in FIG. 10 may be substantially the same as the high voltage limiter 160 of FIG. 5 and the clock generator 180 of FIG. 8, respectively.The sink logic circuit 140 of FIG. 10 may be substantially the same as the sink logic circuit 140 bof FIG. 7.The voltage regulators 100 a, 100 band 100 caccording to at least some embodiments for the inventive ideas may be implemented as a capacitorless or capless voltage regulator, may include the drain 120, and may further include the high voltage limiter 160 and / or the clock generator 180. The overshoot and undershoot of the output power supply voltage VDD_OUT may be prevented by the high voltage limiter 160 and the clock generator 180. Accordingly, the output power supply voltage VDD_OUT can be generated at a relatively stable level.FIG. 11 is a block diagram illustrating a semiconductor device according to at least some embodiments of the inventive ideas.As shown in FIG. 11, a semiconductor device 10 includes a voltage regulator 100, a functional circuit 200, and a controller 50.The voltage regulator 100 and the functional circuit 200 in FIG. 11 may be substantially the same as the voltage regulator 100 and the functional circuit 200 of FIG. 1, respectively.The controller 50 controls the function circuit 200 and the voltage regulator 100. For example, the controller 50 may generate a control signal CONT for controlling an operation of the function circuit 200, and may generate the first clock signal CLK 1, the sink enable signal SINK_EN, and the operation enable signal OP_EN for controlling an operation of the voltage regulator 100. Although not illustrated in FIG. 11, the controller 50 may further generate a drive clock signal provided to the function circuit 200.Although FIG. 11 illustrates an example where the operation enable signal OP_EN is provided from the controller 50, at least in some embodiments, the operation enable signal OP_EN illustrated in FIG. 11 may be provided from the function circuit 200 to the sink logic circuit 140 instead of the controller 50, as illustrated in FIG. 1.In some embodiments, the voltage regulator 100 in FIG. 11 may be replaced with one of the voltage regulators 100 a, 100 band 100 cof FIGS. 5, 8 and 10. In this example, the controller 50 may further generate the second clock signal CLK 2 in FIGS. 8 and 10.According to at least some embodiments of the inventive ideas, the controller 50 may include or be implemented by: one or more circuits or circuit technology (e.g., hardware) specifically configured to execute and / or control some or all of the operations performed by the controller 50 as described in the present disclosure; a memory and one or more processors executing computer readable code (e.g., software and / or firmware) stored in the memory and including instructions that cause the one or more processors to execute and / or control some or all of the operations performed by the controller 50 as described in the present disclosure; or a combination of the above-mentioned hardware and one or more processors executing computer readable code.Although not illustrated in FIG. 11, the semiconductor device 10 may further include a voltage generator that generates at least one of the voltages (e.g., the input supply voltage VDD_IN, the input reference voltage VBREF, the first reference voltage VREF 1, the second reference voltage VREF 2, etc.) provided to the voltage regulator 100.FIGS. 12, 13 and 14 are flowcharts illustrating a method of generating a supply voltage according to at least some embodiments of the inventive ideas.As shown in FIGS. 1, 2, and 12, in a method for generating (or stabilizing) a supply voltage according to at least some embodiments for the inventive ideas, the voltage converter 110 included in the voltage regulator 100 generates the output supply voltage VDD_OUT based on the input supply voltage VDD_IN and the input reference voltage VBREF (step S 100).While the function circuit 200 is not driven, the sink 120 generates the sink current ISINKin response to the sink enable signal SINK_EN(step S 200). The sink current ISINKcorresponds to the load current ILOAD verbraucht while the function circuit 200 is driven. For example, as illustrated in FIG. 2 (e.g., at a time t 1), the sink 120 may be previously enabled in response to activation of the sink enable signal SINK_EN before the functional circuit 200 is actually driven, and the sink current ISINKcorresponding to the load current ILOADmay be generated stepwise.While the function circuit 200 is driven, the sink 120 blocks generation of the sink current ISINKin response to the operation enable signal OP_EN (step S 300). As illustrated in FIG. 2 (e.g., at a time t 2), the sink 120 may be disabled in response to the activation of the operation enable signal OP_EN when the functional circuit 200 is actually driven and the load current ILOADis actually consumed by the functional circuit 200, and the generation of the sink current ISINKmay be blocked.Thereafter, when the function circuit 200 is not driven again, the sink 120 may generate the sink current ISINK erneut in response to the deactivation of the operation enable signal OP_EN(e.g., at a time t 3 in FIG. 2 ). In addition, when the function circuit 200 no longer needs to be actuated or driven, the sink 120 may gradually inhibit generation of the sink current ISINKin response to deactivation of the sink enable signal SINK_EN (e.g., at a time t 6 in FIG. 2 ).As shown in FIGS. 5, 6, and 13, steps S 100, S 200, and S 300 in FIG. 13 may be substantially the same as steps S 100, S 200, and S 300 in FIG. 12. Thus, repeated explanation is omitted.When the level of the output power supply voltage VDD_OUT is higher than the first reference level VTH 1 (step S 400: YES), the high voltage limiter 160 may activate the second control signal CS 2. While the second control signal CS 2 is activated, the sink 20 may control or adjust the sink current ISINKsuch that the level of the output supply voltage VDD_OUTis decreased (step S 500). For example, the sink 120 may generate the sink current ISINK having the maximum magnitude in response to the activated second control signal CS 2.When the level of the output power supply voltage VDD_OUT is at most as high as the first reference level VTH 1 (step S 400: NO), steps S 200 and S 300 may be repeated.As illustrated in FIGS. 8, 9, and 14, steps S 100, S 200, and S 300 in FIG. 14 may be substantially the same as steps S 100, S 200, and S 300 in FIG. 12, respectively. Thus, repeated explanation is omitted.When the level of the output power supply voltage VDD_OUT is lower than the second reference level VTH 2 (step S 600: YES), the clock generator 180 may activate the third control signal CS 3. While the third control signal CS 3 is activated, the clock generator 180 may block generation of the drive clock signal DCLK (step S 700). For example, the clock generator 180 may prevent the drive clock signal DCLK from jumping back and forth in response to the activated third control signal CS 3.When the level of the output power supply voltage VDD_OUT is at least as high as the second reference level VTH 2 (step S 600: NO), steps S 200 and S 300 may be repeated.In some embodiments, the method for generating the supply voltage may be implemented with all steps S 100, S 200, S 300, S 400, S 500, S 600 and S 700.In some embodiments, at least a portion of the method for generating the supply voltage may be implemented as hardware. In other embodiments, at least a portion of the method for generating the supply voltage may be implemented as instructions or program routines (e.g., as a software program). For example, the instructions or program routines may be executed by a processor (not shown) and may be stored in a memory device or memory (not shown).The present disclosure may be used in various types of voltage regulators or an apparatus or system in which the voltage regulators are included, such as a personal computer, a laptop computer, a mobile phone, a smart phone, a tablet computer, personal digital assistants (PDAs), an enterprise digital assistant (EDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation device, a body-worn device, a device belonging to Internet of Things (IoT), a device belonging to Internet of Things (IoE), an e-book, a virtual reality (VR) device, an augmented reality (AR) device, etc.The voltage regulator according to at least some embodiments for the inventive ideas may be implemented as a capacitorless or capless voltage regulator in which no external capacitor and no output capacitor connected to the output terminal or the output node are used, and may have the drain for stabilizing the output supply voltage. The sink may be previously enabled before the functional circuit is actually actuated or driven, and may gradually generate the sink current corresponding to the load current that is expected to be consumed while the functional circuit is actually driven. When the function circuit is enabled and actually operated or driven, and when the load current is actually consumed by the function circuit, the sink may block generation of the sink current ISINK. Accordingly, the magnitude of the total current flowing through the output terminal may not be substantially changed or substantially maintained, the level change of the output supply voltage may be minimized or reduced, and the output supply voltage may be generated at a relatively stable level.In addition, the voltage regulator according to at least some exemplary embodiments of the inventive ideas can also have the high-voltage limiter and / or the clock generator. The overshoot and undershoot of the output power supply voltage can be prevented by the high voltage limiter and the clock generator. Accordingly, the output power supply voltage VDD_OUT can be generated at a relatively stable level.Having thus described embodiments of the inventive ideas, it will be apparent that they can be varied in many ways. Such variations are not to be regarded as a departure from the intended spirit and scope of the embodiments of the inventive ideas, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.

Claims

A voltage regulator comprising: a voltage converter (110; 110a) configured to generate an output supply voltage (VDD_OUT) based on an input supply voltage (VDD_IN) and an input reference voltage (VBREF), and to provide the output supply voltage (VDD_OUT) to an external function circuit (200), wherein the voltage converter (110; 110a) comprises an output terminal (TOUT) configured to output the output supply voltage (VDD_OUT); A drain (120) connected to the output terminal (TOUT), wherein the drain (120) is configured to generate a drain current (ISINK) in response to a drain enable signal (SINK_EN) while the external functional circuit (200) is not driven, and is configured to block generation of the drain current (ISINK) in response to an operation enable signal (OP_EN) while the external functional circuit (200) is driven, wherein the drain current (ISINK) corresponds to a load current (ILOAD) consumed while the external functional circuit (200) is driven.The voltage regulator of claim 1, wherein the sink (120) is configured such that a level of the sink current (ISINK) gradually increases from a zero level (ISN) to a target level (IST) in response to activation of the sink enable signal (SINK_EN), wherein the zero level is for no sink current (ISINK) to be generated, and the target level (IST) corresponds to the load current (ILOAD), and wherein the sink (120) is configured such that the level of the sink current (ISINK) gradually decreases from the target level (IST) to the zero level (ISN) in response to deactivation of the sink enable signal (SINK_EN).The voltage regulator of claim 1, wherein the sink (120) is configured such that a level of the sink current (ISINK) instantaneously decreases from a target level (IST) to a zero level (ISN) in response to activation of the operation enable signal (OP_EN), wherein the zero level (ISN) is indicative that no sink current (ISINK) is generated, and the target level (IST) corresponds to the load current (ILOAD), and wherein the sink is configured such that the level of the sink current (ISINK) instantaneously increases from the zero level (ISN) to the target level (IST) in response to deactivation of the operation enable signal (OP_EN).The voltage regulator of claim 1, wherein the sink (120) comprises: a current generator (130) connected to the output terminal (TOUT), the current generator (130) configured to generate the sink current (ISINK) in response to a first control signal (CS1); and a sink logic circuit (140; 140a) configured to generate the first control signal (CS1) based on the sink enable signal (SINK_EN) and the operation enable signal (OP_EN).The voltage regulator of claim 4, wherein the current generator (130) comprises: a plurality of current level controllers (130a, 130b, 130c, 130n) connected in parallel between the output terminal (TOUT) and a ground voltage, wherein the plurality of current level controllers (130a, 130b, 130c, 130n) are configured to be selectively turned on in response to the first control signal (CS1), and wherein each of the plurality of current level controllers (130a, 130b, 130c, 130n) comprises: a resistor (R1, R2, R3, RN) connected to the output terminal (TOUT); and a transistor (T1, T2, T3, TN) connected between the resistor (R1, R2, R3, RN) and the ground voltage, wherein the transistor (T1, T2, T3, TN) has a control electrode receiving the first control signal (CS1).The voltage regulator of claim 5, wherein the sink logic circuit (140; 140a) comprises: a counter (142) configured to generate a count signal (CNT) that rises and falls in a series of steps based on a first clock signal (CLK1) and the sink enable signal (SINK_EN); and an output circuit (144) configured to generate the first control signal (CS1) based on the count signal (CNT) and the operation enable signal (OP_EN).The voltage regulator of claim 1, further comprising: a high voltage limiter (160) connected to the output terminal (TOUT), wherein the high voltage limiter (160) is configured to generate a control signal (CS2) that is activated when the output supply voltage (VDD_OUT) is higher than a reference level, wherein the sink (120) is configured to control generation of the sink current (ISINK) additionally based on the control signal (CS2), and wherein the sink (120) is configured to generate the sink current (ISINK) to decrease the level of the output supply voltage (VDD_OUT) while the control signal (CS2) is activated.The voltage regulator of claim 1, further comprising: a clock generator (180) connected to the output terminal (TOUT), wherein the clock generator (180) is configured to generate a drive clock signal (DCLK) provided to the external function circuit (200), based on a first clock signal (CLK2) and a control signal (CS3) activated when a level of the output supply voltage (VDD_OUT) is lower than a reference level (VTH2), and wherein the clock generator (180) is configured such that the clock generator (180) blocks generation of the drive clock signal (DCLK) while the control signal (CS3) is activated.The voltage regulator of claim 1, wherein the drain (120) is configured such that a magnitude of the drain current (ISINK) is substantially equal to a magnitude of the load current (ILOAD).A semiconductor device, comprising: an external function circuit (200) configured to operate based on an output supply voltage (VDD_OUT); a voltage regulator (100) configured to generate the output supply voltage (VDD_OUT) based on an input supply voltage (VDD_IN) and an input reference voltage (VBREF), generate a sink current (ISINK) while the external function circuit is not driven in response to a sink enable signal (SINK_EN), and block generation of the sink current (ISINK) while the external function circuit (200) is driven in response to an operation enable signal (OP_EN); and a controller (50) configured to control the external function circuit (200) and the voltage regulator (100), wherein the sink current (ISINK) corresponds to a load current (ILOAD) to be consumed while the external function circuit (200) is driven.

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