DUMMY FIN STRUCTURES AND METHODS FOR THEIR MANUFACTURE

Abstract

Procedure with the following steps: Depositing a first dielectric layer (56) over and along sidewalls of a semiconductor fin (52), the semiconductor fin (52) extending upwardly from a semiconductor substrate (50); Depositing a dielectric material (60) over the first dielectric layer (56), wherein depositing the dielectric material (60) comprises defining a cavity (61) beneath the dielectric material (60) between the semiconductor fin (52) and a second semiconductor fin (52); Recessing the first dielectric layer (56) beneath a top surface of the semiconductor fin (52) to define a dummy fin (62), the dummy fin (62) comprising an upper portion of the dielectric material (60); and Forming a gate stack (92, 94) over and along sidewalls of the semiconductor fin (52) and the dummy fin (62).

Description

Background of the invention

[0001] Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate. The various material layers are patterned using lithography to create circuit components and elements on the substrate.

[0002] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, allowing more components to be integrated into a given area. However, reducing the minimum feature size creates additional problems that need to be addressed.

[0003] US 2016 / 0 043 225 A1 discloses a semiconductor device and its manufacturing method, wherein a stress-generating structure is arranged under a channel region of the semiconductor device.

[0004] US 2017 / 0 040 324 A1 discloses a semiconductor device and its manufacturing method, wherein a dummy fin is used to partially interrupt the active gate element in order to induce a stress or strain in the channel region.

[0005] US 2017 / 0 012 042 A1 discloses a method for fabricating a semiconductor device. The method comprises forming a plurality of semiconductor pillars and forming a dielectric spacer between adjacent semiconductor pillars. Semiconductor material is epitaxially grown on the sidewalls of the adjacent semiconductor pillars, wherein the dielectric spacer prevents a first portion of the epitaxial semiconductor material formed on a first semiconductor pillar from fusing with a second portion of the epitaxial semiconductor material formed on a second semiconductor pillar.

[0006] US 2014 / 0 213 037 A1 discloses a method for fabricating an integrated circuit. The method comprises forming a portion of a semiconductor substrate bound by a confinement insulation material. A dielectric liner material is formed over the confinement insulation material and treated to passivate a surface thereof. An epitaxial layer of semiconductor material is then formed over the portion of the semiconductor substrate. Short description of the drawings

[0007] Aspects of the present invention can best be understood from the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of discussion, the dimensions of various elements may be exaggerated or reduced as desired. Fig. 1 shows an example of a FinFET in a three-dimensional representation, according to some embodiments. The Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7A, Fig. 7B, Fig. 8, Fig. 9, Fig. 10A, Fig. 10B, Fig. 10C, Fig. 11A, Fig. 11B, Fig. 11C, Fig. 11D, Fig. 12A, Fig. 12B, Fig. 12C, Fig. 13A, Fig. 13B, Fig. 13C, Fig. 14A, Fig. 14B, Fig. 14C, Fig. 14D, Fig. 15A, Fig. 15B, Fig. 15C, Fig. 16A, Fig. 16B, Fig. 16C, Fig. 17A, Fig. 17B and Fig. 17C show various representations of intermediate stages of manufacturing a device according to some embodiments. The Fig. 17D, Fig. 17E and Fig. 17F show various representations of a device according to some alternative embodiments. The Fig. 18 to 22 show sectional views of intermediate stages of the manufacture of a device according to some alternative embodiments. The Fig. 23 to 27 and 28A to 28C show sectional views of intermediate stages of fabricating a device according to some alternative embodiments. The Fig. 28D to 28F show various representations of a device according to some alternative embodiments. The Fig. 29 and 30A to 30C show sectional views of intermediate stages of fabricating a device according to some alternative embodiments. The Fig. 31 and 32A to 32C show sectional views of intermediate stages of fabricating a device according to some alternative embodiments. Detailed description

[0008] The following description provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to facilitate the present invention. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and may also include embodiments in which additional elements may be fabricated between the first and second elements such that the first and second elements are not in direct contact. Furthermore, in the present invention, reference numerals and / or letters may be repeated in the various examples.This repetition is for simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0009] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structure to one or more other elements or structures illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the component in use or operation, in addition to the orientation illustrated in the figures. The component may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0010] In various embodiments, structures and methods are provided for forming dummy fins on a semiconductor substrate having fin field-effect transistors (FinFETs). During the manufacturing process of the FinFET devices of the embodiments, dummy gate stacks may first be formed over and along sidewalls of semiconductor fins. These dummy gate stacks are used as placeholders to define the position for functional gate stacks that are later formed in various manufacturing processes (e.g., forming source / drain regions and the like). This process may also be referred to as a gate replacement process.

[0011] By reducing the size of semiconductor features, dummy gate stacks with small pitches can be fabricated in advanced technology nodes. When fabricating dummy gate stacks with small pitches, it may be desirable to maintain a uniform structure of dummy gate stacks even in regions where no semiconductor fins are fabricated. For example, dummy gate stacks can be placed directly on isolation regions arranged around the semiconductor fins in regions with non-uniform fin pitches and / or between boundaries of different FinFET regions. Due to the small pitch and high aspect ratio of dummy gate stacks that are not fabricated over and along fin sidewalls, these "unanchored" dummy gate stacks can easily break apart during the fabrication process.For example, anchored dummy gate stacks are fabricated over and along sidewalls of semiconductor fins and are structurally supported by the semiconductor fins on which they are disposed. In contrast, unanchored dummy gate stacks are fabricated only over an isolation region (and not along sidewalls of the isolation region) and are not as physically secure as anchored gate stacks. Various embodiments are directed to reducing manufacturing defects by fabricating dummy fins (e.g., with one or more insulating layers) to anchor dummy gate stacks that are not fabricated on semiconductor fins. Anchoring dummy gate stacks in this manner has been found to result in fewer manufacturing defects.Another advantage of dummy fins is that they can be used to reduce source / drain bridging in epitaxial source / drain growth processes, as will be discussed in more detail later.

[0012] Fig. 1 shows an example of a FinFET in a three-dimensional representation, according to some embodiments. The FinFET includes a fin 52 on a substrate 50 (e.g., a semiconductor substrate). Isolation regions 64 are disposed in the substrate 50, and the fin 52 protrudes between adjacent isolation regions 64. Although the isolation regions 64 are described / illustrated as regions separated from the substrate 50, the term "substrate" as used herein may be used to refer to only the semiconductor substrate or a semiconductor substrate including the isolation regions. A gate dielectric layer 92 is disposed along sidewalls and over a top surface of the fin 52, and a gate electrode 94 is disposed over the gate dielectric layer 92. Source / drain regions 82 are arranged on opposite sides of the fin 52 with respect to the gate dielectric layer 92 and the gate electrode 94. Fig. 1 shows reference cross-sections used in later figures. Cross-section A-A is along a longitudinal axis of gate electrode 94 and in a direction that is, for example, perpendicular to the direction of current flow between source / drain regions 82 of the FinFET. Cross-section B-B is parallel to cross-section A-A and passes through a source / drain region of the FinFET. Cross-section C-C is perpendicular to cross-section A-A and is along a longitudinal axis of fin 52 and in a direction, for example, of current flow between source / drain regions 82 of the FinFET. Later figures refer to these reference cross-sections for clarity.

[0013] The Fig. 2 to 17C are various illustrations of intermediate stages in the fabrication of FinFETs according to some embodiments. Fig. 2 to 8, 18 to 27, 29 and 30 show the reference cross-section A - A, which in Fig. 1, except that multiple fins / FinFETs are shown. Fig. 9 shows a top-down view. In the Fig. 10A to 17C and 28A to 28C are figures ending with the letter “A” along the reference cross-section A - A of Fig. 1; figures ending with the letter “B” are along a similar cross section B - B of Fig. 1; and figures ending with the letter “C” are taken along a similar cross section C - C of Fig. 1, except that multiple fins / FinFETs are shown. Furthermore, Fig. 17D and Fig. 28D along the reference cross-section A - A of Fig. 1 shown; the Fig. 17E, Fig. 14D and Fig. 28E are along the reference cross-section B - B of Fig. 1; and the Fig. 17F and Fig. 27F are along the reference cross-section C - C of Fig. 1 shown.

[0014] In Fig. 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped or undoped (e.g., with a p-type or an n-type dopant). The substrate 50 may be a wafer, such as a silicon wafer. Generally, in an SOI substrate, a layer of a semiconductor material is fabricated on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, may also be used.In some embodiments, the semiconductor material of substrate 50 may include: silicon; germanium; a compound semiconductor such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0015] The substrate 50 has a region 50C and a region 50D. The region 50C can be used to fabricate n-type devices, such as NMOS transistors, e.g., n-FinFETs. The region 50D can be used to fabricate p-type devices, such as PMOS transistors, e.g., p-FinFETs. The region 50C can be physically separated from the region 50D (as represented by a divider 51), and a number of device structures (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between the region 50C and the region 50D. In some embodiments, the region 50C and the region 50D are used to fabricate the same type of device, such as both regions for n-type or p-type devices. In the following description, only one region (e.g.,either the region 50C or the region 50D) and differences in the manufacture of various structural elements in the other region are described.

[0016] In Fig. 3, fins 52 are formed in the substrate 50. The fins 52 are semiconductor strips. In some embodiments, the fins 52 may be formed in the substrate 50 by etching trenches in the substrate 50. The etching may be performed using a suitable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or the like, or a combination thereof. The etching may be anisotropic. In this embodiment, a mask layer 54 may be used to define a pattern of the fins 52. In some embodiments, the mask layer 54 may comprise silicon oxide, silicon nitride, silicon oxynitride, or the like. In some embodiments, the mask layer 54 comprises multiple sublayers, such as a sublayer of silicon nitride over a sublayer of silicon oxide.

[0017] The fins can be patterned using any suitable method. For example, the fins can be patterned using one or more photolithographic processes, such as double-patterning or multi-patterning processes. In general, double-patterning or multi-patterning processes combine photolithographic and self-aligned processes, which can create structures that have, for example, pitches smaller than those otherwise achievable with a single direct photolithographic process. For example, in one embodiment, a sacrificial layer is formed over a substrate, which is then patterned using a photolithographic process. Spacers are formed along the patterned sacrificial layer using a self-aligned process. Subsequently, the sacrificial layer is removed, and the remaining spacers can then be used to pattern the fins.

[0018] In Fig. 4, a dielectric cap layer 56 is deposited over and along sidewalls of fins 52. Dielectric cap layer 56 may further extend along top surfaces of fins 52 and top surfaces of substrate 50 between fins 52. A conformal deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like, may be used to deposit dielectric cap layer 56. Dielectric cap layer 56 may comprise any suitable insulating material, such as silicon oxide or the like.

[0019] In Fig. 5, an optional dielectric cap layer 58 is deposited over the dielectric cap layer 56 such that the dielectric cap layer 58 is disposed along the sidewalls and top surfaces of the fins 52. The dielectric cap layer 58 may also extend along the top surfaces of the substrate 50 between the fins 52. A conformal deposition process such as CVD, ALD, or the like may be used to deposit the dielectric cap layer 58. The dielectric cap layer 58 may comprise a carbonaceous dielectric layer (e.g., a carbonaceous oxide such as SiOC), a metalaceous dielectric layer (e.g., a metalaceous oxide such as a combination of SiO and a metal), combinations thereof, or the like. In alternative embodiments, the dielectric cap layer 58 may be omitted (see, e.g., Fig. 17C to 17E).

[0020] In Fig. 6, a dielectric material 60 is deposited over the dielectric layers 56 and 58. The dielectric material 60 may be deposited between the fins 52 such that it fills or overfills regions between the fins 52. In some embodiments, the dielectric material 60 may be deposited by flow deposition, spin-on deposition, or the like. In some embodiments, the deposition of the dielectric material 60 may define voids 61 between adjacent ones of the fins 52 and between the dielectric material 60 and the dielectric layers 56 / 58. The voids 61 may arise, for example, due to a high aspect ratio between adjacent ones of the fins 52. A height of the voids 61 may be smaller than a final height of later-fabricated dummy fins, for example, upper ends of the voids 61 may be lower than upper ends of dummy fins 62 (see Fig. 8). It has been found that, taking this height relationship into account, device performance is not affected by the presence of the cavities 61. In other embodiments, no cavities 61 are formed. The dielectric material 60 may comprise a carbon-containing dielectric layer (e.g., a carbon-containing oxide, such as SiOC), a metal-containing dielectric layer (e.g., a metal-containing oxide, such as a combination of SiO and a metal), or the like. In some embodiments, the mass fraction of carbon and / or metal in the dielectric material 60 is less than a corresponding mass fraction of carbon and / or metal in the dielectric cap layer 58 (if present). For example, the dielectric cap layer 58 may comprise SiOC with more than 10 mass % carbon, and the dielectric material 60 may comprise SiOC with less than 10 mass % carbon.

[0021] In Fig. 7A, the top surfaces of the fins 52 are exposed using a planarization, for example, a chemical mechanical polishing (CMP), and / or an etch-back process (e.g., a dry etch process). In particular, upper portions of the dielectric material 60, the dielectric cap layer 58 (if present), the dielectric cap layer 56, and the mask layer 54 are removed, thereby exposing the fins 52. In some embodiments, after exposing the fins 52, the top surfaces of the dielectric material 60, the dielectric cap layer 58, the dielectric cap layer 56, and the fins 52 are substantially coplanar. In other embodiments, after exposing the fins 52, the top surfaces of the dielectric material 60, the dielectric cap layer 58, the dielectric cap layer 56, and the fins 52 are not coplanar (see, e.g., Fig. 7B). Variations in height may be due to different material compositions of the fins 52, the dielectric cap layer 56, the dielectric cap layer 58 (if present), and the dielectric material 60, which are polished or etched at different rates during a suitable planarization process. While subsequent figures show these top surfaces as coplanar for ease of explanation, it is understood that embodiments with non-coplanar top surfaces, such as those shown in Fig. 7B may also be considered in later processing steps and / or later described embodiments.

[0022] In Fig. 8, a further etch-back process is performed on the dielectric cap layer 56. The dielectric cap layer 56 is recessed such that portions of the semiconductor fins 52 and the dummy fins 62 protrude above a top surface of the dielectric cap layer 56. In some embodiments, after the recessing, a height of the semiconductor fins 52 may be substantially equal to a height of the dummy fins 62. The dummy fins 62 consist of upper portions of the dielectric cap layer 58 (if present) and upper portions of the dielectric material 60 that protrude above the top surface of the dielectric cap layer 56. Thus, the dummy fins 62 may have a different material composition than the semiconductor fins 52, and the dummy fins 62 may be insulating fins.In addition, remaining portions of the dielectric cap layer 56, lower portions of the dielectric cap layer 58, and lower portions of the dielectric material 60 (collectively referred to as isolation region 64) provide electrical isolation between adjacent fins 52, and may further provide shallow trench isolation (STI) regions between the fins 52, eliminating the need to fabricate a separate STI region.

[0023] In further embodiments, a separate STI region is formed (e.g., between a bottom surface of the dielectric cap layer 56 and the substrate 50). For example, Fig. 29 illustrates an embodiment in which a separate STI region 204 is formed between bottom surfaces of the dielectric cap layer 56 and top surfaces of the substrate 50 (denoted by 50A). The STI region 204 may comprise a suitable insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or the like. In the embodiment of Fig. 29, individual fins 52 may be connected by a mesa 50A (sometimes referred to as a crown). The mesa 50A is a portion of the substrate 50. Multiple fins 52 may extend from a single mesa 50A connected to a lower portion of the substrate 50 (denoted by 50B). The mesa 50A may enable better structural stability when forming fins with a high aspect ratio (e.g., the fins 52). The STI region 204 may be formed to extend along lower portions of the fins 52 as well as along sidewalls of the mesa 50A. The patterning of the mesa 50A and the formation of the STI region 204 may, in various embodiments, be performed prior to the deposition of the dielectric cap layer 56. For ease of explanation, embodiments are shown in subsequent figures in which the mesa 50A and the STI region 204 are not shown.It is clear that the embodiment of . Fig. 29 can be integrated into later process steps and linked to later descriptions. For example, the Fig. 30A to 30C show a FinFET device after further processing, e.g., using similar processes as described below in the Fig. 10A to 17C, wherein like reference numerals denote like elements manufactured by like processes, wherein a separate STI region is manufactured as described with reference to Fig. 29 is described. Fig. 30A is along the reference cross section A - A of Fig. 1 created, Fig. 30B is along the reference cross section B - B of Fig. 1 created, and Fig. 30C is along the reference cross section C - C of Fig. 1 created.

[0024] Let’s get to Fig. 8. For patterning the dielectric cap layer 56, a selective etching process may be used, in which the dielectric cap layer 56 is selectively etched at a higher rate than the dielectric cap layer 58, the dielectric material 60, and the fins 52. For example, fluorine- and nitrogen-containing chemicals or the like may be used for the etching process, and the etching may be performed at a temperature of about 30°C to about 120°C. This selective etching may be performed, for example, by using carbon and / or a metal in the dielectric cap layer 58 and the dielectric material 60.

[0025] In some embodiments, it may be advantageous to epitaxially grow a material in an NMOS region that is different from the material in a PMOS region. In various embodiments, the fins 52 may be made of silicon germanium (Si x Ge 1-x, where x can range from 0 to 1), silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, materials available for fabricating a III-V compound semiconductor include InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like.

[0026] Furthermore, Fig. 8, corresponding wells (not shown) may be formed in the fins 52 and / or the substrate 50. In some embodiments, a p-well may be formed in the region 50C, and an n-well may be formed in the region 50D. In some embodiments, a p-well or an n-well may be formed in both regions 50C and 50D.

[0027] In the embodiments with different tub types, different implantation steps for the area 50C and the area 50D (see Fig. 2) a photoresist or other masks (not shown) may be used. For example, a photoresist may be formed over the fins 52 and the dummy fins 62 in the region 50C. The photoresist may be patterned to expose the region 50D, such as a PMOS region, of the substrate 50. The photoresist may be formed by spin-coating and may be patterned using suitable photolithographic techniques. After the photoresist has been patterned, an implantation of an n-type dopant is performed in the region 50D, and the photoresist may act as a mask to largely prevent n-type dopants from being implanted into the region 50C, such as an NMOS region. The n-type dopants may be phosphorus, arsenic, or the like, and they are applied at a concentration equal to or less than 10 18 cm -3 is, for example, about 10 17 cm -3 up to about 10 18 cm-3 is implanted into the area. After implantation, the photoresist is removed, for example, using a suitable stripping process.

[0028] After the region 50D has been implanted, a photoresist is formed over the fins 52 and the dummy fins 62 in the region 50D. The photoresist is patterned to expose the region 50C, such as an NMOS region, of the substrate 50. The photoresist may be formed by spin-coating and may be patterned using suitable photolithographic techniques. After the photoresist has been patterned, an implantation of a p-type dopant is performed in the region 50C, and the photoresist may act as a mask to largely prevent p-type dopants from being implanted into the region 50D, such as the PMOS region. The p-type dopants may be boron, BF2, or the like, and they are applied at a concentration equal to or less than 1018 cm -3 is, for example, about 10 17 cm -3 up to about 10 18 cm -3 is implanted into the area. After implantation, the photoresist is removed, for example, using a suitable stripping process.

[0029] Following the implantation of regions 50C and 50D, an anneal may be performed to activate the p- and / or n-type dopants that have been implanted. In some embodiments, the grown materials of the epitaxial fins may be doped in situ during growth, which may eliminate the need for implantation, but in situ and implantation doping may also be used together.

[0030] Fig. 9 shows a top-down view of the fins 52 and the dummy fins 62. As shown, the fins 52 are enclosed by insulating materials (e.g., a combination of the dielectric cap layer 56, the dielectric cap layer 58, and the dielectric material 60). Furthermore, in the dummy fins 62, the dielectric material 60 may be enclosed by the dielectric cap layer 58. Fig. Figure 9 shows various cross sections referred to in later figures. A cross section D - D corresponds to the cross section A - A of Fig. 1, a cross section E - E corresponds to the cross section B - B of Fig. 1, and a cross section F - F corresponds to the cross section C - C of Fig. 1.

[0031] In the Fig. 10A to 10C, a dielectric dummy layer 66 is formed on the fins 52 and the dummy fins 62. Fig. 10A shows a sectional view along the line D - D of Fig. 9 and the line A - A from Fig. 1, Fig. 10B shows a sectional view along the line E - E of Fig. 9 and line B - B from Fig. 1, and Fig. 10C shows a sectional view along the line F - F of Fig. 9 and the line C - C from Fig. 1. The dielectric dummy layer 66 may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown using suitable methods. For example, the Fig. 10A to 10C illustrate dummy dielectric layer 66 formed using an exemplary thermal oxidation process in which dummy dielectric layer 66 is selectively grown on semiconductor fins 52, but not on dummy fins 62. In further embodiments (e.g., where dummy dielectric layer 66 is deposited), dummy dielectric layer 66 is formed on both semiconductor fins 52 and dummy fins 62. A dummy gate layer 68 is formed over dummy dielectric layer 66, and a mask layer 70 is formed over dummy gate layer 68. Dummy gate layer 68 may be deposited over dummy dielectric layer 66 and then planarized, for example, using CMP. Mask layer 70 may be deposited over dummy gate layer 68.The dummy gate layer 68 may be a conductive material selected from the group consisting of polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. In one embodiment, amorphous silicon is deposited and recrystallized to create polysilicon. The dummy gate layer 68 may be deposited by physical vapor deposition (PVD), CVD, sputtering, or other methods known and used in the art for depositing conductive materials. The dummy gate layer 68 may also be made of other materials that have high etch selectivity by etching isolation regions. The mask layer 70 may, for example, comprise SiN, SiON, or the like. In this example, only one dummy gate layer 68 and only one mask layer 70 are deposited over the regions 50C and 50D (see FIG. Fig. 2). In some embodiments, separate dummy gate layers may be formed in region 50C and region 50D, and separate mask layers may be formed in region 50C and region 50D.

[0032] The Fig. 11A to 17C show various further steps in the fabrication of exemplary components. Fig. 11A to 16C show structural elements in each of the regions 50C and 50D. For example, the Fig. 11A to 16C can be used for both region 50C and region 50D. Where appropriate, differences in the structures of region 50C and region 50D are described in the text accompanying each figure.

[0033] In the Fig. 11A to 11D, the mask layer 70 may be patterned using suitable photolithographic and etching processes to produce masks 70. Fig. Figure 11D shows a top-down view of the semiconductor device. Fig. Figure 11 shows various cross sections referred to in later figures. The cross section D - D corresponds to the cross section A - A of Fig. 1, the cross section E - E corresponds to the cross section B - B of Fig. 1, and the cross section F - F corresponds to the cross section C - C of Fig. 1. Fig. 11A shows a sectional view along the line A - A of Fig. 1 and the line D - D from Fig. 11D, Fig. 11B shows a sectional view along the line B - B of Fig. 1 and the line E - E from Fig. 11D, and Fig. 11C shows a sectional view along the line C - C of Fig. 1 and the line F - F from Fig. 11D.

[0034] The pattern of the masks 70 may then be transferred to the dummy gate layer 68 and the dummy dielectric layer 66 using a suitable etching process to form dummy gates 72. The dummy gates 72 cover respective channel regions of the fins 52. The pattern of the masks 70 may be used to physically separate each of the dummy gates 72 from adjacent dummy gates. Furthermore, the dummy gates 72 may have a longitudinal direction that is substantially perpendicular to the longitudinal direction of respective epitaxial fins 52 and the dummy fins 62. Furthermore, the dummy fins 62 may provide additional structural support for the dummy gates 72 formed above and along sidewalls of the dummy fins 62. For example, without the dummy fins 62, the dummy gates 72 that are not located above the fins 52 can be manufactured with planar bottom surfaces. In these embodiments (ieWithout the dummy fins 62, the dummy gates 72 with planar bottom surfaces have less structural support and may break apart, particularly if they have high aspect ratios (e.g., with heights of about 130 nm to about 160 nm and widths of about 10 nm to about 20 nm), leading to manufacturing defects. Thus, by using the dummy fins 62 in various embodiments, the structural support for the dummy gates 72 may be advantageously improved and manufacturing defects reduced.

[0035] In addition, gate seal spacers (not explicitly shown) may be formed on exposed surfaces of the dummy gates 72, the masks 70, and / or the fins 52. The gate seal spacers may be formed using thermal oxidation or deposition followed by an anisotropic etch.

[0036] After the gate seal spacers have been fabricated, implantations for lightly doped source / drain (LDD) regions (not explicitly shown) can be performed. In the embodiments with different device types, similar to the implantations described above with reference to Fig. 8, a mask, such as a photoresist, may be formed over region 50C while exposing region 50D, and dopants of a corresponding type (e.g., n-type or p-type dopants) may be implanted into the exposed fins 58 in region 50D. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over region 50D while exposing region 50C, and dopants of a corresponding type may be implanted into the exposed fins 52 in region 50C. The mask may then be removed. The n-type dopants may be some of the n-type dopants discussed above, and the p-type dopants may be some of the p-type dopants discussed above. The lightly doped source / drain regions may have a dopant concentration of about 10 15 cm -3 up to about 10 16 cm -3Annealing can be performed to activate the implanted dopants.

[0037] In the Fig. 12A to 12C, gate spacers 74 are formed on the gate seal spacers (not explicitly shown) along sidewalls of the dummy gates 72. The gate spacers 74 may be formed by conformally depositing a material followed by anisotropic etching of the material. The material of the gate spacers 74 may be silicon nitride, SiCN, a combination thereof, or the like.

[0038] In the Fig. 13A to 13C and 14A to 14C, epitaxial source / drain regions 82 are formed in the fins 52. The epitaxial source / drain regions 82 are formed in the fins 58 such that each dummy gate 72 is located between respective adjacent pairs of the epitaxial source / drain regions 82. In some embodiments, these epitaxial source / drain regions 82 may extend into the fins 52. In some embodiments, the gate spacers 74 are used to separate the epitaxial source / drain regions 82 from the dummy gates 72 by an appropriate lateral distance such that the epitaxial source / drain regions 82 do not short-circuit later-formed gates of the resulting FinFETs.

[0039] Let us first look at the Fig. 13A to 13C. Here, parts of the semiconductor fins 52 are etched, such as the parts of the fins 52 that are not covered by the dummy gates 72 in the cross sections B - B and C - C of Fig. 1 are masked (see Fig. 13B and Fig. 13C). By etching the semiconductor fins 52, they may be recessed beneath a top surface of the dielectric cap layer 56. A selective etching process may be used to recess the fins 52, in which the fins 52 are etched without significantly etching the dummy gates 72 or the dummy fins 62. In various embodiments, the fins 52 may be recessed separately in the regions 50B and 50C, for example, while the other region is masked.

[0040] In the Fig. 14A to 14C, the epitaxial source / drain regions 82 in region 50C, e.g., the NMOS region, may be formed by masking region 50D, e.g., the PMOS region, and by etching the source / drain regions of the fins 58 in region 50C, creating recesses in the fins 58. Then, the epitaxial source / drain regions 82 in region 50C are epitaxially grown in the recesses. The epitaxial source / drain regions 82 may comprise a suitable material, such as a material suitable for n-type FinFETs. For example, if the fin 58 is made of silicon, the epitaxial source / drain regions 82 in region 50C may comprise silicon, SiC, SiCP, SiP, or the like. The epitaxial source / drain regions 82 in the region 50C may have surfaces that are raised from respective surfaces of the fins 58 and may have chamfers.In some embodiments, the dummy fins 62 provide physical separation between adjacent ones of the epitaxial source / drain regions 82 in the region 50C and prevent merging of adjacent epitaxial source / drain regions 82 in the region 50C during epitaxy.

[0041] The epitaxial source / drain regions 82 in region 50D, e.g., the PMOS region, may be formed by masking region 50C, e.g., the NMOS region, and etching the source / drain regions of the fins 58 in region 50D to create recesses in the fins 58. Then, the epitaxial source / drain regions 82 in region 50D are epitaxially grown in the recesses. The epitaxial source / drain regions 82 may comprise a suitable material, such as a material suitable for p-type FinFETs. For example, if the fin 58 is made of silicon, the epitaxial source / drain regions 82 in region 50D may comprise SiGe, SiGeB, Ge, GeSn, or the like. The epitaxial source / drain regions 82 in the region 50D may also have surfaces that are raised from respective surfaces of the fins 58 and may have chamfers.In some embodiments, the dummy fins 62 provide physical separation between adjacent ones of the epitaxial source / drain regions 82 in the region 50D and prevent merging of adjacent epitaxial source / drain regions 82 in the region 50D during epitaxy.

[0042] The epitaxial source / drain regions 82 and / or the fins 52 may be implanted with dopants to form source / drain regions, similar to the process discussed above for forming lightly doped source / drain regions, followed by an anneal. The source / drain regions may have a doping concentration of about 10 19 cm -3 up to about 10 21 cm -3The n- and / or p-type dopants for the source / drain regions may be some of the dopants discussed above. In some embodiments, the epitaxial source / drain regions 82 may be doped in situ during growth.

[0043] Due to the epitaxial processes used to form the epitaxial source / drain regions 82 in the regions 50C and 50D, the top surfaces of the epitaxial source / drain regions 82 have chamfers that extend laterally outward beyond sidewalls of the fins 52. As shown in Fig. 14B, the top surfaces of the epitaxial source / drain regions 82 may contact the sidewalls of the dummy fins 62, and the dummy fins 62 may prevent adjacent epitaxial source / drain regions 82 from fusing. This may be particularly advantageous in areas with small pitches (e.g., in memory regions) of a chip where different devices are closely spaced, and the dummy fins 62 may serve to prevent the fusing of the epitaxial source / drain regions 82 of different devices adjacent to each other (e.g., an n-type device and a p-type device). Alternatively, as shown in Fig. 14D, the dummy fins 62 may be etched back before the epitaxial source / drain regions 82 are formed. For example, a height H2 of the dummy fins 62 in Fig. 14D smaller than a height H1 of the dummy fins 62 in the Fig. 13B and Fig. 14B. Due to the etching, the dummy fins 62 do not prevent the fusion of adjacent epitaxial source / drain regions. Therefore, Fig. 14D, some epitaxial source / drain regions 82 are located above the dummy fins 62, and they have a fused profile. Fused epitaxial source / drain regions may be beneficial for increasing a current transport area of ​​the device, which lowers resistance. In some embodiments, the different profiles of the epitaxial source / drain regions 82 and the dummy fins 62 in the Fig. 14B and Fig. 14D in a single die. For example, epitaxial source / drain regions 82 and dummy fins 62, which are Fig. 14B shown configuration (ie, non-fused source / drain regions), found in a first region of a die, and epitaxial source / drain regions 82 and dummy fins 62 having the configuration shown in Fig. 14D (i.e., fused source / drain regions) are found in a second region of the die. In a specific example, the first region of the die is a memory region, and the second region of the die is a logic region. Subsequent embodiments show only non-fused epitaxial source / drain regions 82, but the configuration described in connection with Fig. 14D may also be used for the subsequent embodiments either in place of or together with the non-fused epitaxial source / drain regions.

[0044] In the Fig. 15A to 15C, an ILD (interlayer dielectric) 88 is deposited over the structure shown in the Fig. 14A to 14C. The ILD 88 may be made of a dielectric material and may be deposited using a suitable process such as CVD, plasma-enhanced CVD (PECVD), or flowable chemical vapor deposition (FCVD). The dielectric materials may be phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed using a suitable process may also be used. In some embodiments, a contact etch stop layer (CESL) (not shown) is disposed between the ILD 88 and the epitaxial source / drain regions 82, the hard mask 70, and the gate spacers 74.

[0045] Subsequently, a planarization process, such as CMP, may be performed to bring the top surface of the ILD 88 level with the top surfaces of the dummy gate electrodes 68. In one embodiment, the planarization process is performed using a planarization system 200. The planarization process may also remove the masks 70 on the dummy gate electrodes 68, as well as portions of the gate seal spacers and the gate spacers 74 along the sidewalls of the masks 70. After the planarization process, the top surfaces of the dummy gate electrodes 68, the gate spacers 74, and the ILD 88 are level. Thus, the top surfaces of the dummy gate electrodes 68 are exposed through the ILD 88.

[0046] After planarization, the dummy gate electrodes 68 and portions of the dummy dielectric layer 60 located directly beneath the exposed dummy gate electrodes 68 are removed in one or more etching steps to form recesses. In some embodiments, the dummy gate electrodes 68 are removed using an anisotropic dry etching process. For example, the etching process may be a dry etching process using reactive gases that selectively etch the dummy gate electrodes 68 without etching the ILD 88 or the gate spacers 74. Each recess exposes a channel region of a respective fin 52. Each channel region is disposed between adjacent pairs of the epitaxial source / drain regions 82. During removal, the dummy dielectric layer 60 may be used as an etch stop layer when the dummy gate electrodes 68 are etched.The dummy dielectric layer 60 may also be removed after removing the dummy gate electrodes 68.

[0047] In the Fig. 16A through 16C, gate dielectric layers 92 and gate electrodes 94 for replacement gates are formed. The gate dielectric layers 92 are conformally deposited in the recesses, such as on the top surfaces and sidewalls of the fins 52 and the dummy fins 62, and on the sidewalls of the gate spacers 74. The gate dielectric layers 92 may also be formed on the top surface of the ILD 88. In some embodiments, the gate dielectric layers 92 comprise silicon oxide, silicon nitride, or multilayers thereof. In some embodiments, the gate dielectric layers 92 are made of a high-k dielectric material, and in these embodiments, the gate dielectric layers 92 may have a k value greater than about 7.0 and may comprise a metal oxide or silicate of Hf, Al, Zr, La, Mg, Ba, Ti, or Pb, or combinations thereof.The manufacturing methods for the gate dielectric layers 92 may be molecular beam deposition (MBD), ALD, PECVD, and the like.

[0048] The gate electrodes 94 are each deposited over the gate dielectric layers 92. The gate electrodes 94 may be made of a metal-containing material such as TiN, TaN, TaC, Co, Ru, Al, or combinations thereof, or multilayers thereof. While only one gate electrode 94 is shown, any number of work function adjustment layers may be deposited in the recesses 90. After filling the gate electrodes 94, a planarization process, such as CMP, may be performed to remove excess portions located above the top of the ILD 88, the gate dielectric layers 92, and the gate electrode 94 material. The remaining portions of the gate electrode 94 material and the gate dielectric layers 92 thus form replacement gates of the resulting FinFETs. The gate electrodes 94 and the gate dielectric layers 92 may be collectively referred to as a gate or a gate stack.The gate and gate stack may extend along the sidewalls of a channel portion of the fins 52 and along the sidewalls of the dummy fins 62.

[0049] The formation of the gate dielectric layers 92 in region 50C may occur simultaneously with that in region 50D, such that the gate dielectric layers 92 in each region are made of the same materials, and the formation of the gate electrodes 94 may also occur simultaneously in both regions, such that the gate electrodes 94 in each region are made of the same materials. In some embodiments, the gate dielectric layers 92 in each region may be formed using different processes, such that they may be made of different materials, and the gate electrodes 94 in each region may also be formed using different processes, such that they may be made of different materials. If different processes are used, different masking steps may be used to mask and expose corresponding regions.

[0050] In the Fig. 17A through 17C, an ILD 108 is deposited over the ILD 88. In one embodiment, the ILD 108 is a flowable layer formed using a flowable CVD process. In some embodiments, the ILD 108 is made of a dielectric material such as PSG, BSG, BPSG, USG, or the like, and may be deposited using a suitable process such as CVD or PECVD.

[0051] In addition, the Fig. 17A through 17C, contacts 110 and 112 are formed by the ILD 108 and the ILD 88 using exemplary contact fabrication techniques. In some embodiments, an annealing process may be performed to create a silicide at the interface between the epitaxial source / drain regions 82 and the contacts 112 before the contacts 112 are formed. The contact 110 is physically and electrically connected to the gate electrode 94, and the contacts 112 are physically and electrically connected to the epitaxial source / drain regions 82. Fig. Figure 17C shows contacts 110 and 112 in the same cross-section, but in other embodiments, contacts 110 and 112 may be arranged in different cross-sections. Furthermore, the positions of contacts 110 and 112 in the Fig. 17A through 17C are illustrative only and are not intended to be limiting in any way. For example, contact 110 may be vertically aligned with semiconductor fin 52, as shown, or it may be disposed at a different position on gate electrode 94. Furthermore, contacts 112 may be formed before, simultaneously with, or after the formation of contact 110.

[0052] The Fig. 17D to 17F show a device in which the dielectric layer 58 is omitted. In these embodiments, the dummy fins 62 are defined by portions of the dielectric layer 60 that extend above the dielectric layer 56. Because the dummy fins 62 are defined by only one layer, they have the same material composition throughout. Furthermore, a combination of the dielectric layer 56, the lower portions of the dielectric layer 60, and the cavities 61 (if present) may enable separation between adjacent semiconductor fins 52.

[0053] The Fig. 18 to 22 show sectional views of intermediate stages in the manufacture of a component according to further embodiments. In contrast to the embodiments of Fig. 2 to 9 will be in the Fig. 18 to 22, the mask layer 54 is removed (e.g., with a suitable planarization or etch-back process) before the dielectric layer 56 is formed. In these embodiments, the dielectric layer 56 may be formed directly on top of the semiconductor fins 52 without any mask layers 54 therebetween. The subsequent processing may be substantially the same as the processing in the embodiment of Fig. 2 to 9, where like reference numerals indicate like elements made by like processes. For example, in Fig. 19 an optional layer 58 is deposited over the dielectric layer 56. In Fig. 20, a dielectric material 60 is deposited over the dielectric layer 56 and the dielectric layer 58 (if present). The dielectric material 60 is deposited to at least partially fill regions between the semiconductor fins 52, and it is further deposited to overfill and cover the dielectric layers 56 and 58 (if present). Fig. 21, a planarization process is used for the dielectric material 60 to expose the top surfaces of the fins 52, the dielectric layer 56, and the dielectric layer 58 (if present). Fig. 21 that the fins 52, the dielectric layer 56, the dielectric layer 58 and the dielectric material 60 are coplanar after planarization, but in other embodiments these top surfaces may be non-planar (as shown, for example, in Fig. 7B). Subsequently, Fig. 22, an etch-back process is performed on the dielectric layer 56 to define the semiconductor fins 52 and the dummy fins 62, which may comprise, for example, upper portions of the dielectric layer 58 (if present) and the dielectric material 60. After the semiconductor fins 52 and the dummy fins 62 have been formed (see Fig. 22), further process steps similar to those described above with reference to the Fig. 10A to 17C, to fabricate functional FinFET devices. Fig. 18 through 22 illustrate the use of the optional dielectric layer 58, in other embodiments, the dielectric layer 58 may be omitted and the dielectric material 60 may be deposited directly on the dielectric layer 56.

[0054] The Fig. 23 to 27 show sectional views of intermediate stages in the manufacture of a component according to further embodiments. Fig. Figure 23 shows a sectional view at a manufacturing stage corresponding to that of Fig. 6, wherein like reference numerals indicate like elements manufactured by like processes. Fig. Although Figure 23 shows the use of the dielectric layer 58, the dielectric layer 58 is optional. In other embodiments, the dielectric layer 58 is omitted (see, for example, Figures Fig. 28D to 28F).

[0055] In Fig. 24, an etch-back process is used to pattern the dielectric material 60 to expose the dielectric layer 58 (if present) or the dielectric layer 56 (if the optional dielectric layer 58 is missing). In Fig. 25, a dielectric material 202 is deposited over the dielectric layer 56 and the dielectric layer 58 (if present). In some embodiments, the dielectric material 202 may be deposited using a flowable deposition process, a spin-on process, or the like. The dielectric material 202 may include a carbon-containing dielectric layer (e.g., a carbon-containing oxide, such as SiOC), a metal-containing dielectric layer (e.g., a metal-containing oxide, such as a combination of SiO and a metal), or the like. In some embodiments, the mass fraction of carbon and / or metal in the dielectric material 202 is less than a corresponding mass fraction of carbon and / or metal in the capping dielectric layer 58.For example, the dielectric cap layer 58 may comprise SiOC with greater than 10 mass % carbon, and the dielectric material 202 may comprise SiOC with less than 10 mass % carbon. The material composition of the dielectric material 202 and that of the dielectric material 60 may be the same or different. For example, the dielectric material 202 and the dielectric material 60 may have the same or different mass fractions of carbon / metal. In some embodiments, the dielectric material 202 provides additional protection for the dielectric material 60, and the dielectric material 202 encapsulates the dielectric material 60.

[0056] In Fig. 26, the top surfaces of the dielectric layer 56 are exposed using a planarization (e.g., a CMP) and / or an etch-back process (e.g., a dry etch process). In some embodiments, after exposing the dielectric layer 56, the top surfaces of the dielectric material 202 and the dielectric layer 56 are substantially coplanar.

[0057] In Fig. 27, a further etch-back process is performed on the dielectric cap layer 56. The dielectric cap layer 56 is recessed so that the semiconductor fins 52 and the dummy fins 62 protrude above the top surface of the etched dielectric cap layer 56. After the dielectric cap layer 56 has been recessed, the hard mask 54 may also be removed from the top surfaces of the fins 52, for example, using a suitable etching process. In some embodiments, after the recessing, a height of the semiconductor fins 52 may be smaller than a height of the dummy fins 62. The dummy fins 62 consist of upper portions of the dielectric cap layer 58 (if present), upper portions of the dielectric material 60, and remaining portions of the dielectric material 202. Thus, the dummy fins 62 may have a different material composition than the semiconductor fins 52, and the dummy fins 62 may be insulating fins.In addition, remaining portions of the dielectric cap layer 56, lower portions of the dielectric cap layer 58, and lower portions of the dielectric material 60 (collectively referred to as isolation region 64) provide electrical isolation between adjacent fins 52, and may further provide STI regions between the fins 52, eliminating the need to fabricate a separate STI region.

[0058] In further embodiments, a separate STI region is formed (e.g., between a bottom surface of the dielectric cap layer 56 and the substrate 50). For example, Fig. 31 illustrates an embodiment in which a separate STI region 204 is formed between lower portions of the dielectric cap layer 56 and an upper portion of the substrate 50 (labeled 50A). In the embodiment of Fig. 30A to 30C, individual fins 52 may be connected by a mesa 50A (sometimes referred to as a crown). The mesa 50A is a portion of the substrate 50. Multiple fins 52 may extend from a single mesa 50A connected to a lower portion of the substrate 50 (denoted as 50B). The mesa 50A may enable better structural stability when manufacturing fins with a high aspect ratio (e.g., fins 52). The STI region 204 may be manufactured to extend along lower portions of the fins 52 as well as along sidewalls of the mesa 50A. For ease of explanation, embodiments are shown in subsequent figures in which the mesa 50A and the STI region 204 are not shown. It will be appreciated that the embodiment of Fig. 31 can be integrated into later process steps and linked to later descriptions. For example, the Fig. 32A to 32C show a FinFET device after further processing, e.g., using similar methods as described above in the Fig. 10A to 17C, wherein like reference numerals indicate like elements fabricated by like processes, using a separate STI region and the dielectric material 202 as described with reference to Fig. 31 is described. Fig. 32A is along the reference cross section A - A of Fig. 1 created, Fig. 32B is along the reference cross section B - B of Fig. 1 created, and Fig. 32C is along the reference cross section C - C of Fig. 1 created.

[0059] In some embodiments, a selective etch process may be used to etch back the dielectric cap layer 56, in which the dielectric cap layer 56 is selectively etched at a higher rate than the dielectric cap layer 58, the dielectric material 60, and the fins 52. For example, carbon and / or a metal may be used in the dielectric cap layer 58 and the dielectric material 60 for this selective etching.

[0060] After the semiconductor fins 52 and the dummy fins 62 have been manufactured (see Fig. 27), further process steps similar to those described above with reference to the Fig. 10A to 17C to fabricate functional FinFET devices. The resulting structures are shown in Fig. 28A (which is a component along a similar cross-section as A - A of Fig. 1 shows), in Fig. 28B (which shows a component along a similar cross-section as A - A of Fig. 1 shows) and in Fig. 28C (which is a component along a similar cross-section as A - A of Fig. 1), where like reference numerals denote like elements fabricated by like processes. Because the dummy fins 62 extend over the semiconductor fins 52, the dummy fins 62 may be even more effective in reducing the fusion of adjacent epitaxial source / drain regions 82. The Fig. 23 to 27 show the removal of the mask layer 54 after the deposition of the dielectric material 202, but in other embodiments the mask layer 54 may also be removed before the deposition of the dielectric layer 56 (as shown, for example, in Fig. 18). In these embodiments, the dielectric layer 56 can be fabricated directly on the sidewalls and top of the fins 52 (see Fig. 18).

[0061] The Fig. 28D to 28F show a component similar to the component shown in the Fig. 28A to 28C, with the dielectric layer 58 omitted. In the Fig. 28D to 28F, similar reference numerals denote similar elements which can be assembled by similar methods as in the Fig. 28A to 28C. In these embodiments, the dummy fins 62 are defined by portions of the dielectric layer 60 that extend above the dielectric layer 56 and the dielectric material 202. Additionally, a combination of the dielectric layer 56, the lower portions of the dielectric layer 60, and the cavities 61 (if present) may provide separation between adjacent semiconductor fins 52.

[0062] The invention is defined by the main claim and the subordinate claims. Further embodiments of the invention are recited in the dependent claims.

Claims

[1] Procedure with the following steps: Depositing a first dielectric layer (56) over and along sidewalls of a semiconductor fin (52), the semiconductor fin (52) extending upwardly from a semiconductor substrate (50); Depositing a dielectric material (60) over the first dielectric layer (56), wherein depositing the dielectric material (60) comprises defining a cavity (61) beneath the dielectric material (60) between the semiconductor fin (52) and a second semiconductor fin (52); Recessing the first dielectric layer (56) beneath a top surface of the semiconductor fin (52) to define a dummy fin (62), the dummy fin (62) comprising an upper portion of the dielectric material (60); and Forming a gate stack (92, 94) over and along sidewalls of the semiconductor fin (52) and the dummy fin (62). [2] The method of claim 1, wherein depositing the dielectric material (60) comprises covering a top surface of the first dielectric layer (56) with the dielectric material (60), the method further comprising planarizing the dielectric material (60) to expose the first dielectric layer (56). [3] The method of any preceding claim, wherein recessing the first dielectric layer (56) comprises etching the first dielectric layer (56) at a rate higher than that for the dielectric material (60). [4] The method of any preceding claim, further comprising depositing a second dielectric layer (58) over the first dielectric layer (56) prior to depositing the dielectric material (60), wherein the dummy fin (62) has an upper portion comprised of the second dielectric layer (58). [5] A method according to any one of the preceding claims, further comprising: Recessing the dielectric material (60) beneath a top surface of the first dielectric layer (56) prior to recessing the first dielectric layer (56); Depositing a second dielectric material (202) over the dielectric material (60) and the first dielectric layer (56); and Planarizing the second dielectric material (202) to expose the first dielectric layer (56). [6] The method of any preceding claim, further comprising patterning the semiconductor substrate (50) using a mask layer (54) to define the semiconductor fin (52), wherein the first dielectric layer (56) is deposited over and along sidewalls of the mask layer (54). [7] A method according to any one of the preceding claims, further comprising: Structuring the semiconductor substrate (50) using a mask layer (54) to define the semiconductor fin (52); and Removing the mask layer (54) before depositing the first dielectric layer (56). [8] Device with: a first semiconductor fin (52) and a second semiconductor fin (52) extending upward from a semiconductor substrate (50); a separation region (64) having a first dielectric layer (56) and disposed between the first semiconductor fin (52) and the second semiconductor fin (52); a dummy fin (62) extending upwardly from the separation region (64), the dummy fin (62) comprising a first dielectric material (60) extending from a position below a top surface of the first dielectric layer (56) to a position above the top surface of the first dielectric layer (56); a cavity (61) between the dielectric material (60) and the dielectric layer (56); and a gate stack (92, 94) extending over and along sidewalls of the first semiconductor fin (52), over and along sidewalls of the second semiconductor fin (52), and over and along sidewalls of the dummy fin (62). [9] The device of claim 8, wherein the first dielectric layer (56) comprises silicon oxide and the first dielectric material (60) comprises a carbonaceous oxide, a metalaceous oxide, or a combination thereof. [10] The device of claim 8 or 9, wherein the dummy fin (62) comprises a second dielectric layer (58) disposed between the first dielectric layer (56) and the first dielectric material (60). [11] The device of claim 10, wherein a mass fraction of carbon in the second dielectric layer (58) is greater than a mass fraction of carbon in the first dielectric material (60). [12] The device of claim 10 or 11, wherein a mass fraction of the metal in the second dielectric layer (58) is greater than a mass fraction of the metal in the first dielectric material (60). [13] The device of any one of claims 8 to 12, wherein the dummy fin (62) further comprises a second dielectric material (202) covering a top surface of the first dielectric material (60). [14] The device according to any one of claims 8 to 13, wherein top surfaces of the dummy fin (62) and the first semiconductor fin (52) are substantially at the same height. [15] The device of any one of claims 8 to 14, wherein the dummy fin extends higher than the first semiconductor fin. [16] The device of any one of claims 8 to 15, further comprising a semiconductor mesa (50A) connecting the first semiconductor fin (52) to the second semiconductor fin (52), wherein the isolation region (64) further comprises a third dielectric material (204) disposed between the first dielectric layer (56) and the semiconductor mesa (50A), and the third dielectric material (204) further extends along sidewalls of the semiconductor mesa (50A). [17] Device according to one of claims 8 to 16, further comprising: a second dummy fin (62) disposed on a side of the first semiconductor fin (52) opposite the dummy fin (62), the second dummy fin (62) extending upward from the separation region (64) and comprising the first dielectric material (60); and a source / drain region (82) disposed between the dummy fin (62) and the second dummy fin (62). [18] Procedure with the following steps: Depositing a first dielectric layer (56) over and along sidewalls of a plurality of semiconductor fins (52); Depositing a dielectric material (60) over the first dielectric layer (56), wherein the dielectric material (60) comprises carbon, metal, or a combination thereof and is disposed between each of the plurality of semiconductor fins (52), wherein depositing the dielectric material (60) comprises defining a cavity (61) under the dielectric material (60) between a first semiconductor fin of the plurality of semiconductor fins (52) and a second semiconductor fin (52) of the plurality of semiconductor fins (52); Planarizing the dielectric material (60) to expose the first dielectric layer (56); Etching the first dielectric layer (56) using an etchant that etches the first dielectric layer (56) at a higher rate than the dielectric material, wherein the etching of the first dielectric layer (56) defines a plurality of dummy fins (62) extending over a top surface of the first dielectric layer (56), the plurality of dummy fins (62) comprising at least a portion of the dielectric material (60); and Forming a gate stack (92, 94) over and along sidewalls of the plurality of semiconductor fins (52) and over and along sidewalls of the plurality of dummy fins (62). [19] The method of claim 18, further comprising, prior to depositing the dielectric material (60), depositing a second dielectric layer (58) over the first dielectric layer (56), wherein the second dielectric layer (58) comprises carbon, metal, or a combination thereof, and the plurality of dummy fins (62) comprises at least a portion of the second dielectric layer (58).

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