Memory modules and memory systems with the same

Abstract

Memory module (100, 100a, 720, 730, 950) which has the following features: a plurality of semiconductor memory devices (200, 201a~201e, 202a~202e, 203a~203e, 204a~204e, 500) connected to an identical module circuit board (101), each of the plurality of semiconductor memory devices (200, 201a~201e, 202a~202e, 203a~203e, 204a~204e, 500) having a memory cell arrangement (300) comprising a plurality of dynamic memory cells, the plurality of semiconductor memory devices (200, 201a~201e, 202a~202e, 203a~203e, 204a~204e, 500) being configured to perform a training operation simultaneously, the plurality of semiconductor memory devices (200, 201a~201e, 202a~202e, 203a~203e, 204a~204e, 500) has a receiving interface circuit (400, 400a, 400b, 520, 621) which is configured to to perform the training operation to search for selected equalization coefficients of an equalizer (410, 522) based on a training structure from a memory controller (25, 710), and to transmit a training information signal to the memory controller (25, 710) in a training mode in response to a training command from the memory controller (25, 710), wherein the training information signal has the selected equalization coefficients, wherein the receiving interface circuit (400, 400a, 400b, 520, 621) has the following: the equalizer (410, 522), which is configured to generate an equalizer output structure by equalizing the training structure based on control equalization coefficients in the training mode; and a self-training circuit (430, 530) which is configured to provide the control equalization coefficients for the equalizer (410, 522), wherein the self-training circuit (430, 530) is configured to to generate an error count value that indicates a difference between the equalizer output structure and a reference structure, and adaptively adjust search equalizer coefficients to provide the control equalizer coefficients for the equalizer (410, 522) based on the error count value and a reference value, wherein The equalizer (410, 522) uses the search equalization coefficients to search for the selected equalization coefficients.

Description

BACKGROUND 1. Technical field

[0001] Exemplary embodiments relate to a storage device. For example, at least some exemplary embodiments relate to storage modules and storage systems that incorporate the same features. 2. Description of the state of the art

[0002] A semiconductor memory can be a storage device implemented using a semiconductor such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), or the like. Semiconductor memory devices are typically divided into volatile and non-volatile storage devices.

[0003] A volatile storage device refers to a storage device in which stored data is lost when a power supply is switched off. Conversely, a non-volatile storage device refers to a storage device that retains stored data when a power supply is switched off. Because dynamic random-access memory (DRAM), which is a type of volatile storage device, has a high access speed, DRAM is widely used as working memory, buffer memory, main memory, and the like in computing systems or computer systems. With the development of computing technologies and computer technologies, the demand for DRAM as working memory in computing systems is increasing.Since a DRAM memory cell generally contains a capacitor and a transistor, it is difficult to reduce the cell size below a constant level. Therefore, it is difficult to implement high-capacity DRAM within a limited area.

[0004] To implement high capacity, multiple DRAMs are arranged in a single memory module. A training operation can be performed sequentially on the DRAMs to configure them for proper operation based on the results of this operation.

[0005] From US patent 2010 / 0005281A1, a memory buffer, a memory system, and a method for power-up initialization and testing of a cascaded interconnect memory system are known. The memory buffer includes a bus interface to connections in a high-speed channel for communication with a memory controller via a direct connection or via a cascade circuit through another memory buffer. The interface is operational in a Static Bit Communication (SBC) mode and a high-speed mode. The memory buffer also includes a Field Service Interface (FSI) slave for receiving FSI signals from an FSI master. Furthermore, the memory buffer contains logic for executing a power-up and initialization training sequence initiated by the memory controller. SUMMARY

[0006] According to exemplary embodiments, a memory module comprises a plurality of semiconductor memory devices connected to an identical module board or circuit board, wherein the plurality of semiconductor memory devices is configured to perform a training operation simultaneously, wherein the plurality of semiconductor memory devices comprises a receiver interface circuit configured to perform the training operation to search for selected equalization coefficients of an equalizer based on a training structure from a memory controller, and to transmit a training information signal to the memory controller in a training mode in response to a training command from the memory controller, wherein the training information signal comprises the selected equalization coefficients.The receiver interface circuit includes an equalizer, configured to generate an equalizer output structure by equalizing the training structure based on control equalization coefficients in training mode, and a self-training circuit, configured to provide the control equalization coefficients for the equalizer. The self-training circuit is configured to generate an error count, indicating a difference between the equalizer output structure and a reference structure, and to adaptively adjust search equalization coefficients to provide the control equalization coefficients for the equalizer based on the error count and a reference value. The equalizer uses the search equalization coefficients to search for the selected equalization coefficients.

[0007] According to exemplary embodiments, a memory system comprises a memory controller and a memory module, which has a plurality of semiconductor memory devices, wherein the plurality of semiconductor memory devices is configured to perform a training operation simultaneously, wherein the plurality of semiconductor memory devices has a receiver interface circuit configured to perform a training operation to search for selected equalization coefficients of an equalizer based on a training structure received from the memory controller, and to transmit a training information signal to the memory controller in a training mode in response to a training command from the memory controller, wherein the training information signal has the selected equalization coefficients.The receiver interface circuit includes an equalizer, configured to generate an equalizer output structure by equalizing the training structure based on control equalization coefficients in training mode, and a self-training circuit, configured to provide the control equalization coefficients for the equalizer. The self-training circuit is configured to generate an error count, indicating a difference between the equalizer output structure and a reference structure, and to adaptively adjust search equalization coefficients to provide the control equalization coefficients for the equalizer based on the error count and a reference value. The equalizer uses the search equalization coefficients to search for the selected equalization coefficients.

[0008] Consequently, in a memory module containing multiple semiconductor memory devices, these devices simultaneously perform a training process to search for desired (or alternatively, optimal) equalization coefficients and transmit a training information signal containing these coefficients to a memory controller in a training mode. Therefore, the memory module containing these semiconductor memory devices can significantly reduce the training time. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Illustrative, non-restrictive exemplary embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings. Fig. Figure 1 is a block diagram illustrating a storage system according to exemplary embodiments. Fig. Figure 2 is a block diagram, which shows an example of the memory module in Fig. 1 illustrated in detail according to exemplary embodiments. Fig. Figure 3 illustrates a connection relationship between the memory controller and the semiconductor storage devices in the memory system of the Fig. 1. Fig. 4 is a block diagram which shows one of the semiconductor storage devices in Fig. 2 illustrated according to exemplary embodiments. Fig. Figure 5 illustrates an example of the first bank arrangement in the semiconductor storage device of the Fig. 4. Fig. Figure 6 illustrates an example of a connection between the memory controller and a semiconductor storage device in the memory system of the Fig. 1 according to exemplary embodiments. Fig. Figure 7 is a circuit diagram showing an example of the equalizer in the receiver interface circuit in Fig. 6 illustrated according to exemplary embodiments. Fig. Figure 8 is a circuit diagram showing another example of the equalizer in the receiver interface circuit of the Fig. 6 illustrated according to exemplary embodiments. Fig. Figure 9 is a circuit diagram showing another example of the equalizer in the receiver interface circuit of the Fig. 6 illustrated according to exemplary embodiments. Fig. Figure 10 is a block diagram, which shows an example of the margin checker in the self-training circuit of the Fig. 6 illustrated according to exemplary embodiments. Fig. Figure 11 is a block diagram, which shows another example of the margin checker in the self-training circuit of the Fig. 6 illustrated according to exemplary embodiments. Fig. Figure 12 is a block diagram which shows an example of the adaptation machine in the self-training circuit in Fig. 6 illustrated according to exemplary embodiments. Fig. Figure 13 is a block diagram illustrating a semiconductor storage device according to exemplary embodiments. Fig. Figure 14 is a circuit diagram showing the reference voltage generator in the self-training circuit of the Fig. 13 illustrated according to exemplary embodiments. Fig. 15 is a block diagram, which shows another example of the memory module in Fig. 1 illustrated in detail according to exemplary embodiments. Fig. 16 is a block diagram which shows an example of the control device in the storage module of the Fig. 15 illustrated according to exemplary embodiments. Fig. Figure 17 illustrates an example of the training information storage table in Fig. 16 according to exemplary embodiments. Fig. 18 is a diagram to describe a termination with a mid-tap. Fig. Figure 19 is a diagram describing a pseudo-open drain termination. Fig. 20 is a time diagram which is an example of a training operation of the memory module of the Fig. 2 or of the memory module of the Fig. 15 illustrated. Fig. Figure 21 is a block diagram illustrating a storage system according to exemplary embodiments. Fig. Figure 22 is a flowchart illustrating a method for operating a memory module according to exemplary embodiments. Fig. Figure 23 is a block diagram illustrating a memory system which has quad-rank memory modules according to exemplary embodiments. Fig. Figure 24 is a block diagram illustrating a mobile system which includes the storage module according to exemplary embodiments. DETAILED DESCRIPTION

[0010] Exemplary embodiments of the inventive concepts will be more clearly understood from the following detailed description together with the accompanying drawings, where the same reference numerals refer to the same parts across the different figures unless otherwise specified.

[0011] Fig. Figure 1 is a block diagram illustrating a storage system according to exemplary embodiments.

[0012] Referring to Fig. In Figure 1, a storage system 10 has a host 20 and a storage module 100. The host 20 can have a storage controller 25.

[0013] The memory module 100 may include a control device (or register-based or buffered clock driver, RCD, where the RCD may be considered a control device) 110, a serial presence detect (SPD) chip 180, and an integrated power management circuit (PMIC) 190. Furthermore, the memory module 100 may include semiconductor devices 200.

[0014] The control device 110 can control the semiconductor memory devices 200 and the PMIC 190 under the control of the memory controller 25. For example, the control device 110 can receive an address ADDR, a command CMD, and a clock signal CLK from the memory controller 25. In response to received signals, the control device 110 can control the semiconductor memory devices 200 such that data received via a data signal DQ and a data strobe signal DQS is written to the semiconductor memory devices 200, or such that data stored in the semiconductor memory devices 200 is output via the data signal DQ and the data strobe signal DQS. For example, the control device 110 can transmit the address ADDR, the command CMD, and the clock signal CLK from the memory controller 25 to the semiconductor memory devices 200.

[0015] The semiconductor memory devices 200 can write data received via the data signal DQ and the data strobe signal DQS under the control of the control device 110. Alternatively, the semiconductor memory devices 200 can output the written data via the data signal DQ and the data strobe signal DQS under the control of the control device 110. The semiconductor memory devices 200 can have various memory configurations.

[0016] For example, the semiconductor memory devices 200 can have DRAM-based volatile memory devices. For example, the semiconductor memory devices 200 can have a volatile memory device such as DRAM, SRAM, and / or SDRAM. The semiconductor memory devices 200 can have a dual-data-rate 5 (DDR5) SDRAM.

[0017] The SPD chip 180 can be a programmable read-only memory (for example, EEPROM). The SPD chip 180 can contain initial information or device information DI of the memory module 100. In exemplary embodiments, the SPD chip 180 can contain the initial information or device information DI, such as a module shape, module configuration, storage capacity, module type, execution environment, and the like, of the memory module 100. When the storage system 10, which includes the memory module 100, is powered on, the host 20 can read the device information DI from the SPD chip 180 and can detect the memory module 100 based on the device information DI. The host 20 can control the memory module 100 based on the device information DI from the SPD chip 180.For example, the host 20 can detect a type of semiconductor memory device 200 contained in the memory module 100 based on the device information DI from the SPD chip 180.

[0018] In exemplary embodiments, the SPD chip 180 can communicate with the host 20 via a serial bus. The SPD chip 180 can communicate with the control device 110 via a serial bus. The serial bus can comprise at least one of two-wire serial buses, such as an Inter-Integrated Circuit (I2C), a System Management Bus (SMBus), a Power Management Bus (PMBus), an Intelligent Platform Management Interface (IPMI), a Management Component Transport Protocol (MCTP), and the like.

[0019] The control device 110 can control the PMIC 190 via a first control signal CTL1 and can control the semiconductor memory devices 200 via a second control signal CTL2. The second control signal CTL2 can contain the address ADDR, the instruction CMD, and the clock signal CLK.

[0020] The PMIC 190 receives an input voltage VIN, generates a power supply voltage VDD based on the input voltage, and provides the power supply voltage VDD to the semiconductor memory devices 200. The semiconductor memory devices 200 operate based on the power supply voltage VDD.

[0021] Fig. Figure 2 is a block diagram, which shows an example of the memory module in Fig. 1 illustrated in detail according to exemplary embodiments.

[0022] In Fig. 2. PMIC 190 does not illustrate the usefulness of the declaration.

[0023] Referring to Fig. 2 The memory module 100 comprises the control device 110, which is arranged (or attached) in a printed circuit board (or a module board or module plate) 101, a plurality of semiconductor memory devices 201a~201e, 202a~202e, 203a~203e and 204a~204e, a plurality of data buffers 141~145 and 151~155, module resistor units 160 and 170 and the SPD chip 180.

[0024] Here, the printed circuit board 101, which is a printed circuit board, can extend in a second direction D2 perpendicular to a first direction D1 between an edge section 103 and a second edge section 105 of the first direction D1. The control device 110 can be arranged at the center of the printed circuit board 101. The plurality of semiconductor memory devices 201a~201e, 202a~202e, 203a~203e and 204a~204e can be arranged in plurality of rows between the control device 110 and the first edge section 103 and between the control device 110 and the second edge section 105. In this case, the semiconductor memory devices 201a~201e and 202a~202e can be arranged along plurality of rows between the control device 110 and the first edge section 103.The semiconductor storage devices 203a~203e and 204a~204e can be arranged along a plurality of rows between the control device 110 and the second edge section 105.

[0025] A section of the semiconductor memory devices 201a~201e and 202a~202e can be an error correction code (ECC) memory device. The ECC memory device can perform an ECC encoding operation to generate parity bits over data to be written to the memory cells, and an ECC decoding operation to correct any errors that occur in the data being read from the memory cells.

[0026] Each of the plurality of semiconductor memory devices 201a~201e, 202a~202e, 203a~203e and 204a~204e can be coupled to correspond to one of the data buffers 141~145 and 151~155 via a data transmission line for receiving / transmitting the data signal DQ of the data strobe signal DQS.

[0027] The control device 110 can provide a command / address signal for the semiconductor storage devices 201a~201e via a command / address transmission line 161 and can provide a command / address signal for the semiconductor storage devices 202a~202e via a command / address transmission line 163. Additionally, the control device 110 can provide a command / address signal for the semiconductor storage devices 203a~203e via a command / address transmission line 171 and can provide a command / address signal for the semiconductor storage devices 204a~204e via a command / address transmission line 173.

[0028] The command / address transmission lines 161 and 163 can be jointly connected to the module resistor unit 160, which is arranged to be adjacent to the first boundary section 103, and the command / address transmission lines 171 and 173 can be jointly connected to the module resistor unit 170, which is arranged to be adjacent to the second boundary section 105. Each of the module resistor units 160 and 170 can have a termination resistor Rtt / 2 connected to a termination voltage Vtt. In this case, an arrangement of the module resistor units 160 and 170 can reduce the number of module resistor units, thereby reducing the area occupied by termination resistors.

[0029] Additionally, each of the majority of semiconductor memory devices 201a~200e, 202a~202e, 203a~203e and 204a~204e can be a DDR5 SDRAM. The SPD chip 180 is arranged to be adjacent to the control device 110.

[0030] Fig. Figure 3 illustrates a connection relationship between the memory controller and the semiconductor storage devices in the memory system of the Fig. 1.

[0031] Referring to Fig. 3. The memory module 100 may comprise at least one first rank of the semiconductor memory device MDRKO and one second rank of the semiconductor memory device MDRK1. Some sections of the semiconductor memory devices 201a~201e, 202a~202e, 203a~203e, and 204a~204e may correspond to the at least one first rank of the semiconductor memory device MDRKO, and another section of the semiconductor memory devices 201a~201e, 202a~202e, 203a~203e, and 204a~204e may correspond to the at least one second rank of the semiconductor memory device MDRK1. The at least one first rank of the semiconductor memory device MDRKO may comprise a receive interface circuit 400a, and the at least one second rank of the semiconductor memory device MDRK1 may comprise a receive interface circuit 400b.

[0032] The memory controller 25 can transmit a training command TR_CMD to the semiconductor memory devices MDRKO and MDRK1 via a first transmission line TL1 and can transmit a training structure TP to the semiconductor memory devices MDRKO and MDRK1 via a second transmission line TL2. The receiver interface circuits 400a and 400b in the semiconductor memory devices MDRKO and MDRK1 simultaneously perform a training (operation) using the training structure TP in response to the training command TR_CMD and can transmit training information signals TIS1 and TIS2, i.e., results of the training, to the memory controller 25.

[0033] The memory controller 25 can have a training information storage table 27 and can store the training information signals TIS1 and TIS2 for each of the semiconductor memory devices MDRKO and MDRK1 in the training information storage table 27.

[0034] In an exemplary embodiment, the memory controller 25 can periodically transmit the training instruction TR_CMD to the semiconductor memory devices MDRKO and MDRK1, or can transmit the training instruction TR_CMD to the semiconductor memory devices MDRKO and MDRK1 in response to a training request from at least one of the semiconductor memory devices MDRKO and MDRK1.

[0035] Fig. 4 is a block diagram which shows one of the semiconductor devices in Fig. 2 illustrated according to exemplary embodiments.

[0036] Referring to Fig. 4 The semiconductor storage device 201a can include a control logic circuit 210, an address register 220, a bank control logic 230, a row address multiplexer 240, a column address latch 250, a row decoder 260, a column decoder 270, a memory cell array 300, a read amplifier unit 285, an input / output (I / O) gating circuit 290, a data input / output (I / O) buffer 295, a refresh counter, an error correction code (ECC) machine 390, a receive interface circuit 400a and a transmit interface circuit 395.

[0037] The memory cell arrangement 300 can have a first to eighth bank arrangement 310~380. The row decoder 260 can have a first to eighth bank row decoder 260a~260h, each coupled to the first to eighth bank arrangement 310~380; the column decoder 270 can have a first to eighth bank column decoder 270a~270h, each coupled to the first to eighth bank arrangement 310~380; and the read amplifier unit 285 can have a first to eighth bank read amplifier 285a~285h, each coupled to the first to eighth bank arrangement 310~380. The first to eighth bank arrangement 310~380, the first to eighth bank row decoder 260a~260h, the first to eighth bank column decoder 270a~270h and the first to eighth bank read amplifier 285a~285h can form the first to eighth bank.Each of the first to eighth bank arrangements 310~380 can have a plurality of word lines WL, a plurality of bit lines BL and a plurality of memory cells MC, which are formed at interfaces of the word lines WL and the bit lines BL.

[0038] Although the semiconductor storage device 201a in Fig. As illustrated in Figure 4 showing eight banks, the semiconductor storage device 201a can have any number of banks.

[0039] Address register 220 can receive an address ADDR, which includes a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR, from the control device 110. Address register 220 can allocate the received bank address BANK_ADDR to the bank control logic 230, the received row address ROW_ADDR to the row address multiplexer 240, and the received column address COL_ADDR to the column address latch 250.

[0040] The bank control logic 230 can generate bank control signals in response to the bank address BANK_ADDR. One of the first to eighth bank row decoders 260a~260h, corresponding to the bank address BANK_ADDR, can be activated in response to the bank control signals, and one of the first to eighth bank column decoders 270a~270h, corresponding to the bank address BANK_ADDR, can be activated in response to the bank control signals.

[0041] The line address multiplexer 240 can receive the line address ROW_ADDR from address register 220 and can receive a refresh line address REF_ADDR from refresh counter 245. The line address multiplexer 240 can selectively output the line address ROW_ADDR or refresh the refresh line address REF_ADDR as a line address RA. The line address RA, which is output by the line address multiplexer 240, can be applied to the first to eighth bank line decoders 260a~260h.

[0042] The activated one of the first to eighth bank line decoders 260a~260h can decode the line address RA, which is output by the line address multiplexer 240, and can activate a word line corresponding to the line address RA. For example, the activated bank line decoder can generate a word line driver voltage based on the power supply voltage VDD and can apply the word line driver voltage to the word line corresponding to the line address RA.

[0043] The column address latch 250 can receive the column address COL_ADDR from the address register 220 and can temporarily store the received column address COL_ADDR. In some embodiments, in a burst mode, the column address latch 250 can generate column addresses that increment the received column address COL_ADDR. The column address latch 250 can apply the temporarily stored or generated column address to the first through eighth bank column decoders 270a–270h.

[0044] The activated one of the first to eighth bank column decoders 270a~270h can decode the column address COL_ADDR, which is output by the column address latch 250, and can control the I / O gating circuit 290 to output data corresponding to the column address COL_ADDR.

[0045] The I / O gating circuit 290 can include a circuit for controlling input / output data. The I / O gating circuit 290 can also include read data latches for storing data output from the first to eighth bank arrangement 310-380, and write drivers for writing data to the first to eighth bank arrangement 310-380.

[0046] Data to be read from a bank arrangement of the first to eighth bank arrangements 310-380 can be sampled by a read amplifier coupled to the bank arrangement from which the data is to be read and can be stored in the read data latches. The data stored in the read data latches can be made available to the memory controller 25 via the data I / O buffer 295 and the transfer interface circuit 395 after the ECC machine 390 performs ECC decoding on the data. Data to be written to a bank arrangement of the first to eighth bank arrangements 310-380 can be made available to the data I / O buffer 295 by the memory controller 25. The ECC machine 390 performs ECC encoding on the data intended for the data I / O buffer 295, and the ECC machine 390 provides the encoded data for the I / O gating circuit 290.

[0047] The receiver interface circuit 400 can perform a training operation in training mode to determine desired (or alternatively optimal) equalization coefficients based on a training structure PT from the memory controller 25 and can transmit a flag signal FG, which is associated with the training, to the memory controller 25 directly or via the transmission interface circuit 395.

[0048] The control logic circuit 210 can control operations of the semiconductor storage device 201a. For example, the control logic circuit 210 can generate control signals for the semiconductor storage device 201a to perform a write or read operation. The control logic circuit 210 can include an instruction decoder 211, which decodes a CMD instruction received by the memory controller 25 via the control device 110 and a mode register 212, which sets an operating mode of the semiconductor storage device 201a.

[0049] For example, the command decoder 211 can generate the control signals corresponding to the CMD command by decoding a write enable signal, a row address strobe signal, a column address strobe signal, a chip select signal, etc. The control logic circuit 210 can generate a mode signal MS, which indicates training mode and normal mode, and can provide the mode signal MS for the receive interface circuit 400a and the transmit interface circuit 395.

[0050] The receiving interface circuit 400 can, in response to the mode signal MS, determine the desired (or alternatively the optimal) equalization coefficients of an equalizer or equalizer based on the training structure TP in the training mode, can receive the data DQ based on the desired (or alternatively the optimal) equalization coefficients and can provide the data DQ for the data I / O buffer 295 in the normal mode.

[0051] Fig. Figure 5 illustrates an example of the first bank arrangement in the semiconductor storage device of the Fig. 4.

[0052] Referring to Fig. In the first bank arrangement 310, a plurality of word lines WL1~WL2m (m is a natural number greater than two), a plurality of bit lines BL1~BL2n (n is a natural number greater than two), and a plurality of memory cells MCs are arranged near interfaces between the word lines WL1~WL2m and the bit lines BL1~BL2n. In one embodiment, each of the plurality of memory cells MCs can have a dynamic random-access memory (DRAM) cell structure. The plurality of word lines WL1~WL2m, to which the plurality of memory cells MCs are connected, can be defined as rows of the first bank arrangement 310, and the plurality of bit lines BL1~BL2n, to which the plurality of memory cells MCs are connected, can be defined as columns of the first bank arrangement 310.

[0053] Fig. Figure 6 illustrates an example of a connection between the memory controller and a semiconductor storage device in the memory system of the Fig. 1 according to exemplary embodiments.

[0054] Referring to Fig. 6. A storage system can include the storage controller 25 and the semiconductor storage device 201a.

[0055] The memory controller 25 and the semiconductor memory device 201a can be connected to each other by a transmission line TL2. Even if a pair of contact points PDH2 and PDS2, the transmission line TL, which connects the contact points PDH2 and PDS2, and a pair of contact points PDH3 and PDS3 in Fig. As illustrated in Figure 6 for the purpose of illustration, each of the memory controller 25 and the semiconductor storage device 201a can have a plurality of input / output contact points and a plurality of transmission lines connecting the input / output contact points.

[0056] The memory controller 25 can include an internal circuit 26 and a transfer driver 28. The transfer driver 28 in the memory controller 25 can output the training structure TP to the contact point PDH2 based on a stored training structure STP from the internal circuit 26.

[0057] The semiconductor storage device 201a can include an internal circuit 205, the receive interface circuit 400a, and a signal combiner 207. The internal circuit 205 can correspond to components which are found in the semiconductor storage device 201a of the Fig. 4 are included, with the exception of the receive interface circuit 400a and the transmit interface circuit 395.

[0058] The receive interface circuit 400a can include an equalizer 410, a demultiplexer 405, and a self-training circuit 430. The self-training circuit 430 can include a margin checker 460, an adaptation machine 480, a register 490, and a multiplexer MUX.

[0059] In training mode, the equalizer 410 can equalize the training structure TP based on the control equalization coefficient CEC to output an equalizer output structure ETP. In response to the mode signal, the demultiplexer 405 can provide the equalizer output structure ETP for the margin checker 460 in training mode and can provide the equalizer output structure ETP for the internal circuit 205 in normal mode.

[0060] The self-training circuit 430 can perform a training (operation) to search for the desired (or alternatively the optimal) equalization coefficients of the equalizer 410 in response to the equalizer output structure ETP and can transmit a training information signal TIS, which has the desired (or alternatively optimal) equalization coefficients OEC, to the memory controller 25.

[0061] The margin checker 460 can compare the equalizer output structure ETP with a reference structure to output an error count value ECV, which indicates a difference between the equalizer output structure ETP and the reference structure. The adaptation engine 480 can adaptively adjust search equalization coefficients SEC to find the desired (or alternatively optimal) equalization coefficients OEC based on the error count value ECV and can configure the equalizer 410 with the search equalization coefficients SEC as the control equalization coefficients CEC.

[0062] When the training is complete, the adaptation machine 480 can provide the signal combiner 207 with a flag signal FG, which includes a pass / fail bit and a memory identifier bit. The pass / fail bit can indicate whether the training was successful or not, and the memory identifier bit can identify the semiconductor memory device 210a.

[0063] Register 490 can store the search equalization coefficients SEC as the desired (or alternatively, the optimal) equalization coefficients OEC when the difference between the equalizer output structure ETP and the reference structure becomes a desired (or alternatively, a minimum) value. It can provide the memory controller 25 with the desired (or alternatively, the optimal) equalization coefficients as a section of the training information signal TIS in training mode, and it can provide the equalizer 410 with the desired (or alternatively, the optimal) equalization coefficients OEC as the control equalization coefficients CEC in normal mode. Register 49 can provide the desired (or alternatively, optimal) equalization coefficients OEC for the signal combiner 207 in response to a control signal RCTL from the adaptation machine 480.

[0064] The signal combiner 207 can receive the flag signal FG and the desired (or alternatively optimal) equalization coefficients OEC, can combine the flag signal FG and the desired (or alternatively optimal) equalization coefficients OEC into the training information signal TIS, and can transmit the training information signal TIS to the internal circuit 26 of the memory controller 25 via the contact points BDS3 and BDH3.

[0065] Although not illustrated, the memory controller can be used in 25 Fig. 6. The receiver interface circuit comprises a receiver interface circuit, such as the receiver interface circuit 400a. The receiver interface circuit can receive a training structure from the semiconductor memory device 201a, perform training to search for desired (or alternatively, optimal) equalization coefficients of an equalizer in the receiver interface circuit, and store the searched desired (or alternatively, optimal) equalization coefficients in a register in the memory controller 25 in training mode. The receiver interface circuit can receive a data signal DQ from the semiconductor memory device 201a based on the desired (or alternatively, optimal) equalization coefficients and can provide the data signal DS for the internal circuit 26 in normal mode.

[0066] Fig. Figure 7 is a circuit diagram showing an example of the equalizer in the receiver interface circuit in Fig. 6 illustrated according to exemplary embodiments.

[0067] Referring to Fig. 7 an equalizer 410a with a continuous time-linear equalizer (CTLE) can be implemented and the equalizer 410a can have resistors RD1 and RD2 which are connected to a power supply voltage VDD, an input unit 411, a filter 414 and bias transistors 415 and 416.

[0068] The input unit 411 can include n-channel metal-oxide-semiconductor (NMOS) transistors 412 and 413. NMOS transistor 412 is coupled to resistor RD1 at node N11, and NMOS transistor 413 is coupled to resistor RD2 at node N12. The filter 414 can include resistor RS and capacitor CS, which are coupled in parallel between the sources of NMOS transistors 412 and 413.

[0069] The bias transistor 415 has a drain coupled to capacitor CS at node N13, a gate that receives a reference bit REFk, and a source coupled to a ground voltage VSS. The bias transistor 416 has a drain coupled to capacitor CS at node N14, a gate that receives the reference bit REFk, and a source coupled to the ground voltage VSS. The reference bit REFk can correspond to the control equalization coefficient CEC.

[0070] An input bit Xk is applied to the gates of NMOS transistors 412 and 413 in input unit 411, and an output bit Yk is provided at nodes N11 and N12. The input bit Xk can be one of a successive sequence of the training structure TP.

[0071] Fig. Figure 8 is a circuit diagram showing another example of the equalizer in the receiver interface circuit in Fig. 6 illustrated according to exemplary embodiments.

[0072] Referring to Fig. In 18, an equalizer 410 can be implemented with a feedforward equalizer (FFE), and the equalizer 410 can have delay elements 421-42s, multipliers 431-43s, an adder 417, and a subtractor 418. Here, s is an integer greater than one.

[0073] The delay elements 421-42s can successively delay the input bit Xk, the multipliers 431-43s multiply the outputs of the delay elements 421-42s by control equalization coefficients CW1-CWs, the adder 417 adds the outputs of the multipliers 431-43s, and the subtractor 418 subtracts an output of the adder 417 from the input bit Xk to provide the output bit Yk. The output bit Yk can be one of a successive sequence of the equalizer output structure ETP.

[0074] Fig. Figure 9 is a circuit diagram showing another example of the equalizer in the receiver interface circuit of the Fig. 6 illustrated according to exemplary embodiments.

[0075] Referring to Fig. Equalizer 400c can be implemented with a decision-feedback equalizer (DEF), and equalizer 410c can include delay elements 441-44s, multipliers 451-45s, an adder SUM, a subtractor 419, and decision logic. The delay elements 441-44s, the multipliers 451-45s, and the adder SUM can form a feedback filter FF.

[0076] The delay elements 441-44s can successively delay a decision bit Dk. The multipliers 451-45s multiply the outputs of the delay elements 431-43s by the control equalizer coefficients CW1-CWs. The adder SUM adds the outputs of the multipliers 41-45s, and the subtractor 419 subtracts an output of the adder SUM from the input bit Xk to provide the output bit Yk. The decision logic 440 can determine a logic level of the output bit Yk based on the clock signal CLK to provide the decision bit Dk. The decision bit Dk can be one of a successive sequence of the equalizer output structure ETP.

[0077] The DEF410 can compensate for errors between symbols caused by signal distortion by using feedback-weighted values ​​through the control equalization coefficients CW1~CWs for the decision bit DK via the feedback filter FF.

[0078] The equalizer 410 in the receiver interface circuit 400a in Fig. 6 can be done by the FFE 410b of the Fig. 8 and the DEF 410c of the Fig. 9 be implemented. In this case, the FFE 410b receives the input bit Xk to provide the output bit Yk, and the DEF 410c receives the output bit Yk of the FFE 410 as an input bit to output the decision bit Dk.

[0079] Fig. Figure 10 is a block diagram showing an example of the margin checker in the self-training circuit in Fig. 6 illustrated according to exemplary embodiments.

[0080] Referring to Fig. 10. A margin checker 460a can have a register 462, a bit comparator 461 and an error counter 463.

[0081] Register 462 stores expected values ​​of the training structure TP as a reference structure PDP. Bit comparator 461 compares bits of the equalizer output structure ETP and the reference structure PDP to output a comparison signal CS. Bit comparator 461 can have multiple exclusive OR gates. Error counter 463 can output the error count ECV based on the comparison signal CS. Therefore, the error count ECV can represent a number of different bits between the training structure TP and the reference structure PDP.

[0082] Fig. Figure 11 is a block diagram, which shows another example of the margin checker in the self-training circuit of the Fig. 6 illustrated according to exemplary embodiments.

[0083] Referring to Fig. 11. A margin checker 460b can have a replica path 464, a bit comparator 465 and an error counter 467.

[0084] The replica path 464 is formed by replicating a path that specifies the equalizer output structure ETP in response to the training structure TP and is independent of any external influence. The replica path 464 outputs a reference structure ETP' in response to the training structure TP. The reference structure ETP' can correspond to an expected structure, ensuring that the equalizer output structure ETP experiences no noise or interference. The bit comparator 465 compares corresponding bits of the equalizer output structure ETP and the reference structure ETP' to output a comparison signal CS. The bit comparator 465 can have multiple exclusive OR gates. The error counter 467 can output the error count ECV based on the comparison signal CS. Thus, the error count ECV can indicate a number of different bits between the training structure TP and the reference structure ETP'.

[0085] Fig. Figure 12 is a block diagram which shows an example of the adaptation machine in the self-training circuit in Fig. 6 illustrated according to exemplary embodiments.

[0086] Referring to Fig. 12 The adaptation machine 480 can include an adaptive algorithm implementation machine 481, a controller 483 and a register 485.

[0087] Register 485 stores a reference value RV. The adaptive algorithm implementation machine 481 receives the error count value ECV and the reference value RV and outputs an adaptive coefficient control signal ADCS to reduce (or alternatively minimize) any difference between the error count value ECV and the reference value RV based on the error count value ECV and the reference value RV.

[0088] The controller 483 provides the equalizer 410 with the search equalization coefficient SEC as the control equalization coefficient CEC in response to the adaptive coefficient control signal ACCS. The controller 483 outputs the search equalization coefficient SEC as the desired (or alternatively, the optimal) equalization coefficient OEC when the difference between the error count ECV and the reference RV becomes the desired (or alternatively, the minimum) value. Additionally, when the adaptive coefficient control signal ACCS indicates that the difference between the error count ECV and the reference RV becomes the desired (or alternatively, the minimum) value, the controller 783 outputs the flag signal FG, which contains the pass / fail bit indicating successful training, and the memory identifier bit MID, which identifies a corresponding semiconductor memory device, namely the semiconductor memory device 201a.

[0089] The Adaptive Algorithm Implementation Machine 481 can output the Adaptive Coefficient Control Signal ACCS to make the difference between the error count value ECV and the reference value RV to the desired (or alternatively the minimum) value by using, for example, a zero-enforcement (ZF) algorithm, a least mean squares (LMS) algorithm, and a recursive least squares (RLS) algorithm.

[0090] The ZF algorithm converges the error count ECV to zero, the LMS algorithm generates the least mean square error of the difference between the error count ECV and the reference value RV, and the RLS algorithm generates at least the least square mean of the difference between the error count ECV and the reference value RV using feedback.

[0091] Fig. Figure 13 is a block diagram illustrating a semiconductor storage device according to exemplary embodiments.

[0092] Each of the semiconductor memory devices 201a~201e, 202a~202e, 203a~203e and 204a~204e in the memory module 100 in Fig. 2. A semiconductor storage device can be 500 of the Fig. Insert 13.

[0093] Referring to Fig. 13 The semiconductor storage device 500 can include an internal circuit 510, a receiving interface circuit 520, a temperature sensor 560 and a signal combiner 570.

[0094] The receive interface circuit 520 can include a (receive) buffer 521, an equalizer 522, a demultiplexer 523, and a self-training circuit 530. The self-training circuit 530 can include a margin checker 531, an adaptation machine 533, a register 535, a multiplexer MUX, a code search circuit 540, and a reference voltage generator 550.

[0095] Since the configuration and operation of each of the equalizer 522 and the demultiplexer 523 are substantially similar to the configuration and operation of each of the equalizer 410 and the demultiplexer 405, and the configuration and operation of each of the margin checker 531, the adaptation machine 533 and the register 535 are substantially similar to the configuration and operation of each of the margin checker 460, the adaptation machine 480 and the register 490 in Fig. Since there are 6, a detailed description of the equalizer 522, the demultiplexer 523, the margin checker 531, the adaptation machine 533 and the register 535 will be omitted.

[0096] In training mode, the buffer 521 compares the training structure TP with a reference voltage VREF to generate a buffer signal SB. The equalizer 522 equalizes the buffer signal SB based on the control equalization coefficient CEC to provide the equalizer output structure ETP.

[0097] The reference voltage generator 550 can generate the reference voltage VREF in response to a control code CCD. In training mode, the code search circuit 540 can output a scan code, which changes sequentially, as the control code for searching for a desired (or alternatively optimal) code corresponding to a desired (or alternatively optimal) voltage level of the reference voltage VREF, and can store the searched code CCD in register 535.

[0098] When the code search circuit 540 searches for the desired (or alternatively optimal) control code which corresponds to the desired (or alternatively optimal) voltage level of the reference voltage VREF, the training to search for desired (or alternatively optimal) values ​​of the control equalization coefficients CEC is as described above.

[0099] Register 535 can store the control code CCD, corresponding to the desired (or alternatively optimal) voltage level, as the desired (or alternatively optimal) control code OCD, and can store the search equalization coefficients SEC as the desired (or alternatively optimal) equalization coefficients OEC when the difference between the equalizer output structure ETP and the reference structure becomes a desired (or alternatively a minimum) value. Register 535 can provide the signal combiner 570 with the desired (or alternatively optimal) control code OCD and the desired (or alternatively optimal) equalization coefficients OEC, and the signal combiner 570 can combine the desired (or alternatively optimal) control code OCD, the desired (or alternatively optimal) equalization coefficients OEC, and the flag signal FG to generate the training information signal TIS.The signal combiner 570 can transmit the training information signal TIS to the memory controller 25 via the path PDS3.

[0100] The temperature sensor 560 can sample the operating temperature of the semiconductor memory device 500, compare the operating temperature with at least one reference temperature, and transmit a training request signal TRRQ to the memory controller 25 via a contact point PDS4 if the operating temperature is higher than the reference temperature. The training request signal TRRQ can be a signal that requests training of the semiconductor memory device 500.

[0101] The memory controller 25 can apply a training command TR_CMD to the semiconductor memory device 500 in response to the training request signal TRRQ, after the semiconductor memory device 500 has completed a current memory operation. The semiconductor memory device 500 can then set the desired (or alternatively optimal) control code OCD and the desired (or alternatively optimal) equalization coefficients OEC at an elevated temperature in response to the training command TR_CMD.

[0102] Fig. Figure 14 is a circuit diagram showing the reference voltage generator in the self-training circuit in Fig. 13 illustrated according to exemplary embodiments.

[0103] Fig. Figure 14 illustrates the reference voltage generator 550 of a resistor division scheme.

[0104] Referring to Fig. 14. The reference voltage generator 550 can have a plurality of division resistors R and a plurality of switches SW1~SWp. The division resistors R can be connected in series between a first division node N1 and a p-th division node Np. A first voltage VR1 can be applied to the first division node N1, and a second voltage VR2 lower than the first voltage VR1 can be applied to the p-th node Np. For example, the first voltage VR1 can be a power supply voltage, and the second voltage VR2 can be a ground voltage. The switches SW1~SWp can be connected in parallel between the division nodes N1~Np and an output node NO. The switches SW1~SWp can control electrical connections between the division nodes N1~Np and the output node NO in response to code bits C[1]~C[p] of the control code CCD.

[0105] For example, only one of the code bits C[1]~C[p] can be activated as a thermometer code at a time, and the switch corresponding to the activated code bit can be turned on to provide the voltage of the corresponding division node for the output node NO as the reference voltage VREF. For example, the aforementioned sequential change of the scan code can be performed by selectively activating the code bits C[1]~C[p].

[0106] The code bits C[1]~C[p] can be activated sequentially, one by one, in the direction from the p-th code bit C[1]~C[p] to the first code bit C[1], thus providing the reference voltage VREF, which increases stepwise. Conversely, the code bits C[1]~C[p] can be activated sequentially, one by one, in the direction from the first code bit C[1] to the p-th code bit C[p], thus providing the reference voltage VREF, which decreases stepwise.

[0107] Fig. 15 is a block diagram, which shows another example of the memory module in Fig. 1 illustrated in detail according to exemplary embodiments.

[0108] A 100a memory module of the Fig. 15 differs from the memory module 100 of the Fig. 2 in that the memory module 100a has no data buffers which receive / transmit the data signal DQ and the data strobe signal DQS to / from the plurality of semiconductor memory devices 201a~201e, 202a~202e, 203a~203e and 204a~204e. The memory module 100a can receive / transmit the data signal DQ and the data strobe signal DQS to / from the memory controller 25 via a control device 110a. Additionally, the control device 110a can transmit the training structure TP to the semiconductor memory devices 201a~201e, 202a~202e, 203a~203e and 204a~204e, can receive the training information signal TIS from each of the semiconductor memory devices 201a~201e, 202a~202e, 203a~203e and 204a~204e and transmit the training information signal TIS to the memory controller 25 in the training mode.

[0109] In an exemplary embodiment, each of the semiconductor memory devices 201a~201e, 202a~202e, 203a~203e, and 204a~204e can receive the training structure TP from the memory controller 25 via the control device 110a in training mode and can receive / transmit the data signal DQ and the data strobe signal DQS to the memory controller 25 via the control device 110a. In this case, the control device 110a can receive the training information signal TIS from each of the semiconductor memory devices 201a~201e, 202a~202e, 203a~203e, and 204a~204e and can transmit the training information signal TIS to the memory controller 25.

[0110] Fig. 16 is a block diagram which shows an example of the control device in the storage module of the Fig. 15 illustrated according to exemplary embodiments.

[0111] Referring to Fig. 16 The control device 110a can include a memory management unit 111 and a training management unit 113.

[0112] The memory management unit 111 can receive the clock signal CLK, the command CMD, the address ADDR, and the data signal DQ, and can repeat the clock signal CLK, the command CMD, the address ADDR, and the data signal DQ for the semiconductor memory devices 200. Additionally, the memory management unit 111 can receive the training structure TP and can repeat the training structure TP for the semiconductor memory devices 200 in training mode.

[0113] The training management unit 113 can receive the training information signal TIS from each of the semiconductor memory devices 200 and can transmit the training information signal TIS to the memory controller 25. The training management unit 113 can have a training information storage table 115.

[0114] Fig. Figure 17 illustrates an example of the training information storage table in Fig. 16 according to exemplary embodiments.

[0115] Referring to Fig. 17. The training information storage table 115 can store the memory identifier bit MID, which identifies each of the semiconductor memory devices 200, the optical control code OCD of each of the semiconductor memory devices 200, and the desired (or alternatively optimal) equalization coefficients OEC of each of the semiconductor memory devices 200. The memory identifier bit MID can have identifiers ID1~IDt of the semiconductor memory devices 200, the desired (or alternatively optimal) equalization coefficients OEC can have desired (or alternatively optimal) equalization coefficients OEC1~OECt of the semiconductor memory devices 200, and the optical control code OCD can have optical control codes OCD1~OCDt of the semiconductor memory devices 200.

[0116] Fig. 18 is a diagram to describe a termination with a centralized time tap (CTT).

[0117] Referring to Fig. 18. A transmission driver 70 in the memory controller can operate a contact point PDH2 based on the training structure TP from an internal circuit. The contact point PDH2 in the memory controller can be connected to a contact point PDS2 of a semiconductor memory device via a transmission line TL2. A termination circuit 80 of the CTT scheme can be connected to the PDS2 of the semiconductor memory device for impedance matching. The receive buffer BF in the semiconductor memory device can compare the training structure TP via the contact point PDS2 with the reference voltage VREF to provide the buffer signal SB for an internal circuit of the semiconductor memory device.

[0118] The transfer driver 70 can include a pull-up unit connected between a first power supply voltage VDDQ and the junction PDH2, and a pull-down unit connected between the junction PDH2 and a second power supply voltage VSSQ lower than the first power supply voltage VDDQ. The pull-up unit can include a turn-on resistor RON and a PMOS transistor MP1, which is switched on in response to the training structure TP. The pull-down unit can include a turn-on resistor RON and an NMOS transistor MN1, which is switched on in response to the training structure TP. The turn-on resistors RON can be omitted, and each turn-on resistor RON can represent a resistance between the voltage node and the junction PDH2 when both transistors MP1 and MN1 are switched on.

[0119] Termination circuit 80 of the CTT scheme can include a first termination circuit connected between the first power supply voltage VDDQ and junction PDS2, and a second termination circuit connected between junction PDS2 and the second power supply voltage VSSQ. The first termination circuit can include a termination resistor RTT around a PMOS transistor MP2, which is turned on in response to a low voltage. The second termination circuit can include a termination resistor RTT and an NMOS transistor MN2, which is turned on in response to a high voltage. The termination resistors RTT can be omitted, and each termination resistor RTT can represent a resistance between the voltage node and junctions PDSs when both transistors MP2 and MN2 are turned on.

[0120] Fig. Figure 19 is a diagram to describe a pseudo-open drain (POD = pseudo-open drain) termination.

[0121] Referring to Fig. 19 The description of the transfer driver 70 is the same as in Fig. 18.

[0122] Termination circuit 81 of the POD termination scheme can include a termination resistor RTT and an NMOS transistor MN2, which is switched on in response to a high voltage. The termination resistor RTT can be omitted, and the termination resistor RTT can represent a resistance between the voltage node and the junction PDS2 when the NMOS transistor MN2 is switched on.

[0123] An on-die termination resistor of each of the semiconductor memory devices 201a~201e, 202a~202e, 203a~203e and 204a~204e in the memory module 100 of the Fig. 1 or in the memory module 100a of the Fig. 15 can be set to be equal to each other in the training mode.

[0124] Fig. 20 is a time diagram which is an example of a training operation of the memory module of the Fig. 2 or memory module of the Fig. 15 illustrated.

[0125] In Fig. 20, it is assumed that a rank in the memory module 100 of the Fig. 2 or in the memory module 100 of the Fig. 15 r semiconductor memory devices can have. Here, r is an integer greater than one.

[0126] Referring to Fig. At a time selection point T1, the memory controller 25 activates chip selection signals CS1~CSr with a logically low level, which are each applied to semiconductor memory devices 200. When the chip selection signals CS1~CSr are activated, the semiconductor memory devices 200 are selected and activated simultaneously.

[0127] At a time selection point T2, the memory controller 25 can simultaneously send the training command TR_CMD to the semiconductor memory devices 200 to initiate training of the control equalization coefficients CEC of the equalizer 410 and the training structure TP. Between time selection points T2 and T3, the receiver interface circuit 400a simultaneously performs training TROP1~TROPr in each of the semiconductor memory devices 200 to find the desired (or alternatively optimal) equalization coefficients OEC by equalizing the training structure TP based on the control equalization coefficients CEC. The semiconductor memory device 200 terminates the TROP1~TROPr training individually around time selection point T3. The time selection point at which the training is terminated can differ among the semiconductor memory devices 200.The semiconductor storage device 200 can transmit the training information signal TIS to the storage controller 25 each time before the training is completed.

[0128] At time selection point T3, training is terminated and memory controller 25 disables the chip selection signals CS1~CSr with a logic high level. At time selection point T4, memory controller 25 enables the chip selection signals CS1~CSr with a logic low level and the semiconductor memory devices 200 are activated. At time selection point T5, memory controller 25 applies an equalization coefficient setting command ECST, which indicates the end of training mode, to the semiconductor memory devices 200. In response to the equalization coefficient setting command ECST, the semiconductor memory devices 200 disable the mode signal MS to indicate normal mode.

[0129] Fig. Figure 21 is a block diagram illustrating a storage system according to exemplary embodiments.

[0130] Referring to Fig. 21. A memory system 600 can comprise a semiconductor memory device 601, a system-on-a-chip (SoC) 630, an interposer 640, and a package substrate 650. The SoC 630 can comprise a memory controller 631.

[0131] The semiconductor memory device 610 can be a high-bandwidth memory (HBM) device and can include a buffer die 620 and a first to eighth core die 611 to 618. The buffer die 620 and the first to eighth core die 611 to 618 can be interconnected via silicon through-holes.

[0132] The buffer die 620 can include a receiver interface circuit 621, perform training to find the desired (or alternatively optimal) equalization coefficients in training mode, and transmit the training information signal, which contains the desired (or alternatively optimal) equalization coefficients, to the memory controller 631. The receiver interface circuit 621 can connect to the receiver interface circuit 600a. Fig. 6 or the 520 receiving interface circuit in Fig. Insert 13.

[0133] The interposer 640 connects the SoC 630 and the buffer die 620 using a wire. The package substrate 650 supports the SoC 630 and the semiconductor memory device 610 and connects the SoC 630 and the semiconductor memory device 610 to a motherboard.

[0134] The semiconductor memory device 610 can replace any of the semiconductor memory devices 201a~201e, 202a~202e, 203a~203e, and 204a~204e. In a memory module incorporating the semiconductor memory devices 610, the semiconductor memory devices 610 perform training simultaneously and transfer the training results to the memory controller in training mode. Therefore, the memory module incorporating the semiconductor memory devices 610 can significantly reduce training time.

[0135] Fig. Figure 22 is a flowchart illustrating a method for operating a memory module according to exemplary embodiments.

[0136] Referring to the Fig. 1 to 22 a memory module 100 can have a plurality of semiconductor memory devices 200 which are mounted on a module board or a module circuit board 101.

[0137] In operation S610, each of the semiconductor memory devices 200 can search for desired (or alternatively optimal) equalization coefficients OEC of an equalizer 410, which receives a training structure TP in a training mode, in response to a training instruction TR_CMD from a memory controller 25.

[0138] In operation S620, each of the semiconductor memory devices 200 can transfer the desired (or alternatively optimal) equalization coefficients OEC to the memory controller 25.

[0139] In Operation S630, each of the semiconductor memory devices 200 can perform a memory operation based on data received from the memory controller 52 by using the desired (or alternatively optimal) equalization coefficients OEC in a normal mode.

[0140] According to this method for operating the memory module, the semiconductor memory devices can perform training simultaneously and transfer the training results to the memory controller in training mode. Therefore, the training time can be significantly reduced according to this method.

[0141] Fig. Figure 23 is a block diagram illustrating a memory system which has quad-rank memory modules according to exemplary embodiments.

[0142] Referring to Fig. 23. A storage system 700 can comprise a storage controller 710 and at least one or more storage modules 720 and 730. The storage controller 710 can comprise a transfer driver 711 and a receive driver 713.

[0143] The 710 memory controller can control the 720 and 730 memory modules to execute instructions supplied by a processor or host. The 710 memory controller can be implemented within a processor or host, or it can be integrated with an application processor or a system-on-a-chip (SoC). For signal integrity, source termination can be implemented with a resistor RTT on a bus 740 of the 710 memory controller. The resistor RTT is connected to a power supply voltage VDDQ.

[0144] The first memory module 720 and the second memory module 730 can be coupled to the memory controller 710 via bus 740. Each of the first memory module 720 and the second memory module 730 can control the memory module 100. Fig. 2 or the 100a memory module of the Fig. 15. The first memory module 720 can have at least one or more memory ranks RNK1 and RNK2, and the second memory module 730 can have one or more memory ranks RNK3 and RNK4. Each of the first memory module 720 and the second memory module 730 can have the memory module 100 of the Fig. 2 or the 100a memory module of the Fig. 15 and can perform the aforementioned training on the semiconductor memory devices by units of one rank simultaneously.

[0145] Fig. Figure 24 is a block diagram illustrating a mobile system which includes the storage module according to exemplary embodiments.

[0146] Referring to Fig. 24. A mobile system 900 can include an application processor 910, a connectivity module 920, a memory module 950, a non-volatile memory component 940, a user interface 930, and a power supply 970. The application processor 910 can include a memory controller 911.

[0147] The 910 application processor can run applications such as a web browser, a game application, a video player, etc. The 920 connectivity module can establish wired or wireless communication with an external device.

[0148] The memory module 950 can store data processed by the application processor 910 or operate as a working memory. The memory module 950 can include a plurality of semiconductor memory devices 951–95q (q being a natural number greater than three) and a control device 962. Each of the semiconductor memory devices 951–95q can include the receive interface circuit 400a. Fig. 6 or the 520 receiving interface circuit in Fig. 13.

[0149] The non-volatile storage device 940 can store a boot image for booting or starting up the mobile system 900. The user interface 930 can have at least one input device, such as a keyboard, a touchscreen, etc., and at least one output device, such as a speaker, a display, etc. The power supply 970 can supply an operating voltage to the mobile system 900.

[0150] In some embodiments, the Mobile System 900 and / or components of the Mobile System 900 can be housed in various forms.

[0151] Exemplary embodiments can be applied to systems that use memory modules.

[0152] According to one or more exemplary embodiments, the units and / or devices described above as comprising elements of each of the plurality of semiconductor storage devices 200, such as elements of the control logic circuit 210 and the receive interface circuit 400a, comprising the self-training circuit 430 and one or more other components discussed above, may be implemented using hardware, a combination of hardware and software, or a non-perishable storage medium that stores software executable to perform the functions thereof.

[0153] Hardware may be implemented using a processing circuit such as, but not limited to, one or more processors, one or more central processing units (CPUs), one or more controllers, one or more arithmetic logic units (ALUs), one or more digital signal processors (DSPs), one or more microcomputers, one or more field programmable gate arrays (FPGAs), one or more systems-on-a-chip (SoCs), one or more programmable logic units (PLUs), one or more microprocessors, one or more application-specific integrated circuits (ASICs), or any other device or devices capable of responding to and executing instructions in a defined manner.

[0154] Software can consist of a computer program, program code, instructions, or some combination thereof for independently or collectively instructing or configuring a hardware device to operate as desired. The computer program and / or program code can include a program or machine-readable instructions, software components, software modules, data files, data structures, etc., capable of being implemented by one or more hardware devices, such as one or more of the hardware devices mentioned above. Examples of program code include both machine code, which is generated by a compiler, and higher-level program code, which is executed using an interpreter.

[0155] For example, if a hardware device is a computer processing device (such as one or more processors, CPUs, controllers, ALUs, DSPs, microcomputers, microprocessors, etc.), the computer processing device can be configured to execute program code by performing arithmetic, logical, and input / output operations according to the program code. Once the program code is loaded into the computer processing device, the computer processing device can be programmed to execute the program code, thereby transforming the computer processing device into a special-purpose computer processing device. In a more specific example, when the program code is loaded into a processor, the processor is programmed to execute the program code and corresponding operations, thereby transforming the processor into a special-purpose processor.In another example, the hardware device can be an integrated circuit that is custom-made into a special-purpose processing circuit (for example, an ASIC).

[0156] A hardware device, such as a computer processing device, can run an operating system (OS) and one or more software applications that run the OS. In response to the execution of the software, the computer processing device can also access, store, manipulate, process, and generate data. For the sake of simplicity, one or more exemplary embodiments of a computer processing device may be presented; however, a person skilled in the art will recognize that a hardware device can have multiple processing elements and multiple types of processing elements. For example, a hardware device can have multiple processors or a processor and a controller. Additionally, other processing configurations are possible, such as parallel processors.

[0157] Software and / or data may be executed permanently or temporarily on any type of storage medium, including but not limited to any machine, component, physical or virtual equipment, or computer storage medium or device capable of receiving instructions or data to be interpreted by a hardware device. The software may also be distributed across networked computer systems, such that the software is stored and executed in a distributed manner. In particular, for example, software and data may be stored by one or more computer-readable recording media, including physical or non-perishable computer-readable storage media, as discussed herein.

[0158] Storage media may also comprise one or more storage devices, including units and / or devices, according to one or more exemplary embodiments. The one or more storage devices may be physical or non-perishable computer-readable storage media, such as random-access memory (RAM), read-only memory (ROM), a permanent mass storage device (such as a hard disk drive), and / or any other similar data storage mechanism capable of storing and recording data. The one or more storage devices may be configured to store computer programs, program code, instructions, or some combination thereof for one or more operating systems and / or to implement the exemplary embodiments described herein.Computer programs, program code, instructions, or combinations thereof can also be loaded from a separate computer-readable storage medium into one or more storage devices and / or one or more computer processing devices using a drive mechanism. Such separate computer-readable storage media can include a Universal Serial Bus (USB) flash drive, a memory stick, a Blu-ray / DVD / CD-ROM drive, a memory card, and / or similar computer-readable storage media. Alternatively, computer programs, program code, instructions, and combinations thereof can be loaded into one or more storage devices and / or one or more computer processing devices from a remote data storage device via a network interface rather than from a computer-readable storage medium.Additionally, computer programs, program code, instructions, or combinations thereof can be loaded into one or more storage devices and / or one or more processors by a remote computing system or computer system configured to transmit and / or distribute the computer programs, program code, instructions, or combinations thereof over a network. The remote computing system can transmit and / or distribute the computer programs, program code, instructions, or combinations thereof via a wired interface, an air interface, a wireless interface, and / or any other similar medium.

[0159] The one or more hardware devices, storage media, computer programs, program code, instructions, or some combination thereof may be specifically designed and constructed for the purpose of the exemplary embodiments, or they may be known devices which are changed and / or modified for the purposes of exemplary embodiments.

Claims

[1] Memory module (100, 100a, 720, 730, 950) comprising the following: a plurality of semiconductor memory devices (200, 201a~201e, 202a~202e, 203a~203e, 204a~204e, 500) connected to an identical module circuit board (101), each of the plurality of semiconductor memory devices (200, 201a~201e, 202a~202e, 203a~203e, 204a~204e, 500) having a memory cell arrangement (300) comprising a plurality of dynamic memory cells, the plurality of semiconductor memory devices (200, 201a~201e, 202a~202e, 203a~203e, 204a~204e, 500) being configured to perform a training operation simultaneously, the plurality of semiconductor memory devices (200, 201a~201e, 202a~202e, 203a~203e, 204a~204e, 500) has a receiving interface circuit (400, 400a, 400b, 520, 621) which is configured to to perform the training operation to search for selected equalization coefficients of an equalizer (410, 522) based on a training structure from a memory controller (25, 710), and to transmit a training information signal to the memory controller (25, 710) in a training mode in response to a training command from the memory controller (25, 710), wherein the training information signal has the selected equalization coefficients, wherein the receiving interface circuit (400, 400a, 400b, 520, 621) has the following: the equalizer (410, 522), which is configured to generate an equalizer output structure by equalizing the training structure based on control equalization coefficients in the training mode; and a self-training circuit (430, 530) which is configured to provide the control equalization coefficients for the equalizer (410, 522), wherein the self-training circuit (430, 530) is configured to to generate an error count value that indicates a difference between the equalizer output structure and a reference structure, and adaptively adjust search equalization coefficients to provide the control equalization coefficients for the equalizer (410, 522) based on the error count value and a reference value, wherein The equalizer (410, 522) uses the search equalization coefficients to search for the selected equalization coefficients. [2] Memory module (100, 100a, 720, 730, 950) according to claim 1, wherein the plurality of semiconductor memory devices (200, 201a~201e, 202a~202e, 203a~203e, 204a~204e, 500) is configured to perform the training operation simultaneously with a rank unit of the plurality of semiconductor memory devices (200, 201a~201e, 202a~202e, 203a~203e, 204a~204e, 500). [3] Memory module (100, 100a, 720, 730, 950) according to claim 2, wherein the equalizer (410, 522) comprises at least one of a continuous time-linear equalizer, a feedforward equalizer and a decision-feedback equalizer. [4] Memory module (100, 100a, 720, 730, 950) according to claim 2, wherein the self-training circuit (430, 530) is configured to to store the reference structure in a register which is connected to the self-training circuit (430, 530), to generate a comparison signal based on the equalizer output structure and the reference structure, and to output the error count value in response to the comparison signal. [5] Memory module (100, 100a, 720, 730, 950) according to claim 2, wherein the self-training circuit (430, 530) is configured to to output the reference structure via a replica path (464) in response to the training structure, wherein the replica path (464) replicates a path which provides the equalizer output structure while being independent of any external influence, to generate a comparison signal based on the equalizer output structure and the reference structure, and to output the error count value in response to the comparison signal. [6] Memory module (100, 100a, 720, 730, 950) according to claim 2, wherein the self-training circuit (430, 530) is configured to to output an adaptive coefficient control signal based on the error count value and the reference value, to provide the equalizer (410, 522) with the search equalization coefficients as the control equalization coefficients in response to the adaptive coefficient control signal such that the adaptive coefficient control signal instructs a controller connected to the self-training circuit (430, 530) to reduce a difference between the error count value and the reference value, and to output the sought-after equalization coefficients as the selected equalization coefficients in response to the fact that the difference between the error count value and the reference value reaches a lower limit. [7] Memory module (100, 100a, 720, 730, 950) according to claim 6, wherein the controller is configured to output a flag signal comprising a pass / fail bit and a memory identifier bit when the adaptive coefficient control signal indicates that the difference between the error count value and the reference value has reached the lower limit, wherein the pass / fail bit indicates whether the training operation is successful for a corresponding one of the plurality of semiconductor memory devices (200, 201a~201e, 202a~202e, 203a~203e, 204a~204e, 500), and the memory identifier bit identifies the corresponding one of the plurality of semiconductor memory devices (200, 201a~201e, 202a~202e, 203a~203e, 204a~204e, 500). [8] Memory module (100, 100a, 720, 730, 950) according to claim 6, wherein the self-training circuit (430, 530) is configured to reduce the difference between the error count value and the reference value using a zero-forcing algorithm, a least mean squares error algorithm and a recursive least squares algorithm. [9] Memory module (100, 100a, 720, 730, 950) according to claim 2, wherein the receive interface circuit (400, 400a, 400b, 520, 621) further comprises a demultiplexer (405, 523) which is configured to to provide the self-training circuit (430, 530) with the equalizer output structure of the equalizer (410, 522) in the training mode, and to provide an internal circuit (26, 205) with an output of the equalizer (410, 522) in response to data received by the memory controller (25, 710) in a normal mode, wherein the memory module (100, 100a, 720, 730, 950) switches between training mode and normal mode in response to a mode signal. [10] Memory module (100, 100a, 720, 730, 950) according to claim 2, wherein the self-training circuit (430, 530) further comprises a register configured to store the control equalization coefficients, and the self-training circuit (430, 530) is configured to transmit the control equalization coefficients as the selected equalization coefficients to the memory controller (25, 710) in response to a difference between the error count value and the reference value reaching a lower limit. [11] Memory module (100, 100a, 720, 730, 950) according to claim 2, wherein each of the semiconductor memory devices (200, 201a~201e, 202a~202e, 203a~203e, 204a~204e, 500) is configured to: to receive the selected equalization coefficients and a flag signal in response to a difference between the error count value and the reference value reaching a lower limit, wherein the flag signal includes a pass / fail bit and a memory identifier bit, the pass / fail bit indicating a pass or failure of the training operation and the memory identifier bit identifying a corresponding semiconductor memory device (200, 201a~201e, 202a~202e, 203a~203e, 204a~204e, 500); and to transmit to the memory controller (25, 710) the training information signal, which further includes the selected equalization coefficients and the flag signal. [12] Memory module (100, 100a, 720, 730, 950) according to claim 2, wherein each of the semiconductor memory devices (200, 201a~201e, 202a~202e, 203a~203e, 204a~204e, 500) further comprises a signal combiner (207, 570), and wherein the signal combiner (207, 570) is configured to: to receive the control equalization coefficients as the selected equalization coefficients when the difference between the error count value and the reference value becomes a minimum value, to receive a flag signal which has a pass / fail bit and a memory identifier bit, where the pass / fail bit indicates whether the training operation is successful for a corresponding one of the plurality of semiconductor memory devices (200, 201a~201e, 202a~202e, 203a~203e, 204a~204e, 500), and the memory identifier bit identifies the corresponding one of the plurality of semiconductor memory devices (200, 201a~201e, 202a~202e, 203a~203e, 204a~204e, 500), and to combine the training information signal with the selected equalization coefficients and the flag signal to generate a combined training information signal, wherein the memory module further comprises the following: a control device (110, 110a) configured to receive the combined training information signal from each of the semiconductor memory devices (200, 201a~201e, 202a~202e, 203a~203e, 204a~204e, 500) and to transmit the combined training information signal to the memory controller (25, 710), and the control device (110, 110a) has a memory configured to store the combined training information signal for each of the semiconductor memory devices (200, 201a~201e, 202a~202e, 203a~203e, 204a~204e, 500). [13] Memory module (100, 100a, 720, 730, 950) according to claim 2, wherein the receive interface circuit (400, 400a, 400b, 520, 621) is further configured to to compare the training structure with a reference voltage in order to output a comparison signal, to generate the reference voltage in response to a control code to search for the control code that corresponds to a desired voltage level of the reference voltage in the training mode, and to output the control code in normal mode. [14] Memory module (100, 100a, 720, 730, 950) according to claim 1, wherein each of the semiconductor memory devices (200, 201a~201e, 202a~202e, 203a~203e, 204a~204e, 500) further comprises: a temperature sensor (560) which is configured to to sample the operating temperature of a corresponding semiconductor storage device (200, 201a~201e, 202a~202e, 203a~203e, 204a~204e, 500), and to transmit a training request signal to the memory controller (25, 710) in response to the operating temperature being greater than a reference temperature, wherein the training request signal requests the training operation of the corresponding semiconductor memory device (200, 201a~201e, 202a~202e, 203a~203e, 204a~204e, 500), wherein the receive interface circuit (400, 400a, 400b, 520, 621) of each of the plurality of semiconductor memory devices (200, 201a~201e, 202a~202e, 203a~203e, 204a~204e, 500) is configured to set an on-die termination resistance of equal relative to each other in the training mode, and Each of the semiconductor memory devices (200, 201a~201e, 202a~202e, 203a~203e, 204a~204e, 500) has a double data rate 5 (DDR5) synchronous dynamic random access memory (SDRAM). [15] Storage system comprising the following: a memory controller (25, 710); and a memory module (100, 100a, 720, 730, 950) comprising a plurality of semiconductor memory devices (200, 201a~201e, 202a~202e, 203a~203e, 204a~204e, 500), each of the plurality of semiconductor memory devices (200, 201a~201e, 202a~202e, 203a~203e, 204a~204e, 500) comprising a memory cell arrangement (300) comprising a plurality of dynamic memory cells, wherein the plurality of semiconductor memory devices (200, 201a~201e, 202a~202e, 203a~203e, 204a~204e, 500) is configured to simultaneously perform a training operation, wherein the majority of semiconductor memory devices (200, 201a~201e, 202a~202e, 203a~203e, 204a~204e, 500) have a receive interface circuit (400, 400a, 400b, 520, 621) configured to to perform a training operation to search for selected equalization coefficients of an equalizer (410, 522) based on a training structure received from the memory controller (25, 710), and to transmit a training information signal to the memory controller (25, 710) in a training mode in response to a training command from the memory controller (25, 710), wherein the training information signal has the selected equalization coefficients, wherein the receiving interface circuit (400, 400a, 400b, 520, 621) has the following: the equalizer (410, 522), which is configured to generate an equalizer output structure by equalizing the training structure based on control equalization coefficients in the training mode; and a self-training circuit (430, 530) which is configured to provide the control equalization coefficients for the equalizer (410, 522), wherein the self-training circuit (430, 530) is configured to to generate an error count value that indicates a difference between the equalizer output structure and a reference structure, and adaptively adjust search equalization coefficients to provide the control equalization coefficients for the equalizer (410, 522) based on the error count value and a reference value, wherein The equalizer (410, 522) uses the search equalization coefficients to search for the selected equalization coefficients.

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