Adaptive cache management

Abstract

Storage device (120) that receives read and write commands from a host (102), wherein the storage device (120) has the following: a non-volatile memory (124), part of which is called intermediate storage (IS) memory and another part is called main storage (MS) memory, wherein the IS memory (132) has lower write and read latencies, greater endurance and lower storage density and capacity than the MS memory (134); and an intermediate storage (IS) manager (334) that is configured to predict host activity and to select and execute a relocation scheme based on the predicted host activity in order to selectively relocate one or more parts of data from the IS storage (132) to the MS storage (134) according to the selected relocation scheme; where the IS Manager (334) is configured to: to update the predicted host activity from time to time and to select and execute another migration scheme based on the updated predicted host activity; and to identify and store further potential host activity patterns (128) based on at least one activity log (126) and to generate and store further relocation schemes, each of which is associated with one of the identified further potential host activity patterns; the further relocation schemes are available for selection and execution by the IS Manager (334) after generation and storage.

Description

BACKGROUND

[0001] A storage device containing non-volatile memory can include a portion of the non-volatile memory referred to as intermediate storage (IS) and another portion referred to as main storage (MS). IS is used in storage devices to provide faster write throughput and can also serve as a secure zone for quickly storing host data before it is written to the MS. IS can also function as a non-volatile memory cache, enabling very fast access to active data stored within IS.The general concept is to use more expensive non-volatile memory, which has lower write and read latencies, greater endurance, and lower storage density and capacity than IS memory, and less expensive non-volatile memory, which has higher write and read latencies, lower endurance, and higher storage density and capacity than MS memory. The more expensive IS memory, which will likely account for less than 10 percent of a storage device's total storage budget, may include single-level cell (SLC) memory, in which a single data bit is stored per memory cell. Alternatively, or additionally, the IS memory may include storage class memory (SCM).In contrast, the less expensive MS memory, which will likely account for more than ninety percent of the total storage budget, can include multi-level cell (MLC) memory, storing two or more bits per memory cell. MLC memory, as the term is used here, can contain memory cells storing two, three, or four data bits, or potentially even more than four data bits per cell. Accordingly, as the term is used here, MLC memory also includes triple-level cell (TLC) and quad-level cell (QLC) memory.

[0002] The process of transferring data from IS storage to MS storage is called a "relocation." Relocation is performed to free up space in IS storage. While IS storage is generally superior in both performance and endurance, it is too small to effectively cache all host data. Conventional techniques for performing a relocation typically rely on simple heuristics, such as FIFO (First-In-First-Out), or an aging algorithm.However, conventional relocation methods, also known as conventional relocation schemes, are not optimal for many use cases. This is because there is a clear distinction between what would be an optimal relocation scheme for use in a storage device used for streaming video and what would be an optimal relocation scheme for use in a storage device used for repeatedly updating the same relatively small piece of data. Video streaming is an extreme use case where an entire flash drive is written and then immediately and repeatedly rewritten. Repeatedly updating the same relatively small piece of data is another extreme use case at the opposite end of the spectrum, where the same logical block address (LBA) can be rewritten repeatedly.

[0003] In various scenarios, an IS storage device may run low on storage while still requiring it, which could reduce write throughput and is generally undesirable. However, the read latency from IS storage is also lower than from MS storage. Therefore, it is advantageous to avoid moving a piece of data from IS storage to MS storage by reading it shortly after writing, as its read latency would be lower if it were held in IS storage.

[0004] Publication US 2016 / 0054931A1 concerns storage devices and methods for optimizing the use of storage devices, where file system metadata is processed in host write requests to determine information about future host write operations. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a block diagram representing an embodiment of a storage device connected to (or embedded in) a host device that can implement embodiments of the technology described herein. Fig. 2 is a block diagram of an exemplary implementation of the hardware architecture for a control of the storage device, which is located in Fig. 1 is introduced, which can implement certain embodiments of the technology described herein. Fig. Figure 3 is a block diagram of an example storage device. Fig. Figure 4 is a block diagram of an example of a non-volatile memory die. Fig. Figure 5 is a high-level flowchart used to summarize procedures for performing adaptive management of IS storage according to certain embodiments of the present technology. Fig. Figure 6 is a high-level flowchart used to explain how the selected and executed relocation scheme may change over time. Fig. 7A is a flowchart used to provide additional details of one of the Fig. to describe the 5 presented steps, wherein this step involves the selection of one from a variety of stored relocation schemes which are used to selectively relocate data from IS storage to MS storage according to an embodiment of the present technology. Fig. 7B is a flowchart used to provide additional details of one of the Fig. to describe the 5 presented steps, wherein this step involves the selection of one from a multitude of stored relocation schemes which are used to selectively relocate data from the IS storage to the MS storage according to a further embodiment of the present technology. Fig. Figure 8 is a flowchart used to explain how further potential host activity patterns can be identified and further migration schemes can be generated and stored according to certain embodiments of the present technology. Fig. Figure 9 illustrates a first example activity log, based on which a host activity pattern can be predicted, and the predicted host activity pattern can be used to select a relocation scheme. Fig. Figure 10 illustrates a second exemplary activity log, based on which a host activity pattern can be predicted, and the predicted host activity pattern can be used to select a relocation scheme. Fig. Figure 11 is a comprehensive flowchart that provides some additional details on how a relocation scheme can be implemented after selection according to an embodiment. Fig. Figure 12 is a comprehensive flowchart that provides some additional details on how an alternative relocation scheme can be implemented after selection according to an embodiment. DETAILED DESCRIPTION

[0005] According to the invention, a storage device that receives read and write commands from a host and a method for use by a storage device having the features of the independent claims are provided; dependent claims relate to preferred embodiments.

[0006] Storage devices capable of adaptive management of the intermediate storage and methods for using them are described herein. Such a storage device may include non-volatile memory, wherein a portion of the non-volatile memory is designated as intermediate storage (IS) and another portion is designated as main storage (MS). The IS storage has lower read and write latencies, higher endurance, and lower storage density and capacity than the MS storage. For example, the IS storage may include single-level cell (SLC) flash memory, storing a single data bit per memory cell, and the MS storage may include multi-level cell (MLC) flash memory, storing two or more data bits per memory cell.According to certain embodiments of the present technology, which are described in more detail below, a plurality of relocation schemes are stored, each of which is associated with one of a plurality of potential host activity patterns. Additionally, an activity log is maintained that tracks operations relating to data stored in the non-volatile memory, and a host activity pattern is predicted based on the activity log. According to certain embodiments, one of the plurality of stored relocation schemes is selected to be applied to data stored in the IS memory, the selection being made based on the predicted host activity pattern. The selected relocation scheme is then executed to selectively relocate one or more portions of data from the IS memory to the MS memory according to the selected relocation scheme.Before providing additional details on the embodiments of the present technology, it is first useful to describe an exemplary storage device with which embodiments of the present technology can be implemented.

[0007] The following detailed description refers to the accompanying drawings, which form part thereof and depict illustration-specific embodiments. It is understood that other embodiments may be used and that mechanical and electrical modifications may be made. The following detailed description is therefore not to be understood as restrictive. Throughout the following description, the same reference numerals or reference designators are used to denote identical parts or elements. Furthermore, the first digit of a three-digit reference number and the first two digits of a four-digit reference number identify the drawing in which the reference number first appears.

[0008] Fig. Figure 1 is a block diagram representing an embodiment of a storage device 120 connected to (or embedded in) a host device 102, wherein the host device 102 can implement embodiments of the present technology described below. With reference to Fig. 1. The host device 102 stores data in the storage device 120 and retrieves data from it by issuing write and read commands. The storage device 120 can be embedded in the host device 102 or be in the form of a card, a USB (Universal Serial Bus) drive, or other removable storage media, such as a solid-state drive (SSD), which is detachably connected to the host device 102 via a mechanical and electrical connector. The host device 102 can be any of a range of fixed or portable data-generating devices, such as a personal computer, a smartphone, a personal digital assistant (PDA), a server, a set-top box, or the like. More generally, the host device 102 can include host logic that performs the functions of a smartphone, PDA, laptop, server, set-top box, etc.Although not specifically shown, the host may contain and / or communicate with a read-only memory (ROM).

[0009] The host device 102, which can be more accurately referred to as host 102, can contain one or more processors 104 that execute one or more application programs 106. The application programs 106 communicate with a file system 110 via one or more application programming interfaces (APIs) 108 when data is to be stored in or retrieved from the storage device 120. The file system 110 can be a software module that runs on the processor(s) 104 and manages the files in the storage device 120. The file system 110 manages clusters of data in the logical address space. Common operations performed by a file system 110 include creating, opening, writing (saving), reading (retrieving), locating, moving, copying, and deleting files.The file system 110 can contain circuits, software, or a combination of circuits and software.

[0010] The file system 110 can be a standalone chip or software executable by the processor(s) 104 of the host 102. A storage device driver 112 on the host 102 can translate instructions from the file system 110 for transmission over a communication channel 114 between the host 102 and the storage device 120. The interface for communication over the communication channel 114 can be any number of well-known interfaces, such as SD, MMC, USB storage device, SATA, SCSI, and PCI Express interfaces. A file system data structure, such as a file allocation table (FAT), can be stored in the memory (e.g., 124 or 206) of the storage device 120. The host 102 can use the file system data structure to maintain a logical address space for all logical block addresses (LBAs) assigned to data by the host 102.In addition to its use as a reference to the communication channel between the host 102 and the storage device 120, the reference number 114 can also be used to refer to host interface signals transmitted over the communication channel 114. Furthermore, the reference number 114 can refer to changes in host memory that are read and retrieved by the storage device 120 according to a protocol such as NVMe or AHCI operating over the PCI Express transport. The host device 102, which can also be more concisely referred to as host 102, uses the file system 110 to address files stored in the storage device 120, which may involve writing data to and reading data from the non-volatile memory 124 of the storage device 120. Examples of file system types that can be used by Host 102 include, but are not limited to, FAT32, exFAT, ext2 / 3 / 4, HFS+ and NTFS.

[0011] The storage device 120 includes a controller 122 (which can also be referred to as the memory controller 122) that communicates with the non-volatile memory 124 via signals 123. The reference numeral 123 can also be used to refer to a communication channel between the controller 122 and the non-volatile memory 124. It should be noted that Fig. Figure 1 shows a logical representation of the non-volatile memory 124. In one embodiment, the non-volatile memory 124 can be implemented using one or more memory dies.

[0012] The non-volatile memory 124 can store management tables 125 and one or more activity logs 126. As described in more detail below, according to certain embodiments of the present technology, the non-volatile memory 124 can store a plurality of potential host activity patterns 128, and for each of the potential host activity patterns, a linking relocation scheme. The plurality of potential host activity patterns and linked relocation schemes can alternatively be stored in read-only memory (e.g., ROM 318 in Fig. 3) stored in storage device 120.

[0013] In one embodiment, the management tables 125 include one or more L2P (logic-to-physical mapping) tables and one or more P2L (physical-to-logic mapping) tables. The controller 122 can use the management tables 125 to map logical block addresses (LBAs) to physical block addresses (PBAs). Such tables 125 can be used to map LBAs directly to PBAs, or LBAs can be mapped to intermediate or virtual block addresses that are mapped to PBAs. Other variations are also possible. In some embodiments, the host data 130 is stored in blocks (e.g., Block 0, Block 1, Block 2, ...). In some exemplary embodiments, a block of non-volatile memory cells is the erase unit. In some embodiments, a block represents a plurality of memory cells grouped by common bit lines and word lines.Instructions or commands, such as write commands, sent from host 102 to storage device 120 via communication channel 114 can include logical block addresses (LBAs). In contrast, instructions or commands sent via communication channel 123 can include physical block addresses (PBAs).

[0014] The one or more activity log(s) 126 track write operations performed on the host 102 in response to receiving write commands from the host 102. Additionally, the activity log(s) 126 track read operations performed on the host 102 in response to receiving read commands from the host 102. Entries in the activity logs 126 can be specified in the form of logical block addresses (LBAs) and / or LBA ranges, preferably with time information (e.g., a timestamp) indicating when write and read operations are performed. As described in more detail below, according to certain embodiments of the present technology, a host activity pattern can be predicted based on the activity log(s) 126. The predicted host activity pattern may include a predicted write pattern.Additionally or alternatively, the predicted host activity pattern can include a predicted read pattern.

[0015] Continue on Fig. Referring to 1, the non-volatile memory 124 includes a part called intermediate storage (IS) and another part called main storage (MS). As in Fig. As shown in Figure 1, the host data 130 can be stored in IS memory and in MS memory. More precisely, when the storage device 120 receives a write command from the host 102, the storage device 120 can respond by storing host data either in the portion of non-volatile memory 124 designated as IS memory 132 or in the portion of non-volatile memory 124 designated as MS memory 134. Several known techniques can be used by the memory controller 122 to determine whether data should be stored in IS memory 132 or MS memory 134. Additionally, several known techniques can be used by the memory controller 122 to move (i.e., transfer) data from IS memory 132 to MS memory 134.Embodiments of the present technology, which are described in more detail below, are not related to any specific technique used by the memory controller 122 to determine whether data should first be stored in the IS memory 132 or in the MS memory 134. Furthermore, embodiments of the present technology, which are described in more detail below, generally relate to improved techniques for relocating (i.e., transferring) data from the IS memory 132 to the MS memory 134.

[0016] As in Fig. As shown in Figure 1, host data 130 is stored in both IS memory 132 and MS memory 134. Individual blocks (e.g., Block 0, Block 1, Block 2, ...) of the host data 130 can be subdivided into pages of memory cells for operational purposes. The memory cells of each block can, for example, be subdivided into eight pages P0–P7. Alternatively, there can be 16, 32, or more pages of memory cells within each block. The page is the unit of data programming and reading within a block, containing the minimum amount of data that can be programmed or read simultaneously. However, to increase the operational parallelism of the storage system, such pages within two or more blocks can be logically linked to form meta-pages. A meta-page can, for example, be formed from a physical page from each of the four blocks (e.g.,A metapage can, for example, contain page P2 in each of the four blocks, but the pages of a metapage do not necessarily have to have the same relative position within each of the blocks. A metapage can be the maximum unit of programming.

[0017] Continue on Fig. With reference to 1, the IS memory 132 exhibits lower write and read latencies than the MS memory 134. In other words, the IS memory 132 can be written to and read from at higher speeds than the MS memory 134. Additionally, the IS memory 132 has a higher endurance than the MS memory 134. For example, the expected lifetime of each cell in the IS memory 132 might be 20,000 program / erase (P / E) cycles, while the expected lifetime of each cell in the MS memory 134 might be 2,000 P / E cycles. In this case, the cells in the IS memory 132 would have 10 times the endurance of the cells in the MS memory 134. This is just one example and is not intended to be exhaustive. The IS 132 memory also has a lower storage density and capacity than the MS 134.More precisely, individual cells of IS memory 132 can store fewer bits of host data than individual cells of MS memory 134, and a significantly smaller portion of the non-volatile memory 124 used to store host data 130 can be allocated to IS memory 132 than is allocated to MS memory 134. More generally, the more expensive IS memory 132 likely occupies less than 10 percent of the total memory budget of the storage device 120, and depending on the storage device 120, may occupy as little as 2 percent or less of the total memory budget. The exact ratio of IS memory 132 to MS memory 134 depends on the specific product and generally affects the cost relative to the performance and endurance of the storage device 120.

[0018] According to certain embodiments, the IS memory 132 can include a single-level cell (SLC) memory, in which a single data bit is stored per memory cell, which can also be referred to as a memory element or area. More precisely, the SLC memory can be operated to store two recognizable load levels to store a bit that can have one of two possible states: 0 or 1. The IS memory 132 can alternatively or additionally include forms of persistent byte-addressable memory, including a ReRAM, a phase-change memory, or a magnetic RAM. In contrast, the less expensive MS memory 134 can include a multi-level cell (MLC) memory, in which two or more bits are stored per memory cell.MLC memory, as the term is used herein, can contain memory cells, storing two, three, or four data bits, or potentially even more than four data bits, per memory cell. Accordingly, as the term is used herein, MLC memory also encompasses TLC (Triple-Level Cell) and QLC (Quad-Level Cell) memory. For example, MLC memory can be operated to store four detectable charge levels, which can be used to store four states, and can store two data bits: 00, 01, 10, or 11. In another example, if the MLC memory is TLC memory, it can be operated to store eight detectable charge levels, which can be used to store eight states, and can contain three data bits: 000, 001, 010, 011, 100, 101, 110, or 111.In yet another example, if the MLC memory is a QLC memory, it can be operated to store sixteen recognizable charge levels, which can be used to store sixteen states and can contain four data bits: 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, or 1111. The IS 132 memory can be more concisely referred to as IS 132. Similarly, the MS 134 memory can be more concisely referred to as MS 134.

[0019] As explained above, IS Memory 132 can be used in the background to enable faster write throughput and can also be used as a safe zone to quickly store host data before it is stored in MS Memory 134. IS Memory 132 can also function as a non-volatile memory cache, allowing very fast access to active data stored in IS Memory 132. The general concept is to use more expensive non-volatile memory, which has lower write and read latencies, greater endurance, and lower storage density and capacity than IS Memory 132, and less expensive non-volatile memory, which has higher write and read latencies, lower endurance, and higher storage density and capacity than MS Memory 134.

[0020] As explained above, the background process of data transfer from IS memory 132 to MS memory 134 is referred to as a "relocation." The relocation is performed to free up space within IS memory 132, making it available to store incoming host data. In certain embodiments, the relocation is performed as a background process without intervention from the host 102. Preferably, a relocation is performed when the storage device 120 is idle, or more precisely, when it is not responding to write or read commands received from the host 102. In certain situations, the storage medium 120 may run out of IS memory 132 while it is still needed, which could reduce write throughput and is generally undesirable.However, since the read latency from IS memory 132 is also shorter than from MS memory 134, it makes sense to avoid moving data that would be used shortly after being written, as the read latency would be lower if it were kept in IS memory 132.

[0021] While the IS 132 memory is generally superior in both performance and endurance, it is too small to effectively cache all host data. Conventional techniques for performing a relocation typically rely on simple heuristics, such as FIFO (First-In-First-Out) or an aging algorithm. However, conventional relocation methods, also known as conventional relocation schemes, are not optimal for many use cases because there is a clear distinction between what would be an optimal relocation scheme for use in a storage device used for streaming video and what would be an optimal relocation scheme for use in a storage device used for repeatedly updating the same relatively small piece of data.The example of video streaming is an extreme use case where an entire flash drive is written and then immediately and repeatedly rewritten. Repeatedly updating the same relatively small piece of data is another extreme use case at the other end of the spectrum, where the same LBA can be rewritten repeatedly. Between these extreme scenarios lies a large gray area. Implementations of the present technology, which are explained in more detail below, can be used to manage relocation in a way that provides improved read and write performance compared to conventional relocation.However, before further details of such embodiments of the present technology are provided, additional exemplary details of the storage device 120, which can be used to implement embodiments of the present technology, are given with reference to . Fig. 2, Fig. 3 and Fig. 4 described.

[0022] Fig. Figure 2 is a block diagram of an exemplary embodiment of the hardware architecture for a controller 122 that can be used to implement the technology described herein. The controller 122 includes one or more processors 200 communicating with a host interface 202 and a memory interface 204. The host interface 202 communicates with the host device 102 via host interface signals 114. In one embodiment, the host interface 202 is an MMC (Multi Media Card) interface. In another embodiment, the host interface 202 is a UFS (Universal Flash Storage) interface. The memory interface 204 communicates with the non-volatile memory 124 via signals 123 and can be any suitable interface, including toggle mode 200, 400, or 800.The processor(s) 200 also communicate with a working memory (RAM) 206, which is a local volatile memory for the controller 122 and can therefore also be referred to as the controller RAM 206. The RAM 206 can be any type of volatile memory (e.g., DRAM, SRAM, etc.). In one embodiment, the RAM 206 stores code (software and / or firmware) that programs the processor(s) 200 to perform the functions described below for managing the storage device 120, including selecting and executing a relocation scheme. In another embodiment, one or more processor(s) 200 include custom hardware (FPGAs, ASICs, etc.) with or without software to perform the functions described below for managing the storage device 120, including selecting and executing a relocation scheme.

[0023] The storage device 120 can include memory management functions. During operation, the processor(s) 200 can execute memory management instructions (which may be contained within instructions) for the operation of the memory management functions. The memory management functions can control the allocation of one or more portions of memory within the storage device 120, such as the control RAM 206. For example, memory management functions can allocate a portion of the control RAM 206 for a data cache. Memory management functions can also specify which portion of the non-volatile memory 124 is IS memory 132 and which portion is MS memory 134. One, some, or all of the memory management functions can be performed by one or more separate elements within the storage device 120.A portion of the control RAM 206 can be used to cache copies of the management tables 125, or parts thereof, to enable the controller 122 to perform logical-to-physical (LTP) and physical-to-logical (PTL) address translations much faster than if the controller 122 had to constantly access the management tables 125 stored in non-volatile memory. For example, the control RAM 206 can include an LTP cache that can store one or more tables (or parts thereof) used for LTP translations, and a PTL cache that can store one or more tables (or parts thereof) used for PTL translations.The control RAM 206 can also be used to cache other information stored in the non-volatile memory 124 to provide fast access to such information by the control 122 and, more specifically, by the processor(s) 200. For example, the control RAM 206 can include an activity log cache 226, which can store a copy of the activity log(s) 126 (or parts thereof), and an activity pattern and relocation scheme cache 228, which can store the potential host activity patterns and the associated relocation schemes 128 (or parts thereof) used to perform the relocation from IS memory 132 to MS memory 134.

[0024] Fig. Figure 3 is a block diagram of an exemplary embodiment of the storage device 120. However, the embodiment shown in Figure 3 can be modified to reflect the following: Fig. The architecture shown in Figure 3 can also be used to implement other types of non-volatile storage devices. Fig. Figure 3 shows that the storage device 120 includes the controller 122, which is connected to one or more non-volatile memory dies 308 (which are located in the Fig. 1 shown non-volatile memory 124) is connected. Fig. Section 3 provides details of some of the software components of the controller 122, which are discussed in more detail below. Depending on the technology used to implement the IS memory 132, the IS memory may be located in a different non-volatile memory 308 than the MS memory 134, or the same non-volatile memory 308 may contain some of the IS memory 132 and some of the MS memory 134.

[0025] As used herein, the Controller 122, for a system using non-volatile memory, is a device that manages the data stored in the non-volatile memory and communicates with a host. The Controller 122 can have various functions in addition to the specific functionality described herein. For example, the Controller 122 can format the non-volatile memory to ensure that the memory functions properly, identify bad memory cells (the physical storage unit), and allocate spare memory cells to replace future failed cells. A portion of the free memory cells can be used to hold the firmware for the operation of the Controller and to implement other functions. The firmware can also be read into the local volatile memory during operation.When a host needs to read data from or write data to non-volatile memory, it communicates with the Controller 122. If the host provides a logical address to which data should be read / written, the Controller 122 translates the logical address received from the host into a physical address in the physical flash memory. The Controller 122 can also perform various memory management functions, such as, but not limited to, wear balancing (distributing write operations across memory dies or blocks to prevent certain memory blocks from being worn out by repeated overwriting) and garbage collection (once a block is full, only the valid data pages are moved to a new block so that the full block can be erased and reused).

[0026] The interface between the controller 122 and the non-volatile memory die 308 can be any suitable flash interface, such as Toggle Mode 200, 400, or 800, or any other communication interface, such as PCI Express. In some embodiments, the memory device 120 includes a single channel between the controller 122 and the non-volatile memory die 308; however, the subject matter described here is not limited to a single memory channel. For example, in some memory system architectures, two, four, eight, or more channels may be present between the controller 122 and the memory die 308, depending on the controller functions. In each of the embodiments described here, more than a single channel may be present between the controller 122 and the memory die 308, even if a single channel is shown in the drawings.

[0027] As in Fig. As shown in Figure 3, the controller 122 includes a frontend module 312 that interacts with a host, a backend module 310 that interacts with one or more non-volatile memory dies 308, and various other modules that perform functions which will now be described.

[0028] The in Fig. The three components of the controller 122 shown can take the form of a bundled functional hardware unit (e.g., an electrical circuit) intended for use with other components, program code (e.g., software or firmware) executable by one or more processors, a processing circuit that typically performs a specific function among related functions, or a standalone hardware or software component connected to a larger system. For example, each module can include an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), an electrical circuit, a digital logic circuit, an analog circuit, a combination of discrete circuits, gates, or any other type of hardware or combination thereof.Alternatively or additionally, each module may include software stored in a processor-readable device (e.g., local volatile memory) to program a processor to perform the functions described herein.

[0029] The storage device 120 includes a random access memory (RAM) 206 (same local volatile memory as above in relation to Fig. 2 explained) and a read-only memory (ROM) 318. Again with reference to the modules of the controller 122, a buffer manager / bus controller 314 manages the RAM 206 and controls the internal bus arbitration of the controller 122. The ROM 318 stores the boot code for the controller. Although it is in Fig. In embodiments 3, the RAM 216 or the ROM 318 are shown to be arranged separately from (but connected to) the controller 122. In other embodiments, either the RAM 216 or the ROM 318, or both, can be located within the controller. In still other embodiments, parts of the RAM and the ROM can be located both inside and outside the controller. Furthermore, in some implementations, the controller 122, the RAM 206, and the ROM 318 can be arranged on separate semiconductor elements. In certain embodiments, instead of storing the potential host activity patterns and assigning relocation schemes to the non-volatile memory 124, the potential host activity patterns and association relocation schemes can be stored in the ROM 318.

[0030] The frontend module 312 includes the host interface 202 (introduced in the discussion on Fig. 2) and a physical layer interface (PHY) 322, which provides the electrical interface with the next-level host or storage controller. The choice of host interface type 202 may depend on the type of storage used. Example host interface types 202 may include, but are not limited to, SATA, SATA Express, SAS, Fibre Channel, USB, PCIe, MMC, UFS, and NVMe. The host interface 202 typically facilitates the transmission of data, control signals, and timing signals. In one embodiment, the front-end module 312 provides the single communication interface adapted to communicate with an external computing device (e.g., host) for the controller 122 and the storage die 308 of the storage device 120.

[0031] The backend module 310 includes an ECC (Error Correction Code) engine 324, which encodes the data bytes received from the host and decodes the data bytes read from the non-volatile memory die 308, correcting errors. The ECC engine 324 may include circuitry for receiving data and generating one or more codewords that represent an encoding of the data. For example, the ECC engine 324 may be configured to use Reed-Solomon encoding, a BCH code, an LDPC (Low Density Parity Check) code, one or more other error detection and correction codes, or a combination thereof. A command sequencer 326 generates command sequences, such as program and erase command sequences, to be transferred to the non-volatile memory die 308. A RAID (Redundant Array of Independent Dies) module 328 manages the generation of RAID parity and the recovery of failed data.RAID parity can be used as an additional level of integrity protection for the data written to the non-volatile storage system 124. In some cases, the RAID module 328 can be part of the ECC engine 324. It should be noted that RAID parity can be added as an additional die or dies, but it can also be added within the existing die, e.g., as an extra layer, an extra block, or extra WLs within a block. A storage interface 204 (introduced in the discussion on...) Fig. 2) It delivers the instruction sequences to the non-volatile memory die 308 and receives status information from the non-volatile memory die 308. In one embodiment, the memory interface 204 can be a DDR (Double Data Rate) interface and / or a Toggle Mode 200, 400, or 800 interface. A flash control layer 332 controls the overall operation of the backend module 310.

[0032] During the process of writing data to memory, such as IS memory 132, the data can be encoded with additional bits (“parity bits”) to form a codeword. If noise is present, some of the bits representing the codeword may change, corrupting the original codeword with errors. When the codeword is read from memory, a decoder can be used to identify and correct the errors using error correction coding (ECC). For example, Bose-Chaudhuri-Hocquenghem (BCH) ECC schemes are used in applications where bit errors tend to be uncorrelated. The transfer of data from IS memory 132 to MS memory 134 can be performed with or without ECC control. When data is written to IS memory 132, an error can be introduced into a codeword.If a codeword containing an error is moved from IS memory 132 to MS memory 134 without first decoding and correcting the error, as can happen in on-chip copy (OCC) operations, the error can become a hard error (if the MLC-type flash memory is programmed with the wrong voltage), which can affect throughput and endurance. To reduce the probability and severity of hard errors in MS memory 134, data moved from IS memory 132 can be decoded and error-corrected before being re-encoded with parity bits and moved (i.e., transferred) to MS memory 134. For example, the memory controller 122 can perform such decoding, error correction, and re-encoding of data, a process that can be referred to as a copy-through controller (CTC). While the use of CTC should reduce hard errors, it increases the move latency.

[0033] Additional components of the in Fig. The storage device 120 shown in Figure 3 includes a Flash Translation Layer (FTL) or Media Management Layer (MML) 338, which performs wear compensation of memory cells of the non-volatile memory die 308. The storage device 120 also includes other discrete components 340, such as external electrical interfaces (e.g., as part of the host interface and the storage interface), external RAM, resistors, capacitors, or other components that may be connected to the controller 122. In alternative embodiments, one or more of the physical layer interfaces 322, the RAID module 328, the media management layer 338, and the buffer management / bus controller 314 are optional components that may not be necessary in the controller 122.

[0034] The Flash Translation Layer (FTL) or Media Management Layer (MML) 338 can be integrated as part of the flash management system, enabling it to handle errors and interact with the host. Specifically, the FTL 338 is responsible for the non-volatile memory management components. In particular, the FTL 338 may include an algorithm in the memory device's firmware that translates write operations from the host into write operations to the memory of a memory die 308. The FTL 338 may be necessary because: 1) the memory may have limited endurance; 2) the memory can only be written in multiples of pages; and / or 3) the memory cannot be written unless it is erased as a block. The FTL 338 understands these potential memory limitations, which may not be apparent to the host.Accordingly, the FTL 338 attempts to translate write operations from the host into writes to the non-volatile memory 124, which can be flash memory. The FTL 338 also manages the process of mapping between logical addresses from the host and physical addresses on the memory die 308. This can include updating the L2P and P2L tables during programming, erasing, and executing movement instructions.

[0035] The FTL 338 is represented by a cache management (IS) controller 334, which can also be referred to as IS management 334. The IS manager 334 can select from a variety of possible relocation schemes stored in non-volatile memory 124 (e.g., in the activity patterns and relocation schemes 128), in ROM 318, and / or in control RAM 206 (e.g., in the activity patterns and relocation scheme cache 228). As described in more detail below, the IS manager 334 can select a relocation scheme based on a predicted host activity pattern and execute (or initiate the execution of) the selected relocation scheme. The IS-Manager 334 can predict an activity pattern based on the activity log(s) 126 stored in non-volatile memory 124 and / or the activity log cache 226 stored in control RAM 206.As described in more detail below, according to certain embodiments of the present technology, the IS-Manager 334 can determine when the relocation scheme should be changed. Furthermore, according to certain embodiments of the present technology, the IS-Manager 334 can identify new or additional potential host activity patterns and generate associated relocation schemes to supplement the stored potential host activity patterns and relocation schemes 128, after which the new relocation schemes would be available for selection and execution by the IS-Manager 334. Alternatively, the IS management control 334, or a part thereof, can be contained in the backend module 310. For example, the backend module 310 can execute relation schemes using the logic of the FTL 338.It is also possible that part of the IS management controller 334 BZ is implemented by the frontend module 312, and in particular by the host interface 202 (of the frontend module 312), which records one or more activity logs 126. More generally, the IS manager 334 is implemented by the storage controller 122 according to certain embodiments.

[0036] According to certain embodiments, the relocation is carried out using a special hardware circuit, e.g. one of the other discrete components 340, which are in Fig. Figure 3 illustrates this. One advantage of such embodiments is that the relocation can be performed without having to stop the memory controller 122's operation. This would allow for both a reasonable relocation latency and lower error rates in the MS memory 134. In this way, a relatively high ECC (low parity) rate can be used for storing the data in the IS memory 132, and later the data can be decoded and recoded at a lower ECC (higher parity) rate for longer-term storage in the MS memory 134.

[0037] Fig. Figure 4 is a functional block diagram of an example memory die 308. The in Fig. The four components shown are electrical circuits. In one embodiment, the memory die 308 includes a monolithic three-dimensional memory structure 426 made of non-volatile memory cells, a control circuit 410, and read / write circuits 428. In other embodiments, a two-dimensional array of memory cells can be used. The memory structure 426 is addressable via word lines through a row decoder 424 and via bit lines through a column decoder 432. The read / write circuits 428 include several read blocks 450, including SB1, SB2, ..., SBp (sampling circuit), and enable the parallel reading or programming of one side of memory cells. Commands and data are transmitted between the control 122 and the memory die 308 via signal lines 123. In one embodiment, the memory die 308 includes a set of input and / or output (I / O) pins connected to the signal lines 123.

[0038] One embodiment of the memory structure 426 features a monolithic three-dimensional memory structure in which multiple memory layers are formed above (and not within) a single substrate, such as a wafer, without any intervening substrates. The memory structure 426 can include any type of non-volatile memory monolithically formed in one or more physical layers of arrays of memory cells, which have an active area arranged above a silicon substrate. In one embodiment, the memory structure 426 implements a three-dimensional NAND flash memory. An example of a three-dimensional NAND flash memory is found in U.S. Patent No. 9,548,130, which is incorporated herein by reference in its entirety. Other embodiments include two-dimensional NAND flash memory, two-dimensional NOR flash memory, ReRAM crosspoint memory, magnetoresistive memory (e.g.,MRAM), phase-change memory (e.g., PCRAM), and others.

[0039] The control circuit 410 works in conjunction with the read / write circuits 428 to perform memory operations (e.g., erase, program, read, and others) on the memory structure 426 and includes a state machine 412, an on-chip address decoder 414, and a power control module 416. The state machine 412 provides die-level control of memory operations. In one embodiment, the state machine 412 is programmable by software. In other embodiments, the state machine 412 does not use software and is fully implemented in hardware (e.g., electrical circuits). In one embodiment, the control circuit 410 includes registers, ROM fuses, and other storage devices for storing default values, such as base voltages and other parameters.The on-chip address decoder 414 provides an address interface between the addresses used by the host 102 or the controller 122 and the hardware address used by the decoders 424 and 432. The power control module 416 controls the power and voltages supplied to the word lines and bit lines during memory operations. It may include drivers for word lines, selection transistors, source lines, and other components. The power control module 416 may include charge pumps for generating voltages. The sample blocks 450 contain bit line drivers.

[0040] Any combination of the control circuit 410, the state machine 412, the decoders 414 / 424 / 432, the power control module 416, the scanning blocks 450, the read / write circuits 428 and the control 122 can be considered as one or more circuit(s) performing the functions described herein.

[0041] Multiple memory elements in the 426 memory structure can be configured to be connected in series or to allow each element to be accessed individually. As a non-restrictive example, flash memory devices in a NAND configuration (NAND flash memory) typically contain memory elements connected in series. A NAND string is an example of a set of memory cells and selection gate transistors connected in series that can be used within the 426 memory structure. A NAND flash memory can be configured as an array composed of multiple NAND strings, where a NAND string is composed of multiple memory cells that share a single bit line and are accessed as a group. Alternatively, memory elements can be configured so that each element is accessible individually, e.g., a NOR memory array.NAND and NOR memory configurations are examples, and memory cells may be configured differently.

[0042] Memory cells can be arranged in an ordered array at the individual storage device level, such as in a multitude of rows and / or columns. However, memory elements can also be arranged in irregular or non-orthogonal configurations, or in structures that are not considered arrays.

[0043] In one embodiment, a three-dimensional storage array is arranged such that memory cells occupy multiple levels or multiple storage device levels, forming a structure in three dimensions (i.e., in the x, y, and z directions, where the z direction is substantially perpendicular and the x and y directions are substantially parallel to the main surface of the substrate). As a non-limiting example, a three-dimensional storage structure can be arranged vertically as a stack of multiple two-dimensional storage device levels. As another non-limiting example, a three-dimensional storage array can be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate, i.e., in the y-direction), each column containing multiple memory cells. The vertical columns can be arranged in a two-dimensional configuration, e.g.,in an xy-plane, resulting in a three-dimensional arrangement of memory cells with memory cells on multiple vertically stacked memory levels. Other configurations of memory elements in three dimensions can also form a three-dimensional memory array.

[0044] As a non-restrictive example, in a three-dimensional NAND memory array, the memory elements can be coupled to form vertical NAND strings that traverse multiple horizontal memory device levels. Other three-dimensional configurations can be considered, where some NAND strings contain memory elements in a single memory level, while other strings contain memory elements that extend across multiple memory levels. An exemplary memory system is a three-dimensional memory structure that incorporates vertical NAND strings with charge-trapping material. Three-dimensional memory arrangements can also be configured in a NOR configuration.

[0045] The memory structure 426 can also be a ReRAM crosspoint memory. An example of a ReRAM crosspoint memory includes reversible resistive switching elements arranged in crosspoint arrays, accessed by X lines and Y lines (e.g., word lines and bit lines). In another embodiment, the memory cells can include conductive bridge memory elements. A conductive bridge memory element can also be referred to as a programmable metallization cell. A conductive bridge memory element can be used as a state-change element based on the physical displacement of ions within a solid electrolyte. In some cases, a conductive bridge memory element can include two solid metal electrodes, one relatively inert (e.g., tungsten) and one electrochemically active (e.g., silver or copper), with a thin film of the solid electrolyte between the two electrodes.As the temperature increases, so does the mobility of the ions, thus decreasing the programming threshold for the conductive bridge memory cell. Therefore, the conductive bridge memory element can exhibit a wide range of programming threshold values ​​across a temperature range.

[0046] The memory structure 426 can also be a magnetoresistive memory (MRAM), which stores data by means of magnetic memory elements. In one example, the elements are formed from two ferromagnetic plates, each capable of holding a magnetization, separated by a thin insulating layer. One of the two plates is a permanent magnet set to a specific polarity; the magnetization of the other plate can be changed to match that of an external field for storing the memory. A memory device is constructed from a grid of such memory cells. In one programming embodiment, each memory cell is situated between a pair of write lines arranged at right angles to each other, parallel to the cell, one above and one below the cell. When current is passed through them, an induced magnetic field is generated.

[0047] The 426 memory structure can also be a phase-change memory (PCRAM) that exploits the unique behavior of chalcogenide glass. One embodiment uses a GeTe-Sb₂Te₃ superlattice to achieve non-thermal phase changes by simply altering the coordination state of the germanium atoms with a laser pulse (or light pulse from another source). Therefore, the programming doses are laser pulses. The memory cells can be inhibited by preventing them from receiving the light. It should be noted that the use of "pulse" in this document does not require a rectangular pulse, but rather involves a (continuous or non-continuous) vibration or a jolt of sound, current, voltage, light, or other wave. The 426 memory structure contains many memory cell blocks.An average professional will recognize that the technology described herein is not limited to a single specific storage structure, but covers many relevant storage structures within the scope of the technology, as described herein and as.

[0048] As explained above, certain embodiments of the present technology relate to improved techniques for relocating (i.e., transferring) data from IS memory (e.g., 132) to MS memory (e.g., 134), non-volatile memory (e.g., 124), or a storage device (e.g., 120). The comprehensive flowchart of Fig. Section 5 is used to describe certain such techniques. In particular, the comprehensive flowchart of Fig. 5 is used to summarize methods for performing adaptive management of IS memories. Such methods can be used by a storage device (e.g., 120) that receives read and write commands from a host (e.g., 102) and includes a non-volatile memory (e.g., 124) and a memory controller (e.g., 122) in communication with the non-volatile memory (124) and the host (102), wherein the non-volatile memory (e.g., 124) includes a portion of its memory referred to as IS memory (e.g., 132) and another portion referred to as MS memory (e.g., 134), the IS memory having lower read and write latencies, greater endurance, and lower memory density and capacity than the MS memory.

[0049] With reference to Fig. Step 502 involves storing a variety of relocation schemes, each associated with one of a variety of potential host activity patterns. These potential host activity patterns, which may include potential write and read patterns, can be determined by analyzing activity logs from numerous different storage devices used to store data for hosts operated by numerous different types of users. For example, if the host is a low-power, single-processor notebook computer and the user is a student who primarily streams movies and browses the internet, the host's potential activity patterns will be very different from those of a high-performance, multi-processor computer used for simulations and / or computer modeling, and the user is an engineer.The potential host activity patterns can include a specific number (e.g., 100, 500, or 1000, but not limited to these) of the most frequently expected activity patterns identified through the analysis of numerous different activity logs. Each potential host activity pattern is associated with a relocation scheme, preferably optimized for specific host activity patterns. There can be a one-to-one correspondence between relocation schemes and potential host activity patterns. In other words, a unique relocation scheme can be stored for each potential host activity pattern. Alternatively, it is possible for more than one potential host activity pattern to be mapped to the same relocation scheme.For example, 1000 potential host activity patterns can be stored, but only 800 relocation schemes are stored, so certain potential host activity patterns share the same relocation scheme.

[0050] In certain embodiments, a preferred relocation scheme for a potential host activity pattern can be determined by optimizing a cost function. An example cost function might attempt to minimize or otherwise account for costs associated with reading data from IS storage, transferring (i.e., relocating) data from IS storage to MS storage, and reading data from MS storage. These costs might be in the form of latency and / or power consumption. This is just one example of a cost function that can be used to determine relocation schemes for potential host activity patterns and is not intended to cover all areas. Different relocation schemes might have different relocation characteristics, such as, but not limited to, different time and length characteristics.Time properties can specify how often, or more generally, the timing details of when a data transfer should occur. Length properties, for example, can specify the length of data fragments to be transferred from IS storage to MS storage.

[0051] With brief reference to Fig. 1. The multitude of potential host activity patterns and the associated relocation schemes 128 are represented as stored in non-volatile memory 124 and can, in particular, be stored in MS memory 134. The multitude of potential host activity patterns and associated relocation schemes can alternatively be stored in the Fig. ROM 318 shown in the diagram can be stored. Additionally, as shown in Fig. Figure 2 illustrates that, to enable faster and more energy-efficient access to the multitude of potential host activity patterns and associated relocation schemes, a copy of the multitude of potential host activity patterns and associated relocation schemes (or parts thereof) is stored in a cache 228 in the RAM 206, which is contained in and / or accessible from the storage controller 122. An initial multitude of potential host activity patterns and associated relocation schemes 128 can be identified and stored in the storage device 120 during a one-time initial configuration of the storage device 120, for example, after the storage device 120 has been manufactured but not yet released for sale. The potential host activity patterns and associated relocation schemes 128, or parts thereof, can be copied to the cache 228 each time the storage device 120 is powered on or reset.As described below, according to certain embodiments or the present technology, additional potential host activity patterns and association relocation schemes can be added after the storage device 120 has been distributed and is used to store host data for a user.

[0052] With renewed reference to Fig. Step 504 includes maintaining one or more activity logs that track operations related to data stored in the non-volatile memory 124 of the storage device 120. Such activity logs may, but are not limited to, write operations to write data to IS memory 132, write operations to write data to MS memory 134, read operations to read data from IS memory 132, and read operations to read data from MS memory 134. With brief reference to Fig. 1. One or more activity logs 126 can be stored in the non-volatile memory 124. As in Fig. As shown in Figure 2, to enable faster and more energy-efficient access to the activity logs 126, a copy of the activity logs 126 (or parts thereof) can be stored in a cache 226 in RAM 206, which is contained in and / or accessible by the memory controller 122. Entries in the activity logs 126 can be specified in the form of logical block addresses (LBAs) and / or LBA ranges, preferably with time information (e.g., a timestamp) indicating when write and read operations are performed. In this way, the relative timing of the write and read operations, including the time intervals between such operations, can be tracked.

[0053] With renewed reference to Fig. Step 506 involves storing data (e.g., host data) in the IS memory (e.g., 132) of the storage device (e.g., 120) in response to receiving one or more write commands from a host (e.g., 102). Any or several different known or future techniques can be used by a memory controller (e.g., 122) to determine when data should be stored in IS memory 132. For example, for certain storage devices 120, data may always be stored in the IS memory 132 of the storage device before being moved to MS memory 134 at a later time according to a relocation scheme. For another storage device 120, the memory controller 122 may determine that in certain cases, data should be written directly to MS memory 134 without first being stored in IS memory 132.Other variations are also possible and fall within the scope of the embodiments described here. According to one embodiment, when data is stored in IS memory 132, the activity log is updated, or more precisely, one or more corresponding entries are added to the activity log. Accordingly, although step 504 precedes step 506 in . Fig. As shown in Figure 5, aspects of step 504 occur simultaneously with or shortly after aspects of step 506. More generally, the activity log can be updated whenever read and write operations occur.

[0054] Continue on Fig. As referred to in section 5, step 508 involves predicting a host activity pattern based on the activity log(s). A predicted host activity pattern can be specified in the form of LBAs and / or LBA ranges, and also in the form of temporal information. A predicted host activity pattern can be a predicted write pattern. Additionally or alternatively, a predicted host activity pattern can be a predicted read pattern. More generally, a predicted host activity pattern can be a predicted pattern of write and / or read operations performed for the host 102, which writes data to and reads data from the storage device 120. Step 508 can be performed by the storage controller 122, or more specifically, by its IS manager 334. It would also be possible for step 508 to be performed by a circuit or other discrete component (e.g., a microcontroller).340) is performed, which is intended for predicting host activity patterns and may also be used to select and / or execute relocation schemes. The activity log(s) 126 may be stored in non-volatile memory 126, and the activity log(s) or parts thereof may be redeemed in the RAM activity log cache 226, as described above.

[0055] Step 508 can be performed by recognizing a repeating pattern from the activity log and predicting that the pattern will continue to repeat. As a first example, an activity log might specify that data is written to a certain range of LBAs, then read 30 times before being deleted, and then this activity is repeated 100 times. The sample contents of such an activity log are shown in Fig. Figure 9 is shown. Based on the activity log, step 508 can predict that this same activity pattern will continue to be repeated. In other words, an initial example of a predicted host activity pattern might be repeatedly writing data to a specific range of LBAs, then reading data from that specific range of LBAs thirty times, and then deleting the data from that specific range of LBAs.

[0056] As a second example, an activity log can specify that: data is written to LBA 0 to LBA 99, then data is read from LBA 3 and LBA 5; and then, after a pause, data is written to LBA 100 to LBA 199, and data is read from LBA 103 and LBA 105; and then, after a pause, data is written to LBA 200 to 299, and then data is read from LBA 203 and LBA 205; and then, after a pause, data is written to LBA 300 to 399, and then data is read from LBA 303 and LBA 305; and then, after a pause, data is written to LBA 400 to 499, and then data is read from LBA 403 and LBA 405; and then, after a pause, data is written to LBA 500 to 599, and then data is read from LBA 503 and LBA 505. The exemplary content of such an activity log is in Fig. Figure 10 illustrates this. Based on the activity log, it can be predicted that the data will next be written to LBA 600 to 699 and then read from LBA 603 and 605. More generally, a second example predicted host activity pattern might be writing to LBAs N*100 to (N*100)+99 and reading data from LBAs (N*100)+3 and (N*100)+5, where N is an integer that is incremented. These are just a few examples and are not intended to be exhaustive.

[0057] Referring back to the flowchart of Fig. Step 510 involves selecting one of the many stored relocation schemes to apply to the data stored in IS storage. The selection in Step 510 is performed based on the host activity pattern predicted in Step 508. Exemplary details on how to select one of the many stored relocation schemes to apply to the data stored in IS storage are described below in Step 508, with reference to the... Fig. 7A and Fig. 7B described.

[0058] Next, in step 512, the selected relocation scheme is executed to selectively relocate (i.e., transfer) one or more portions of the data stored in IS memory (e.g., 132) to MS memory (e.g., 134). Referring again to the first example mentioned above (where the predicted host activity pattern indicated that data would be written to a certain range of LBAs, then read 30 times before being deleted, and then this activity would be repeated 100 times), the relocation scheme selected in step 510 and executed in step 512 can then result in the data that continues to be written, repeatedly read, and then deleted being stored only in IS memory (without ever being relocated to MS memory), and all other data stored in IS memory being relocated to MS memory.

[0059] Reference is now made to the second example, in which the predicted host activity pattern consisted of writing data to LBAs N*100 to (N*100)+99, reading from LBAs (N*100)+3 and (N*100)+5, and then deleting the data. Assuming that the data is always stored first in IS memory (e.g., 132), the relocation scheme selected in step 510 and executed in step 512 can result in the data equivalent to 100 LBAs being held in IS memory for a sufficient amount of time so that the two LBAs (i.e., LBAs (N*100)+3 and (N*100)+5) can be read, and then all 100 LBAs can be relocated to MS memory (e.g., 134). The high-level flowchart of Fig. Figure 11 illustrates some additional details of how such a relocation scheme, after being selected in step 510, can be implemented in step 512 according to one embodiment. With reference to Fig. In step 1102, in response to receiving a write command to store data in LBA N*100 to LBA ((N*100)+99), the LBAs are mapped to physical block addresses (PBAs) corresponding to IS memory 132, and the LTP mapping within the management tables 125 is updated accordingly. As specified in step 1104, the data is retained in IS memory 132 for a sufficient time to allow portions of the data from LBA ((N*100)+3) and LBA ((N*100)+5)) to be read, which are mapped to PBAs in IS memory 132. After the data parts have been read from the LBA ((N*100)+3) and the LBA ((N*100)+5)) and more generally from the IS memory 132, the data is then moved to the MS memory 134 (according to the relocation scheme selected in step 510 based on the predicted host activity pattern), and the LTP mapping within the management tables 125 is updated accordingly.

[0060] An alternative relocation scheme, which can be selected in step 510 and executed in step 512, can result in only the two read LBAs (i.e., LBAs (N*100)+3 and (N*100)+5) being held in IS memory (e.g., 132) for a sufficient amount of time to allow this portion of the data to be read, while the rest of the data is essentially immediately relocated to MS memory (e.g., 134). Then, after the two LBAs (i.e., LBAs (N*100)+3 and (N*100)+5) have been read for IS memory, they are also relocated to MS memory. These are just a few examples and are not intended to be exhaustive.

[0061] The high-level flowchart of Fig. Figure 12 illustrates some additional details of how such an alternative relocation scheme, after being selected in step 510, can be implemented in step 512 according to one embodiment. With reference to Fig. In step 1202, in response to receiving a write command to store data in LBA N*100 to LBA ((N*100)+99), the LBAs are mapped to physical block addresses (PBAs) corresponding to IS memory 132, and the LTP mapping within the management tables 125 is updated accordingly. As specified in step 1204, the data is retained in IS memory 132 for a sufficient time to allow portions of the data from LBA ((N*100)+3) and LBA ((N*100)+5)) to be read, which are mapped to PBAs in IS memory 132.As specified in step 1206, while waiting for the data parts (corresponding to LBA ((N*100)+3) and LBA ((N*100)+5)) to be read from IS memory, other data parts in the range of the LBAs (from LBA N*100 to LBA ((N*100)+99)) are moved from IS memory 132 to MS memory 134 (according to the relocation scheme selected based on the predicted host activity pattern), and the management tables 125 are updated accordingly. Then, after the data parts (corresponding to LBA ((N*100)+3) and LBA ((N*100)+5) have been read from IS memory 132, these data parts are moved from IS memory 132 to MS memory 134 (according to the relocation scheme selected based on the predicted host activity pattern). (host activity pattern selected), and the management tables are updated accordingly to map the LBAs to PBAs in MS memory 134. Whether this is generally true with regard to . Fig. The relocation scheme described in section 11, or the one generally referred to, Fig. The migration scheme described in section 12, which is the one associated with a particular predicted activity pattern of the host (and thus selected in step 510), may depend on the cost function used to generate the migration schemes and the costs (e.g., latency and energy consumption costs) associated with the various operations related to writing and reading data to and from IS memory 132 and MS memory 134, as well as the costs of moving data from IS memory 132 to MS memory 134, but is not limited to these.

[0062] With reference to Fig. 6. According to certain embodiments of the present technology, in step 614 it is determined from time to time (e.g., periodically or due to a periodic or aperiodic trigger event) whether or not a different relocation scheme should be applied to the data stored in the IS. As specified in step 616, in response to the determination that a different relocation scheme should be applied to the data stored in the IS, another relocation scheme is selected from the plurality of stored relocation schemes to be applied to the data stored in the IS. Then, in step 618, the selected other relocation scheme is executed to selectively relocate one or more parts of the data from the IS to the MS according to the selected other relocation scheme.In certain embodiments, step 614 is performed by determining, based on the activity log (to which entries are added when read and write operations are performed), whether the predicted host activity has changed and, if so, whether a different migration scheme should be selected (based on the newly or changed predicted host activity) and then executed. The predicted host activity can change if the host user changes their behavior, for example, by switching from using the host to stream a video to using the host to run a simulation.

[0063] Steps 614, 616 and 618, which refer to Fig. The steps described in section 6 can be carried out according to steps 508, 510 and 512, which refer to Fig. 5 described. According to certain embodiments, steps 614, 616, and 618 can actually be further instances of steps 508, 510, and 512. More precisely, with reference to Fig. 5. After step 512 has been executed, another instance of step 508 can be performed, and if the predicted host activity pattern has changed (i.e., if there is a new predicted host activity pattern), then a different relocation scheme can be selected at another instance of step 510 and executed at another instance of step 512. Such a return to step 508 is represented by the dashed, arrowed line 513. Furthermore, as explained above, the activity log(s) stored in step 504 can be continuously updated as additional write and / or read operations are performed, and the data stored in IS memory in step 506 can continuously change in response to write commands received from the host, as well as based on portions of data stored in IS memory that are relocated to MS memory in cases of step 512.

[0064] Fig. Section 7A is now used to describe additional details of step 510 according to an embodiment of the present technology. More specifically, Fig. Section 7A is used to describe how one of the stored migration schemes can be selected based on a predicted host activity pattern. Referring to Fig. In step 702, the predicted host activity pattern is compared to one of the stored potential host activity patterns to generate a match score indicating the degree of similarity between the predicted host activity pattern and that of the potential host activity patterns. As can be seen from steps 704 and 702, such comparisons are repeated until a match score is determined for each of the stored potential host activity patterns. Then, in step 706, the relocation scheme associated with the potential host activity pattern with the highest match score is selected.

[0065] Fig. Reference 7B is now used to describe additional details of step 510 according to another embodiment of the present technology. With reference to Fig. 7B is in step 702 (which is the same as step 702 in Fig. Step 7A compares the predicted host activity pattern with one of the stored potential host activity patterns to generate a defined match score, indicating the degree of similarity between the predicted host activity pattern and the one of the potential host activity patterns. Next, in step 703, it is determined whether the match score exceeds a match threshold. If the match score exceeds the match threshold, in step 705, the stored relocation scheme associated with the potential host activity pattern with the match score that exceeds the threshold is selected.If the match score does not exceed the match threshold, as can be seen from steps 704 and 702, such comparisons are repeated until one of the potential host activity patterns has a match score that exceeds the match threshold and is selected in step 705, or until all potential host activity patterns have been compared to the predicted host activity pattern, and if none has a match score that exceeds the match threshold, the potential host activity pattern with the highest match score is selected in step 706. In the section with reference to... Fig. In the embodiment described in Section 7B, the relocation scheme is selected that is associated with the first potential host activity pattern identified as having a conformance score exceeding a specified conformance threshold. More generally, according to certain embodiments, a relocation scheme can be selected that is associated with one of the potential host activity patterns identified as having a conformance score exceeding a specified conformance threshold. Alternatively or additionally, the relocation scheme can be selected that is associated with the potential host activity patterns identified as having the highest conformance score. Other variations are also possible while still remaining within the scope of the embodiments described herein. In other words, referring back to Fig. In step 510, the selection of one of the many stored relocation schemes based on the results of the comparisons may involve either selecting the one of the many stored relocation schemes associated with one of the potential host activity patterns with the highest match score, or selecting one of the many stored relocation schemes associated with a stored potential host activity pattern for which the match score exceeds the specified match threshold.

[0066] With reference to Fig. 8. According to certain embodiments of the present technology, one or more additional potential host activity patterns that can be used to write data to and / or read data from the non-volatile memory can be identified from time to time in step 802 based on the activity log, which, as explained above, is continuously updated. Furthermore, Fig. As described above, in step 804, another relocation scheme can be generated for each of the identified additional potential host activity patterns, and in step 806, the additional relocation scheme(s) are saved along with the associated additional potential host activity patterns. After generation and saving, the additional relocation scheme(s) are then available to IS Manager 334 for selection and execution. As above, with reference to the flowchart of Fig.As described in section 5, the initial multitude of potential host activity patterns (and associated relocation schemes) stored in step 502 could have been identified and stored in storage device 120 during a one-time initial configuration, for example, after storage device 120 was manufactured but before it was released for sale. In contrast, steps 802, 804, and 806 are performed after storage device 120 is already being used by a host device 102 to write and read data to and from the non-volatile memory 124 of storage device 120.

[0067] According to certain embodiments, the storage controller 122 or its IS manager 334 may determine that it is expedient to identify additional potential host activity patterns if comparisons between a predicted host activity pattern and the stored potential host activity patterns do not yield match point values ​​exceeding a specified match threshold. This would provide a probable indication that none of the stored relocation schemes is substantially optimized for the data stored in the IS storage. Alternatively or additionally, further potential host activity patterns may be identified periodically or aperiodically in response to another type of trigger.In certain embodiments, another potential host activity pattern may simply be a predicted host activity pattern for which no similar stored potential host activity pattern yet exists (e.g., a predicted host activity pattern for which no match point value has exceeded a specified match threshold). In other embodiments, further potential host activity patterns may be identified more generally based on recurring patterns identified from the stored activity log. In certain embodiments, further potential host activity patterns and further associated relocation schemes are identified and generated by the storage device 120 itself, e.g., by the storage controller 122 or its IS manager 334.In other embodiments, further potential host activity patterns and further relocation schemes associated with them can be uploaded to the stored device 120 during a firmware update or the like.

[0068] The memory controller 122 or its IS manager 334 can generate another migration scheme associated with an identified further potential host activity pattern by optimizing a cost function. An example cost function might attempt to minimize or otherwise account for costs associated with reading data from IS memory, transferring (i.e., moving) data from IS memory to MS memory, and reading data from MS memory, but is not limited to these. The costs might be in the form of latency and / or power consumption, but are not limited to these. This is just one example of a cost function and is not intended to be exhaustive.

[0069] According to certain embodiments of the present technology, the processes performed to achieve adaptive management of the IS storage are executed as background processes. These may include processes used to predict a host activity pattern based on an activity log, to select one of a variety of stored relocation schemes based on the predicted host activity pattern, and to execute the selected relocation scheme. Other processes that may be executed as background processes may include processes used to determine whether or not a different relocation scheme should be applied, as well as the selection and execution of that different relocation scheme.Other processes that can be run as background processes may include processes used to identify further potential host activity patterns and to generate and store further shift schemes associated with those further potential host activity patterns.

[0070] Implementations of the technology described herein should increase read and write throughput for most users and also result in fewer blocks being over-provisioned. This should have a beneficial effect on increasing endurance and reducing power consumption.

[0071] Certain embodiments of the present technology relate to a storage device that receives read and write commands from a host, wherein the storage device includes non-volatile memory and an intermediate storage (IS) manager. The non-volatile memory comprises a portion, one part of which is referred to as intermediate storage (IS) and another part as main storage (MS), wherein the IS storage has lower read and write latencies than the MS storage, the IS storage has greater endurance than the MS storage, and the IS storage has lower storage density and capacity than the MS storage.The IS manager is configured to predict host activity and select and execute a relocation scheme based on the predicted host activity, thereby selectively relocating one or more portions of data from the IS memory to the MS memory according to the selected relocation scheme. In certain embodiments, the IS memory includes single-level cell (SLC) flash memory, storing a single data bit per memory cell, and the MS memory includes multi-level cell (MLC) flash memory, storing two or more data bits per memory cell.

[0072] The storage device may include a memory controller communicating with the non-volatile memory. The memory controller is configured to determine whether data stored in the non-volatile memory in response to write commands received from the host should be written to the information storage (IS) or the main storage (MS) memory. The IS manager may be implemented by the memory controller. Alternatively, the IS controller may be implemented by another component of the storage device communicating with the memory controller.

[0073] The storage device may also include random-access memory (RAM) with which the IS manager and / or the storage controller communicate. According to certain embodiments, an activity log that tracks the write and read operations performed on the host is stored in at least one of the RAM or non-volatile memory locations, and the IS manager is configured to predict host activity based on the activity log. The predicted host activity that the IS manager forecasts based on the activity log may include a predicted write pattern, a predicted read pattern, and / or a predicted write / read pattern.

[0074] In certain embodiments, a plurality of relocation schemes are stored in the non-volatile memory, ROM, and / or RAM of the storage device, each of which is associated with one of a plurality of potential host activity patterns. In such embodiments, the IS manager can be configured to select one of the plurality of relocation schemes based on the results of comparisons between the predicted host activity pattern and at least some of the plurality of potential host activity patterns. The potential and predicted host activity patterns are specified in certain embodiments in the form of logical block addresses (LBAs) or LBA ranges.

[0075] According to certain embodiments, the IS manager is configured to update the predicted host activity pattern from time to time and select and execute a different migration scheme based on the updated predicted host activity.

[0076] In certain embodiments, the IS manager is configured to identify and store further potential host activity patterns based on the activity log, and to generate and store further relocation schemes, each of which is associated with one of the identified further potential host activity patterns. Such further relocation schemes are available to the IS manager for selection and execution after they have been generated and stored.

[0077] Certain embodiments of the present technology relate to methods for use by a storage device that receives read and write commands from a host and includes non-volatile memory and a memory controller communicating with the non-volatile memory, wherein the non-volatile memory comprises a portion referred to as IS memory and another portion referred to as MS memory. As explained above, the IS memory has lower write and read latency, higher endurance, and lower storage density and capacity than the MS memory. According to certain embodiments, such a method involves storing a plurality of relocation schemes, each associated with one of a plurality of potential host activity patterns, and maintaining one or more activity logs that track operations related to the data stored in the non-volatile memory.The procedure also includes storing data in IS storage in response to receiving one or more write commands from a host. The procedure further includes predicting a host activity pattern based on the activity log(s) and selecting one of the many stored relocation schemes to apply to the data stored in IS storage. This selection is made based on the predicted host activity pattern. The procedure further includes executing the selected relocation scheme to selectively move one or more portions of the data from IS storage to MS storage according to the selected relocation scheme.

[0078] According to certain embodiments, the activity log(s) maintained to track the write and read operations performed on the host, and the predicted host activity predicted based on the activity log, include at least one predicted write pattern, one predicted read pattern, or a predicted write and read pattern. Selecting one of the multitude of stored relocation schemes to apply to the data stored in the IS storage may involve comparing the predicted host activity pattern with at least some of the multitude of potential host activity patterns, each associated with one of the relocation schemes, and selecting one of the multitude of stored relocation schemes based on the results of the comparisons.

[0079] According to certain embodiments, comparing the predicted host activity pattern with at least some of the multitude of stored potential host activity patterns involves, for each comparison, generating a match score that indicates a degree of similarity between the predicted host activity pattern and one of the potential host activity patterns. In such embodiments, selecting one of the multitude of stored relocation schemes based on the results of the comparisons can either involve selecting the one of the multitude of stored relocation schemes associated with the potential host activity pattern with the highest match score, or selecting a stored relocation scheme that corresponds to one of the potential host activity patterns (e.g.,include those assigned to a first) for which the agreement point value exceeds a specified agreement threshold.

[0080] According to certain embodiments, the method also includes determining whether or not a different relocation scheme should be applied to the data stored in IS memory. In response to the determination that a different relocation scheme should be applied to the data stored in IS memory, a different relocation scheme is selected from the multitude of stored relocation schemes to be applied to the data stored in IS memory, the selection being based on a new predicted write pattern. The selected relocation scheme is then executed to selectively relocate one or more portions of the data from IS memory to MS memory according to the selected relocation scheme.

[0081] According to certain embodiments, the method also includes identifying, based on the activity log, one or more additional potential host activity patterns and generating and storing one or more additional displacement schemes, each of which is associated with one of the identified additional potential host activity patterns. The additional displacement scheme(s) are available for selection and execution after generation and storage.

[0082] According to certain embodiments, a storage device includes non-volatile memory, part of which is designated as IS memory and another part as MS memory. The IS memory has lower write and read latencies than the MS memory, the IS memory has higher endurance than the MS memory, and the IS memory has lower storage density and capacity than the MS memory. The storage device also includes means for predicting a host activity pattern based on write and read operations performed on a host, means for selecting one of the many potential relocation schemes based on the predicted host activity pattern, and means for executing the selection of one of the many potential relocation schemes to selectively relocate at least some of the data stored in the IS memory to the MS memory.The means for predicting the host activity pattern can be the IS manager 334 and / or the memory controller 122 and / or another discrete component 340. The means for selecting one of the many potential relocation schemes based on the predicted host activity pattern can be the IS manager 334 and / or the memory controller 122 and / or another discrete component 340. The means for executing the selection of one of the many potential relocation schemes can be the IS manager 334 and / or the memory controller 122 and / or another discrete component 340. Each of the means described above can take the form of a bundled functional hardware unit (e.g., an electrical circuit) intended for use with other components, program code (e.g.,Software or firmware) executable by a (micro)processor or processing circuit that typically performs a specific function among related functions, or a standalone hardware or software component that interacts with a larger system. For example, each module may include an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a circuit, a digital logic circuit, an analog circuit, a combination of discrete circuits, gates, or any other type of hardware or combination thereof. Alternatively or additionally, each means may include software stored in a processor-readable device (e.g., memory) for programming a processor to perform the functions described herein.

[0083] According to certain embodiments, the storage device also includes means for tracking write or read operations performed on behalf of the host. The means for tracking write or read operations can be an activity log. Such an activity log can be stored in non-volatile memory 124 and / or RAM 206. In such embodiments, the means for predicting the host activity pattern can predict the host activity pattern using the means for tracking write and read operations performed on behalf of the host.Furthermore, the means of predicting the host activity pattern can be configured to update the predicted host activity pattern in response to the means of selecting one of the multitude of potential relocation schemes choosing another from the multitude of potential relocation schemes, and in response to the means of executing executing the selected other from the multitude of potential relocation schemes.

[0084] According to certain embodiments, the storage device includes means for identifying another potential host activity pattern and means for generating another relocation scheme for the other potential host activity patterns. Once generated, the further relocation scheme is available for selection by the selection means and for execution by the execution means. The means for identifying another potential host activity pattern can be the IS manager 334 and / or the memory controller 122 and / or another discrete component 340. The means for generating the further relocation scheme can be the IS manager 334 and / or the memory controller 122 and / or another discrete component 340. Each of the means described above can take the form of a bundled functional hardware unit (e.g.,an electrical circuit) intended for use with other components, program code (e.g., software or firmware) executable by a (micro)processor or processing circuit that typically performs a specific function or related functions, or a standalone hardware or software component that interacts with a larger system. For example, each module may include an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a circuit, a digital logic circuit, an analog circuit, a combination of discrete circuits, gates, or any other type of hardware or combination thereof. Alternatively or additionally, each means may include software embedded in a processor-readable device (e.g., a microcontroller, a microcontroller, or a microcontroller).stored in a memory) in order to program a processor to perform the functions described herein.

[0085] For the purposes of this document, the terms "write" and "save" are often used interchangeably, as are the terms "write" and "save".

[0086] For the purposes of this document, reference in the description to “one embodiment”, “one (single) embodiment”, “some embodiments” or “another embodiment” can be used to describe different embodiments or the same embodiment.

[0087] For the purposes of this document, a connection can be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when an element is described as connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via intermediary elements. When an element is described as directly connected to another element, there are no intermediate elements between the element and the other element. Two devices are "in communication" when they are connected, directly or indirectly, to enable the transmission of electronic signals to each other.

[0088] For the purposes of this document, the terms “based on” and “depending on” can be interpreted as “at least partially based on”.

[0089] Although various embodiments of the present technology have been described above, they should be considered as examples and not as limitations. It will be apparent to the person skilled in the art that various modifications in form and detail are possible without departing from the spirit and scope of the technology. Although some variations have already been described in detail, other modifications or additions are possible, for example. In particular, further features and / or variations may be provided in addition to those set forth herein. For example, the implementations described above may be directed to various combinations and partial combinations of the disclosed features and / or combinations and partial combinations of several further features disclosed above.Furthermore, the logical sequence depicted in the accompanying figures and / or described herein does not require the specific sequence shown to achieve the desired results. Other embodiments may fall within the scope of the following claims.

[0090] Embodiments of the present technology have been described above with the aid of functional blocks that illustrate the performance of certain functions and their relationships. The limits of these functional blocks have often been defined herein for the sake of simplicity. Alternative limits may be defined as long as the specified functions and relationships are performed accordingly. Each of these alternative limits is thus within the scope and spirit of the claimed technology. A person skilled in the art will recognize that these functional blocks can be implemented by discrete components, application-specific integrated circuits, processors, suitable software, and the like, or any combination thereof.

Claims

[1] Storage device (120) that receives read and write commands from a host (102), the storage device (120) comprising: a non-volatile memory (124), part of which is called intermediate storage (IS) memory and another part is called main storage (MS) memory, wherein the IS memory (132) has lower write and read latencies, greater endurance and lower storage density and capacity than the MS memory (134); and an intermediate storage (IS) manager (334) that is configured to predict host activity and to select and execute a relocation scheme based on the predicted host activity in order to selectively relocate one or more parts of data from the IS storage (132) to the MS storage (134) according to the selected relocation scheme; where the IS Manager (334) is configured to: to update the predicted host activity from time to time and to select and execute another migration scheme based on the updated predicted host activity; and to identify and store further potential host activity patterns (128) based on at least one activity log (126) and to generate and store further relocation schemes, each of which is associated with one of the identified further potential host activity patterns; the further relocation schemes are available for selection and execution by the IS Manager (334) after generation and storage. [2] Storage device according to claim 1, wherein: the storage device includes a storage controller (122) in communication with the non-volatile memory (124); the memory controller (122) is configured to determine whether data stored in the non-volatile memory (124) in response to write commands received from the host should be stored in the IS memory (132) or the MS memory (134); and the IS manager (334) is implemented by the memory controller (123) or by another component of the storage device that communicates with the memory controller. [3] Storage device according to one of claims 1 or 2, wherein: the storage device also has a direct access memory (RAM); an activity log (226) that records the write and Read operations are tracked and stored in at least one of the RAM or non-volatile memory locations; the IS Manager (334) is set up to predict host activity based on the activity log (226); and the predicted host activity that the IS Manager (334) predicts based on the activity log (226) has at least one of a predicted write pattern, a predicted read pattern, or a predicted write and read pattern. [4] Storage device according to one of claims 1, 2 or 3, wherein: the IS memory (132) has a flash memory of the SLC (Single-Level Cell) type, in which a single data bit is stored per memory cell; and the MS memory (134) has a flash memory of the MLC (Multi-Level Cell) type, with two or more data bits stored per memory cell. [5] Method for use by a storage device (120) which receives read and write commands from a host (102) and which includes a non-volatile memory (124) and a memory controller (122) in communication with the non-volatile memory, wherein the non-volatile memory includes a portion referred to as intermediate storage (IS) memory and another portion designated as main storage (MS) memory, wherein the IS memory (132) has lower write and read latencies, higher endurance, and lower storage density and capacity than the MS memory (134), the method comprising: Store (502) a variety of relocation schemes, each of which is associated with one of a variety of potential host activity patterns (128); Maintain (504) one or more activity logs (126) which track the operations related to the data stored in non-volatile memory for a host; Storing (506) data in IS memory (132) in response to receiving one or more write commands from the host; Predictions (508) of a host activity pattern based on at least one of one or more activity logs (126); Selecting (510) one of the many stored relocation schemes to apply to the data stored in IS storage (132), the selection being performed based on the predicted host activity pattern; and Execute (512) the selected relocation scheme to create one or to selectively move several parts of the data from the IS memory (132) to the MS memory (134) according to the selected relocation scheme. [6] Method according to claim 5, wherein: the one or more activity logs (126) track at least one of the write or read operations performed on the host (102); and the predicted host activity, which is predicted based on at least one of one or more activity logs (126), exhibits at least one of a predicted write pattern, a predicted read pattern, or a predicted write and read pattern. [7] Method according to one of claims 5 or 6, wherein the selection (510) of one of the plurality of stored relocation schemes for application to the data stored in the IS memory (132) comprises the following: Comparing the predicted host activity pattern with at least some of the multitude of potential host activity patterns (128), each associated with one of the relocation schemes; and Selecting one of the many stored relocation schemes based on the results of the comparisons. [8] Method according to claim 7, wherein: comparing (702) the predicted host activity pattern with at least some of the multitude of stored potential host activity patterns (128) involves, for each of the comparisons, generating a match point value that indicates a degree of similarity between the predicted host activity pattern and one of the potential host activity patterns (128); and The selection of one of the many stored relocation schemes, based on the results of the comparisons, involves either selecting (706) the one of the many stored relocation schemes that is associated with one of the many potential host activity patterns (128) with the highest matching point value, or selecting (705) one of the many stored relocation schemes that is associated with one of the many potential host activity patterns (128) for which the matching point value exceeds a specified matching threshold. [9] Method according to one of claims 6, 7 or 8, further comprising: Determine (614) whether or not to apply another of the stored relocation schemes to the data stored in the IS memory (132); in response to determining (616) that another of the stored shift schemes should be applied to the data stored in IS memory (132), selecting another from the plurality of stored shift schemes to apply to the data stored in IS memory (132), the selection being based on a new predicted write pattern; and Execute (618) the selected other of the relocation schemes to selectively relocate one or more parts of the data from the IS memory (132) to the MS memory (134) according to the selected other of the relocation schemes. [10] Method according to one of claims 6, 7, 8 or 9, further comprising: Identify (802) further potential host activity patterns (128) based on the one or more activity logs (126) and generate (804) and store (806) further relocation schemes, each of which is associated with one of the identified further potential host activity patterns (128); the further relocation schemes are available for selection and execution after generation and storage; and where the potential and predicted host activity patterns are defined in the form of logical block addresses (LBAs) or LBA ranges.

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