INTEGRATED CHIP AND INTEGRATED CIRCUIT WITH TRANSISTORLESS MEMORY CELL AND METHOD FOR THE PRODUCTION THEREOF

Abstract

Integrated chip, comprising: an operative magnetic tunnel junction (MTJ) device coupled to a bit line, the operative MTJ device configured to store a data state; and a regulating access device coupled between the MTJ device and a first word line, the regulating access device comprising one or more regulating MTJ devices configured to control a current provided to the operative MTJ device, wherein the regulating access device comprises: a first regulatory MTJ device coupled between the first word line and the operative MTJ device; and a second regulatory MTJ device coupled between a second word line and the operational MTJ device, wherein the first word line and the second word line are coupled to a word line decoder.

Description

GENERAL STATE OF THE ARTMany modern electronic devices include electronic memory configured to store data. Electronic memories may be volatile memories or non-volatile memories. Volatile memories store data when turned on, while nonvolatile memories are capable of storing data when hanged. Magneto-resistive RAM (MRAM) is a promising candidate for next generation non-volatile memory technology.The prior art relating to the subject matter of the invention can be found, for example, in the publications DE 602 03 302 T2, U.S. Pat. No. 2018 / 0 248 553 A1, U.S. Pat. No. 2017 / 0 148 903 A1, U.S. Pat. No. 2014 / 0 334 216 A1, DE 10 2015 221 521 A1 and DE 10 2005 053 717 A1.The object is to improve corresponding memories.The object is achieved by the integrated cip according to claim 1, the integrated circuit according to claim 9 and the method according to claim 13.BRIEF DESCRIPTION OF THE DRAWINGSThe aspects of the present disclosure will be best understood from the following detailed description when read with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. The dimensions of the various features may be arbitrarily increased or decreased effectively for understanding the discussion. FIG. 1 illustrates a schematic diagram of some embodiments of a memory circuit with a regulating access device configured to provide access to an operative magnetic tunnel junction (MTJ= Magnet) device. FIG. 2 illustrates a schematic diagram of some additional embodiments of a memory circuit with a regulating access device, including regulating MTJ devices configured to selectively provide access to an operative MTJ device.FIGS. 3A-3C illustrate schematic diagrams of some embodiments of read and write operations of the disclosed memory circuit of FIG. 2.FIGS. 4A-4B illustrate some embodiments of cross-sectional views of a built-in chip corresponding to the disclosed memory circuit of FIG. 2.FIGS. 5A-5B illustrate some additional embodiments of a memory circuit with a regulating access device configured to selectively provide access to an operative MTJ device.FIGS. 6A-6B illustrate some additional embodiments of a memory circuit with a regulating access device configured to selectively provide access to an operative MTJ device.FIGS. 7A-7B illustrate some additional embodiments of a memory circuit with a regulating access device configured to selectively provide access to an operative MTJ device.FIGS. 8A-8B illustrate some additional embodiments of a memory circuit with a regulating access device configured to selectively provide access to an operative MTJ device.FIGS. 9-12 illustrate some embodiments of a method of forming a built-in chip with a memory circuit having memory cells, including a regulating access device configured to selectively provide access to an operative MTJ device. FIG. 13 illustrates a flow diagram of some embodiments of a method of forming a built-in chip with a memory circuit having memory cells including a regulating access device configured to selectively provide access to an operative MTJ device.DETAILED DESCRIPTIONThe following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. To simplify the present disclosure, specific examples of components and arrangements will be described below. For example, formation of a first feature over or on a second feature in the description below may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for purposes of simplicity and clarity and does not in itself impose any relationship between the various embodiments and / or configurations discussed.Further, spatial reference terms such as "below," "below," "lower," "above," "upper," and the like may be used herein to facilitate the description to describe the description of an element or feature with respect to (a) other element(s) or feature(s) as depicted in the figures. The spatial reference terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial references used herein interpreted accordingly in a similar manner.Magneto-resistive RAM (MRAM) cells include a magnetic tunnel junction (MTJ) vertically disposed between conductive electrodes. The MTJs include a pinned layer separated from a free layer by a tunnel barrier layer. The magnetic orientation of the attached layer is static (i.e., fixed), while the magnetic orientation of the free layer is capable of switching between a parallel configuration and an anti-parallel configuration with respect to that of the attached layer. The parallel configuration provides a low resistance state that digitally stores data as a first bit value (e.g., a logic "1"). The anti-parallel configuration provides a high resistance state that digitally stores data as a second bit value (e.g., a logic "o").As the functionality of built-in chips increases, the need for more memory also increases, causing designers and manufacturers of built-in chips to increase the amount of memory available while decreasing the size and power consumption of a built-in chip. To achieve this goal, the size of memory cell components has been apparently reduced over the past decades. One of the advantages of MTJ devices over other memory types is that the MTJ of an MTJ device can be fabricated to be very small. However, in MRAM cells, a drive transistor (i.e., an access transistor) is used to selectively provide a voltage and / or current to an associated MTJ device during read and / or write operations. Since MRAM cells generally use a relatively high(s) voltage and / or current for write operations, the size of the drive transistors may be relatively large. While an MTJ of an MRAM cell may be created to have a small size, the relatively large size of the drive transistor limits the manner in which small MRAM cells within a memory array can be scaled down.The present disclosure relates, in some embodiments, to a built-in chip comprising a memory array having multiple memory cells (e.g., MRAM cells) that do not include drive transistors (i.e., that do not use drive transistors to provide a voltage and / or current to a memory cell). Instead, the plurality of memory cells each include a regulating access device configured to selectively provide access to operative MTJ devices within the memory array. The regulatory access device includes one or more regulatory MTJ device(s) coupled to an operative MTJ device. This one or more MTJ device(s) is / are configured to selectively provide access to the operative MTJ device by controlling (i.e., regulating) a current provided to the operative MTJ device. By using the regulating access device to selectively provide access to operative MTJ devices within a memory array, a size of memory cells (e.g., MRAM cells) within the memory array can be reduced because the size no longer depends on a drive transistor.FIG. 1 illustrates a schematic diagram of some embodiments of a memory circuit 100 having a regulating access device configured to selectively provide access to an operative MTJ device.The memory circuit 100 comprises a memory array 102 having a plurality of memory cells 104 a,1-104b,2. The plurality of memory cells 104 a,1-104b,2 are arranged within the memory array 102 in rows and / or columns. For example, a first row includes memory cells 104 a, 1 and 104 a, 2, while a first column includes memory cells 104 a, 1 and 104 b, 1. In some embodiments, the plurality of memory cells 104 may comprise a plurality of MRAM cells in a,1-104b,2 fashion.The plurality of memory cells 10, 4 a,1-104b,2( e.g., MRAM cells) each include an operative MTJ device 106 coupled to a regulating access device 108. The surgical MTJ device 106 includes a magnetic tunnel junction (MTJ) with an attached layer 110a separated from a free layer 114a by a tunnel dielectric barrier 112a. The pinned layer 110a has a magnetization that is fixed, while the free layer 114a has a magnetization that can be either parallel (i.e., a "P" state) or anti-parallel (i.e., an "AP" state) with respect to the magnetization of the pinned layer 110a during operation (by the tunneling magneto-resistance effect (TMR)). A relationship between the magnetizations of the pinned layer 100 aand the free layer 114 adefines a resistance state of the MTJ, thereby allowing the plurality of memory cells 104 a,1-104 b b,2 to each store a data state having a value based on a resistance of the operational MTJ device 106 within a memory cell. For example, a first memory cell 104 a,1 will store either a first bit value (e.g., a logic "0") when a first operational MTJ device 106 a,1 has a low resistance state or a second bit value (e.g., a logic "1") when the first operational MTJ device 106 a,1 has a high resistance state.The regulatory access device 108 each has a high resistance by which a current provided to an associated operative MTJ device 106 can be controlled. For example, a first regulating access device 108 a,1 is configured to control a stream provided to a first operative MTJ device 106 a,1 a second regulating access device 108 b,1 is configured to control a stream provided to a second operative MTJ device 106 b,1 etc. The regulatory access device 108 is configured to selectively provide access to one or more operational MTJ device(s) 106 within the memory array 102 by controlling a current provided to the operational MTJ devices 106.In some embodiments, regulatory access device 108 may include one or more regulatory MTJ device(s) 109, each including an MTJ having an attached layer 1106 separated from a free layer 114 bby a tunnel dielectric barrier 112 b. For example, in some embodiments, the regulatory access device 108 may include a first regulatory MTJ device and a second regulatory MTJ device 206 coupled in parallel to an associated operational MTJ device 106. In some embodiments, the first regulating MTJ device, the second regulating MTJ device, and the operative MTJ device 106 each include an MTJ with a pinned layer separated from a free layer by a tunnel dielectric barrier. In some embodiments, the attached layer 110 may include cobalt (Co), iron (Fe), boron (B), nickel (Ni), ruthenium (Ru), iridium (Ir), platinum (Pt), or the like. In some embodiments, the tunnel dielectric barrier may include magnesium oxide (MgO), aluminum oxide (Al 2 O 3) or the like. In some embodiments, the free layer may comprise cobalt (Co), iron (Fe), boron (B), or the like.In some embodiments, the regulatory access device 108 may include one or more resistors (e.g., thin film resistors including tantalum nitride, tantalum, titanium nitride, titanium, tungsten, or the like). In some embodiments, for example, the regulatory access device 108 may include a first thin sheet resistor and a second thin sheet resistor coupled in parallel to the surgical MTJ device 106. In various embodiments, the regulatory access device 108 may include resistors having substantially similar sizes or different sizes.The memory array 102 is coupled to control the control circuit 115 by means of a plurality of bit lines BL 1- BL 2 and a plurality of word lines WL 1- WL 2. In some embodiments, the control circuit 115 includes a bit line decoder 116 coupled to the plurality of bit lines BL 1- BL 2 and a word line decoder 118 coupled to the plurality of word lines WL 1- WL 2. The regulatory access device 108 is coupled between a word line WL x( x=1 or 2) and an operative MTJ device 106, while the operative MTJ device 106 is coupled between the regulatory access device 108 and a bit line BL y( y=1 or 2).To access an operational MTJ device 106, the bit line decoder 116 is configured to selectively provide signals (e.g., current voltages) to one or more bit lines BL 1- BL 2 based on an address S ADDR1 received from a controller 120, while the word line decoder 118 is configured to selectively provide one or more word line(s) WL 1- WL 2 based on an address S ADDR2, received from the controller 120. The regulatory access device 108 is configured to regulate a current provided by the signals to an associated operational MTJ device 106, thereby selectively providing access to an associated operational MTJ device 106. For example, during a write operation within the memory array 102, the regulatory access device 108 may provide a current to an operational MTJ device within a selected memory cell that is greater than or equal to a minimum switching current (i.e., a current sufficient to change a data state of a memory cell) while providing a current that is less than the minimum switching current to operate MTJ devices within unselected memory cells.Using the regulating access device 108 to selectively provide access to an operative MTJ device 106 provides memory cells without a drive transistor. The presence of memory cells without a drive transistor allows a size of the memory array 102 to be reduced, thereby improving performance and reducing the cost of the memory circuit 100.FIG. 2 illustrates a schematic diagram of some additional embodiments of a memory circuit 200 with a regulating access device, including regulating MTJ devices configured to selectively provide access to an operative MTJ device.The memory circuit 200 includes a memory array 102 having a plurality of memory cells 202 a,1-202b,2. ( e.g., MRAM cells) arranged in rows and columns. The plurality of memory cells 202 a,1-202c,3 each include an operational MTJ device 106 configured to store data and a regulating access device 108 configured to selectively provide access to the operational MTJ device 106 by regulating a current provided to the operational MTJ device 106.In some embodiments, the regulatory access device 108 may include a first regulatory MTJ device 204 and a second regulatory MTJ device 206 coupled to the same layer of the MTJ device 106. For example, the first regulating MTJ device 204 and the second regulating MTJ device 206 may both be coupled to a secured layer 110 of the operative MTJ device 106. In some embodiments, the first regulating MTJ device 204 is coupled between the operative MTJ device 106 and a first word line WL x( x=1,3,5) and the second regulating MTJ device 206 is coupled between the operative MTJ device 106 and a second word line WL y( y=2,4,6). For example, in a first memory cell 202 a,1 a first MTJ device 204 is coupled between an operative MTJ device 106 and a word line WL 1, while a second regulating MTJ device 206 is coupled between the operative MTJ device 106 and a word line WL 2.The first regulating MTJ device 204, the second regulating MTJ device 206, and the operative MTJ device 106 each include an MTJ with an attached layer 110 separated from a free layer 114 by a tunnel dielectric barrier 112. In some embodiments, the attached layer 110 may include cobalt (Co), iron (Fe), boron (B), nickel (Ni), ruthenium (Ru), iridium (Ir), platinum (Pt), or the like. In some embodiments, the tunnel dielectric barrier 112 may include magnesium oxide (MgO), aluminum oxide (Al 2 O 3) or the like. In some embodiments, the free layer 114 may include cobalt (Co), iron (Fe), boron (B), or the like.During operation, a word line decoder 118 is configured to selectively apply signals to one or more word line(s) WL 1- WL 6 coupled to the memory array 102, and a bit line decoder 116 is configured to selectively apply signals to one or more bit line(s) BL 1- BL 3 coupled to the memory array 102. By selectively applying signals to the one or more word line(s) WL 1- WL 6 and the one or more bit line(s) BL 1- BL 3 different ones of the plurality of MTJ operational devices 106 can be selectively accessed in mutually exclusive fashion.For example, FIGS. 3A-3B illustrate schematic diagrams 300 and 302 of some embodiments of a write operation of the memory circuit 200 of FIG. 2. The write operation shown in schematic diagrams 300 and 302 is a non-limiting example of a method of performing a write operation. In other embodiments, other write operation performance methods may be used alternately.The write operation illustrated in FIGS. 3A-3B writes a first data state to one or more memory cell(s) in a row of a memory array during a first operation (shown in FIG. 3A ) and then writes a second data state to one or more cell(s) in the row of the memory array during a second, subsequent operation (shown in FIG. 3B ), such that a 2-step process is used to write data to a full row of a memory array 102. Thus, it is understood that the current provided by the MTJ must be stronger than a switching current (i.e., critical switching current) to write data to an MTJ device. Currents no greater than the switching current will not cause switching between resistance states and therefore will not write data to the MTJ devices within the memory array 102. In some embodiments, the disclosed write operation may be performed with the regulating MTJ devices (e.g., 204- 206 in FIG. 2 ) in a high resistance state such that isolation is provided between selected and unselected cells.As shown in the schematic diagram 300 of FIG. 3A, the first operation of the write operation is performed by writing a first data state to the operational MTJ devices within a first memory cell 202 a,1 and a third memory cell 202 a,3 in a first row 301 of the memory array 102. The first operation of the write operation is performed by applying a first non-zero bias voltage V 1( e.g., 2V) to word lines WL 1 and WL 2, a second non-zero bias voltage V 2( e.g., 6V) to word line WL 3, a third non-zero bias voltage V 3( e.g., 8V) to bit lines BL 1 and BL 3 and a fourth non-zero bias voltage V 4( e.g., 4V) to bit line BL 2. A difference between the first non-zero bias voltage V 1( e.g., 2V) and the third non-zero bias voltage V 3( e.g., 8V) causes a first current I 1 to flow through the regulating MTJ devices within the first memory cell 202 a,1 and the third memory cell 202 a,3. The first current I 1 is weaker than the switching current I SW, so that the status of the regulating MTJ devices within the first memory cell 202 a,1 and the third memory cell 202 a,3 does not change. However, the current from the regulating MTJ devices is added so that a current twice as strong as the first current I 1, flows through the operational MTJ devices within the first memory cell 202 a,1 and the third memory cell 202 a,3. The current twice as high as the first current I 1, is higher than the switching current I SW, so that a first data state is written to the operational MTJ devices within the first memory cell 202 a,1 and the third memory cell 202 a,3.An operational MTJ device within the second memory array 202 a,2 is not affected by the first operation of the write operation, as a difference between the first non-zero bias voltage V 1( e.g., 2V) and the fourth non-zero bias voltage V 4( e.g., 4V) causes a second current I 2 to flow through the regulating MTJ devices within the second memory cell 202 a,2. However, twice the second current I 2 is weaker than the switching current I SW, so that a data state is not written to an operational MTJ device within the second memory cell 202 a,2. Similarly, MTJ devices coupled to word lines WL 3 and WL 4 are also unaffected by the first act of the write operation.As shown in the schematic diagram 302 of FIG. 3B, the second operation of the write operation is performed by writing a second data state to the operational MTJ device within a second memory cell 202 a,2 in the first row 301 of the memory array 102. The second operation of the write operation is performed by applying a first non-zero bias voltage V 1( e.g., 6 V) to the word lines WL 1 and WL 2, a second non-zero bias voltage V 2( e.g., 2 V) to the bit lines BL 1 and BL 3 and a third non-zero bias voltage V 3( e.g., 0 V) to the bit line BL 2. A difference between the first non-zero bias voltage V 1( e.g., 6 V) and the third non-zero bias voltage V 3( e.g., 0 V) causes a first current I 1 to flow through the regulating MTJ devices within the second memory cell 202 a,2. The first current I 1 is weaker than the switching current I SW, so that the states of the regulating MTJ devices within the second memory cell 202 a,2 do not change. However, twice the first current I 1( which flows through the operational MTJ device within the second memory cell 202 a,2 ) is greater than the switching current I SW, so that the second data state is caused to be written to an operational MTJ device within the second memory cell 202 a,2.Operational MTJ devices within the first memory cell 202 a,1 and the third memory cell 202 a,3 are not affected by the second operation of the write operation because a difference between the first non-zero bias voltage V 1( e.g., 6 V) and the second non-zero bias voltage V 2( e.g., 2 V) causes a second current I 2, which is weaker than the switching current, to flow through regulating MTJ devices within the first memory cell 202 a,1 and the third memory cell 202 a,3. However, the second current I 2 is twice as weak as the switching current I SW, so that a data state is not written to the operational MTJ devices within the first memory cell 202 a,1 and the third memory cell 202 a,3.FIG. 3C illustrates some embodiments of a schematic diagram 304 illustrating a read operation reading a data state from an operational MTJ device.As shown in schematic diagram 304, a read operation is performed on a first operational MTJ device within first memory cell 202 a,1 by applying a first non-zero bias voltage V 1( e.g., 2 V) to word line WL 1. The first non-zero bias voltage, V1, will cause a read current I R to pass through the first operational MTJ device within the first memory cell 202 a,1. The read current I R, which passes through the first operational MTJ device, has a value that depends on a resistance state of the first operational MTJ device. For example, if the first operational MTJ device is in a low resistance state (e.g., storing a logic "0"), the read current I R will be greater than if the first operational MTJ device is in a high resistance state (e.g., storing a logic "1").In some embodiments, the bit line decoder 116 may include a multiplexer configured to determine a desired output of the memory array 102. The multiplexer is configured to selectively provide the read current I R from the first operational MTJ device within the first memory cell 202 a,1 to a sense amplifier 306 configured to compare the current I R with a reference current I REF generated by a source current 308 to determine a data state stored in the first operational MTJ device within the first memory cell 202 a,1.FIG. 4A illustrates a cross-sectional view of some embodiments of a built-in chip 400 corresponding to the memory array 102 of FIG. 2.The built-in chip 400 includes a dielectric structure 404 disposed over a substrate 402. The dielectric structure 404 surrounds a first memory cell 202 a,1 and a second memory cell 202 b,1, which is positioned laterally adjacent to the first memory cell 202 a,1. The dielectric structure 404 further surrounds a plurality of conductive interconnect layers 406a-406c. In some embodiments, the dielectric structure 404 may include multiple stacked ILD layers. In various embodiments, the plurality of stacked ILD layers may include one or more of silicon oxide, fluorine doped silicon oxide, carbon doped silicon oxide, or the like. In various embodiments, multiple conductive interconnect layers 406 a- 406 cmay include copper, aluminum, tungsten, carbon nanotubes, or the like.The first memory cell 202 a,1 and the second memory cell 202 b,1 each include a regulating access device 108 and an operative MTJ device 106. The regulatory access device 108 is coupled to a first interconnect layer 406a defining a plurality of word lines WL 1- WL 4. Two of the plurality of word lines WL 1- WL 4 are coupled to respective memory cells within a row of the memory array 102 of FIG. 2. For example, word lines WL 1- WL 2 may be coupled to first memory cell 202 a,1 in a first row, and word lines WL 3- WL 4 may be coupled in second memory cell 202 b,1 in a second row. In some embodiments, the plurality of word lines WL 1- WL 4 may be separated from the substrate 402 by a non-zero distance d. A second interconnect layer 406b is disposed between the regulating access device 108 and the operative MTJ device 106. The operational MTJ device 106 is further coupled to a third interconnect layer 406c that defines a bit line BL 1 coupled to the operational MTJ device 106 within the memory cells that is disposed within a column of the memory array 102. For example, bit line BL 1 is coupled to an operative MTJ device 106 within a column of memory array 102 of FIG. 2.In some embodiments, the operative MTJ device 106 is coupled between a bit line BL z( z=1.2) and a word line WL x( x=1.3) by a continuous conductive path that includes a plurality of conductive interconnect layers 406 a- 406 cand that does not extend through the substrate 402. In some embodiments, the MTJ device 106 is not directly over an access transistor device configured to control access to the operative MTJ device 106.In some embodiments, the regulatory access device 108 includes a first regulatory MTJ device 204 and a second regulatory MTJ device 206. The first regulating MTJ device 204, the second regulating MTJ device 206, and the operative MTJ device 106 each include an MTJ vertically disposed between a bottom electrode via 408 and a top electrode via 410. In some embodiments, the top electrode via 410 may be coupled to a overlying interconnect layer via a via 412 (e.g., a copper via). In some embodiments, the bottom electrode via 408 and the top electrode via 410 may comprise a metal, such as titanium nitride (TiN), tantalum nitride (TaN), titanium (Ti), tantalum (Ta), or the like. In some embodiments, the second interconnect layer 406b extends continuously from directly above the first regulating MTJ device 204 to directly above the second regulating MTJ device 206.The MTJs of the first regulating MTJ device 204, the second regulating MTJ device 206, and the operative MTJ device 106 each include a free layer 114 and a pinned layer 110 separated by a tunnel dielectric barrier 112. The free layer 114 has a magnetic moment configured to change in response to an electrical signal (e.g., a current). The fixed layer 110 has a fixed magnetic direction configured to function as a reference magnetic direction and / or to reduce a magnetic effect of the free layer 114. In some embodiments, one or more MTJs may include additional layers. For example, in some embodiments, one or more MTJs may include a ferromagnetic layer between the bottom electrode via 408 and a first pinned layer. In other embodiments, one or more MTJs may be additional pinned layers (e.g., a first additional pinned layer, a second additional pinned layer, etc.) and / or additional free layers (e.g., a first additional free layer, a second additional layer, etc.) arranged in various ways to improve performance of the MTJs.FIG. 4B illustrates a cross-sectional view of some alternative embodiments of a built-in chip 414 corresponding to the memory array 102 of FIG. 2.The built-in chip 414 includes a dielectric structure 404 disposed over a substrate 402. The dielectric structure 404 surrounds a first memory cell 202 a,1. The first memory cell 202 a,1 includes an operative MTJ device 106 and a regulating access device 108 having a first regulating MTJ device 204 and a second regulating MTJ device 206.The dielectric structure 404 further surrounds a plurality of conductive interconnect layers 406a-406f. The plurality of conductive interconnect layers 406 a- 406 finclude a first interconnect layer 406 aextending as a continuous structure directly below an operative MTJ device 106, a first regulating MTJ device 204, and a second regulating MTJ device 206 of the first memory cell 202 in a,1 fashion. The first interconnect layer 406 ais coupled to the operational MTJ device 106, the first regulating MTJ device 204, and the second regulating MTJ device 206 of the first memory cell 202 in a,1 via a second interconnect layer 406 band a first of a plurality of vias 412 a. A third interconnect layer 406c includes discrete interconnect structures defining two word lines WL 1- WL 2 coupled to respective memory cells within a column of the memory array 102 of FIG. 2, and a bit line BL 1, coupled to respective memory cells within a row of the memory array 102 of FIG. 2. In some embodiments, the operational MTJ device 106, the first regulating MTJ device 204, and the second regulating MTJ device 206 of the first memory cell 202 may be coupled in a,1 to the third interconnect layer 406 cvia second multiple vias 412 b.In some embodiments, one or more additional memory cell(s) may be arranged in a,1 over the first memory cell 202. In such embodiments, a fourth interconnect layer 406d extends as a continuous structure directly below an operational MTJ device 106, a first regulating MTJ device 204, and a second regulating MTJ device 206 of the second memory cell 202 a,1. The fourth interconnect layer 406 dis coupled to the operational MTJ device 106, the first regulating MTJ device 204, and the second regulating MTJ device 206 of the second memory cell 202 a,2 via a fifth interconnect layer 406 eand third, multiple vias 412 c. A sixth interconnect layer 406f defines two word lines WL 3- WL 4, coupled to respective memory cells within a column of the memory array 102 of FIG. 2, and a bit line BL 2, coupled to respective memory cells within a row of the memory array 102 of FIG. 2. In some embodiments, the operational MTJ device 106, the first regulating MTJ device 204, and the second regulating MTJ device 206 of the second memory cell 202 may be coupled in a,2 to the sixth interconnect layer 406f via fourth multiple vias 412d.In other embodiments (not shown), one or more additional memory cell(s) may be arranged laterally adjacent to the first memory cell 202 in a,1 fashion. In some such embodiments, the memory cells within a memory array may be arranged laterally adjacent to each other on the same interconnect layers.Thus, it is understood that the chips 400 and 414 incorporated in FIGS. 4A-4B are two non-limiting embodiments of a incorporated chip that could implement the memory array 102 of FIG. 2, and that other implementations may be used in alternative embodiments.In some embodiments, the regulating MTJ devices within a regulating access device may have one and the same size. In other embodiments, the regulating MTJ devices within a regulating access device may have different sizes from each other and / or from an operative MTJ device. For example, FIG. 5A illustrates a schematic diagram of some additional embodiments of a memory circuit 500 with a regulating access device having regulating devices of different sizes.The memory circuit 500 includes a plurality of memory cells 502 a,1-502c,3 each including an operational MTJ device 106 configured to store data, and a regulating access device 108 selectively configured to provide access to the operational MTJ device 106. The regulatory access device 108 includes a first regulatory MTJ device 504 and a second regulatory MTJ device 506 coupled to the same layer of the associated MTJ device 106. The first regulating MTJ device 504 is coupled between a first word line (e.g., WL 1) and the operative MTJ device 106, while the second regulating MTJ device 506 is coupled between a second word line (e.g., WL 2) and the operative MTJ device 106. The operational MTJ device 106 is further coupled to a first bit line (e.g., BL 1).FIG. 5B illustrates a cross-sectional view 508 of some embodiments of a built-in chip corresponding to the memory array 500 of FIG. 5A. As shown in cross-sectional view 508, the first regulating MTJ device 504 has a first size (e.g., a first width w 1) and the second regulating MTJ device has a second size (e.g., a second width w 2), which is different than the first size. The first size of the first regulating MTJ device 504 provides the first regulating MTJ device 504 with a stronger switching current that can allow stronger currents. In some embodiments, the operational MTJ device 106 has a third size (e.g., a third width w 3) that is different from the first size and the second size.FIGS. 6A-6B illustrate some additional embodiments of a built-in chip comprising a memory circuit with a regulating access device configured to selectively provide access to an operative MTJ device.FIG. 6A illustrates a schematic diagram of a memory circuit 600 having multiple memory cells 602 a,1-602c,3 arranged in rows and columns. The plurality of memory cells 602 a,1-602c,3 each including an operational MTJ device 106 configured to store data and a regulating access device 108 selectively configured to selectively provide access to the operational MTJ device 106. The regulatory access device 108 includes a regulatory MTJ device 604 coupled between a word line WL x( x=1, 2, 3) and a bias line BVL y( y=1, 2, 3). The operative MTJ device 106 is coupled between the bias line BVL y and a bit line BL z( z=1, 2, 3).The plurality of memory cells 602 a,1-602c,3 are coupled to a control circuit 607. The control circuit 607 includes a bit line decoder 116 configured to selectively apply signals to one or more bit line(s) BL z a word line decoder 118 configured to selectively apply signals to one or more word line(s) WL x, and a bias circuit 606 configured to selectively apply signals to one or more bias lines BVL y. In some embodiments, word line decoder 118 and bias circuit 606 may include one and the same circuit element (i.e., word line decoder 118 may apply signals to bias lines BVL y ).During operation, the bias circuit 606 and word line decoder 118 may apply voltages to the bias lines BVL y and word lines WL x to access an operational MTJ device 106 such that a value of the regulating MTJ device 604 is adjusted within a row of the memory array 102. Bit line decoder 116 may then apply bit line voltages that allow access to a selected one of the plurality of memory cells 602 a,1-602c,3 without access to unselected ones of the plurality of memory cells 602 a,1-602c,3.For example, to write data to an operational MTJ device 106 within a first memory cell 602 a,1 a first set of bias voltages may be applied to a first word line WL 1 and a first bias line BVL y. The first set of bias voltages provides a low resistance to the regulating access device 108 within a first row. A second set of bias voltages may be applied to a bias line BVL y and word lines WL 1 in other rows, thus imparting high resistance to the regulating access device 108 within other rows. Then, a bit line voltage is applied to the first bit line BL 1. A low resistance of the regulating access device within the first memory cell 602 a,1 causes a high current (e.g., greater than a switching current) to flow through the operative MTJ device within the first memory cell 602 a,1 while a high resistance of the regulating access device within the second memory cell 602 a,2 causes a low current (e.g., less than a switching current) to flow through the operative MTJ device within the second memory cell 602 a,1.FIG. 6B illustrates a cross-sectional view 608 of some embodiments of a built-in chip corresponding to the memory array 600 of FIG. 6A.FIGS. 7A-7B illustrate some additional embodiments of a built-in chip comprising a memory circuit with a regulating access device configured to selectively provide access to an operative MTJ device.FIG. 7A illustrates a schematic diagram of some additional implementations of a memory circuit 700 having multiple memory cells 702 a,1-702c,3 arranged in rows and columns. The plurality of memory cells 702 a,1-702c,3 each including an operational MTJ device 106 configured to store data and a regulating access device 108 selectively configured to selectively provide access to the operational MTJ device 106.The regulatory access device 108 includes a first regulatory MTJ device 204 and a second regulatory MTJ device 206 coupled to the same layer of the associated MTJ device 106. The first regulating MTJ device 204 is coupled between a first of a plurality of word lines WL 1- WL 3 and a first of a plurality of bias lines BVL 1- BVL 3. The second regulating MTJ device 206 is coupled between a first of a plurality of bit lines BL 1- BL 3 and a first of a plurality of bias lines BVL 1- BVL 3. The operative MTJ device 106 is coupled between the first of a plurality of bias lines BVL 1- BVL 3 and a second of a plurality of bit lines BL 1- BL 6.During operation, a bit line decoder 116 is configured to selectively apply signals to one or more bit line(s) BL 1- BL 6 and a word line decoder 118 is configured to selectively apply signals to one or more word line(s) WL 1- WL 3 and one or more bias lines BVL 1- BVL 3. The applied signals cause generation of a current within the first regulating MTJ device 204 based on a voltage provided to a full column of the memory array 102, while coupling of the regulating access device 108 to the bit line BL 2 causes a current within the second regulating MTJ device 206 to be generated based on a voltage provided to a full row of the memory array 102. Coupling the regulating access device to bit lines and word lines extending in different directions allows for improved isolation between memory cells of the memory array 102.FIG. 7B illustrates a cross-sectional view 704 of some additional embodiments of a built-in chip corresponding to the memory array 700 of FIG. 7A.FIGS. 8A-8B illustrate some additional embodiments of a built-in chip comprising a memory circuit with a regulating access device configured to selectively provide access to an operative MTJ device.FIG. 8A illustrates a schematic diagram of some additional embodiments of a memory circuit 800 with a regulating access device 108 comprising a first regulating MTJ device 804, a second regulating MTJ device 806, and a third regulating MTJ device 808. The first regulating MTJ device 804 is coupled between a first word line (e.g., WL 1) and a first bias line (e.g., BVL 1) the second regulating MTJ device 806 is coupled between a second word line (e.g., WL 2) and the first bias line (e.g., BVL 1) the third regulating MTJ device 808 is coupled between the first bias line (e.g., BVL 1) and the operative MTJ device 106. The operational MTJ device 106 is coupled between the third regulating MTJ device 808 and a first bit line (e.g., BL 1). The inclusion of the third regulating MTJ device 808 provides greater flexibility to the regulating access device 108 by creating different resistances for controlling current within an associated operative MTJ device 106.FIG. 8B illustrates a cross-sectional view 810 of some embodiments of a built-in chip corresponding to the memory array 800 of FIG. 8A.Although the operations and / or devices illustrated in FIGS. 2-8B are described with respect to a regulating access device having regulating MTJ devices, it is understood that the disclosed memory cell is not limited to such an embodiment. Instead, the operations and / or devices of FIGS. 2-8B may be performed in alternative embodiments and / or may include a regulating access device with regulating thin film resistances (e.g., including tantalum, tantalum nitride, titanium, tungsten, or the like).FIGS. 9-12 illustrate cross-sectional views 900-1200 of some embodiments of a method of forming a built-in chip with a memory circuit having memory cells (e.g., MRAM cells) including a regulating access device configured to selectively provide access to an operative MTJ device. Although FIGS. 9-12 are described with respect to a method, it is understood that the structures disclosed in FIGS. 9-12 are not limited to such a method, but may instead be solely structures independent of the method.As shown in cross-sectional view 900 of FIG. 9, a first interconnect layer 406 ais formed over a substrate 402. In some embodiments, the first interconnect layer 406 ais formed by forming a first dielectric continuous (ILD) layer 904 over the substrate 402. In some embodiments, the first ILD layer 904 may be separated from the substrate 402 by one or more additional dielectric layer(s) 902. The first ILD layer 904 is structured to define a slot 906. In some embodiments, the first ILD layer 904 may be patterned by forming a patterned capping layer (not shown) over the first ILD layer 904 and performing an etching process to remove portions of the first ILD layer 904 that are not covered by the patterned capping layer. A conductive material is formed within the slot 906, followed by a subsequent planarization process (e.g., a chemical planarization process) to form the first interconnect layer 406 a.In various embodiments, the substrate 402 may be any type of semiconductor body (e.g., silicon, SiGe, SOI, etc.), such as a semiconductor wafer and / or one or more die(s) on a wafer, as well as any other type of semiconductor and / or epitaxial layers associated therewith. In some embodiments, the ILD layer 904 may comprise one or more dielectric material(s) such as silicon dioxide (SiO 2), SiCOH, a fluorosilicate glass, a phosphate glass (e.g., a boron phosphate silicate glass), or the like. In some embodiments, the conductive material may include a metal (e.g., tungsten, aluminum, etc.) formed via a deposition process (e.g., CVD, PVD, PE-CVD, ALD, etc.). In various embodiments, the first interconnect layer 406 amay be a first interconnect wire layer, a second interconnect wire layer, a third interconnect wire layer, or a higher metal interconnect wire layer.As shown in cross-sectional view 1000 of FIG. 10, a plurality of bottom electrode vias 408 are formed over a top surface of first interconnect layer 406 a. The plurality of bottom electrode vias 408 are surrounded by a dielectric layer 1002. In some embodiments, the dielectric layer 1002 may be deposited over the first interconnect layer 406 aand then selectively patterned to define bottom electrode via openings. The plurality of bottom electrode vias 408 are then formed within the bottom electrode via openings by a deposition process. In various embodiments, the dielectric layer 1002 may include one or more of silicon carbide, silicon rich oxygen, TEOS (tetraethyl orthosilicate), or the like. In various embodiments, the plurality of bottom electrode vias 408 may include a conductive material, such as titanium, titanium nitride, tantalum, or the like.A plurality of MTJ devices 106, 204, and 206 are formed over a plurality of bottom electrode vias 408. The plurality of MTJ devices 106, 204, and 206 each include an MTJ with an attached layer 110 separated from a free layer 114 by a tunnel dielectric barrier 112. In some embodiments, the attached layer 110 may be formed to contact the bottom electrode vias 408. In other embodiments, the free layer 114 may be formed to contact the bottom electrode vias 408. One of the plurality of MTJ devices 106, 204, and 206 includes an operational MTJ device 106 configured to store a data state. One or more of the plurality of MTJ devices 106, 204, and 206 includes / include regulating MTJ devices 204 and 206 disposed within a regulating access device 108 configured to control (i.e., regulate) a current provided to an associated operative MTJ device 106.In some embodiments, the plurality of MTJ devices 106, 204, and 206 may be formed simultaneously. For example, in some embodiments, the plurality of MTJ devices 106, 204, and 206 may be formed by applying a magnetic attached film over the dielectric layer 1002 and the plurality of bottom electrode vias 408, which form a dielectric barrier film over the magnetic attached film and form a magnetic film free of the dielectric barrier film. One or more patterning process(s) is / are performed on the magnetically attached film, the dielectric barrier layer, and the magnetic free film to define the plurality of MTJ devices 106, 204, and 206. In other embodiments, the plurality of MTJ devices 106, 204, and 206 may be formed at different times.As shown in cross-sectional view 1100 of FIG. 11, a plurality of top electrode vias 410 are formed over a plurality of the MTJ devices 106, 204, and 206. The plurality of upper electrode vias 410 are surrounded by a second ILD layer 1102. In some embodiments, the second ILD layer 1102 may be deposited over the plurality of MTJ devices 106, 204, and 206 and then selectively patterned to define top electrode via openings. The plurality of upper electrode openings 410 are then formed within the upper electrode via openings by a deposition process. In various embodiments, the second ILD layer 1102 may include one or more dielectric material(s) such as silicon dioxide (SiO 2), SiCOH, a fluorosilicate glass, a phosphate glass (e.g., a boron phosphate silicate glass), or the like. In various embodiments, the plurality of upper electrode vias 410 may include a conductive material, such as titanium, titanium nitride, tantalum, or the like.A second interconnect layer 406 bis formed within a third ILD layer 1104 over the plurality of MTJ devices 106, 204, and 206. In some embodiments, the second interconnect layer 406 bincludes a plurality of interconnect structures defining a bit line BL 1 and one or more word lines WL 1- WL 2 of a first memory cell 202 a,1. In some embodiments, the third ILD layer 1104 may include a dielectric (e.g., an oxide, a weak k dielectric, or an ultra-weak k dielectric) formed by one or more deposition process(s) (e.g., PVD, CVD, PE-CVD, etc.). The second interconnect layer 406 bmay be formed by selectively etching the third ILD layer 1104 to form openings within the third ILD layer 1104. A conductive material (e.g., copper and / or aluminum) is then deposited within the openings followed by a subsequent planarization process (e.g., a chemical mechanical planarization process) to form the first interconnect layer 406 b.As shown in cross-sectional view 1200 of FIG. 12, a second memory cell 202 b,1 may be formed over the first memory cell 202 a,1. The second memory cell 202 b,1 may include an operative MTJ device 106 and a regulating access device 108 having regulating MTJ devices 204 and 206 formed between a third interconnect layer 406c and a fourth interconnect layer 406d. The second memory cell 202 b,1 may be formed according to operations analogous to those described in FIGS. 9-11.FIG. 13 illustrates a flow diagram of some embodiments of a method 1300 of forming a built-in chip with a memory circuit having memory cells (e.g., MRAM cells) including a regulating access device configured to selectively provide access to an operative MTJ device.Thus, while the method 1300 is illustrated and described below as a series of acts or events, it will be appreciated that the illustrated arrangement of such acts or events is not to be interpreted in a limiting sense. For example, some operations may occur in different orders and / or concurrently with other operations or events other than those illustrated and / or described herein. In addition, not all illustrated operations need be necessary to implement one or more aspect(s) or embodiment(s) of the description herein. Further, an operation / operations described herein may / may be performed separately in one or more operation / operations and / or one or more phases.At 1302, a first interconnect layer is formed over a substrate. The first interconnect layer may be formed within a first ILD layer over the substrate. FIG. 9 illustrates a cross-sectional view 900 of some embodiments corresponding to operation 1302.At 1304, a plurality of bottom electrode vias are formed directly over a continuous top surface of the first interconnect layer. FIG. 10 illustrates a cross-sectional view 1000 of some embodiments corresponding to operation 1304.At 1306, a plurality of MTJ devices are formed directly over the plurality of bottom electrode vias. The plurality of MTJ devices include an operational MTJ device and one or more regulatory MTJ device(s). FIG. 10 illustrates a cross-sectional view 1000 of some embodiments corresponding to operation 1306.At 1308, a plurality of top electrode vias are formed directly over the plurality of MTJ devices. FIG. 11 illustrates a cross-sectional view 1100 of some embodiments corresponding to operation 1308.At 1310, a second interconnect layer having a plurality of interconnect structures is formed over the plurality of upper electrode vias. The plurality of interconnect structures define a bit line and one or more word line(s). FIG. 11 illustrates a cross-sectional view 1100 of some embodiments corresponding to operation 1310.Operations 1302- 1310 form a first memory cell over the substrate. In some embodiments, operations 1302- 1310 may be repeated (as shown in operation 1312) to form a second memory cell over the first memory cell. FIG. 12 illustrates a cross-sectional view 1200 of some embodiments corresponding to operation 1312.Although method 1300 describes a memory circuit method including memory cells (e.g., MRAM cells) with a regulating access device including MTJ devices, it is understood that in other embodiments the regulating device may include resistors (e.g., thin foil resistors). In such embodiments, the MTJ operational device may be formed by a first set of operations (at 1306), while the resistive regulating device may be formed by a second set of operations (occurring between 1306 and 1308). For example, after the formation of the operative MTJ (at 1306), resistors may be formed using one or more etch process(s).Accordingly, in some embodiments, this disclosure relates to a memory cell (e.g., an MRAM cell) that does not have a drive transistor (e.g., an access transistor). Instead, the memory cell includes a regulating access device having one or more regulating MTJ device(s) configured to selectively provide access to an operative MTJ device.

Claims

An integrated chip, comprising: an operational magnetic tunnel junction, MTJ, device coupled to a bit line, the operational MTJ device configured to store a data state; and a regulating access device coupled between the MTJ device and a first word line, the regulating access device comprising one or more regulating MTJ devices configured to control a current provided to the operational MTJ device, the regulating access device comprising: a first regulating MTJ device coupled between the first word line and the operational MTJ device; and a second regulating MTJ device coupled between a second word line and the operative MTJ device, wherein the first word line and the second word line are coupled to a word line decoder.The integrated chip of claim 1, wherein the one or more MTJ devices each comprise: a pinned layer; a dielectric barrier layer; and a free layer separated from the pinned layer by the dielectric barrier layer.The integrated chip of claim 1 or 2, wherein the first regulating MTJ device is larger in size than the second MTJ device.The integrated chip of any preceding claim, wherein the operational MTV device is not directly over an access transistor device.The integrated chip of any preceding claim, further comprising: a bias line coupled between a first regulating MTJ device and the operative MTJ device.The integrated chip of any preceding claim, wherein the operative MTJ device is laterally separated from a first regulating MTJ device by a dielectric structure disposed over a substrate.The integrated chip of claim 6, further comprising: a second operational MTJ device disposed within a memory cell directly above the operational MTJ device, wherein the second operational MTJ device is configured to store a second data state.The integrated chip of any preceding claim, wherein the operative MTV device is coupled between the bit line and the first word line by a continuous conductive path that does not extend through a semiconductor substrate underlying the operative MTJ device.An integrated circuit, comprising: a first interconnect layer disposed within a dielectric structure over a substrate, the first interconnect layer separated from the substrate by the dielectric structure; an operative MTJ device disposed directly over the first interconnect layer and configured to store a data state, the operative MTJ device electrically coupled between a bit line and a first word line via a continuous conductive path that includes a plurality of interconnect layers and that does not extend through the substrate; a regulating access device comprising a first regulating MTJ device coupled between the first word line and the operative MTJ device, the first regulating MTJ device configured to control a current provided to the operative MTJ device, the first regulating MTJ device having a first pinned layer separated from a first free layer by a first dielectric barrier layer; and a second regulating MTJ device coupled between a second word line and the operative MTJ device, the first word line and the second word line coupled to a word line decoder.The integrated circuit of claim 9, wherein the first interconnect layer extends continuously from directly below the operative MTJ device to directly below the first regulating MTJ device.The integrated circuit of claim 9 or 10, wherein the first regulating MTJ device is different in size than the second MTJ device.The integrated circuit of any of the preceding claims 9 to 11, further comprising: a bias line coupled between the first regulating MTJ device and the operative MTJ device, the bias line coupled to a bias circuit configured to selectively apply a bias voltage to the bias line.A method of forming an integrated circuit, comprising: forming a first interconnect layer over a substrate; forming a plurality of MTJ devices directly over the first interconnect layer, wherein the plurality of MTJ devices comprise an operative MTJ device and one or more regulating MTJ devices configured to selectively control a current flowing to the operative MTJ device; forming a second interconnect layer over the plurality of MTJ devices, one or both of the first interconnect layer and the second interconnect layer forming a bit line and one or more word lines, the one or more regulating MTJ devices comprising: a first regulating MTJ device coupled between a first word line of the one or more word lines and the operative MTJ device; and a second regulating MTJ device coupled between a second word line of the one or more word lines and the operative MTJ device, wherein the first word line and the second word line are coupled to a word line decoder.The method of claim 13, wherein the one or more regulating MTJ devices each comprise: a pinned layer; a free layer; and a dielectric barrier layer disposed between the pinned layer and the free layer.The method of claim 13 or 14, further comprising: simultaneously forming the operative MTJ device and the one or more regulating MTJ devices.

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