GATE-IN-PANEL GATE DRIVER AND ORGANIC LIGHT-EMITTING DISPLAY DEVICE HAVING THE SAME

Abstract

Organic light-emitting display device, comprising: a display panel (10) comprising: a substrate; a plurality of data lines (15) on the substrate; a plurality of gate lines (17, 18) on the substrate and oriented transversely to the data lines (15); and a plurality of pixels connected to the data lines (15) and the gate lines (17, 18); a data driver configured to supply data voltages (DATA) to the data lines (15); and a gate-in-panel gate driver (13) configured to supply gate pulses to the gate lines (17, 18), wherein the gate driver (13) is configured to drive the display panel (10) within a single image in a plurality of blocks of pixel rows (HL), wherein the single image has a plurality of cycles, and wherein each of the cycles has a data write period, at least one black data insertion period (BDI) and at least one precharge period (Pre), wherein during the data write period of one cycle of the plurality of cycles, the data voltages (DATA) are supplied to the pixel rows (HL) of a jth block, and during the at least one black data insertion period (BDI) of the cycle, a black image is written into the pixel rows (HL) of a qth block simultaneously, where j is a natural number and q is a natural number different from j, wherein the gate driver (13) has a plurality of stages (STG) which are connected to the pixel rows (HL) respectively, where each of the stages (STG) has: a first pull-up transistor (Tpu_CR) configured to output carrier signals (CARRY) corresponding to timings of carrier clocks in response to a Q-node voltage; and a second pull-up transistor (Tpu_SC) configured to output scan signals (SCAN) corresponding to scan clock times in response to the Q-node voltage, and the carrier clocks (CRCLK) have: an image clock signal for loading the Q node to generate a corresponding one of the scan signals (SCAN) output during the data write period; and a black data insertion clock signal for loading the Q node to generate a corresponding one of the scan signals (SCAN) output during the at least one black data insertion period (BDI).

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2017-0174431, filed on December 18, 2017. BACKGROUNDTechnical field

[0002] The present disclosure relates to a gate-in-panel gate driver and a display device having the same. Description of the technology used

[0003] Flat panel displays (FPDs) are widely used for monitors for desktop computers, portable computers such as laptops and PDAs, mobile phones, etc., due to their thinness and lightweight characteristics. Examples of such flat panel displays include liquid crystal displays (LCDs), plasma display panels (PDPs), field emission displays (FEDs), and organic light-emitting diode displays (OLEDs).

[0004] Meanwhile, black-screen insertion techniques have been proposed to reduce the motion picture response time (MPRT) of a display device. This technology aims to remove an image from a previous frame by displaying a black image (specifically, a black image) between each video frame. However, conventional black-screen display techniques require double the video frame rate, resulting in a lack of data loading time.

[0005] US 2016 / 0078834 A1 describes a gate driver circuit and a display device using the same. The gate driver circuit includes a first shift register configured to sequentially shift a gate start pulse in response to a gate shift clock and output a gate pulse shifted in blocks, each block including a plurality of gate lines; a second shift register configured to sequentially shift the gate start pulse in response to the gate shift clock and output a gate pulse shifted in blocks; and a controller configured to supply the gate shift clock to one of the first and second shift registers.

[0006] US 2010 / 0079361 A1 describes that, in a pixel of a display device, a first transistor, whose second terminal is connected to a first terminal of a light-emitting element, supplies a drive current corresponding to a voltage between a control terminal and the second terminal to a light-emitting element, and that a second terminal of the light-emitting element is connected to a drive voltage. At least one second transistor transmits a black voltage corresponding to a black-gray to the control terminal of the first transistor in a first and a second period, and transmits a gray voltage corresponding to an input image signal to the control terminal of the first transistor in a third period.A third transistor is connected between the first terminal of the light-emitting element and a power supply line to transmit a reference voltage. The third transistor is turned on in the first period and turned off in the second period. A capacitor is connected between the control terminal and the source of the first transistor, storing a control voltage based on a threshold voltage of the first transistor in the second period, and storing a voltage based on the control voltage and the threshold voltage in the third period. SHORT DESCRIPTION

[0007] The invention is based on the object of providing a gate-in-panel (GIP) gate driver and an organic light-emitting display (OLED) device incorporating such a device, in which the motion picture response time (MPRT) is improved by inserting black data without increasing the drive frequency. This object is achieved by an organic light-emitting display (OLED) device and a gate-in-panel (GIP) gate driver according to the independent claims. Further embodiments are described in the dependent claims.In accordance with one aspect of the present invention, there is provided an organic light-emitting display (OLED) device comprising: a display panel comprising a substrate, a plurality of data lines on the substrate, a plurality of gate lines on the substrate and oriented transversely to the data lines, and a plurality of pixels connected to the data lines and the gate lines; a data driver configured to supply data voltages to the data lines; and a gate-in-panel (GIP) gate driver configured to supply gate pulses to the gate lines.

[0008] The gate driver is configured to drive the display panel in a plurality of blocks of pixel rows within a frame, wherein the one frame has a plurality of cycles, each of the cycles having a data write period, at least one black data insertion period, and at least one precharge period.

[0009] The data voltages are supplied to the pixel rows of a block j during the data writing period of one cycle of the plurality of cycles, and during the at least one black data insertion period of the cycle, a black image is written into the pixel rows of a block q simultaneously.

[0010] j is a natural number and q is a natural number different from j.

[0011] The gate driver has a plurality of stages that are connected to the pixel rows accordingly.

[0012] Each of the stages comprises: a first pull-up transistor configured to output carrier signals in response to a Q-node voltage corresponding to carrier clock timings; and a second pull-up transistor configured to output scan signals corresponding to scan clock timings in response to the Q-node voltage, and the carrier clocks comprise: an image clock signal for charging the Q-node to generate a corresponding one of the scan signals output during the data write period; and a black data insertion (BDI) clock signal for charging the Q-node to generate a corresponding one of the scan signals output during the at least one black data insertion period.

[0013] The GIP gate driver may be configured to control zk pixel rows during each cycle of the plurality of cycles, where z is a natural number greater than 1 and k may be a natural number that can satisfy: z(k-1) <eine Gesamtzahl der Pixelzeilen≤zk.

[0014] During a data write period having zk horizontal periods, the GIP gate driver can sequentially output scan signals and the data driver can supply data voltages to the zk pixel rows, and, during k black data insertion periods, the GIP gate driver can supply scan signals to z pixel rows simultaneously and the data driver can write black data to the z pixel rows simultaneously.

[0015] Each of the at least one black data insertion period may last one horizontal period.

[0016] During the at least one precharge period following the at least one black data insertion period, the gate driver may supply a scan signal and a sample signal to a next pixel row to which a final data voltage may be supplied during the data write period.

[0017] The carrier clocks may maintain a turn-off voltage during at least one black data insertion period.

[0018] The carrier clocks may include 16 carrier clocks, the scan clocks may include 16 scan clocks, and each cycle may include 20 horizontal periods, the carrier clocks may be sequentially output during a time period from a first horizontal period to a 16th horizontal period, and an interval between the image clock signal and the BDI clock signal of the carrier clock may correspond to a portion of the data write period of 8 horizontal periods, a black data insertion period of 1 horizontal period, and a precharge period of 1 horizontal period.

[0019] There may be a time difference of 16n+8 horizontal periods between the carrier clock signal for writing data to a pixel row i and the carrier clock signal for writing black data to the pixel rows i.

[0020] n can be a natural number and i can be a natural number.

[0021] The carrier clocks may comprise 16 carrier clocks, the scan clocks may comprise 16 scan clocks, and each cycle may comprise 40 horizontal periods. The carrier clocks may be sequentially output during a time period from a first horizontal period to a sixteenth horizontal period. An interval between the image clock signal and the BDI clock signal of the carrier clocks may correspond to a portion of the data write period of 8 horizontal periods, to a black data insertion period of 1 horizontal period, and to a precharge period of 1 horizontal period. There may be a time difference of 32n+8 horizontal periods between the carrier clock signal for writing the image data into a pixel row i and the carrier clock signal for writing black data into the pixel row i.

[0022] n can be a natural number and i can be a natural number.

[0023] The carrier clocks may have 16 carrier clocks, the scan clocks may have 12 scan clocks, and each cycle may have 60 horizontal periods, and first to 16th carrier clocks may be output sequentially for 60 horizontal periods, from a first horizontal period to a sixtieth horizontal period.

[0024] A first half of a cycle of the first to eighth carrier clocks may correspond to the image clock signal of the carrier clock, and the first half of a cycle of the ninth to sixteenth carrier clocks may correspond to the BDI clock signal of the carrier clock.

[0025] There may be a time difference of 48n+24 horizontal periods between the carrier clock signal for writing image data to a pixel row i and the carrier clock signal for writing black data to the pixel row i.

[0026] n can be a natural number and i can be a natural number.

[0027] The carrier clocks may have 12 carrier clocks, the scan clocks may have 12 scan clocks, and each cycle may have 60 horizontal periods, first to twelfth carrier clocks may be output sequentially for 60 horizontal periods, from a first horizontal period to a sixtieth horizontal period.

[0028] A first half of a cycle of the first to sixth carrier clocks may correspond to the image clock signal of the carrier clock, and the first half of a cycle of the seventh to twelfth carrier clocks may correspond to the BDI clock signal of the carrier clock.

[0029] There may be a time difference of 48n+24 horizontal periods between the carrier clock signal for writing image data to a pixel row i and the carrier clock signal for writing black data to the pixel row i.

[0030] n can be a natural number and i can be a natural number.

[0031] Each of the plurality of stages may include: a first Q-node control transistor configured to charge the Q-node in a forward mode in response to a forward carrier signal; and a second Q-node control transistor configured to discharge the Q-node in the forward mode in response to a reverse carrier signal.

[0032] Output times of the forward carrier signals and the reverse carrier signals can be specified longer than scan times of the blocks of the display panel.

[0033] The second Q-node control transistor may be configured to charge the Q-node in a reverse mode in response to the reverse carrier signal, and the first Q-node control transistor may be configured to apply a turn-off voltage to the Q-node in the reverse mode in response to the forward carrier signal.

[0034] Each of the plurality of blocks can have 8k pixel rows.

[0035] k can be a natural number.

[0036] The output timings of the forward carrier signal applied to the first Q-node control transistor of an (8k+a)th stage and the output timings of the reverse carrier signal applied to the second Q-node control transistor of an (8k+[9-a])th stage may be the same.

[0037] a can be a natural number less than or equal to 8.

[0038] The output timings of the reverse carrier signal applied to the second Q-node control transistor of the (8k+a)th stage and the output timings of the forward carrier signal applied to the first Q-node control transistor of the (8k+[9-a])th stage may be the same.

[0039] a can be a natural number less than or equal to 8.

[0040] In another embodiment, the present disclosure provides a gate-in-panel (GIP) gate driver having a plurality of stages. Each of the stages includes: a first pull-up transistor configured to receive a respective carrier clock and, in response to a Q-node voltage of the stage, output carrier signals corresponding to the carrier clock; a second pull-up transistor configured to receive a respective scan clock and output scan signals corresponding to the scan clock in response to the Q-node voltage; a first Q-node control transistor configured, in a forward scan mode, to charge the Q-node in response to a forward carrier signal; and a second Q-node control transistor configured, in the forward scan mode, to discharge the Q-node in response to a reverse carrier signal.

[0041] Each of the carrier clocks may include: an image clock signal for generating a corresponding scan signal outputtable during a data write period; and a black data insertion (BDI) clock signal for generating a corresponding scan signal outputtable during a black data insertion period.

[0042] The carrier clocks can maintain a shutdown voltage during the black data insertion period.

[0043] The black data insertion period can last 1 horizontal period. DESCRIPTION OF THE DIFFERENT VIEWS OF THE DRAWINGS

[0044] The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated herein and constitute a part of this specification, illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. In the drawings: Fig. 1 is a view showing an organic light emitting diode display unit according to the present disclosure; Fig. 2 an equivalent circuit diagram of a pixel shown in Fig. 1, according to an exemplary embodiment; Fig. 3 is a view showing the duty cycle of an organic light emitting diode display unit according to the present disclosure; Fig. 4 is a timing diagram showing the duty cycle of an organic light emitting diode display unit according to the present disclosure; Fig. 5A is an equivalent circuit diagram of a pixel in a programming period according to Fig. 8; Fig. 5B is an equivalent circuit diagram of a pixel in a light emission period according to Fig. 8; Fig. 5C is an equivalent circuit diagram of a pixel in a no-light emission period according to Fig. 8; Fig. 6 is a schematic diagram of stages of a gate driver according to the present disclosure; Fig. 7 and Fig. 8 are views showing voltage variations of stages associated with pixel rows relative to the operation of the gate driver according to a first exemplary embodiment; Fig. 9 is a view showing timings of clocks according to the first exemplary embodiment; Fig. 10 and Fig. 11 are views showing how the clocks and the stages are connected according to the first exemplary embodiment; Fig. 12 is a view showing timings of clocks according to a second exemplary embodiment; Fig. 13 and Fig. 14 are views showing how the clocks and the stages are connected according to the second exemplary embodiment; Fig. 15 is a view showing timings of clocks according to a third exemplary embodiment; Fig. 16 to 18 are views showing how the clocks and the stages are connected according to the third exemplary embodiment; Fig. 19 is a view showing timings of clocks according to a fourth exemplary embodiment; Fig. 20 and Fig. 21 are views showing how the clocks and the stages are connected according to the fourth exemplary embodiment; Fig. 22 and Fig. 23 are views showing a Q-node voltage variation in a bidirectional scan mode of a shift register according to the first to fourth exemplary embodiments; Fig. 24 and Fig. 25 are views showing a shift register and stages for bidirectional scan mode operation according to the present disclosure; Fig. 26 is a view showing a shift register capable of bidirectional scanning according to the first exemplary embodiment; Fig. 27 and Fig. 28 are views showing Q-node voltage variations caused by the shift register capable of bidirectional scanning according to the first exemplary embodiment; Fig. 29 is a view showing a shift register capable of bidirectional scanning according to the second exemplary embodiment; and Fig. 30 is a view showing a shift register capable of bidirectional scanning according to the third exemplary embodiment. DETAILED DESCRIPTION

[0045] Advantages and features of the present disclosure, and methods for achieving the same, may be better understood by reference to the following detailed description of preferred embodiments and the accompanying drawings. However, the present disclosure may be embodied in many different ways and should not be interpreted as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the disclosure to those skilled in the art, and the present disclosure is defined only by the appended claims.

[0046] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Throughout the description, like reference numerals denote substantially similar components. In describing the present disclosure, if it is believed that a detailed description of well-known functions or configurations might unnecessarily obscure the subject matter of the present disclosure, such detailed description will be omitted.

[0047] Although the embodiments of the present disclosure show transistors of a pixel all implemented as n-type, the technical idea of ​​the present disclosure is not limited thereto and may also be applicable to p-type transistors.

[0048] While this description is written with reference to an organic light-emitting display unit, the technical idea of ​​the present disclosure is not limited to the organic light-emitting display unit. For example, the pixels on the display panel shown in Fig. 1 is shown, be formed of liquid crystal cells, and the configuration according to Fig. 1 may be modified for the liquid crystal display device.

[0049] Fig. 1 is a view showing a display device according to an exemplary embodiment of the present disclosure.

[0050] As in Fig. 1, the display device according to the exemplary embodiment of the present disclosure includes a display panel 10, a timing controller 11, a data driver 12, and a gate driver 13.

[0051] A plurality of data lines 15 and reference voltage lines 16, and a plurality of gate lines 17 and 18 are formed on a display portion of the display panel 10. Pixels are formed at the intersections of the data lines 15, the reference voltage lines 16, and the gate lines 17 and 18. For example, each pixel may be connected to a data line 15, a reference voltage line 16, and a gate line 17 and 18. The term "cross" is used herein in its broadest sense, including the meaning of one element crossing or overlapping another element, and does not necessarily require two elements to touch each other.For example, the data lines 15 and the reference voltage lines 16, which extend in a first direction, may overlap with the gate lines 17, 18, which extend in a second direction transverse to the first direction, thus crossing each other, but they may be physically separated from each other, for example, by one or more layers or elements arranged therebetween. In some embodiments, this may also include the meaning that the lines or elements touch each other. The pixels may be horizontally separated from each other row by row. For example, the pixels may be divided into first to nth pixel rows HL1 to HLn. The pixels formed in the same horizontal orientation receive the same scan signal.

[0052] Gate lines 17 and 18 include first gate lines 17 to which scanning signals are applied, and second gate lines 18 to which scanning signals are applied. Each pixel can be connected to one of the data lines 15, one of the reference voltage lines 16, one of the first gate lines 17, and one of the second gate lines 18. Each pixel includes an OLED and a control transistor and can be operated in a duty cycle mode to control the light emission duty cycle of the OLED.

[0053] Such a pixel receives a high-potential control voltage EVDD and a low-potential control voltage EVSS. The thin-film transistors (TFTs) forming the pixel can be implemented as p-type or n-type, or as a hybrid of the two. Semiconductor layers of the TFTs forming the pixel can comprise any suitable material and, in some embodiments, can comprise amorphous silicon, polysilicon, or oxide.

[0054] The data driver 12 converts input image data RGB into a data voltage and supplies this data voltage to the data lines 15 under the control of the timing controller 11. Furthermore, the data driver 12 generates a reference voltage and supplies it to the reference voltage lines 16 under the control of the timing controller 11.

[0055] Under the control of the timing controller 12, the gate driver 13 generates a scanning signal synchronized with the data voltage and supplies it to the first gate lines 17 and generates a scanning signal synchronized with the reference voltage and supplies it to the second gate lines 18.

[0056] The scan signal generated for duty cycle operation during a frame includes first and second scan signals, and the gate driver 13 applies the first scan signal and the second scan signal separately to the same pixel during a frame. The first scan signal and the second scan signal are applied with a time difference between them.

[0057] The scanning signal generated for duty cycle operation during a frame consists only of a first scanning pulse, and the first scanning pulse can be applied to the pixel in synchronization with the first scanning signal. It is possible for the scanning signal generated for duty cycle operation during a frame to consist only of a first scanning pulse and a second scanning pulse, and the gate driver 13 can apply the first scanning pulse to the pixel in synchronization with the first scanning signal and then apply the second scanning pulse to the pixel after the first scanning pulse.

[0058] The gate driver 13 may include a level shifter and a shift register. The level shifter is implemented as an integrated circuit (IC) on a printed circuit board (not shown) connected to the display panel 10. The level shifter shifts the level of a start signal, a carrier clock CRCLK, a scan clock SCCLK, a sample clock SECLK, etc., and then supplies them to the shift register. The shift register has a plurality of stages connected in a cascade. The level shifter outputs two or more start signals in a frame and supplies them to the shift register. In some embodiments, the gate driver 13 may be a gate-in-panel (GIP) gate driver disposed in a non-active area of ​​the display panel 10. For example, the GIP gate driver 13 may be formed directly on a substrate of the display panel 10.

[0059] The timing controller 11 receives input image data RGB from a host system 14 via an interface circuit (not shown) and supplies this image data RGB to the data driver 12 via various interface methods such as mini-LVDS.

[0060] The timing controller 11 receives timing control signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a dot clock signal DCLK from the host system 14 and generates control signals for controlling the operating times of the data driver 12 and the gate driver 13. The control signals include a gate timing control signal GDC for controlling the operating time of the gate driver 13, a source timing control signal DDC for controlling the operating time of the data driver 12, and a duty control signal DCON for controlling the light emission duty cycle of the OLED.

[0061] Fig. 2 is a view showing an example of the pixel. Fig. Figure 2 shows a pixel having an organic light emitting diode.

[0062] Referring to Fig. 2, a pixel according to the present disclosure includes an OLED, a control thin film transistor DT, a storage capacitor Cst, a first switching TFT ST1, and a second switching TFT ST2.

[0063] The OLED includes an anode connected to a source node Ns, a cathode connected to an input terminal of the low-potential control voltage EVSS, and an organic compound layer formed between the anode and the cathode.

[0064] The control transistor DT controls the control current flowing through the OLED depending on the voltage difference between a gate node Ng and a source node Ns. The control transistor DT has a gate electrode connected to the gate node Ng, a drain electrode connected to an input terminal of the high-potential control voltage EVDD, and a source electrode connected to the source node Ns. The storage capacitor Cst is connected between the gate node Ng and the source node Ns.

[0065] The first switching TFT ST1 applies a data voltage on a data line 15 to the gate node Ng in response to a scan signal SCAN by switching the current flow between the data line 15 and the gate node Ng. The first switching TFT ST1 has a gate electrode connected to a first gate line 17, a drain electrode connected to the data line 15, and a source electrode connected to the gate node Ng.

[0066] The second switching TFT ST2 applies a reference voltage Vref on the reference voltage line 16 to the source node Ns in response to a scanning signal SEN by switching the current flow between the reference voltage line 16 and the source node Ns. The second switching TFT ST2 has a gate electrode connected to a second gate line 18, a drain electrode connected to the reference voltage line 16, and a source electrode connected to the source node Ns.

[0067] The display panel 10 of the display device, which in Fig. 1 can be implemented using a liquid crystal display device having a liquid crystal cell. On a lower substrate of the display panel implemented in a liquid crystal display device, there are data lines, gate lines, TFTs, pixel electrodes connected to the TFTs, and storage capacitors connected to the pixel electrodes. Each pixel adjusts the amount of transmitted light using liquid crystal molecules controlled by a voltage difference between the pixel electrode, which stores the data voltage via the TFT, and a common electrode to which a common voltage Vcom is applied.

[0068] Fig. 3 and Fig. 4 are views for explaining the duty cycle of an organic light emitting display device according to the present disclosure.

[0069] Referring to the Fig. 3 and Fig. 4. In the organic light-emitting display device according to the present disclosure, image data and black data are written within one frame period. That is, the organic light-emitting display device according to the present disclosure can use black data insertion technology without increasing the frame rate.

[0070] Fig. 4 shows control waveforms of a scanning signal SCAN, a scanning signal SEN, and a data voltage DATA applied to a first pixel in a first pixel row HL1. That is, one frame for a duty cycle operation includes a programming period Tp in which the voltage between the gate node Ng and the source node Ns is set in response to a control current, a light-emitting period Te in which the OLED emits light in response to a control current, and a no-light-emitting period Tb in which the OLED does not emit light. The light-emitting duty cycle may correspond to the light-emitting period Te, and the black duty cycle may correspond to the black period Tb. As shown in Fig. 4, the scanning signal includes an image scanning signal Pa1 synchronized with the timing of writing image data and a BDI scanning signal Pa2 for black data insertion (BDI) synchronized with the timing of writing black data.

[0071] The Fig. 5A to 5C are views showing how a pixel operates during the programming period, the light emission period, and the no-light emission period, respectively.

[0072] As in Fig. As shown in Figure 5A, in the programming period Tp, the first switching TFT ST1 of the first pixel is turned on in response to an image scanning signal Pa1 of a scanning signal SCAN to apply a first data voltage D1 to the gate node Ng. In the programming period Tp, the second switching TFT ST2 of the first pixel is turned on in response to a first scanning pulse Pb1 of a scanning signal SEN to apply a reference voltage Vref to the source node Ns. This sets the voltage between the gate node Ng and the source node Ns of the first pixel in accordance with a control current.

[0073] As in Fig. 5B, in the light emission period Te, the first switching TFT ST1 of the first pixel is turned off in response to the scanning signal SCAN, and the second switching TFT ST2 of the first pixel is turned off in response to the scanning signal SEN. The voltage Vgs between the gate node Ng and the source node Ns, which is set for the first pixel in the programming period Tp, is maintained in the light emission period Te. In this case, the voltage Vgs between the gate node Ng and the source node Ns is smaller than a threshold voltage Vth of the control transistor DT of the first pixel. Therefore, a control current flows through the control transistor of the first pixel during the light emission period Te. With this control current, the potential of the gate node Ng and the potential of the source node are boosted while the voltage Vgs between the gate node Ng and the source node Ns is maintained in the light emission period Te.When the potential of the source node Ns is amplified to an operating point level of the OLED, the OLED of the first pixel emits light.

[0074] As in Fig. As shown in Figure 5C, in the no-light-emission period Tb, the first switching TFT ST1 of the first pixel is turned on in response to a BDI scan pulse Pa2 of the scan signal SCAN to apply a black data voltage Bdata to the gate node Ng. The second switching TFT ST2 of the first pixel remains off in response to the scan signal SEN. Here, the black data voltage Bdata is a data voltage for displaying a black image.

[0075] During the light emission period Te, the scanning signal SCAN and the scanning signal SEN are sequentially applied to the pixel rows, and the pixel rows are sequentially supplied with the data voltage.

[0076] At a time when the no-light emission period Tb starts, a plurality of BDI scanning pulses Pa2 are turned on simultaneously and therefore a plurality of pixel rows simultaneously receive the black data voltage Bdata.

[0077] An image scan pulse Pa1 for writing an image data voltage is output at an image clock time, and a BDI scan pulse Pa2 for writing a black data voltage Bdata is output at a BDI clock time.

[0078] Fig. 6 is a schematic diagram of stages of a gate driver according to the present disclosure.

[0079] Referring to Fig. 6, an ith stage (i is a natural number) of the shift register includes first to third pull-up transistors Tpu_CR, Tpu_SC, and Tpu_SE, which output clocks according to the voltage of a Q node. The ith stage STGi is a stage that outputs a scan signal SCAN and a sampling signal SEN to control an ith pixel row HLi.

[0080] The Q node is charged by receiving a start signal or a previous carrier signal carry[i-3], or discharged by receiving a signal or a subsequent carrier signal carry[i+3]. The carrier signals received by the i-th stage are not limited to i±3, but can vary depending on the design.

[0081] The first pull-up transistor Tpu_CR has a gate electrode connected to the Q node, a drain electrode to which a carrier clock CRCLK is applied, and a source electrode connected to a first output terminal n1. When the Q node is charged, the first pull-up transistor Tpu_CR outputs a carrier signal carry[i] to the first output terminal n1 using the carrier clock CRCLK applied to the drain electrode.

[0082] The second pull-up transistor Tpu_SC has a gate electrode connected to the Q node, a drain electrode to which a scan clock SCCLK is applied, and a source electrode connected to a second output terminal n2. When the Q node is charged, the second pull-up transistor Tpu_SC outputs a scan signal SCAN[i] to the second output terminal n2 using the scan clock SCCLK applied to the drain electrode.

[0083] The third pull-up transistor Tpu_SE has a gate electrode connected to the Q node, a drain electrode to which a sampling clock SECLK is applied, and a source electrode connected to a third output terminal n3. When the Q node is charged, the third pull-up transistor Tpu_SE outputs a sampling signal SEN[i] to the third output terminal n3 using the sampling clock SECLK applied to the drain electrode.

[0084] The first pulldown transistor Tpd_CR has a gate electrode connected to a QB node, a drain electrode connected to an input terminal of the low-potential voltage VSS, and a source electrode connected to the first output terminal n1. The first pulldown transistor Tpd_CR discharges the first output terminal n1 to the low-potential voltage VSS in response to a QB node voltage.

[0085] The second pulldown transistor Tpd_SC has a gate electrode connected to the QB node, a drain electrode connected to the input terminal of the low-potential voltage VSS, and a source electrode connected to the second output terminal n2. The second pulldown transistor Tpd_SC discharges the second output terminal n2 to the low-potential voltage VSS in response to the QB node voltage.

[0086] The third pulldown transistor Tpd_SE has a gate electrode connected to the QB node, a drain electrode connected to the input terminal of the low-potential voltage VSS, and a source electrode connected to the third output terminal n3. The third pulldown transistor Tpd_SE discharges the third output terminal n3 to the low-potential voltage VSS in response to the QB node voltage.

[0087] An inverter INV controls the voltages of the Q node and the QB node in opposite directions.

[0088] The gate driver according to the present disclosure controls zk pixel rows during one cycle within one frame period. One cycle includes an image data write period, a black data insertion period, and a precharge period. A period in which image data is written to one pixel row can be defined as a horizontal period 1H, and the black data insertion period BDI and the precharge period can each correspond to a horizontal period 1H. The black data insertion period BDI is repeated k times within one cycle. The precharge period Pre comes after the black data insertion period BDI. The precharge period Pre is a period following the black data insertion period BDI and in which the gate nodes of the pixels connected to the next pixel row are precharged.

[0089] In other words, in one cycle according to the present disclosure, (z+2) horizontal periods are repeated k times, which include an image data write period corresponding to z horizontal periods (z≧2), a black data insertion period corresponding to one horizontal period, and a precharge period corresponding to one horizontal period. First exemplary embodiment

[0090] The gate driver according to the first exemplary embodiment drives 16 pixel rows during one cycle.

[0091] That is, an image data write period lasts 8 horizontal periods within 1 / 2 a cycle, then a black data write period lasts 1 horizontal period, and then a precharge period lasts 1 horizontal period. In this way, 10 horizontal periods are repeated once more to drive 8 pixel rows, and as a result, the gate driver according to the first exemplary embodiment drives 16 pixel rows during a cycle of 20 horizontal periods.

[0092] The Fig. 7 and Fig. 8 are views showing Q node voltage variation of stages in the gate driver according to the first exemplary embodiment. Fig. 9 is a view showing carrier clocks, scan clocks, and sampling clocks according to the first exemplary embodiment. Fig. 10 and Fig. 11 are views showing how the stages and the carrier clocks, scan clocks, and sample clocks are connected. Of the horizontal periods shown in the Fig. 7 to 9, the periods indexed by numbers (e.g., 0, 1, 2, etc.) denote image data writing periods, BDI denotes black data insertion periods, and Pre denotes precharge periods. Hereinafter, an i-th horizontal period refers to an image data writing period in which image data is written into an (i+16j)-th pixel row (j is an integer greater than or equal to 0; 0 <i+16j≤Gesamtzahl von Pixelzeilen) geschrieben werden. Ein Signal zum An- oder Ausschalten des Q-Knoten korrespondiert zu einer Stufe, die ein Trägersignal zu einem korrespondierenden Zeitpunkt ausgibt. D.h., ein Signal zum Anschalten des Q-Knoten einer fünften Stufe ist ein Trägersignal, das von einer ersten Stufe ausgegeben wird, und ein Signal zum Ausschalten des Q-Knoten der fünften Stufe ist ein Trägersignal, das von einer neunten Stufe ausgegeben wird.

[0093] The scan cycles that Fig. 9 determine the timing of the scan signal and the sampling clocks, which are shown in Fig. 9 determine the timing of a scanning signal. That is, when the scanning clocks have a turn-on voltage, the stages output a scanning signal, and when the scanning clocks have a turn-on voltage, the stages output a scanning signal.

[0094] As a result, the gate driver according to the first exemplary embodiment sequentially outputs a scan signal and a sample signal during an image data write period corresponding to 8 horizontal periods. Then, during a black data write period, the gate driver simultaneously supplies a scan signal to a plurality of pixel rows. Furthermore, the gate driver outputs a scan signal and a sample signal during a precharge period.

[0095] As in Fig. As shown in Figure 9, the carrier clocks CRCLK, the scan clocks SCCLK, and the sample clocks SECLK each have 16 phases. The carrier clocks CRCLK, the scan clocks SCCLK, and the sample clocks SECLK each have a cycle of 20 horizontal periods. One cycle is a period in which 16 pixel rows are driven.

[0096] The turn-on voltage of the carrier clocks CRCLK, scan clocks SCCLK, and sample clocks SECLK is maintained for two horizontal periods (2H), and then a turn-off voltage is maintained for eight horizontal periods (8H). The turn-on voltage of the 1st to 16th carrier clocks CRCLK1 to CRCLK16 can be divided into an image write clock and a black data write clock. The image write clock and the black data write clock alternate. That is, the image write clock is inverted into the turn-off voltage, and the black data write clock has the turn-off voltage after eight horizontal periods.

[0097] The first through 16th carrier clocks CRCLK1 through CRCLK16 are output sequentially during the image data write period, while maintaining the turn-on voltage for two horizontal periods. The ninth through 16th scan clocks SCCLK9 ​​through SCCLK16 maintain the turn-on voltage during a first black data insertion period, and the first through eighth scan clocks SCCLK1 through SCCLK8 maintain the turn-on voltage during a second black data insertion period.

[0098] The first to 16th carrier clocks CRCLK1 to CRCLK16 are sequentially output during the image data write period while the turn-on voltage is maintained during the 2 horizontal periods.

[0099] Referring to the Fig. 10 and Fig. 11, the first carrier clocks CRCLK, the first scan clocks SCCLK, and the first sample clocks SECLK are connected to the first stage STG. The second carrier clock CRCLK, the second scan clock SCCLK, and the second sample clock SECLK are connected to the second stage STG. Similarly, the ith (i is a natural number less than or equal to 16) carrier clock CRCLK, the ith scan clock SCCLK, and the ith sample clock SECLK are connected to the first stage STG.

[0100] In the first exemplary embodiment, the duty cycle of one light emission period can be set to (16n+8) lines / number of frame lines. The number of frame lines is the sum of the total number of pixel lines and the number of lines corresponding to one vertical darkening interval. In this specification, the duty cycle is defined as the time interval between every two pixel lines, which runs from the time an image data write carrier clock is input to a specific stage to the time a black data insert carrier clock is input to the STG stage.

[0101] The actual insertion of black data into the pixels does not occur at a time when a black data insertion carrier clock is applied, but during a black data insertion period BDI in which a black data insertion scan clock is applied while the Q node of the STG stage is in a charged state. In the present disclosure, a scan signal SCAN for writing image data is output sequentially, and a scan signal SCAN for inserting black data is simultaneously written to a plurality of pixel rows HL during 1 horizontal period. Therefore, each pixel row HL has a slightly different duty cycle for an image display period.

[0102] In the present specification, the duty cycle is defined relative to a time at which a carrier clock CRCLK is input to a stage for loading the Q node, and not relative to an actual image display period.

[0103] For example, if the pixel lines displaying an image on the display panel 10 consist of the first to 2160th pixel lines HL1 to HL2160, there is no dimming interval, and if n is set to 67, the duty cycle is 1080 / 2160 (i.e., (16×67+8) / 2160). That is, if n is set to 67, a display device with 2160 pixel lines has a 50% duty cycle according to the first exemplary embodiment. If the dimming interval corresponds to 320 lines and n is set to 67, the duty cycle is 1080 / 2480, i.e., 43.55%.

[0104] The function of the gate driver during 1 frame according to the first exemplary embodiment when n=67 will be described below.

[0105] While the Q node of the first stage STG is in a charged state, the first stage STG outputs the first carrier signal in response to the first carrier clock CRCLK during the first horizontal period 1H. Then, the first stage STG outputs the first scan signal SCAN in response to the first scan clock SCCLK and outputs the first sampling signal SEN in response to the first sampling clock SECLK. As a result, data is written to the pixels of the first pixel row HL1 during the first horizontal period 1H.

[0106] Similarly, the pixels in the second pixel row HL2 are programmed during the second horizontal period 2H. Then, the pixels in the first pixel row HL1 emit light based on data programmed during the first horizontal period 1H.

[0107] In this line-sequential method, data is sequentially written into the pixels formed in the first to fourth pixel rows HL1 to HL4 during the first to fourth horizontal periods 1H to 4H.

[0108] Next, during the first black data insertion period BDI, the ninth to 16th scan clocks SCCLK9 ​​to SCCLK16 are applied at the power-up voltage, outputting the ninth to 16th scan signals. The pixel rows to which the ninth to 16th scan signals SCAN output during the first black data insertion period BDI are applied may vary depending on the duty cycle.

[0109] Using the line-sequential method, the first to 1072nd pixel lines HL1 to HL1072 sequentially emit light during the first to 1072nd horizontal periods 1H to 1072H. In the black data insertion period BDI, which occurs every 8th line, corresponding to 10 horizontal periods from the first to 1072nd horizontal periods 1H to 1072H, black data is input to a specific group of pixel lines comprising 8 pixel lines, from the 1073rd to the 2160th pixel lines HL1073 to HL2160, indicating the previous frame.

[0110] The 1073rd to 1080th horizontal periods 1080H are periods in which image data is written to the 1073rd to 1080th pixel lines HL, which correspond to operation times ranging from the first horizontal period 1H to the eighth horizontal period 8H.

[0111] When n is set to 67, a carrier clock for inserting black data into the first pixel line is input to the 1081st pixel line, which has a pixel line interval of (16×67+8=1080).

[0112] The operating times in the 1081st to 1088th horizontal periods 1081H to 1088H correspond to the operating times in the first horizontal period 1H to the eighth horizontal period 8H. After the scan signals are sequentially output during the 1081st horizontal period 1081H to the 1084th horizontal period 1084H, the first to eighth scan signals are output during the subsequent black data insertion period BDI, corresponding to the timing of the first to eighth scan clocks SCCLK. The pixels formed in the first to eighth pixel rows HL1 to HL8 are supplied with black data by the first to eighth scan signals output during the black data insertion period BDI. Second exemplary embodiment

[0113] Fig. 12 is a view showing timings of carrier clocks, scan clocks, and sampling clocks for controlling stages according to the second exemplary embodiment. Fig. 13 and Fig. 14 are views showing how the stages and the carrier clocks, scan clocks, and sample clocks are connected. Of the horizontal periods shown in Fig. 12, the periods indexed by numbers denote image data writing periods, BDI denotes black data insertion periods, and Pre denotes precharge periods. Hereinafter, an i-th horizontal period refers to an image data writing period in which image data is written into an (i+32j)-th pixel row (j is an integer greater than or equal to 0, 0 <i+32j≤Gesamtzahl von Pixelzeilen) geschrieben werden.

[0114] As in Fig. As shown in Figure 12, the carrier clocks CRCLK, scan clocks SCCLK, and sampling clocks SECLK each have 16 phases. The carrier clocks CRCLK, scan clocks SCCLK, and sampling clocks SECLK each have a cycle of 40 horizontal periods. In the second exemplary embodiment, the gate driver 13 controls 32 pixel rows during one cycle. In one cycle, the black data insertion period BDI occurs four times, and the precharge period also occurs four times.

[0115] The turn-on voltage of the first through 16th carrier clocks CRCLK1 through CRCLK16 can be split between a video clock and a BDI clock. The first through 16th carrier clocks CRCLK1 through CRCLK16 maintain the turn-on voltage for 2 horizontal periods and the turn-off voltage for 8 horizontal periods.

[0116] In one cycle, the first and second applied turn-on voltages of the first to eighth carrier clocks CRCLK1 to CRCLK8 correspond to image clocks, and the third and fourth applied turn-on voltages correspond to BDI clocks. In one cycle, the first and second applied turn-on voltages of the ninth to 16th carrier clocks CRCLK9 to CRCLK16 correspond to BDI clocks, and the third and fourth voltages correspond to image clocks. In this specification, the application of clocks refers to the application of clocks with a turn-on voltage level. That is, the second turn-on voltage of the first carrier clock refers to the turn-on voltage applied during the eighth and ninth horizontal periods 8H and 9H.

[0117] The first through 16th scan clocks SCCLK1 through SCCLK16 have clocks synchronized with the image clocks of the first through 16th carrier clocks CRCLK1 through CRCLK16. Furthermore, the first through eighth scan clocks SCCLK1 through SCCLK8 maintain the turn-on voltage during the third and fourth black data insertion periods BDI, and the ninth through 16th scan clocks SCCLK9 ​​through SCCLK16 maintain the turn-on voltage during the first and second black data insertion periods BDI.

[0118] The first to 16th sampling clocks SECLK1 to SECLK16 are synchronized with the image clocks of the first to 16th carrier clocks CRCLK1 to CRCLK16.

[0119] Referring to the Fig. 13 and Fig. 14, the first to eighth stages STG1 to STG8 are sequentially connected to the first to eighth carrier clocks CRCLK1 to CRCLK8, the first to eighth scan clocks SCCLK1 to SCCLK8, and the first to eighth sample clocks SECLK1 to SECLK8. Furthermore, the ninth to 24th stages STG9 to STG24 are sequentially connected to the first to 16th carrier clocks CRCLK1 to CRCLK16, the first to 16th scan clocks SCCLK1 to SCCLK16, and the first to 16th sample clocks SECLK1 to SECLK16. Consequently, the 25th to 32nd stages STG25 to STG32 are sequentially connected to the 9th to 16th carrier clocks CRCLK9 to CRCLK16, the 9th to 16th scan clocks SCCLK9 ​​to SCCLK16, and the 9th to 16th sample clocks SECLK9 to SECLK16.

[0120] The operation of the gate driver during a cycle according to the second exemplary embodiment is described below.

[0121] The gate driver according to the second exemplary embodiment drives 32 pixel rows during one cycle. Fig. 12, the -3rd horizontal period -3H to the 0th horizontal period 0H correspond to the previous frame drive period. The precharge period, not shown in the drawing, and the 29th to 32nd horizontal periods following the precharge period have the same operating times as the -3rd horizontal period -3H to the 0th horizontal period 0H.

[0122] The first to fourth stages STG1 to STG4 according to the second exemplary embodiment output first to fourth scanning signals and first to fourth sampling signals during the first horizontal period 1H to the fourth horizontal period 4H. As a result, the first to fourth pixel lines HL1 to HL4 are sequentially supplied with data during the first to fourth horizontal periods 1H to 4H.

[0123] The gate driver 13 outputs ninth to 16th scan signals during the subsequent black data insertion period BDI.

[0124] Then, the precharge period occurs, and the fifth to eighth stages STG5 to STG8 output fifth to eighth scanning signals and fifth to eighth sampling signals during the fifth horizontal period 5H to the eighth horizontal period 8H. As a result, the fifth to eighth pixel lines HL5 to HL8 are sequentially supplied with data during the fifth to eighth horizontal periods 5H to 8H.

[0125] Next, the ninth to twelfth stages STG9 to STG12 output first to fourth scanning signals and first to fourth sampling signals during the ninth horizontal period 9H to the twelfth horizontal period 12H. As a result, the ninth to twelfth pixel lines HL9 to HL12 are sequentially supplied with data during the ninth to twelfth horizontal periods 9H to 12H.

[0126] The ninth to 16th scan signals are output simultaneously during the black data insertion period BDI following the 12th horizontal period 12H.

[0127] Then, the precharge period occurs, and the 13th to 20th stages STG13 to STG20 output 13th to 20th scanning signals and 13th to 20th sampling signals (for example, the scanning and sampling signals of the 5th to 12th scanning clocks SCCLK5 to SCCLK12 and sampling clocks SECLK5 to SECLK12, as shown in the Fig. 12 and Fig. 13). As a result, the 13th to 20th pixel rows HL13 to HL20 are supplied with data sequentially.

[0128] The gate driver 13 outputs first to ninth scanning signals during the black data insertion period BDI following the 20th horizontal period 20H.

[0129] Then, a 21st scan signal and a 21st sampling signal (for example, the scan and sampling signal of the 13th scan clock SCCLK13 and the 13th sampling clock SECLK13, as shown in the Fig. 12 and Fig. 13) during the precharge period.

[0130] The 21st to 24th stages STG21 to STG24 output 21st to 24th scan signals and 21st to 24th sample signals (for example, the scan and sample signals of the 13th to 16th scan clocks SCCLK13 to SCCLK16 and sample clocks SECLK13 to SECLK16, as shown in the Fig. 12 and Fig. 13) during the 21st horizontal period (21H) to the 24th horizontal period (24H). As a result, the 21st to 24th pixel rows are supplied with data.

[0131] The 25th to 28th stages STG25 to STG28 output 25th to 28th scan signals and 25th to 28th sample signals (for example, the scan and sample signals of the 9th to 12th scan clocks SCCLK9 ​​to SCCLK12 and sample clocks SECLK9 to SECLK12, as shown in the Fig. 12 and Fig. 13) during the 25th horizontal period 25H to the 28th horizontal period 28H. As a result, the 25th to 28th pixel rows are supplied with data.

[0132] In the second exemplary embodiment, the duty cycle of one light emission period may be set to (32n+16) lines / number of frame lines.

[0133] For example, when the pixel lines displaying an image on the display panel 10 consist of the first to 2160th pixel lines HL1 to HL2160 and n is set to 33, the duty cycle is 1072 / 2160. That is, when n is set to 33, a display device with 2160 pixel lines has a 49.63% duty cycle according to the second exemplary embodiment. That is, when n is set to 33, during the black data insertion period BDI, which comes immediately after 1072 horizontal lines, black data is written to the first to eighth pixel lines. Third exemplary embodiment

[0134] Fig. 15 is a view showing timings of carrier clocks, scan clocks, and sampling clocks according to the third exemplary embodiment. Fig. 16 to 18 are views showing how the stages and the carrier clocks, scan clocks, and sample clocks are connected.

[0135] As in Fig. As shown in Figure 15, the carrier clocks CRCLK have 16 phases, and the scan clocks SCCLK and SECLK each have 12 phases. The carrier clocks CRCLK, scan clocks SCCLK, and SECLK have a cycle of 60 horizontal periods. In the third exemplary embodiment, the gate driver 13 controls 48 pixel rows during one cycle. In one cycle, the black data insertion period BDI occurs six times, and the precharge period also occurs six times.

[0136] The turn-on voltage of the first to 16th carrier clocks CRCLK1 to CRCLK16 can be divided into a video clock and a BDI clock. The first to 16th carrier clocks CRCLK1 to CRCLK16 maintain the turn-on voltage for 2 horizontal periods and the turn-off voltage for 8 horizontal periods.

[0137] In a cycle, the first to third turn-on voltages of the first to eighth carrier clocks (CRCLK1 to CRCLK8) correspond to image clocks, and the fourth to sixth turn-on voltages correspond to BDI clocks. In a cycle, the first to third turn-on voltages of the ninth to 16th carrier clocks (CRCLK9 to CRCLK16) correspond to BDI clocks, and the fourth to sixth turn-on voltages correspond to image clocks.

[0138] The first to sixth scan clocks SCCLK1 to SCCLK6 are output sequentially four times during the first to 24th horizontal periods 1H to 24H. The seventh to 12th scan clocks SCCLK7 to SCCLK12 are output sequentially four times during the 25th to 48th horizontal periods 25H to 48H. Furthermore, the first to sixth scan clocks SCCLK1 to SCCLK6 maintain the turn-on voltage during the fourth to sixth black data insertion periods BDI, and the seventh to 12th scan clocks SCCLK7 to SCCLK12 maintain the turn-on voltage during the first to third black data insertion periods BDI.

[0139] The first to 12th sampling clocks SECLK1 to SECLK12 are synchronized with the image clocks of the first to 12th scanning clocks SCCLK1 to SCCLK12.

[0140] Referring to the Fig. 16 and Fig. 17, the first to eighth stages STG1 to STG8 are sequentially connected to the first to eighth carrier clocks CRCLK1 to CRCLK8, and the ninth to 16th stages STG9 to STG16 are sequentially connected to the first to eighth carrier clocks CRCLK1 to CRCLK8. The 17th to 32nd stages STG17 to STG32 are sequentially connected to the first to 16th carrier clocks CRCLK1 to CRCLK16. The 33rd to 40th stages STG33 to STG40 are sequentially connected to the ninth to 16th carrier clocks CRCLK9 to CRCLK16, and the 41st to 48th stages STG41 to STG48 are sequentially connected to the ninth to 16th carrier clocks CRCLK9 to CRCLK16.

[0141] Referring to the Fig. 16 to 17, the first to sixteenth stages STG1 to STG6 are sequentially connected to the first to sixth scan clocks SCCLK1 to SCCLK6 and sequentially connected to the first to sixth sample clocks SECLK1 to SECLK6. Furthermore, the seventh to twelfth stages STG7 to STG12 are sequentially connected to the first to sixth scan clocks SCCLK1 to SCCLK6 and sequentially connected to the first to sixth sample clocks SECLK1 to SECLK6. The thirteenth to eighteenth stages STG13 to STG18 are sequentially connected to the first to sixth scan clocks SCCLK1 to SCCLK6 and sequentially connected to the first to sixth sample clocks SECLK1 to SECLK6. The 19th to 30th stages STG19 to STG30 are sequentially connected to the first to 12th scan clocks SCCLK1 to SCCLK12 and sequentially connected to the first to 12th sample clocks SECLK1 to SECLK12.The 31st to 36th stages STG31 to STG36 are sequentially connected to the seventh to 12th scan clocks SCCLK1 to SCCLK12 and sequentially connected to the seventh to 12th sample clocks SECLK7 to SECLK12. The 37th to 42nd stages STG37 to STG42 are sequentially connected to the seventh to 12th scan clocks SCCLK7 to SCCLK12 and sequentially connected to the seventh to 12th sample clocks SECLK7 to SECLK12. The 34th to 48th stages STG43 to STG48 are sequentially connected to the seventh to 12th scan clocks SCCLK7 to SCCLK12 and sequentially connected to the seventh to 12th sample clocks SECLK7 to SECLK12.

[0142] As with the first and second exemplary embodiments, the gate driver according to the third exemplary embodiment outputs a scan signal and a sampling signal synchronized with the timing of the scan clock and the sampling clock. A detailed description of how a pixel operates using the scan signal and the sampling signal is omitted because it is similar or identical to what was described in the previous exemplary embodiments.

[0143] In the third exemplary embodiment, the duty cycle of one light emission period may be set to (48n+24) lines / number of frame lines.

[0144] For example, if the pixel lines displaying an image on the display panel 10 consist of the first to 2160th pixel lines HL1 to HL2160, and n is set to 22, the duty cycle is 1080 / 2160. That is, if n is set to 22, a display device with 2160 pixel lines according to the third exemplary embodiment has a 50% duty cycle. That is, if n is set to 22, during the black data insertion period BDI immediately following 1080 horizontal lines, black data is written to the first to eighth pixel lines. Fourth exemplary embodiment

[0145] Fig. 19 is a view showing timings of carrier clocks, scan clocks, and sampling clocks according to the fourth exemplary embodiment. Fig. 20 and Fig. 21 are views showing how the stages and the carrier clocks, scan clocks and sample clocks are connected.

[0146] As in Fig. As shown in Figure 19, the carrier clocks CRCLK, scan clocks SCCLK, and sample clocks SECLK each have 12 phases. The carrier clocks CRCLK, scan clocks SCCLK, and sample clocks SECLK have a cycle of 60 horizontal periods. In the fourth exemplary embodiment, the gate driver 13 controls 48 pixel rows during one cycle. In one cycle, the black data insertion period BDI occurs six times, and the precharge period also occurs six times.

[0147] The turn-on voltage of the first to 12th carrier clocks CRCLK1 to CRCLK12 can be divided into a video clock and a BDI clock. The first to 12th carrier clocks CRCLK1 to CRCLK12 maintain the turn-on voltage for 2 horizontal periods and the turn-off voltage for 8 horizontal periods.

[0148] In one cycle, the first to fourth turn-on voltages of the first to sixth carrier clocks CRCLK1 to CRCLK6 correspond to image clocks, and the fifth to eighth turn-on voltages correspond to BDI clocks. In one cycle, the first to fourth turn-on voltages of the seventh to 12th carrier clocks CRCLK7 to CRCLK12 correspond to BDI clocks, and the fifth to eighth turn-on voltages correspond to image clocks.

[0149] The first to sixth scan clocks SCCLK1 to SCCLK6 are output sequentially four times during the first to 24th horizontal periods 1H to 24H. The seventh to 12th scan clocks SCCLK7 to SCCLK12 are output sequentially four times during the 25th to 48th horizontal periods 25H to 48H. Furthermore, the first to sixth scan clocks SCCLK1 to SCCLK6 maintain the turn-on voltage during the first to sixth black data insertion periods BDI, and the seventh to 12th scan clocks SCCLK7 to SCCLK12 maintain the turn-on voltage during the first to third black data insertion periods BDI.

[0150] The first to 12th sampling clocks SECLK1 to SECLK12 are synchronized with the image clocks of the first to 12th scanning clocks SCCLK1 to SCCLK12.

[0151] Referring to the Fig. 20 and Fig. 21, the first to sixth stages STG1 to STG6 are sequentially connected to the first to sixth carrier clocks CRCLK1 to CRCLK6, sequentially connected to the first to sixth scan clocks SCCLK1 to SCCLK6, and sequentially connected to the first to sixth sample clocks SECLK1 to SECLK6. The seventh to twelfth stages STG7 to STG12 are sequentially connected to the first to sixth carrier clocks CRCLK1 to CRCLK6, sequentially connected to the first to sixth scan clocks SCCLK1 to SCCLK6, and sequentially connected to the first to sixth sample clocks SECLK1 to SECLK6. Furthermore, the 13th to 18th stages STG13 to STG18 are sequentially connected to the first to sixth carrier clocks CRCLK1 to CRCLK6, sequentially connected to the first to sixth scan clocks SCCLK1 to SCCLK6, and sequentially connected to the first to sixth sample clocks SECLK1 to SECLK6.

[0152] The 19th to 30th stages STG19 to STG13 are sequentially connected to the first to 12th carrier clocks CRCLK1 to CRCLK12, sequentially connected to the first to 12th scan clocks SCCLK1 to SCCLK12, and sequentially connected to the first to 12th sample clocks SECLK1 to SECLK12.

[0153] The 31st to 36th stages STG31 to STG36 are sequentially connected to the seventh to 12th carrier clocks CRCLK7 to CRCLK12, sequentially connected to the seventh to 12th scan clocks SCCLK7 to SCCLK12, and sequentially connected to the seventh to 12th sample clocks SECLK7 to SECLK12.

[0154] The 37th to 42nd stages STG37 to STG42 are sequentially connected to the seventh to 12th carrier clocks CRCLK7 to CRCLK12, sequentially connected to the seventh to 12th scan clocks SCCLK7 to SCCLK12, and sequentially connected to the seventh to 12th sample clocks SECLK7 to SECLK12.

[0155] The 43rd to 48th stages STG43 to STG48 are sequentially connected to the seventh to 12th carrier clocks CRCLK7 to CRCLK12, sequentially connected to the seventh to 12th scan clocks SCCLK7 to SCCLK12, and sequentially connected to the seventh to 12th sample clocks SECLK7 to SECLK12.

[0156] As with the previous exemplary embodiments, the gate driver according to the fourth exemplary embodiment outputs a scan signal and a sampling signal synchronized with the timing of a scan clock and a sampling clock. A detailed description of how a pixel operates using the scan signal and the sampling signal will be omitted because it is similar or identical to what was described in the previous exemplary embodiments.

[0157] In the fourth exemplary embodiment, the duty cycle of one light emission period may be set to (48n+24) lines / number of frame lines.

[0158] For example, if the pixel lines displaying an image on the display panel 10 consist of the first to 2160th pixel lines HL1 to HL2160, and n is set to 22, the duty cycle is 1080 / 2160. That is, if n is set to 22, according to the fourth exemplary embodiment, a display device with 2160 pixel lines has a 50% duty cycle. That is, if n is set to 22, black data is written to the first to eighth pixel lines during the black data insertion period BDI, which occurs immediately after 1080 horizontal lines.

[0159] As described above, the organic light-emitting display device according to the present disclosure can improve a motion picture response time (MPRT) by using a black data display period. Specifically, the organic light-emitting display device according to the present disclosure can display black data without changing the drive frequency. That is, it is possible to improve the motion picture response time by inserting black data without reducing the length of a programming period.

[0160] Furthermore, the organic light-emitting display unit according to the present disclosure can easily vary the duty cycle in accordance with the n value. When a fast-moving image is displayed, the duty cycle is reduced to improve MPRT, and when a steady pattern is displayed, the duty cycle is reduced to nearly 100% to prevent flickering. The duty cycle can be adjusted for each frame using image processing, providing the user with the best image quality.

[0161] As discussed above, the present disclosure enables driving pixel rows in separate blocks and enables BDI by sequentially writing an image to one block of pixel rows using an image clock signal and simultaneously writing black data to the subsequent block of pixel rows using a BDI clock signal.

[0162] Fig. 22 is a view showing a Q-node voltage variation of stages according to the foregoing first to fourth exemplary embodiments. In Fig. 22, the reference symbol 'Out' denotes stages that output a carrier signal, the reference symbol 'Q high' denotes stages that do not output a carrier signal but maintain the turn-on voltage. The reference symbol 'Q low' denotes stages in which the Q node has the turn-off voltage. In Fig. 22, the horizontal axis represents a first to eighth horizontal period and a black data insertion period BDI and a precharge period Pre inserted therebetween. In Fig. 22 represents the vertical axis steps. In Fig. In Figure 22, dotted lines indicate that the output of the corresponding stage is used as a carrier signal to charge the Q node of the subsequent stage, and solid lines indicate that the output of the corresponding stage is used as a carrier signal to set the Q node of the preceding stage to the off-voltage. The stage preceding the kth stage is one of the first to (k-1)th stages, and the stage following the kth stage is one of the (k+1)th to last stages.

[0163] Referring to Fig. 22, in the display device according to the foregoing first to fourth exemplary embodiments, during the black data insertion period BDI of the present disclosure, black data is written simultaneously to 8 pixel lines. To write the black data simultaneously to 8 pixel lines, the Q nodes of the (8k+1)th stage STG[8k+1] to the (8k+8)th stage STG[8k+8] maintain the turn-on voltage during the black data insertion period BDI. Although the (8k+1)th stage STG[8k+1] to the (8k+8)th stage STG[8k+8] do not output a carrier signal during the black data insertion period BDI, the Q nodes of these stages maintain the turn-on voltage. This is because in the black data insertion period BDI, a scan signal SCAN must be output through the second output terminal n2 even if the first to third output terminals n1 to n3 maintain the off voltage.In addition, the Q nodes that maintain the turn-on voltage in the black data insertion period BDI have a turn-on voltage for stages that are turned on in the precharge period Pre.

[0164] Consequently, during the precharge period Pre, the (8k+5)th stage STG[8k+5] outputs an (8k+5)th carrier signal CARRY[8k+5] in response to a carrier clock signal applied to the first pull-up transistor Tpu_CR.

[0165] In order for the Q nodes of the eighth stage to maintain the charged state in the black data insertion period BDI, the Q node of each pixel row must remain switched on for a minimum of (8x1) horizontal periods, as shown in the Fig. 7 and Fig. 8. Accordingly, as shown in Fig. 6, while an (i-3)th carrier signal CARRY(i-3) is used to charge the Q nodes of the stages, an (i+5)th carrier signal CARRY(i+5) is used to set the Q node to the turn-off voltage.

[0166] Furthermore, in the present disclosure, due to the large black data insertion period BDI in which no carrier signal is output, the carrier signals applied to the stages are different from the carrier signals applied to an ordinary shift register. That is, in the ordinary shift register, the interval between the application of the carrier signal to the stages and the bootstrapping of the Q nodes is the same. However, in the present disclosure, the interval between the application of the carrier signals to the stages and the bootstrapping of the Q nodes may vary due to the black data insertion period BDI, as shown in Fig. 22. For example, during the fifth horizontal period, the Q node of the (8k+1)th stage STG[8k+1] is reset by the carrier signal of the (8k+6)th stage STG[8k+6] corresponding to the outputs of the (i+5)th stage. In contrast, during the fifth horizontal period, the Q node of the (8k+2)th stage STG[8k+2] is reset by the carrier signal of the (8k+6)th stage STG[8k+6] corresponding to the outputs of the (i+4)th stage.

[0167] Even if there is a difference in the time period during which the Q node maintains the loaded state relative to the output times of the stages, the shift register will operate without problems. However, changing the scan direction of the shift register can cause malfunction.

[0168] This is described in further detail below.

[0169] A conventional shift register generates scan pulses in a single direction—that is, from the topmost level to the bottommost level. As the application range of display devices expands, a control circuit element arranged on the display panel is not limited to a specific position. To apply the display panel to various display formats, a bidirectional shift register can be used. This is a single shift register that outputs a scan pulse from either the topmost or the bottommost level.

[0170] In the shift register, the operation of the stages includes a set function for charging the Q node with the turn-on voltage and a reset function for discharging the Q node to the turn-off voltage.

[0171] In the shift register, the forward and reverse outputs are opposite in the set function and the reset function. That is, the set function for the forward output is the reset function for the reverse output, and the reverse function for the reverse output is the set function for the forward output.

[0172] Accordingly, a clock signal for controlling the set function and a clock signal for controlling the reset function must be symmetrical.

[0173] Fig. 23 is a view showing a reverse output of the carrier signal generated in Fig. 22. In a bidirectional shift register based on the carrier signals that are Fig. 22, a voltage margin at the Q node may be insufficient in some parts, as shown in Fig. 23 shown.

[0174] This is because in a forward scan mode and a reverse scan mode, a transistor that charges the Q node and a transistor that discharges the Q node play opposite roles. That is, the transistor that charges the Q node in the forward scan mode discharges the Q node in the reverse scan mode, and the transistor that discharges the Q node in the forward scan mode charges the Q node in the reverse scan mode.

[0175] Therefore, if the interval between the loading of the Q-nodes and the initial input of the Q-nodes in the stages differs from the interval between the unloading of the Q-nodes and the initial input of the Q-nodes, as in Fig. 22, the eighth stages may not be able to maintain the turn-on voltage in the pre-charge period Pre, as shown in Fig. 23 shown.

[0176] Next, an example of a shift register capable of bidirectional scanning while using clock signals explained with the first to fourth exemplary embodiments will be described.

[0177] Fig. 24 is a view showing a bidirectional shift register, and Fig. 25 is a view showing the nth stage of the bidirectional shift register used in Fig. 24 is shown.

[0178] Referring to Fig. 24, the shift register comprises nth stages STG1 to STGn. The first to nth stages STG1 to STGn control the Q nodes via a Q node control unit T1 and T2 and sequentially output carrier signals. The Q node control units T1 and T2 comprise first and second transistors T1 and T2. The first transistor T1 receives a forward carrier signal CARRY_F, and the second transistor T2 receives a reverse carrier signal CARRY_R.

[0179] In the forward scan mode, the first transistor T1 charges the Q node in response to the forward carrier signal CARRY_F and resets the Q node to the turn-off voltage in response to the reverse carrier signal CARRY_R.

[0180] In the reverse scan mode, the second transistor T2 charges the Q node in response to the reverse carrier signal CARRY_R and resets the Q node to the turn-off voltage in response to the forward carrier signal CARRY_F.

[0181] Referring to Fig. 25, the nth stage STG[n] of the bidirectional shift register comprises a first transistor T1, a second transistor T2, a Q-node holding element T3, an inverter element, first to third pull-up transistors Tpu_CR, Tpu_SC, and Tpu_SE, and first to third pull-down transistors Tpd_CR, Tpd_SC, and Tpd_SE.

[0182] In Fig. 25, a forward control voltage VDD_F and a reverse control voltage VDD_R vary with the scan mode. Table 1 below shows the voltage levels of the forward control voltage and the reverse control voltage in different scan modes. [Table 1] Vorwärts-Scanmodus Rückwärts-Scanmodus VDD_F VGH VGL VDD_R VGL VGH

[0183] Referring to Table 1, the forward control voltage VDD_F maintains the high potential voltage (VGH) of the turn-on voltage level in the forward scan mode and maintains the low potential voltage (VGL) of the turn-off voltage level in the reverse scan mode. The reverse control voltage VDD_R maintains the high potential voltage of the turn-on voltage level in the reverse scan mode and maintains the low potential voltage of the turn-off voltage level in the forward scan mode.

[0184] The first transistor T1 has a gate electrode receiving the forward carrier signal CARRY_F, a drain electrode connected to an input terminal of the forward control voltage VDD_F, and a source electrode connected to the Q node.

[0185] The second transistor T2 has a gate electrode receiving the reverse carrier signal CARRY_R, a drain electrode connected to the Q node, and a source electrode connected to an input terminal of the reverse control voltage VDD_R.

[0186] The Q-node holding element T3 applies the turn-off voltage to the Q-node when a QB-node has the turn-on voltage. In this regard, the Q-node holding element T3 has a gate electrode connected to the QB-node, a drain electrode connected to the Q-node, and a source electrode connected to an input terminal of the low-potential voltage VGL.

[0187] The inverter element comprises a fourth transistor T4, a Q' pull-up transistor T4I, a Q' pull-down transistor T4q, a fifth transistor T5, a Qb pull-down transistor T5q, a forward QA pull-up transistor T5F and a reverse QA pull-up transistor T5R.

[0188] The fourth transistor T4 applies the turn-on voltage to the QB node when a Q' node has the turn-on voltage. In this regard, the fourth transistor T4 has a gate electrode connected to the Q' node, a drain electrode connected to an input terminal of the high-potential voltage VDD, and a source electrode connected to the QB node.

[0189] The Q' pull-up transistor T4I has a gate electrode and a drain electrode connected to the input terminal of the high-potential voltage VDD, and a source electrode connected to the Q' node. The Q' pull-up transistor T4I performs a diode function to stably supply the high-potential voltage VDD to the Q' node.

[0190] The Q' pulldown transistor T4q has a gate electrode connected to the Q node, a drain electrode connected to the Q' node, and a source electrode connected to the low-potential voltage input terminal VSS. The Q' pulldown transistor T4q maintains the turn-off voltage at the Q' node when the Q node is charged with the turn-on voltage.

[0191] The Qb pulldown transistor T5q has a gate electrode connected to the Q node, a drain electrode connected to the QB node, and a source electrode connected to the input terminal of the low-potential voltage VSS. The Qb pulldown transistor T5q maintains the low-potential voltage VSS at the QB node when the Q node has the turn-on voltage.

[0192] The fifth transistor T5 has a gate electrode connected to a QA node, a drain electrode connected to the QB node, and a source electrode connected to the input terminal of the low-potential voltage VSS.

[0193] The forward QA pull-up transistor T5F has a gate electrode receiving the forward carrier signal CARRY_F, a drain electrode connected to the input terminal of the forward control voltage VDD_F, and a source electrode connected to the QA node.

[0194] The reverse QA pull-up transistor T5R has a gate electrode receiving the reverse carrier signal CARRY_R, a drain electrode connected to the input terminal of the reverse control voltage VDD_R, and a source electrode connected to the QA node.

[0195] The first pull-up transistor Tpu_CR has a gate electrode connected to the Q node, a drain electrode that receives a carrier clock CRCLK, and a source electrode connected to a first output terminal n1. When the Q node is in the charged state, the first pull-up transistor Tpu_CR outputs a carrier signal CARRY[n] to the first output terminal n1 using the carrier clock CRCLK input to the drain electrode.

[0196] The second pull-up transistor Tpu_SC has a gate electrode connected to the Q node, a drain electrode that receives a scan clock SCCLK, and a source electrode connected to a second output terminal n2. When the Q node is in a charged state, the second pull-up transistor Tpu_SC outputs a scan signal SCAN[n] to the second output terminal n2 using the scan clock SCCLK input to the drain electrode (e.g., present at the drain electrode).

[0197] The third pull-up transistor Tpu_SE has a gate electrode connected to the Q node, a drain electrode that receives a sampling clock SECLK, and a source electrode connected to a third output terminal n3. When the Q node is in a charged state, the third pull-up transistor Tpu_SE outputs a sampling signal SEN[n] to the third output terminal n3 using the sampling clock SECLK input to the drain electrode (e.g., present at the drain electrode).

[0198] The first pulldown transistor Tpd_CR has a gate electrode connected to the QB node, a drain electrode connected to the input terminal of the low-potential voltage VSS, and a source electrode connected to the first output terminal n1. The first pulldown transistor Tpd_CR discharges the first output terminal n1 to the low-potential voltage VSS in response to a QB node voltage.

[0199] The second pulldown transistor Tpd_SC has a gate electrode connected to the QB node, a drain electrode connected to the input terminal of the low-potential voltage VSS, and a source electrode connected to the second output terminal n2. The second pulldown transistor Tpd_SC discharges the second output terminal n2 to the low-potential voltage VSS in response to the QB node voltage.

[0200] The third pulldown transistor Tpd_SE has a gate electrode connected to the QB node, a drain electrode connected to the input terminal of the low-potential voltage VSS, and a source electrode connected to the third output terminal n3. The third pulldown transistor Tpd_SE discharges the third output terminal n3 to the low-potential voltage VSS in response to the QB node voltage.

[0201] An example of the Q-node controller is described below.

[0202] Fig. 26 is a view showing carrier signals applied to the Q-node control unit according to the first exemplary embodiment. Fig. 27 is a view showing timings of carrier signals in the forward scan mode according to the first exemplary embodiment.

[0203] Fig. 28 is a view showing timings of carrier signals in the reverse scan mode according to the first exemplary embodiment.

[0204] The first transistor T1 of the (8k+1)th stage STG[8k+1] to the (8k+8)th stage STG[8k+8] is turned on in response to the forward carrier signal CARRY_F, and the second transistor T2 of the same is turned on in response to the reverse carrier signal CARRY_R. In the forward scan mode, the first transistor T1 charges the Q node, and the second transistor T2 resets the Q node. In the reverse scan mode, the second transistor T2 charges the Q node, and the first transistor T1 resets the Q node. The Q node reset operation refers to the application of the turn-off voltage to the Q node.

[0205] Accordingly, the function of stages in the forward scan mode in accordance with the first exemplary embodiment will be described below.

[0206] The first transistor T1 of the (8k+1)th stage STG[8k+1] charges the Q node in response to an (n-3)th carrier signal CARRY[n-3] and the second transistor T2 of the same resets the Q node in response to an (n+5)th carrier signal CARRY[n+5].

[0207] The first transistor T1 of the (8k+2)th stage STG[8k+2] charges the Q node in response to an (n-4)th carrier signal CARRY[n-4] and the second transistor T2 of the same resets the Q node in response to an (n+4)th carrier signal CARRY[n+4].

[0208] The first transistor T1 of the (8k+3)th stage STG[8k+3] charges the Q node in response to the (n-3)th carrier signal CARRY[n-3] and the second transistor T2 of the same resets the Q node in response to the (n+5)th carrier signal CARRY[n+5].

[0209] The first transistor T1 of the (8k+4)th stage STG[8k+4] charges the Q node in response to the (n-4)th carrier signal CARRY[n-4] and the second transistor T2 of the same resets the Q node in response to the (n+4)th carrier signal CARRY[n+4].

[0210] The first transistor T1 of the (8k+5)th stage STG[8k+5] charges the Q node in response to the (n-4)th carrier signal CARRY[n-4] and the second transistor T2 of the same resets the Q node in response to the (n+4)th carrier signal CARRY[n+4].

[0211] The first transistor T1 of the (8k+6)th stage STG[8k+6] charges the Q node in response to an (n-5)th carrier signal CARRY[n-5] and the second transistor T2 of the same resets the Q node in response to an (n+3)th carrier signal CARRY[n+3].

[0212] The first transistor T1 of the (8k+7)th stage STG[8k+7] charges the Q node in response to the (n-4)th carrier signal CARRY[n-4] and the second transistor T2 of the same resets the Q node in response to the (n+4)th carrier signal CARRY[n+4].

[0213] The first transistor T1 of the (8k+8)th stage STG[8k+8] charges the Q node in response to the (n-5)th carrier signal CARRY[n-5] and the second transistor T2 of the same resets the Q node in response to the (n+3)th carrier signal CARRY[n+3].

[0214] In the reverse scan mode, the second transistor T2 charges the Q node in response to the reverse carrier signal and the first transistor T1 resets the Q node in response to the forward carrier signal.

[0215] The function of stages in the reverse scan mode according to the first exemplary embodiment will be described below.

[0216] The second transistor T2 of the (8k+8)th stage STG[8k+8] charges the Q node in response to the (n+3)th carrier signal CARRY[n+3] and the first transistor T1 thereof resets the Q node in response to the (n-5)th carrier signal CARRY[n-5].

[0217] The second transistor T2 of the (8k+7)th stage STG[8k+7] charges the Q node in response to the (n+4)th carrier signal CARRY[n+4] and the first transistor T1 thereof resets the Q node in response to the (n-4)th carrier signal CARRY[n-4].

[0218] The second transistor T2 of the (8k+6)th stage STG[8k+6] charges the Q node in response to the (n+3)th carrier signal CARRY[n+3] and the first transistor T1 thereof resets the Q node in response to the (n-5)th carrier signal CARRY[n-5].

[0219] The second transistor T2 of the (8k+5)th stage STG[8k+5] charges the Q node in response to the (n+4)th carrier signal CARRY[n+4] and the first transistor T1 thereof resets the Q node in response to the (n-4)th carrier signal CARRY[n-4].

[0220] The second transistor T2 of the (8k+4)th stage STG[8k+4] charges the Q node in response to the (n+4)th carrier signal CARRY[n+4] and the first transistor T1 thereof resets the Q node in response to the (n-4)th carrier signal CARRY[n-4].

[0221] The second transistor T2 of the (8k+3)th stage STG[8k+3] charges the Q node in response to the (n+5)th carrier signal CARRY[n+5] and the first transistor T1 thereof resets the Q node in response to the (n-3)th carrier signal CARRY[n-3].

[0222] The second transistor T2 of the (8k+2)th stage STG[8k+2] charges the Q node in response to the (n+4)th carrier signal CARRY[n+4] and the first transistor T1 thereof resets the Q node in response to the (n-4)th carrier signal CARRY[n-4].

[0223] The second transistor T2 of the (8k+1)th stage STG[8k+1] charges the Q node in response to the (n+5)th carrier signal CARRY[n+5] and the first transistor T1 thereof resets the Q node in response to the (n-3)th carrier signal CARRY[n-3].

[0224] The output time of the (n-3)th carrier signal CARRY[n-3] in the forward scan mode is the same as the output time of the (n+3)th carrier signal CARRY[n+3] in the reverse scan mode. That is, the Q-node charging time of the (8k+1)th stage STG[8k+1] in the forward scan mode is the same as the Q-node charging time of the (8k+8)th stage STG[8k+8] in the reverse scan mode. Also, the Q-node charging time of the (n+5)th carrier signal CARRY[n+5] in the forward scan mode is the same as the Q-node charging time of the (n-5)th carrier signal CARRY[n-5] in the reverse scan mode. That is, the Q-node reset time of the (8k+1)th stage STG[8k+1] in the forward scan mode is the same as the Q-node reset time of the (8k+8)th stage STG[8k+8] in the backward scan mode.

[0225] Similarly, the Q-node charge time of the (8k+2)th stage STG[8k+2] in the forward scan mode is the same as the Q-node charge time of the (8k+7)th stage STG[8k+7] in the reverse scan mode. The Q-node reset time of the (8k+2)th stage STG[8k+2] in the forward scan mode is the same as the Q-node reset time of the (8k+7)th stage STG[8k+7] in the reverse scan mode.

[0226] The Q-node charge time of the (8k+3)th stage STG[8k+3] in the forward scan mode is the same as the Q-node charge time of the (8k+6)th stage STG[8k+6] in the reverse scan mode. The Q-node reset time of the (8k+3)th stage STG[8k+3] in the forward scan mode is the same as the Q-node reset time of the (8k+6)th stage STG[8k+6] in the reverse scan mode.

[0227] The Q-node charge time of the (8k+4)th stage STG[8k+4] in the forward scan mode is the same as the Q-node charge time of the (8k+5)th stage STG[8k+5] in the reverse scan mode. The Q-node reset time of the (8k+4)th stage STG[8k+4] in the forward scan mode is the same as the Q-node reset time of the (8k+5)th stage STG[8k+5] in the reverse scan mode.

[0228] In this way, the Q-node controller according to the first exemplary embodiment sets the timings of the carrier signals in the forward scan mode and the reverse scan mode to be symmetrical within a group of stages. As a result, the Q-nodes of the stages in the group have the same charge time and the same reset time in the forward scan mode and the reverse scan mode. For this reason, the Q-nodes in the group of stages can maintain the charged state during the black data insertion period and the precharge period in both the forward and reverse scan modes. The number of symmetrical stages in the group corresponds to the number of pixel rows to which black data is written during the black data insertion period.Every eighth stage is placed in symmetrical relationship to each other (for example, to the other eighth stages) because the stages repeat their function depending on the number of pixel lines into which the black data is written during the black data insertion period BDI.

[0229] Fig. 29 is a view showing carrier signals applied to the Q-node control unit according to the second exemplary embodiment. The first transistor T1 of each of the (8k+1)th stages STG[8k+1] to the (8k+8)th stages STG[8k+8] is turned on in response to the forward carrier signal CARRY_F, and the second transistor T2 thereof is turned on in response to the reverse carrier signal CARRY_R. In the forward scan mode, the first transistor T1 charges the Q-node, and the second transistor T2 resets the Q-node. In the reverse scan mode, the second transistor T2 charges the Q-node, and the first transistor T1 resets the Q-node. The operation of resetting the Q-node refers to applying the turn-off voltage to the Q-node.

[0230] Accordingly, the function of stages in the forward scan mode according to the second exemplary embodiment will be described below.

[0231] The first transistor T1 of the (8k+1)th stage STG[8k+1] charges the Q node in response to an (n-3)th carrier signal CARRY[n-3] and the second transistor T2 of the same resets the Q node in response to an (n+5)th carrier signal CARRY[n+5].

[0232] The first transistor T1 of the (8k+2)th stage STG[8k+2] charges the Q node in response to an (n-3)th carrier signal CARRY[n-3] and the second transistor T2 of the same resets the Q node in response to an (n+4)th carrier signal CARRY[n+4].

[0233] The first transistor T1 of the (8k+3)th stage STG[8k+3] charges the Q node in response to the (n-3)th carrier signal CARRY[n-3] and the second transistor T2 of the same resets the Q node in response to the (n+4)th carrier signal CARRY[n+4].

[0234] The first transistor T1 of the (8k+4)th stage STG[8k+4] charges the Q node in response to the (n-4)th carrier signal CARRY[n-4] and the second transistor T2 of the same resets the Q node in response to the (n+4)th carrier signal CARRY[n+4].

[0235] The first transistor T1 of the (8k+5)th stage STG[8k+5] charges the Q node in response to the (n-4)th carrier signal CARRY[n-4] and the second transistor T2 of the same resets the Q node in response to the (n+4)th carrier signal CARRY[n+4].

[0236] The first transistor T1 of the (8k+6)th stage STG[8k+6] charges the Q node in response to an (n-4)th carrier signal CARRY[n-4] and the second transistor T2 of the same resets the Q node in response to an (n+3)th carrier signal CARRY[n+3].

[0237] The first transistor T1 of the (8k+7)th stage STG[8k+7] charges the Q node in response to the (n-4)th carrier signal CARRY[n-4] and the second transistor T2 of the same resets the Q node in response to the (n+3)th carrier signal CARRY[n+3].

[0238] The first transistor T1 of the (8k+8)th stage STG[8k+8] charges the Q node in response to the (n-5)th carrier signal CARRY[n-5] and the second transistor T2 of the same resets the Q node in response to the (n+3)th carrier signal CARRY[n+3].

[0239] In the reverse scan mode, the second transistor T2 charges the Q node in response to the reverse carrier signal and the first transistor T1 resets the Q node in response to the forward carrier signal.

[0240] The function of stages in the reverse scan mode according to the second exemplary embodiment will be described below.

[0241] The second transistor T2 of the (8k+8)th stage STG[8k+8] charges the Q node in response to the (n+3)th carrier signal CARRY[n+3] and the first transistor T1 thereof resets the Q node in response to the (n-5)th carrier signal CARRY[n-5].

[0242] The second transistor T2 of the (8k+7)th stage STG[8k+7] charges the Q node in response to the (n+3)th carrier signal CARRY[n+3] and the first transistor T1 thereof resets the Q node in response to the (n-4)th carrier signal CARRY[n-4].

[0243] The second transistor T2 of the (8k+6)th stage STG[8k+6] charges the Q node in response to the (n+3)th carrier signal CARRY[n+3] and the first transistor T1 thereof resets the Q node in response to the (n-4)th carrier signal CARRY[n-4].

[0244] The second transistor T2 of the (8k+5)th stage STG[8k+5] charges the Q node in response to the (n+4)th carrier signal CARRY[n+4] and the first transistor T1 thereof resets the Q node in response to the (n-4)th carrier signal CARRY[n-4].

[0245] The second transistor T2 of the (8k+4)th stage STG[8k+4] charges the Q node in response to the (n+4)th carrier signal CARRY[n+4] and the first transistor T1 thereof resets the Q node in response to the (n-4)th carrier signal CARRY[n-4].

[0246] The second transistor T2 of the (8k+3)th stage STG[8k+3] charges the Q node in response to the (n+4)th carrier signal CARRY[n+4] and the first transistor T1 thereof resets the Q node in response to the (n-3)th carrier signal CARRY[n-3].

[0247] The second transistor T2 of the (8k+2)th stage STG[8k+2] charges the Q node in response to the (n+4)th carrier signal CARRY[n+4] and the first transistor T1 thereof resets the Q node in response to the (n-3)th carrier signal CARRY[n-3].

[0248] The second transistor T2 of the (8k+1)th stage STG[8k+1] charges the Q node in response to the (n+5)th carrier signal CARRY[n+5] and the first transistor T1 thereof resets the Q node in response to the (n-3)th carrier signal CARRY[n-3].

[0249] Fig.30 is a view showing carrier signals applied to the Q-node control unit according to the third exemplary embodiment. Each first transistor T1 of the (8k+1)th stage STG[8k+1] to the (8k+8)th stage STG[8k+8] is turned on in response to the forward carrier signal CARRY_F, and the second transistor T2 thereof is turned on in response to the reverse carrier signal CARRY_R. In the forward scan mode, the first transistor T1 charges the Q-node, and the second transistor T2 resets the Q-node. In the reverse scan mode, the second transistor T2 charges the Q-node, and the first transistor T1 resets the Q-node. The operation of resetting the Q-node refers to applying the turn-off voltage to the Q-node.

[0250] Accordingly, the function of stages in the forward scan mode according to the third exemplary embodiment will be described below.

[0251] The first transistor T1 of the (8k+1)th stage STG[8k+1] charges the Q node in response to an (n-3)th carrier signal CARRY[n-3] and the second transistor T2 of the same resets the Q node in response to an (n+5)th carrier signal CARRY[n+5].

[0252] The first transistor T1 of the (8k+2)th stage STG[8k+2] charges the Q node in response to an (n-3)th carrier signal CARRY[n-3] and the second transistor T2 of the same resets the Q node in response to an (n+4)th carrier signal CARRY[n+4].

[0253] The first transistor T1 of the (8k+3)th stage STG[8k+3] charges the Q node in response to the (n-3)th carrier signal CARRY[n-3] and the second transistor T2 of the same resets the Q node in response to the (n+4)th carrier signal CARRY[n+4].

[0254] The first transistor T1 of the (8k+4)th stage STG[8k+4] charges the Q node in response to the (n-3)th carrier signal CARRY[n-3] and the second transistor T2 of the same resets the Q node in response to the (n+3)th carrier signal CARRY[n+3].

[0255] The first transistor T1 of the (8k+5)th stage STG[8k+5] charges the Q node in response to the (n-3)th carrier signal CARRY[n-3] and the second transistor T2 of the same resets the Q node in response to the (n+3)th carrier signal CARRY[n+3].

[0256] The first transistor T1 of the (8k+6)th stage STG[8k+6] charges the Q node in response to an (n-4)th carrier signal CARRY[n-4] and the second transistor T2 of the same resets the Q node in response to an (n+3)th carrier signal CARRY[n+3].

[0257] The first transistor T1 of the (8k+7)th stage STG[8k+7] charges the Q node in response to the (n-4)th carrier signal CARRY[n-4] and the second transistor T2 of the same resets the Q node in response to the (n+3)th carrier signal CARRY[n+3].

[0258] The first transistor T1 of the (8k+8)th stage STG[8k+8] charges the Q node in response to the (n-5)th carrier signal CARRY[n-5] and the second transistor T2 of the same resets the Q node in response to the (n+3)th carrier signal CARRY[n+3].

[0259] In the reverse scan mode, the second transistor T2 charges the Q node in response to the reverse carrier signal and the first transistor T1 resets the Q node in response to the forward carrier signal.

[0260] The function of stages in the reverse scan mode according to the third exemplary embodiment will be described below.

[0261] The second transistor T2 of the (8k+8)th stage STG[8k+8] charges the Q node in response to the (n+3)th carrier signal CARRY[n+3] and the first transistor T1 thereof resets the Q node in response to the (n-5)th carrier signal CARRY[n-5].

[0262] The second transistor T2 of the (8k+7)th stage STG[8k+7] charges the Q node in response to the (n+3)th carrier signal CARRY[n+3] and the first transistor T1 thereof resets the Q node in response to the (n-4)th carrier signal CARRY[n-4].

[0263] The second transistor T2 of the (8k+6)th stage STG[8k+6] charges the Q node in response to the (n+3)th carrier signal CARRY[n+3] and the first transistor T1 thereof resets the Q node in response to the (n-4)th carrier signal CARRY[n-4].

[0264] The second transistor T2 of the (8k+5)th stage STG[8k+5] charges the Q node in response to the (n+3)th carrier signal CARRY[n+3] and the first transistor T1 thereof resets the Q node in response to the (n-3)th carrier signal CARRY[n-3].

[0265] The second transistor T2 of the (8k+4)th stage STG[8k+4] charges the Q node in response to the (n+3)th carrier signal CARRY[n+3] and the first transistor T1 thereof resets the Q node in response to the (n-3)th carrier signal CARRY[n-3].

[0266] The second transistor T2 of the (8k+3)th stage STG[8k+3] charges the Q node in response to the (n+4)th carrier signal CARRY[n+4] and the first transistor T1 thereof resets the Q node in response to the (n-3)th carrier signal CARRY[n-3].

[0267] The second transistor T2 of the (8k+2)th stage STG[8k+2] charges the Q node in response to the (n+4)th carrier signal CARRY[n+4] and the first transistor T1 thereof resets the Q node in response to the (n-3)th carrier signal CARRY[n-3].

[0268] The second transistor T2 of the (8k+1)th stage STG[8k+1] charges the Q node in response to the (n+5)th carrier signal CARRY[n+5] and the first transistor T1 thereof resets the Q node in response to the (n-3)th carrier signal CARRY[n-3].

[0269] As described above, in the shift register according to the second and third exemplary embodiments, the Q-node load time of the (8k+1)th stage STG[8k+1] in the forward scan mode is the same as the Q-node load time of the (8k+8)th stage STG[8k+8] in the backward scan mode. Furthermore, the Q-node reset time of the (8k+1)th stage STG[8k+1] in the forward scan mode is the same as the Q-node reset time of the (8k+8)th stage STG[8k+8] in the backward scan mode.

[0270] Similarly, the Q-node charge time of an (8k+a)th stage in the forward scan mode is the same as the Q-node charge time of an (8k+[9-a])th stage (a is a natural number less than or equal to 8) in the reverse scan mode. The Q-node reset time of the (8k+a)th stage in the forward scan mode is the same as the Q-node reset time of the (8k+[9-a])th stage in the reverse scan mode.

[0271] As mentioned above, in accordance with the exemplary embodiments of the present description, the motion picture response time can be improved without increasing the driving frequency by inserting black data into a frame period.

[0272] Although the embodiments have been described with reference to a number of illustrative embodiments thereof, it is to be understood that many other modifications and embodiments may be devised by those skilled in the art that fall within the scope of this disclosure. More specifically, various variations and modifications of components and / or arrangements of the subject combination arrangements are possible within the scope of the disclosure, the drawings, and the appended claims. In addition to the variations and modifications of the components and / or arrangements, alternative uses will also be apparent to those skilled in the art.

[0273] The various embodiments described above may be combined to provide further embodiments. These and other changes may be made to the embodiments in light of the foregoing detailed description. In general, terms in the following claims should not be interpreted to limit the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments, along with the full scope of equivalents to which such claims are directed. Accordingly, the claims are not limited by the disclosure.

Claims

[1] An organic light-emitting display device comprising: a display panel (10) comprising: a substrate; a plurality of data lines (15) on the substrate; a plurality of gate lines (17, 18) on the substrate and oriented transversely to the data lines (15); and a plurality of pixels connected to the data lines (15) and the gate lines (17, 18); a data driver configured to supply data voltages (DATA) to the data lines (15); and a gate-in-panel gate driver (13) configured to supply gate pulses to the gate lines (17, 18), wherein the gate driver (13) is configured to drive the display panel (10) within a single image in a plurality of blocks of pixel rows (HL), wherein the single image has a plurality of cycles, and wherein each of the cycles has a data write period, at least one black data insertion period (BDI) and at least one precharge period (Pre), wherein during the data write period of one cycle of the plurality of cycles, the data voltages (DATA) are supplied to the pixel rows (HL) of a jth block, and during the at least one black data insertion period (BDI) of the cycle, a black image is written into the pixel rows (HL) of a qth block simultaneously, where j is a natural number and q is a natural number different from j, wherein the gate driver (13) has a plurality of stages (STG) which are connected to the pixel rows (HL) respectively, where each of the stages (STG) has: a first pull-up transistor (Tpu_CR) configured to output carrier signals (CARRY) corresponding to timings of carrier clocks in response to a Q-node voltage; and a second pull-up transistor (Tpu_SC) configured to output scan signals (SCAN) corresponding to scan clock times in response to the Q-node voltage, and the carrier clocks (CRCLK) have: an image clock signal for loading the Q node to generate a corresponding one of the scan signals (SCAN) output during the data write period; and a black data insertion clock signal for loading the Q node to generate a corresponding one of the scan signals (SCAN) output during the at least one black data insertion period (BDI). [2] The organic light-emitting display device according to claim 1, wherein the gate-in-panel gate driver (13) is configured to drive zk pixel rows (HL) during each cycle of the plurality of cycles, where z is a natural number greater than 1 and k is a natural number satisfying: z(k-1) <eine Gesamtzahl von Pixelzeilen≤zk, wobei, während einer Daten-Schreibperiode, die zk horizontale Perioden hat, der Gate-in-Panel Gatetreiber (13) dazu eingerichtet ist, sequenziell Scansignale (SCAN) auszugeben, und der Datentreiber (12) dazu eingerichtet ist, die Datenspannungen (DATA) den zk Pixelzeilen (HL) zuzuführen, und, während k Schwarz-Daten-Einfügeperioden (BDI), der Gate-in-Panel Gatetreiber (13) dazu eingerichtet ist, Scansignale (SCAN) in z Pixelzeilen (HL) gleichzeitig zu schreiben, und der Datentreiber (12) dazu eingerichtet ist, Schwarz-Daten in die z Pixelzeilen (HL) gleichzeitig zu schreiben. [3] An organic light-emitting display device according to claim 1 or 2, wherein each of said at least one black data insertion period (BDI) lasts 1 horizontal period (1H). [4] An organic light-emitting display device according to any one of claims 1 to 3, wherein, during the at least one precharge period (Pre) following the at least one black data insertion period (BDI), the gate driver (13) is arranged to supply a scan signal (SCAN) and a sampling signal (SEN) to a next pixel row (HL) to which a last data voltage (DATA) was supplied during the data write period. [5] The organic light emitting display device according to any one of claims 1 to 4, wherein the carrier clocks (CRCLK) maintain a turn-off voltage during the at least one black data insertion period (BDI). [6] An organic light-emitting display device according to any one of claims 1 to 5, wherein the carrier clocks (CRCLK) comprise 16 carrier clocks, the scan clocks comprise 16 scan clocks, and each cycle comprises 20 horizontal periods, the carrier clocks (CRCLK) are output during a time period ranging from a first horizontal period (1H) to a 16th horizontal period (16H), and an interval between the picture clock signal and the black data insertion clock signal of the carrier clocks (CRCLK) corresponds to a portion of the data write period of 8 horizontal periods, a black data insertion period (BDI) of 1 horizontal period, and a precharge period (Pre) of 1 horizontal period. [7] An organic light-emitting display device according to claim 6, wherein there is a time difference of 16n+8 horizontal periods between the carrier clock signal for writing image data (RGB) into an ith pixel row (HLi) and the carrier clock signal for writing black data into the ith pixel row (HLi), where n is a natural number and i is a natural number. [8] An organic light-emitting display device according to any one of claims 1 to 5, wherein the carrier clocks (CRCLK) comprise 16 carrier clocks, the scan clocks comprise 16 scan clocks, and each cycle comprises 40 horizontal periods, the carrier clocks (CRCLK) are output during a time period running from a first horizontal period to a 16th horizontal period, an interval between the image clock signal and the BDI clock signal of the carrier clocks (CRCLK) corresponds to a portion of the data write period of 8 horizontal periods, a black data insertion period (BDI) of 1 horizontal period and a precharge period (Pre) of 1 horizontal period, and there is a time difference of 32n+8 horizontal periods between the carrier clock signal for writing image data (RGB) into an ith pixel row (HLi) and the carrier clock signal for writing black data into the ith pixel row (HLi), where n is a natural number and i is a natural number. [9] An organic light-emitting display device according to any one of claims 1 to 5, wherein the carrier clocks (CRCLK) comprise 16 carrier clocks, the scan clocks (SCCLK) comprise 12 scan clocks, and each cycle comprises 60 horizontal periods, and first to 16th carrier clocks (CRCLK1, CRCLK2,..., CRCLK16) are output sequentially for 60 horizontal periods from a first horizontal period (1H) to a 60th horizontal period (60H), wherein a first half of a cycle of the first to eighth carrier clocks (CRCLK1, CRCLK2,..., CRCLK8) corresponds to the image clock signal of the carrier clock (CRCLK), and the first half of a cycle of the ninth to 16th carrier clocks (CRCLK9, CRCLK10,.... CRCLK16) corresponds to the black data insertion clock signal of the carrier clock (CRCLK). [10] An organic light-emitting display device according to claim 9, wherein there is a time difference of 48n+24 horizontal periods between the carrier clock signal for writing image data (RGB) into an ith pixel row (HLi) and the carrier clock signal for writing black data into the ith pixel row (HLi), where n is a natural number and i is a natural number. [11] An organic light-emitting display device according to any one of claims 1 to 5, wherein the carrier clocks (CRCLK) comprise 12 carrier clocks, the scan clocks (SCCLK) comprise 12 scan clocks, and each cycle comprises 60 horizontal periods, first to 12th carrier clocks (CRCLK1, CRCLK2,.... CRCLK12) are output for 60 horizontal periods from a first horizontal period (1H) to a 60th horizontal period (60H), and wherein a first half of a cycle of the first to sixth carrier clocks (CRCLK1, CRCLK2,..., CRCLK6) corresponds to the image clock signal of the carrier clock (CRCLK), and the first half of a cycle of the seventh to twelfth carrier clocks (SCCLK7, SCCLK8,..., SCCLK12) corresponds to the black data insertion clock signal of the carrier clock (CRCLK). [12] An organic light-emitting display device according to claim 11, wherein there is a time difference of 48n+24 horizontal periods between the carrier clock signal for writing image data (RGB) into an ith pixel row (HLi) and the carrier clock signal for writing black data into the ith pixel row (HLi), where n is a natural number and i is a natural number. [13] An organic light-emitting display device according to any one of claims 1 to 12, wherein each of the plurality of stages (STG) comprises: a first Q-node control transistor configured to charge the Q-node in response to a forward carrier signal (CARRY_F) in a forward scan mode; and a second Q-node control transistor configured to discharge the Q-node in response to a reverse carrier signal (CARRY_R) in the forward scan mode, wherein the output times of the forward carrier signal (CARRY_F) and the reverse carrier signal (CARRY_R) are set longer than the scan times of each of the blocks of the display panel (10). [14] The organic light-emitting display device according to claim 13, wherein the second Q-node control transistor is configured to charge the Q-node in response to the reverse carrier signal (CARRY_R) in a reverse scan mode, and the first Q-node control transistor is configured to apply a turn-off voltage to the Q-node in response to the forward carrier signal (CARRY_F) in the reverse scan mode. [15] The organic light-emitting display device according to claim 13 or 14, wherein each of the plurality of blocks has 8k pixel lines (HL), where k is a natural number, the output timing of the forward carrier signal (CARRY_F) applied to the first Q-node control transistor of an (8k+a)th stage and the output timing of the reverse carrier signal (CARRY_R) applied to the second Q-node control transistor of an (8k+[9-a])th stage being the same, where a is a natural number less than or equal to 8. [16] The organic light-emitting display device according to claim 15, wherein the output timing of the reverse carrier signal (CARRY_R) applied to the second Q-node control transistor of the (8k+a)th stage and the output timing of the forward carrier signal (CARRY_F) applied to the first Q-node control transistor of the (8k+[9-a])th stage are the same, where a is a natural number less than or equal to 8. [17] Gate-in-panel gate driver (13), comprising: a plurality of stages (STG), each of the stages (STG) comprising: a first pull-up transistor (Tpu_CR) configured to receive a corresponding carrier clock (CRCLK) and to output carrier signals (CARRY) corresponding to the carrier clock (CRCLK) in response to a Q-node voltage of the stage (STG); a second pull-up transistor (Tpu_SC) configured to receive a corresponding scan clock (SCCLK) and, in response to the Q-node voltage, to output scan signals (SCAN) corresponding to the scan clock (SCCLK); a first Q-node control transistor configured to charge the Q-node in response to a forward carrier signal (CARRY_F) in a forward scan mode; and a second Q-node control transistor configured to discharge the Q-node in the forward scan mode in response to a reverse carrier signal (CARRY_R), where each of the carrier clocks (CRCLK) has: an image clock signal for generating a corresponding one of the scan signals (SCAN) output during the data write period; and a black data insertion clock signal for generating a corresponding one of the scan signals (SCAN) output during a black data insertion period (BDI). [18] The gate driver (13) of claim 17, wherein the carrier clocks (CRCLK) maintain a turn-off voltage during the black data insertion period (BDI). [19] A gate driver (13) according to claim 17 or 18, wherein the black data insertion period (BDI) lasts 1 horizontal period.

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