Power semiconductor device

Abstract

Power semiconductor device, comprising: a connection frame (2) with a plurality of electrically independent areas (21, 22, 23, 24, 25); switchable power semiconductor chips (3a, 3b, 3c, 3d, 3e, 3f) attached to the connection frame (2); metallic inner conductors (6) that electrically connect the upper electrodes of the respective power semiconductor chips (3a, 3b, 3c, 3d, 3e, 3f) and the connection frame (2); a conductive connecting element (5) that connects at least the connection frame (2) and the internal conductors (6); and a resin (8) covering the connection frame (2), the power semiconductor chips (3a, 3b, 3c, 3d, 3e, 3f) and the inner conductors (6), wherein a recess (7) is provided along at least one longitudinal end surface (6a) of the inner conductor (6) in a region (23, 24) of the connection frame (2) to which the inner conductor (6) is connected, the power semiconductor device further comprising: an electronic part (4) which is arranged adjacent to the inner line (6) on the same side as the recess (7) with respect to the inner line (6), wherein a distance between the inner conductor (6) and the recess (7) is smaller than a distance between the inner conductor (6) and the electronic part (4).

Description

BACKGROUND OF THE INVENTION Technical field

[0001] The present invention relates to a power semiconductor device on which switchable power semiconductor chips are mounted. Description of the related prior art

[0002] A power semiconductor device is designed such that switchable power semiconductor chips, configured in a circuit pattern, are mounted on a terminal frame and sealed with a molded resin. A power conversion circuit is established by a single such power semiconductor device or by combining a plurality of them.

[0003] Since power semiconductor chips generate heat when supplied with current, causing a temperature increase, it is necessary to control the current supplied to the power semiconductor chips so that a predetermined permissible temperature is not exceeded. In other words, the temperature rise of the power semiconductor chips when they are supplied with current is controlled, and this makes it possible to increase the current supplied, thus enabling operation at maximum power within the range where the temperature of the power semiconductor chips, when supplied with current, is at or below the permissible temperature. As a result, the performance of the power conversion circuit can be improved, and the power output of the power converter can be maximized.

[0004] Examples of methods for improving maximum performance in the range where the temperature of the power semiconductor chip is at or below the allowable temperature include: reducing heat loss caused in the power semiconductor chips; reducing the amount of heat received by the power semiconductor chips from the outside; facilitating the release of the heat generated in the power semiconductor chips; and allowing current to be supplied up to the point where the temperature of the power semiconductor chips, while being monitored, reaches the allowable temperature.

[0005] Since the power semiconductor device is supplied with current through a variety of elements, such as busbars, a terminal frame, and power semiconductor chips, and through the interconnect sections of these elements, it is necessary to ensure a reduction in connection resistance and the reliability of the connection. For example, in JP 2014-78646A, with the aim of ensuring the reduction in resistance and the reliability of the connection of the power semiconductor device, the semiconductor chips and corresponding plate-like internal traces are pre-connected using a conductive interconnect material, and the semiconductor chips are mounted on a terminal frame at a temperature lower than the temperature at which the conductive interconnect material begins to melt again.

[0006] The power semiconductor device known to date has a problem in that when the top electrode of a power semiconductor chip and the terminal frame are connected with a metallic inner conductor, solder melted by heat treatment using a reflow unit or similar device wets the terminal frame and spreads across it, causing a displacement of the inner conductor. If the displaced inner conductor interferes with the power semiconductor chip, there is a risk of a short circuit.

[0007] In previously known power semiconductor devices, for example, a distance of 5 mm or more around the inner conductor is provided to prevent contact between the inner conductor and an adjacent electronic component due to displacement of the inner conductor. However, this prevents the power semiconductor device from being manufactured in a smaller size. Furthermore, a problem arises in ensuring the area of ​​the terminal frame where the inner conductor is to be mounted. This narrows the area of ​​the terminal frame where the power semiconductor chip is mounted and reduces the heat dissipation area of ​​the power semiconductor chip. Consequently, it is not possible to adequately suppress a rise in the temperature of the power semiconductor chip, and thus it is not possible to obtain a high-power power semiconductor device.

[0008] Since it is not possible to prevent the solder from wetting and spreading on the lead frame using the method proposed in JP 2014-78646A, it is necessary to secure the area where the inner trace is to be mounted and to provide a gap around the inner trace. Another problem is that the process of joining the semiconductor chip and inner trace must be performed in advance, and that this joining cannot be done by batch heat treatment using a reflow unit or similar equipment, resulting in reduced productivity.

[0009] Further state of the art is set out in documents US 2007 / 0166877 A1, US 2013 / 0320818 A1, US 2002 / 0056894 A1 and US 2005 / 0173783 A1. PRESENTATION OF THE INVENTION

[0010] The invention was conceived to solve the problems described above and has the objective of providing a power semiconductor device that suppresses a positional displacement of an inner conductor when the inner conductor is connected to a terminal frame, and which has a small size and high power.

[0011] The present invention is defined by the power semiconductor device according to the features of claim 1. The dependent claims represent preferred embodiments.

[0012] The power semiconductor device according to the invention comprises: a terminal frame with a plurality of electrically independent areas; switchable power semiconductor chips attached to the terminal frame; metallic inner conductors electrically connecting the upper electrodes of the respective power semiconductor chips and the terminal frame; a conductive connecting element connecting at least the terminal frame and the inner conductors; and a resin covering the terminal frame, the power semiconductor chips, and the inner conductors, wherein a recess is provided along the inner conductor in an area of ​​the terminal frame to which the inner conductor is connected.

[0013] According to the invention, a recess is provided along the inner conductor in the area of ​​the connection frame to which the inner conductor is connected. This allows the conductive connecting element, which is melted in the area where the connection frame and the inner conductor are joined, to wet only the recess and spread towards it, thus suppressing any displacement of the inner conductor. Since this makes it possible to reduce the distance between the inner conductor and an adjacent electronic component, thereby ensuring a sufficient heat dissipation area for the power semiconductor chip, it is possible to obtain a small, high-performance power semiconductor device.

[0014] The foregoing and other tasks, features, aspects and advantages of the present invention will also become apparent from the following detailed description of the present invention in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS [ Fig. 1] Fig. Figure 1 is a top view showing a power semiconductor device according to embodiment 1 of the invention. [ Fig. 2] Fig. Figure 2 is a sectional view showing the power semiconductor device according to embodiment 1 of the invention. [ Fig. 3] Fig. Figure 3 is a sectional view showing part of the power semiconductor device according to embodiment 1 of the invention. [ Fig. 4] Fig. Figure 4 is a diagram showing a recess in a connection frame of the power semiconductor device according to embodiment 1 of the invention. [ Fig. 5] Fig. Figure 5 is a top view showing a power semiconductor device according to embodiment 2 of the invention. DETAILED DESCRIPTION OF THE PREFERRED EXECUTION FORMS Execution format 1

[0015] A power semiconductor device according to embodiment 1 of the invention is described below on the basis of the drawings. Fig. Figure 1 is a top view schematically showing the power semiconductor device according to embodiment 1. Fig. 2 is a cross-sectional view of the section cut through by AA in Fig. 1 is displayed, and Fig. 3 is a sectional view of the section cut through by BB in Fig. 1 is shown. In the individual drawings, identical and equivalent parts are described with the same reference numerals.

[0016] A power semiconductor device 1 according to embodiment 1 comprises: a metallic connection frame 2, switchable power semiconductor chips 3a, 3b, 3c and 3d (collectively described as power semiconductor chips 3), current sensing resistors 4, solder 5 which is a conductive connecting element, internal conductors 6 which are metallic switching elements, and a molded resin 8 which covers these parts.

[0017] The connection frame 2, which configures the power semiconductor device 1, has a plurality of electrically independent areas 21, 22 and 23. In Fig. In section 21, area 21 is a P-potential line, areas 22 are AC-potential lines, and area 23 is an N-potential line. The power semiconductor chips 3a and 3b, which are the two upper power semiconductor chips of a three-phase AC circuit, are located in area 21, and the power semiconductor chips 3c and 3d, which are the lower power semiconductor chips of the three-phase AC circuit, are each located in one of the two areas 22.

[0018] Furthermore, the two areas 22, in which the respective power semiconductor chips 3c and 3d are located, are each electrically connected via the corresponding resistors 4, which are shunt resistors or the like, to one of two areas 22 in which no power semiconductor chip 3 is located. The areas 22 in which no power semiconductor chip 3 is located are each connected to an external electrode.

[0019] Each of the power semiconductor chips 3 is, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET), but is not limited to this and can be an insulated-gate bipolar transistor (IGBT). The base material used for the power semiconductor chip 3 is silicon (Si), silicon carbide (SiC), silicon nitride (SiN), gallium nitride (GaN), gallium arsenide (GaAs), or the like.

[0020] The power semiconductor chip 3 has a gate section and a gate electrode on its upper surface, in addition to a source electrode, which is also an upper chip electrode. It also has a lower chip electrode on its underside (the gate section and electrodes are not shown). The upper chip electrode of the power semiconductor chip 3 is electrically connected via the inner lead 6 to a region of the terminal frame 2 that is distinct from the region where the power semiconductor chip 3 is mounted. The gate electrode is wire-bonded to a gate terminal configured from a section of the terminal frame 2. When the upper chip electrode and the inner lead 6 are joined with the solder 5, the upper chip electrode is coated with nickel (Ni), thus fulfilling the soldering specifications.

[0021] The terminal frame 2 is formed in a circuit pattern by etching or pressing an alloy plate with copper (Cu), aluminum (Al), or the like as the base material. The front surface of the terminal frame 2 can either be designed so that the base metal is exposed or so that at least part of it is coated.

[0022] As in Fig. As shown in Figure 2, one of the opposing main surfaces of the terminal frame 2 is designated as a mounting surface 2a, while the other is designated as a heat dissipation surface 2b. After the power semiconductor chips 3, the internal conductors 6, the resistors 4, and the like are mounted on the mounting surface 2a and sealed with the molding resin 8, a portion unnecessary for the electrical circuitry is removed. As a result, the terminal frame 2 is divided, forming the electrically independent areas 21, 22, and 23. Furthermore, a heat sink 10 is connected to the heat dissipation surface 2b via an insulating adhesive 9 with high thermal conductivity.

[0023] As in Fig. As shown in Figure 3, the upper chip electrode of the power semiconductor chip 3d and the inner conductor 6 are connected by the solder 5, the lower chip electrode of the power semiconductor chip 3d and area 22 of the terminal frame 2 are connected by the solder 5, and the inner conductor 6 and area 23 of the terminal frame 2 are connected by the solder 5. Furthermore, each of the resistors 4 and the areas 22, which are each arranged on one side of it, is also connected by the solder.

[0024] The inner conductor 6 is one in which a metal plate is processed in a switching element form, and a portion of the inner conductor 6, other than the portion connected to the power semiconductor chip 3 or terminal frame 2, is in contact with the molded resin 8. Furthermore, the inner conductor 6 is arranged so that it is enclosed within the molded resin 8 and, when manufactured, has no external support. The body of the inner conductor 6 is oriented in a direction farther away from the terminal frame 2 than the connecting section, thus preventing a short circuit with the terminal frame 2.

[0025] Furthermore, the cross-sectional area of ​​the body of the inner conductor 6 is determined by the amount of current supplied. It is assumed that the power semiconductor device 1 according to embodiment 1 will receive a current on the order of a few amperes to several hundred amperes, even including a directly applied current. A through-hole and / or a constricted section is provided in the body of the inner conductor 6, thereby increasing the longitudinal thermal resistance of the inner conductor 6 and thus reducing the heat conduction between the power semiconductor chips 3.

[0026] The power semiconductor device 1 is designed such that, as in Fig. Figure 4 shows a recess 7 along at least one longitudinal end face 6a of the inner conductor 6 in the area 23 of the connection frame 2, to which the inner conductor 6 is connected. The recess 7 is designed to narrow the area in which solder, melted in the section where the inner conductor 6 and the area 23 of the connection frame 2 are joined, wets and spreads due to heat treatment by a reflow unit or the like. That is, the molten solder 5 can only wet the connection frame end 7a of the recess 7 and spread over it.

[0027] Furthermore, an electronic component (in embodiment 1, the resistor 4) is provided adjacent to the inner conductor 6 on the same side as the recess 7 with respect to the inner conductor 6, and the distance between the inner conductor 6 and the recess 7 is set such that it is smaller than the distance between the inner conductor 6 and the electronic component. The longitudinal end face 6a of the inner conductor 6 and the terminal frame end 7a of the recess 7 are also set such that they have a distance of 0.5 mm or more between them, taking into account the positional accuracy of the plumb line 5. As in Fig. Figure 4 is shown, if the distance between the longitudinal end surface 6a of the inner conduit 6 and the recess 7 is represented by L1, and the distance between the longitudinal end surface 6a of the inner conduit 6 and the electronic part adjacent to the longitudinal end surface 6a is represented by L2, L1 and L2 satisfy the condition 0.5 mm ≤ L1 < L2.

[0028] By providing this type of recess 7, the longitudinal end face 6a of the inner conductor 6 moves only towards the recess 7, even if the inner conductor 6 shifts position during assembly, thus preventing the inner conductor 6 from coming into contact with the adjacent resistor 4. In a previously known power semiconductor device, a space of 5 mm or more is provided around the inner conductor to prevent contact with the adjacent electronic component due to a positional shift of the inner conductor, but this prevents a reduction in the size of the power semiconductor device. In embodiment 1, by providing the recess 7, it is possible to make the distance between the inner conductor 6 and the resistor 4 narrower than previously known, thereby enabling L2 to meet the condition L2 ≤ 5 mm.

[0029] In the Fig. In the example shown in Figure 4, the recess 7 is formed in a right-angled triangle, and the connecting frame end 7a, which is the hypotenuse of the right-angled triangle, is arranged parallel to the longitudinal end face 6a of the inner conduit 6. However, any shape of the recess 7 is acceptable as long as the recess 7 is formed along the inner conduit 6, and the recess 7 can be formed in a variety of shapes, such as a quadrilateral or an elongated slot. Furthermore, in Fig. 4 the recess 7 is provided along one longitudinal end surface 6a of the inner conduit 6, but if electronic parts are provided adjacent to each of the longitudinal end surfaces on both sides of the inner conduit 6, a recess 7 can be provided along each of the longitudinal end surfaces on both sides of the inner conduit 6.

[0030] In embodiment 1, the two power semiconductor chips 3a and 3b are located in the region 21, which is the P-potential line, and the power semiconductor chips 3c and 3d are each located in one of the two regions 22, which are the AC-potential lines, but the number and arrangement of the power semiconductor chips 3 are not limited to these. Two or more power semiconductor chips 3 can be located on the P-potential line.

[0031] Furthermore, in embodiment 1, solder 5 is used as the conductive connecting element. However, if stress occurs due to temperature changes or the like, when a power converter is used, and a difference in durability arises in a multitude of connection sections, solders of different compositions can be used for each connection section. Moreover, the conductive connecting element is not limited to solder 5; a conductive resin paste, a sintering paste, or the like can also be used as the conductive connecting element.

[0032] According to embodiment 1, the recess 7 is provided along the inner conductor 6 in the area 23 of the connection frame 2 where the inner conductor 6 is connected, whereby the solder 5, which is melted in the part where the connection frame 2 and the inner conductor 6 are connected, only wets the connection frame end 7a of the recess 7 and spreads on it, and thus it is possible to suppress a positional displacement of the inner conductor 6.

[0033] Furthermore, the distance L1 between the inner conductor 6 and the recess 7 is smaller than the distance L2 between the inner conductor 6 and the electronic component, which is located adjacent to the inner conductor 6 on the same side as the recess 7 with respect to the inner conductor 6. Therefore, the inner conductor does not come into contact with the electronic component 6, even if the inner conductor 6 is repositioned. For this reason, it is possible to make the distance between the inner conductor 6 and the electronic component smaller than previously known.

[0034] Furthermore, since it is no longer necessary to provide a space between the inner conductor 6 and the adjacent electronic component, taking into account any positional displacement of the inner conductor 6, and the heat dissipation area of ​​the power semiconductor chip 3 can be ensured accordingly, it is possible to obtain a power semiconductor device 1 with small dimensions and high performance. Moreover, since it is possible to perform the same connection process as previously known by batch heat treatment using a reflow unit or the like, without adding a new step, and since it is also possible to prevent a defect caused by contact between the inner conductor 6 and the adjacent electronic component, it is possible to achieve an improvement in productivity. Example 2

[0035] Fig. Figure 5 is a top view schematically showing a power semiconductor device according to embodiment 2 of the invention. A connection frame 2, which configures a power semiconductor device 1A according to embodiment 2, has several electrically independent areas 21, 22, 24 and 25. Fig. 5, area 21 is a P-potential line, areas 22 and 25 are AC-potential lines, and area 24 is an N-potential line.

[0036] The upper chip electrodes of semiconductor chips 3c and 3d, each located in one of the regions 22, are electrically connected to region 24 by their respective inner conductors 6. Furthermore, power semiconductor chips 3e and 3f are located adjacent to their respective inner conductors 6 in region 24, to which the inner conductors 6 are connected. The upper chip electrodes of power semiconductor chips 3e and 3f are also electrically connected by their respective inner conductors 6 to regions 25 that are different from region 24.

[0037] In the case of the power semiconductor device 1A according to embodiment 2, since a short-circuit fault is feared, which is caused by interference between the inner conductors 6 connected to the area 24 and the respective power semiconductor chips 3e and 3f, a recess 7 is provided between each inner conductor 6 and each corresponding power semiconductor chip 3e and 3f. Because this causes the inner conductor 6 to move only to one terminal frame end 7a of the recess 7, even if a positional displacement of the inner conductor 6 occurs, the inner conductor 6 does not come into contact with the adjacent power semiconductor chips 3e and 3f.

[0038] The areas 22 of the connection frame 2, in which the respective power semiconductor chips 3c and 3d are mounted, each have an extended section 12 opposite the recess 7 and projecting into the inside of the recess. A connection frame end 12a of the extended section 12 is provided parallel to the connection frame end 7a of the recess 7. Since the area of ​​the areas 22 in which the respective power semiconductor chips 3c and 3d are mounted is increased by providing these extended sections 12, the heat dissipation area of ​​the power semiconductor chips 3c and 3d is increased, thereby suppressing a rise in the temperature of the power semiconductor chips 3c and 3d. Since other configurations of the power semiconductor device 1A are the same as in embodiment 1, a description of them is omitted.

[0039] In the Fig.In the example shown in Figure 5, the recess 7 is formed in a triangle, and the connecting frame end 7a, which forms one side of the triangle, is arranged parallel to a longitudinal end surface 6a of the inner conduit 6. However, any shape of the recess 7 is acceptable as long as the recess 7 is formed along the inner conduit 6, and the recess 7 can be formed in a variety of shapes, such as a quadrilateral or an elongated slot.

[0040] According to embodiment 2, the recess 7 is provided between each inner conductor 6 and each respective power semiconductor chip 3e and 3f, which are located in the same area 24. This ensures that the solder melted in the section where the terminal frame 2 and the inner conductor 6 are connected only wets and spreads over the terminal frame end 7a of the recess 7, thus suppressing any displacement of the inner conductor 6. Therefore, it is possible to make the distance between each inner conductor 6 and each respective power semiconductor chip 3e and 3f smaller than previously known.

[0041] Since the inner conductor 6 does not come into contact with the respective power semiconductor chips 3e and 3f, even when displaced, it is possible to prevent a short-circuit fault caused by interference between the inner conductor 6 and each respective power semiconductor chip 3e and 3f. Furthermore, the extended section 12, opposite the recess 7, is provided in each of the areas 22 where the respective power semiconductor chips 3c and 3d are located, thereby increasing the heat dissipation area of ​​the power semiconductor chips 3c and 3d and thus suppressing a rise in the temperature of the power semiconductor chips 3c and 3d.

[0042] For these reasons, according to embodiment 2, the power semiconductor device 1A can be obtained with a small size and high power. The invention is such that the individual embodiments can be freely combined, or any of the individual embodiments can be suitably modified or omitted within the scope of the invention.

Claims

[1] Power semiconductor device comprising: a connection frame (2) with a plurality of electrically independent areas (21, 22, 23, 24, 25); switchable power semiconductor chips (3a, 3b, 3c, 3d, 3e, 3f) attached to the connection frame (2); metallic inner conductors (6) that electrically connect the upper electrodes of the respective power semiconductor chips (3a, 3b, 3c, 3d, 3e, 3f) and the connection frame (2); a conductive connecting element (5) that connects at least the connection frame (2) and the internal conductors (6); and a resin (8) covering the connection frame (2), the power semiconductor chips (3a, 3b, 3c, 3d, 3e, 3f) and the inner conductors (6), wherein a recess (7) is provided along at least one longitudinal end surface (6a) of the inner conductor (6) in a region (23, 24) of the connection frame (2) to which the inner conductor (6) is connected, the power semiconductor device further comprising: an electronic part (4) which is arranged adjacent to the inner line (6) on the same side as the recess (7) with respect to the inner line (6), wherein a distance between the inner conductor (6) and the recess (7) is smaller than a distance between the inner conductor (6) and the electronic part (4). [2] Power semiconductor device according to claim 1, wherein the area (22) of the connection frame (2) in which the power semiconductor chip (3c, 3d) is mounted has an extended section (12) which is opposite the recess (7) and protrudes into the inside of the recess (7). [3] Power semiconductor device according to claim 1 or 2, wherein the recess (7) is formed as a right-angled triangle, and a hypotenuse (7a) of the right-angled triangle is formed parallel to the longitudinal end surface (6a) of the inner conductor (6). [4] Power semiconductor device according to one of claims 1 to 3, wherein if a distance between the longitudinal end surface (6a) of the inner conductor (6) and the recess (7) is represented by L1, and a distance between the longitudinal end surface (6a) of the inner conductor (6) and the electronic part (4) adjacent to the longitudinal end surface (6a) is represented by L2, L1 and L2 satisfy the condition 0.5 mm ≤ L1 < L2. [5] Power semiconductor device according to any one of claims 1 to 4, wherein if a distance between the longitudinal end surface (6a) of the inner conductor (6) and the electronic part (4) adjacent to the longitudinal end surface (6a) is represented by L2, L2 satisfies the condition L2 ≤ 5 mm. [6] Power semiconductor device according to claim 4 or 5, wherein the electronic part (4) is a current sensing resistor. [7] Power semiconductor device according to claim 1 or 2, wherein the power semiconductor chip (3e, 3f) which is different from the power semiconductor chip (3c, 3d) which is connected to the inner conductor (6) is located adjacent to the inner conductor (6) in the area (24) of the connection frame (2) to which the inner conductor (6) is connected, and the recess (7) is provided between the inner conductor (6) and the different power semiconductor chip (3e, 3f).

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