Resistor element array circuit, resistive element array circuit unit and infrared sensor

Abstract

Resistor element array circuit (1), comprising: a multitude of word lines (W, W1 to Wm) which extend in a first direction (X) and are arranged side by side in a second direction (Y); a multitude of bit lines (B, B1 to Bn) which extend in the second direction (Y) and are arranged side by side in the first direction (X); a plurality of resistive elements (R, R(1,1) to R(m,n)), each of which is arranged at an interface of a word line (W, W1 to Wm) and a bit line (B, B1 to Bn) and each of which is coupled to the word line (W, W1 to Wm) and the bit line (B, B1 to Bn); a selection device (SEL) configured to select one (Ws) of the word lines (W, W1 to Wm) and one (Bs) of the bit lines (B, B1 to Bn); and a differential amplifier (AMP) having a positive input terminal (T1), a negative input terminal (T2) and an output terminal (T3), wherein the positive input terminal (T1) is configured to be coupled to the selected (Bs) of the bit lines (B, B1 to Bn) which is selected by the selection device (SEL), wherein the negative input terminal (T2) is configured to be coupled to at least one unselected of the bit lines (B, B1 to Bn) which is not selected by the selection device (SEL), and at least one unselected of the word lines (W, W1 to Wm) which is not selected by the selection device (SEL), wherein the output terminal (T3) is coupled to the negative input terminal (T2); wherein the selected (Ws) of the word lines (W, W1 to Wm), which is selected by the selection device (SEL), is set up to be coupled with a power supply (V).

Description

BACKGROUND

[0001] The disclosure relates to a resistor element array circuit with a resistor element array in which a plurality of resistor elements are arranged, a resistor element array circuit unit which includes the resistor element array circuit, and an infrared sensor which includes the resistor element array circuit.

[0002] A resistor array circuit with a plurality of resistors arranged in a matrix is ​​known. Such a resistor array circuit is used, for example, as an infrared detection circuit. Reference is made, for example, to the unexamined Japanese patent application JP H08-94443A. Such an infrared detection circuit has a plurality of infrared-sensitive resistors arranged therein. Non-limiting examples of the infrared-sensitive resistor include a thermistor, which changes its resistance value depending on a temperature. DEPICTION

[0003] A resistor array circuit according to an embodiment of the disclosure comprises: a plurality of word lines extending in a first direction and arranged side by side in a second direction and coupled to a current supply; a plurality of bit lines extending in the second direction and arranged side by side in the first direction; a plurality of resistor elements, each of which is arranged at an interface of a corresponding word line and a corresponding bit line and of which each is coupled to the corresponding word line and the corresponding bit line; a selection device configured to select one of the word lines and one of the bit lines;a differential amplifier comprising a positive input terminal, a negative input terminal, and an output terminal, wherein the positive input terminal is configured to be coupled to the selected bit line selected by the selection device, wherein the negative input terminal is configured to be coupled to an unselected bit line not selected by the selection device and an unselected word line not selected by the selection device, the output terminal being coupled to the negative input terminal; and a ground terminal coupled to the positive input terminal.

[0004] A resistive element array circuit unit according to an embodiment of the disclosure comprises a plurality of resistive element array circuits, wherein the plurality of resistive element array circuits each comprise a plurality of word lines extending in a first direction and arranged side by side in a second direction and coupled to a current supply, a plurality of bit lines extending in the second direction and arranged side by side in the first direction, a plurality of resistive elements, each of which is arranged at an interface of a corresponding word line and a corresponding bit line and each of which is coupled to the corresponding word line and the corresponding bit line, a selection device configured to select one of the word lines and one of the bit lines, and a differential amplifier.which has a positive input terminal, a negative input terminal, and an output terminal, wherein the positive input terminal is configured to be coupled to the selected bit line selected by the selection device, wherein the negative input terminal is configured to be coupled to an unselected bit line not selected by the selection device, and to an unselected word line not selected by the selection device, and wherein the output terminal is coupled to the negative input terminal, and a ground terminal coupled to the positive input terminal; and a controller configured to perform simultaneous read control of the resistor element array circuits, comprising controlling the current supply to induce an electric current,to be fed successively via the word lines to the resistor elements, which are arranged in the second direction along the one selected bit line.

[0005] An infrared sensor according to an embodiment of the disclosure comprises a resistive element array circuit, wherein the resistive element array circuit comprises: a plurality of word lines extending in a first direction and arranged side by side in a second direction and coupled to a current supply; a plurality of bit lines extending in the second direction and arranged side by side in the first direction; a plurality of resistive elements, each of which is arranged at an interface of a corresponding word line and a corresponding bit line and each of which is coupled to the corresponding word line and the corresponding bit line; a selection device configured to select one of the word lines and one of the bit lines;a differential amplifier comprising a positive input terminal, a negative input terminal, and an output terminal, wherein the positive input terminal is configured to be coupled to the selected bit line selected by the selection device, wherein the negative input terminal is configured to be coupled to an unselected bit line not selected by the selection device and to an unselected word line not selected by the selection device, and wherein the output terminal is coupled to the negative input terminal; and a ground terminal coupled to the positive input terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings are included to facilitate a deeper understanding of the revelation and are incorporated into this description, forming part of it. The drawings illustrate embodiments and, together with the description, serve to explain the principles of the revelation. Fig. Figure 1 is a circuit diagram illustrating a schematic embodiment example of a resistor element array circuit according to an exemplary embodiment. Fig. Figure 2 is an explanatory diagram describing a leakage current path in the Fig. 1 illustrated resistor element array circuit. Fig. Figure 3 is a schematic diagram illustrating a schematic embodiment example of a resistor element array circuit unit according to an exemplary embodiment. DETAILED DESCRIPTION

[0007] Some embodiments of the disclosure are described in detail below with reference to the accompanying drawings.

[0008] It is noted that the following description is intended to provide illustrative examples of the technology and is not to be interpreted as limiting the technology. Factors such as numerical values, shapes, materials, components, component positions, and the manner in which components are coupled serve only for illustration and are not to be interpreted as limiting the technology. Furthermore, elements in the following embodiments that are not mentioned in a highly generic independent claim of the technology are optional and can be provided as required. The drawings are schematic and are not to scale. It is noted that identical elements are identified by the same reference numerals, and any identical descriptions thereof are not intended to be detailed.It should be noted that the description follows in the following order. 1. First embodiment (example of a resistor array circuit with a resistor array) 2. Second embodiment (example of a resistor array circuit unit comprising a plurality of resistor array circuits) 3. Modification example

[0009] It is desirable for an infrared detection circuit to have higher operational reliability.

[0010] It is desirable to provide a resistive element array circuit, a resistive element array circuit unit, and an infrared sensor that are capable of achieving higher operational reliability. [1. First embodiment][Overall design example of the resistor element array circuit 1]

[0011] Fig. Figure 1 is a circuit diagram for the schematic illustration of a complete design example of a resistor array circuit 1 according to a first embodiment of the disclosure. The resistor array circuit 1 can, for example, be mounted on an infrared thermograph and can be configured to convert infrared rays, with which the resistor array circuit is irradiated, into an electrical signal corresponding to an intensity of the infrared rays and to output the electrical signal as an output signal S.

[0012] As in Fig. As illustrated in Figure 1, the resistor array circuit 1, for example, has a plurality of word lines W (W1 to Wm), a plurality of bit lines B (B1 to Bn), a plurality of resistors R (R(1,1) to R(m,n)), a selector SEL, a differential amplifier AMP, and a ground connection GND. The resistor array circuit 1 can also have a resistor RG, a controller CTRL, and wiring lines L1 to L3. It is noted that here, a resistor R, located at the interface of an a-th word line Wa from the word lines W1 to Wm and a b-th bit line Bb from the bit lines B1 to Bn, is designated as R(a,b). [Word guidance W]

[0013] The word lines W extend in an X-axis direction and are arranged side by side in a Y-axis direction. It is noted that although in Fig. Figure 1 illustrates an example in which an m number of word lines W are provided, and it is possible to set the number of word lines W to any desired number. One end of each of the word lines W can be connected to a current supply V in a selection device SEL by means of a selector switch SW1 (which is described elsewhere). After a resistance value of any resistance element R is read from the resistance elements R, a predetermined reading current can be supplied from the current supply V to a word line W corresponding to that resistance element R. In one embodiment of the disclosure, the X-axis direction corresponds to a specific, but non-limiting, example of a "first direction". In another embodiment of the disclosure, the Y-axis direction corresponds to a specific, but non-limiting, example of a "second direction". [Bit line B]

[0014] The bit lines B can each intersect the word lines W. In one example, the bit lines B extend in the Y-axis direction and are arranged side by side in the X-axis direction. However, the bit lines do not necessarily have to be in direct contact with the word lines W and can be separated from the word lines W in the Z-axis direction. It is noted that although in Fig. Figure 1 illustrates an example in which an n number of bit lines B are provided; it is possible to set the number of bit lines B to any desired number. However, in one embodiment, the number of word lines W can be greater than the number of bit lines B. One reason for this is that it is advantageous for preventing a temperature rise of each resistive element R after a resistance value of each resistive element R has been read. [Resistance element R]

[0015] The resistive elements R are each arranged at the interface of a corresponding word line W and a corresponding bit line B. Each resistive element R can have a first end coupled to the corresponding word line W and a second end coupled to the corresponding bit line B. For example, resistive elements R(1,1) to R(1,n) can each be arranged at a corresponding interface of word line W1 and bit lines B1 to Bn, resistive elements R(2,1) to R(2,n) can each be arranged at a corresponding interface of word line W2 and bit lines B1 to Bn, and resistive elements R(m,1) to R(m,n) can each be arranged at a corresponding interface of word line Wm and bit lines B1 to Bn.

[0016] The resistive element R can be an infrared radiation receiving element, which, for example, converts infrared radiation collected by a lens into an electrical signal. In one example, the resistive element R can be a microbolometer comprising: a variable resistance layer, which exhibits a change in resistance depending on a temperature; and an infrared absorption layer, which is positioned adjacent to the variable resistance layer and absorbs infrared radiation, generating heat. The variable resistance layer can, for example, consist of vanadium oxide. The infrared absorption layer can, for example, consist of silicon dioxide (SiO₂). In the resistive element R, the temperature in the infrared absorption layer changes depending on the intensity of the absorbed infrared radiation, and consequently, the resistance value of the variable resistance layer adjacent to the infrared absorption layer changes. [SEL selection facility]

[0017] The selection device SEL can have a selection switch SW1 and a selection switch SW2. The selection switch SW1 selects a word line Ws from the word lines W and can cause the selected word line Ws to be coupled to the wiring line L1. It is noted that Fig. Figure 1 illustrates an example in which the selection switch SW1 selects the word line W2 as the selected word line Ws and couples the word line W2 with the wiring line L1. Alternatively, the selection switch SW2 selects a bit line Bs from the bit lines B. Fig. Figure 1 illustrates an example in which the selector switch SW2 selects bit line B2 as the selected bit line Bs and couples bit line B2 to the wiring line L3. Operations of selector switches SW1 and SW2, which are available in the selector unit SEL, can be executed based on a command transmitted by the controller CTRL. [Differential Amplifier AMP]

[0018] The differential amplifier AMP has a positive input terminal T1, a negative input terminal T2, and an output terminal T3. The positive input terminal T1 is configured to be coupled to the selected bit line B, which is selected by the selector switch SW2. The negative input terminal T2 is configured to be coupled to an unselected bit line B, which is not selected by the selector switch SW2, and to an unselected word line W, which is not selected by the selector switch SW1. The negative input terminal T2 can be coupled to the unselected bit line B and the unselected word line W via the wiring line L2. The output terminal T3 is coupled to the negative input terminal T2. The output terminal T3 can be coupled to the negative output terminal T2 via the wiring line L2. [Ground connection GND and resistor RG]

[0019] The ground terminal GND is connected to the positive input terminal T1. The ground terminal GND can also be connected to the positive input terminal T1 via the wiring line L3. The resistor RG can be provided on the wiring line L3 between the ground terminal GND and the positive input terminal T1. The resistor RG can be a variable resistor or a fixed resistor. [Controller CTRL]

[0020] The CTRL controller can control the current supply V to cause a read current C to be fed sequentially via the word lines W to the respective resistor elements R, which are arranged in the Y-axis direction along the bit line B. It is noted that the current supply V can be provided within or outside of the resistor element array circuit 1. [Reading process of the resistor array circuit 1]

[0021] The resistor element array circuit 1 is able to read a resistance value in each resistor element R, for example, in the following way.

[0022] In an exemplary case, the controller CTRL can, provided that in the resistor element array circuit 1 an (m×n) number of resistor elements R are arranged in a matrix, that is, an m number of resistor elements R are arranged in the Y-axis direction and an n number of resistor elements R are arranged in the X-axis direction, sequentially read the current C in a circuit through which a resistor is arranged in a matrix. Fig. 1. The arrow A illustrates the sequence in which all of the (m×n) number of resistor elements R are fed, and can cause the output signal S to be output from the output terminal T3 of the differential amplifier AMP.

[0023] In one example, the controller CTRL can sequentially supply the read current C to the resistor elements R, starting, for example, with resistor element R(1,1) as the first resistor element R, then from resistor element R(2,1) to resistor element R(m,1), i.e., those arranged in the Y-axis direction, such that the resistor elements R are counted sequentially. That is, the controller CTRL can perform a control operation that first causes the selector switch SW2 to select bit line B1, and which, for resistor elements R(1,1), R(2,1), R(3,1), ... and R(m,1), i.e., those arranged along bit line B1, causes the selector switch SW1 to sequentially select word lines W1 to Wm, thereby causing the current supply V to apply the read current C sequentially to word lines W1 to Wm.

[0024] The controller CTRL can then supply the read current C sequentially to the resistor elements R, from resistor element R(1,2) to resistor element R(m,2), i.e., those arranged in the Y-axis direction, such that the resistor elements R are counted one after the other. That is, the controller CTRL can perform a control action that causes the selector switch SW2 to select bit line B2, and which, for the resistor elements R(1,2), R(2,2), R(3,2), ... and R(m,2), i.e., those arranged along bit line B2, causes the selector switch SW1 to select word lines W1 to Wm sequentially, thereby causing the current supply V to apply the read current C sequentially to the word lines W1 to Wm.

[0025] The controller CTRL can then sequentially supply the read current C to the resistor elements R, from resistor element R(1,n) to resistor element R(m,n), i.e., those arranged in the Y-axis direction, such that the resistor elements R are counted sequentially. That is, the controller CTRL can perform a control operation that causes the selector switch SW2 to select the bit line Bn, and which, for the resistor elements R(1,n), R(2,n), R(3,n), ... and R(m,n), i.e., those arranged along the bit line Bn, causes the selector switch SW1 to sequentially select the word lines W1 to Wm, thereby causing the current supply V to apply the read current C sequentially to the word lines W1 to Wm.

[0026] In this way, the resistor element array circuit 1 is able to read a resistance value of each resistor element R as an output signal S from the output terminal T3 of the differential amplifier AMP.

[0027] It is noted that Fig. Figure 1 illustrates a path for the read current C, along which the resistor R(2,2) is selected. In resistor array circuit 1, the word line W2 can be selected by switch SW1, and the bit line B2 can be selected by switch SW2. In this case, the read current C can be supplied from the power supply V to word line W2 via wiring line L1, after which the read current C can flow through resistor R(2,2) and into wiring line L3. The read current C can then flow through resistor RG and out to ground (GND). The magnitude of the read current C can be limited depending on the resistance value of resistor RG, and it is therefore possible to reduce the electrical current consumption during the read operation in resistor array circuit 1 depending on the resistance value of resistor RG. [Functions and exemplary effects of the resistor element array circuit 1]

[0028] As described above, the resistive element array circuit 1 according to the first embodiment comprises the differential amplifier AMP, which includes: the positive input terminal T1, which is configured to be coupled to the selected bit line B, which is selected by the selector SEL; the negative input terminal T2, which is configured to be coupled to an unselected bit line and an unselected word line; and the output terminal T3, which is coupled to the negative input terminal T2. Accordingly, the positive input terminal T1, the negative input terminal T2, and the output terminal T3 present in the differential amplifier AMP each have substantially the same electrical potential.Therefore, the output signal S is essentially not affected by the electrical potential of the unselected bit line and the electrical potential of the unselected word line and has more precise values.

[0029] Furthermore, the resistor array circuit 1 according to the first embodiment can also include the resistor RG, which is provided between the positive input terminal T1 of the differential amplifier AMP and the ground terminal GND. Accordingly, it is possible to limit the read current C flowing into the ground terminal GND by setting the resistance value of the resistor RG to a suitable value. Consequently, it is possible to reduce the electrical current consumption during the entire read operation performed in the resistor array circuit 1.

[0030] The infrared detection circuit disclosed in unexamined Japanese patent application (J-PA) No. H08-94443, however, couples an output from a selected cell to a negative output terminal of an inverting amplifier op-amp and couples a positive input terminal of the inverting amplifier op-amp to ground. Furthermore, the infrared detection circuit from J-PA No. H08-94443 couples both an unselected row and an unselected column to ground, causing an electrical potential of the unselected row and an electrical potential of the unselected column to be equal to the electrical potential of the inverting amplifier op-amp. The infrared detection circuit from J-PA No. H08-94443 avoids leakage current from the unselected row through the configuration described above.However, according to H08-94443, a reading current flowing into the unselected series consequently flows into the ground, which can significantly increase the electrical power consumption in the entire infrared detection circuit.

[0031] In this respect, the resistor array circuit 1 according to the first embodiment causes the positive input terminal T1, the negative input terminal T2, and the output terminal T32, which are present in the differential amplifier AMP, to have essentially the same electrical potential with each other, and also features the resistance RG. Therefore, it is possible to increase the stability of the output signal S and to limit the read current C flowing to the ground terminal GND, thereby reducing the electrical current consumption during the entire read operation performed in the resistor array circuit 1. That is to say, the resistor array circuit 1 according to the first embodiment predictably exhibits higher operational reliability with lower electrical current consumption.

[0032] Furthermore, in such a resistor array circuit 1, the reading current C is supplied to the resistor R as described above, whereupon the resistance value of the resistor R is read. However, the resistor R can generate heat through the supply of the reading current C. In some cases, this can influence the resistance value, which is intended to change depending on the radiant heat being measured. In the resistor array circuit 1 according to the first embodiment, a case can occur in which the reading current C, although a small amount, flows to an unselected resistor R, which is not the selected resistor R. As shown in the explanatory diagram from Fig. Figure 2 illustrates that a leakage current CC can occur, for example, in a case where the word line W2 is selected by the selector switch SW1 and the bit line B2 is selected by the selector switch SW2, for instance, on a path marked CC by an arrow. In this case, the resistance value of the unselected resistor R can increase because the unselected resistor R, through which the leakage current CC passes, generates heat. Consequently, the output signal S, which contains information regarding the intensity of the absorbed infrared rays, can be affected.

[0033] Accordingly, in the resistor array circuit 1, the controller CTRL can control the current supply V to cause the read current C to be supplied sequentially via the word lines W to the resistor elements R, which are arranged along the bit line B in the Y-axis direction. In this way, it is possible to suppress the influence on the output signal S caused by the heat generated by the leakage current. One reason for this is that the period during which the read current C flows continuously with respect to a single word line W (period of continuous electrical current supply) is shorter compared to a case in which, for example, the respective resistance values ​​of the resistor elements R, which are arranged along a word line W in the Y-axis direction, are read sequentially.In other words, extending the period of continuous electrical current supply with respect to a single word line W also increases the amount of heat generated in the resistive elements R arranged along the word line W. However, since the controller CTRL is able to shorten the period of continuous electrical current supply by controlling the current supply V as described above, it is possible to reduce the amount of heat generated in the resistive element R.

[0034] Furthermore, the resistor array circuit 1 is able to suppress the influence on the output signal S caused by the heat generated by the resistor element R in a case where the number "m" of word lines W is less than the number "n" of bit lines B (m>n). Some reasons for this are given below. One reason is that in a case where the same number of resistor elements R are arranged as when m>n, it is possible to reduce the number of resistor elements R arranged in each word line W compared to a case where the number "n" of bit lines is greater than the number "m" of word lines W (m <n), zu verringern. Daher ist es möglich, ein Gesamtmaß an Wärmeerzeugung sämtlicher entlang einer Wortleitung W angeordneten Widerstandselemente R zu unterbinden, wenn der Lesestrom C der relevanten Wortleitung W zugeführt wird.Another reason is that, in the case where the same number of resistive elements R are arranged as the number of resistive elements R when m>n, it is possible to maintain a time interval from the end of the successive electrical current supply to the word lines W until the beginning of the next successive electrical current supply to the same word lines W, compared to the case where the number "n" of bit lines B is greater than the number "m" of word lines W (m <n), zu erhöhen. Daher ist es möglich, einen längeren Zeitraum zur Kühlung der entlang jeder Wortleitung W angeordneten Widerstandselemente R zu gewährleisten und einen Temperaturanstieg in den entlang jeder Wortleitung W angeordneten Widerstandselementen R zu unterbinden. [2. Second embodiment][Overall design example of the resistor element array circuit unit 2]

[0035] Fig. Figure 3 is a schematic diagram illustrating an overall design example of a resistor array circuit unit 2 according to a second embodiment of the disclosure. The resistor array circuit unit 2 has a plurality of resistor array circuits 1 (1A to 1D). It is noted that although Fig.Figure 3 illustrates an example in which four resistor array circuits 1A to 1D are present; any embodiment of the disclosure is not limited thereto. Furthermore, the resistor array circuits 1A to 1D each have essentially the same configuration as the resistor array circuit 1 described in the first embodiment. However, in the resistor array circuit unit 2, a controller CTRL is not present in any of the resistor array circuits 1A to 1D, and a controller 3 is provided jointly to all resistor array circuits 1A to 1D.

[0036] The controller 3 simultaneously performs a read control of the resistor element array circuits 1A to 1D. The read control can control the current supply V to cause the read current C to be supplied sequentially via the word lines W to the resistor elements R, which are arranged in the Y-axis direction along a bit line B. Furthermore, the controller 3 can include a memory 31 and a central processing unit (CPU) 32. In one embodiment of the disclosure, the CPU 32 corresponds to a specific, but non-limiting, example of a "processor". The memory 31 can contain a plurality of resistance value data pieces, which are read from the resistor element array circuits 1A to 1D by the aforementioned read control. The CPU 32 can output the resistance value data pieces stored in the memory 31 sequentially.

[0037] As described above, in the resistor element array circuit unit 2 according to the second embodiment, a plurality (for example, four) areas, i.e., resistor element array circuits, are assigned to a plurality of resistor elements arranged in a matrix, and the reading operation on the areas is performed simultaneously. Therefore, it is possible to obtain the output signal S in a shorter time. [3. Modification example]

[0038] Some embodiments of the disclosure have been described above. However, the disclosure is not limited to such embodiments and can be modified in various ways.

[0039] The description of the preceding embodiments of the disclosure was presented, for example, with reference to specific examples of configurations (such as the arrangement and number) of the respective components of the resistor element array circuit 1. However, the examples of configurations of the respective components are not limited to those described in the preceding embodiments; for example, any other arrangement and any other number can be implemented.

[0040] Furthermore, according to the preceding embodiments of the disclosure, the case was described in which the resistive element array circuit is mounted on an infrared thermographic system, and the infrared rays irradiating the resistive element array circuit are converted into an electrical signal corresponding to the intensity of the infrared rays, and the electrical signal is output as the output signal S. However, the disclosure is not limited to this. For example, the resistive element is not limited to a microbolometer and can be a magnetic tunnel junction element. In this case, it is possible to use the resistive element array circuit as a magnetoresistive random-access memory (MRAM) circuit.

[0041] Furthermore, in the resistor element array circuit unit 2 described in the second embodiment, the resistor element array circuits 1 (1A to 1D) can be provided on the same substrate or can be provided on two or more substrates.

[0042] Furthermore, a series of processes described in the preceding embodiments of the disclosure can be executed by hardware (circuit) or software (program). In a case where the series of processes is executed by software, the software is provided by a group of programs that cause a computer to perform various functions. Each program can be used by pre-storing it on the computer or by installing it on the computer from a network or storage medium.

[0043] It should be noted that the effects described here are merely exemplary and not limiting, and may include other effects.

[0044] In one embodiment, the resistive element array circuit and the resistive element array circuit unit can each be used, for example, for infrared thermography or an infrared sensor. In another embodiment, the resistive element array circuit and the resistive element array circuit unit can be used as a memory processing circuit, which employs a magnetoresistive element or a variable resistance element as the resistive element, the latter of which changes its resistance depending on an electrical voltage.

[0045] Furthermore, the disclosure includes any possible combination of some or all of the various embodiments and modification examples described and incorporated herein.

[0046] According to the resistive element array circuit, the resistive element array circuit unit, and the infrared sensor in one embodiment of the disclosure, the positive input terminal, the negative input terminal, and the output terminal present in the differential amplifier can each have substantially the same electrical potential. Therefore, the resistive element array circuit, the resistive element array circuit unit, and the infrared sensor are not affected by an electrical potential in the unselected bit line and the unselected word line, and any variation of an electrical voltage is prevented.

[0047] According to the resistor element array circuit, the resistor element array circuit unit and the infrared sensor in an embodiment of the disclosure, it is possible to achieve higher operational reliability.

Claims

[1] Resistor element array circuit (1), comprising: a multitude of word lines (W, W1 to Wm) which extend in a first direction (X) and are arranged side by side in a second direction (Y); a multitude of bit lines (B, B1 to Bn) which extend in the second direction (Y) and are arranged side by side in the first direction (X); a plurality of resistive elements (R, R(1,1) to R(m,n)), each of which is arranged at an interface of a word line (W, W1 to Wm) and a bit line (B, B1 to Bn) and each of which is coupled to the word line (W, W1 to Wm) and the bit line (B, B1 to Bn); a selection device (SEL) configured to select one (Ws) of the word lines (W, W1 to Wm) and one (Bs) of the bit lines (B, B1 to Bn); and a differential amplifier (AMP) having a positive input terminal (T1), a negative input terminal (T2) and an output terminal (T3), wherein the positive input terminal (T1) is configured to be coupled to the selected (Bs) of the bit lines (B, B1 to Bn) which is selected by the selection device (SEL), wherein the negative input terminal (T2) is configured to be coupled to at least one unselected of the bit lines (B, B1 to Bn) which is not selected by the selection device (SEL), and at least one unselected of the word lines (W, W1 to Wm) which is not selected by the selection device (SEL), wherein the output terminal (T3) is coupled to the negative input terminal (T2); wherein the selected (Ws) of the word lines (W, W1 to Wm), which is selected by the selection device (SEL), is set up to be coupled with a power supply (V). [2] Resistor element array circuit (1) according to claim 1, further comprising a ground terminal (GND) coupled to the positive input terminal (T1) and a resistor (RG) provided between the positive input terminal (T1) and the ground terminal (GND). [3] Resistor element array circuit (1) according to claim 1 or 2, further comprising a controller (CTRL) which is configured to control the current supply (V) to cause an electric current to be supplied successively via the word lines (W, W1 to Wm) to the resistive elements (R, R(1,1) to R(m,n)) which are arranged in the second direction (Y) along the selected bit lines (Bs). [4] Resistor element array circuit (1) according to any one of claims 1 to 3, wherein a number (m) of word lines (W, W1 to Wm) is greater than a number (n) of bit lines (B, B1 to Bn). [5] Resistor element array circuit unit (2) comprising: a plurality of resistor element array circuits (1, 1A to 1D), wherein the plurality of resistor element array circuits (1, 1A to 1D) each have a multitude of word lines (W, W1 to Wm) which extend in a first direction (X) and are arranged side by side in a second direction (Y), a multitude of bit lines (B, B1 to Bn) which extend in the second direction (Y) and are arranged side by side in the first direction (X), a plurality of resistive elements (R, R(1,1) to R(m,n)), each of which is arranged at an interface of a word line (W, W1 to Wm) and a bit line (B, B1 to Bn) and each of which is coupled to the word line (W, W1 to Wm) and the bit line (B, B1 to Bn), a selection device (SEL) which is set up to select one (Ws) of the word lines (W, W1 to Wm) and one (Bs) of the bit lines (B, B1 to Bn), a differential amplifier (AMP) having a positive input terminal (T1), a negative input terminal (T2) and an output terminal (T3), wherein the positive input terminal (T1) is configured to be coupled to the selected (Bs) of the bit lines (B, B1 to Bn) selected by the selection device (SEL), wherein the negative input terminal (T2) is configured to be coupled to at least one unselected bit line (B, B1 to Bn) not selected by the selection device (SEL), and at least one unselected word line (W, W1 to Wm) not selected by the selection device (SEL), and wherein the output terminal (T3) is coupled to the negative input terminal (T2); and a controller which is configured to perform read control of the resistor element array circuits (1, 1A to 1D) simultaneously, comprising controlling a current supply (V) to cause an electric current to be supplied sequentially via the word lines (W, W1 to Wm) to the resistor elements (R, R(1,1) to R(m,n)) which are arranged in the second direction (Y) along the one selected bit line (Bs), wherein the selected (Ws) of the word lines (W, W1 to Wm), which is selected by the selection device (SEL), is set up to be coupled with the power supply (V). [6] Resistor element array circuit unit (2) according to claim 5, wherein the controller (3) comprises: a memory (31) which is configured to store a plurality of resistance value data, each of which is read by the read control from the resistor element array circuits (1, 1A to 1D); and a processor (32) which is configured to output the resistance value data stored in the memory (31) one after the other. [7] Infrared sensor comprising a resistive element array circuit (1) according to claim 1. [8] Infrared sensor comprising a resistive element array circuit unit (2) according to claim 5.

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