METHOD FOR MANUFACTURING AN MRAM STORAGE DEVICE

Abstract

Method for manufacturing a storage device, comprising: Formation of a first magnetoresistive random access memory cell, MRAM cell (134), over a substrate; Formation of a second MRAM cell (136) above the substrate; Forming an intermediate dielectric layer, ILD layer (140), over the substrate, wherein the ILD layer (140, 502) comprises side walls that define a first well (141) between the first MRAM cell (134) and the second MRAM cell (136); Forming a dielectric layer (142, 144, 504, 602) over the ILD layer (140, 502) wherein the dielectric layer (142, 144, 504, 602) comprises sidewalls that define a second well (610) directly above the first well (141); and Removing the second well (610), a section of the ILD layer (140, 502) and a section of the dielectric layer (142, 144, 504, 602), wherein an upper surface of the ILD layer (140, 502) and an upper surface of the dielectric layer (142, 144, 504, 602) meet at a horizontal line, wherein the horizontal line is substantially straight, the procedure, prior to the removal of the second tub (610), further comprises: Performing a first etching process to remove a section of the ILD layer (140, 502) and a section of the dielectric layer (142, 144, 504, 602), wherein the first etching process defines a second top surface of the ILD layer (140, 502) and a second top surface of the dielectric layer (142, 144, 504, 602); and Filling the second vat (610) with a first material, wherein the first material is the same material as a material comprising the dielectric layer (142, 144, 504, 602), wherein an upper surface of the first material is located above the second upper surface of the ILD layer (140, 502) and the second upper surface of the dielectric layer (142, 144, 504, 602).

Description

GENERAL STATE OF THE ART

[0001] Many modern electronic devices contain electronic memory. This electronic memory can be volatile or non-volatile. Non-volatile memory retains its stored data even without power, whereas volatile memory loses its data when power is lost. Magnetoresistive Random Access Memory (MRAM) is a promising candidate for next-generation non-volatile electronic memory due to its advantages over current electronic memory. Compared to current non-volatile memory, such as flash memory, MRAM is typically faster and has better endurance.Compared to current volatile memory, such as Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM), MRAM typically exhibits similar performance and density, but lower energy consumption.

[0002] Document US 2017 / 0194557A1 describes a semiconductor structure with memory cells comprising a magnetic tunnel junction, an upper electrode over the magnetic tunnel junction, and a metal layer over the upper electrode. The memory cells are covered with a dielectric protective layer.

[0003] Document US 2018 / 0261649A1 describes a method for forming a semiconductor structure, which involves forming pillar structures on the top surface of a substrate. Contacts are formed between the pillar structures and the contacts. An insulator is formed between the pillar structures and the contacts.

[0004] Document US 2018 / 0097175A1 describes a semiconductor device structure comprising a magnetoresistive random-access memory device within an insulating layer. The semiconductor device structure includes a first electrode, a magnetic tunnel junction above the first electrode, a second electrode above the magnetic tunnel junction, and an insulating spacer surrounding the sidewalls of the first electrode, the magnetic tunnel junction, and the second electrode. The top surfaces of the insulating spacer and the second electrode protrude from the insulating layer. The semiconductor device structure also includes a conductive pad above the insulating layer that is electrically connected to the second electrode.

[0005] The task is to improve appropriate storage devices.

[0006] The problem is solved by the method for manufacturing a storage device according to claim 1. Further embodiments of the invention are described in the dependent claims.

[0007] the BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Aspects of this disclosure are best understood from the following detailed description in conjunction with the accompanying figures. Note that, in accordance with industry practice, various features are not drawn to scale. The dimensions of the various features may have been arbitrarily enlarged or reduced for the clarity of the discussion. Fig. Figure 1 shows a cross-sectional view of some embodiments of a storage device comprising two MRAM cells, each with a magnetic tunnel junction (MTJ), according to the present disclosure. Fig. Figure 2 shows a cross-sectional view of some embodiments of a storage device comprising an embedded memory area comprising two MRAM cells, each with a magnetic tunnel junction (MTJ), and a logic area, according to the present disclosure. Fig. Figures 3A-3B represent top views of some embodiments of a storage device comprising an embedded memory area comprising two MRAM cells and a logic area, according to the present disclosure. Fig. Figures 4-14 represent cross-sectional and / or top views of some embodiments of a method for forming a storage device comprising an embedded memory area comprising two MRAM cells, each with an MTJ, and a logic area, according to the present disclosure. Fig. Figure 15 presents a method in the form of a flowchart, which illustrates some embodiments of a method for forming a storage device comprising two MRAM cells according to the present disclosure. DETAILED DESCRIPTION

[0009] The present disclosure provides many different embodiments or examples for realizing various features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are in direct contact, and also embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and, in itself, does not establish any relationship between the various designs and / or configurations discussed.

[0010] Furthermore, for the sake of simplicity, spatially relative terms such as "below," "under," "lower," "above," "upper," and the like may be used here to describe the relationship of one element or feature to another element(s) or feature(s), as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device during use or operation, in addition to the orientation depicted in the figures. The device may be oriented differently (rotated by 90 degrees or with other orientations), and the words used herein to describe spatial relations may be interpreted accordingly.

[0011] Magnetoresistive random-access memory (MRAM) cells are located in an embedded memory area, generally within an interconnected local area diagram (ILD) structure surrounding stacked interconnect layers, above a substrate. The MRAM cells are generally contained within an array of multiple MRAM cells arranged in rows and columns. The multiple MRAM cells are separated from each other by a similar spacing. An MRAM cell generally includes a magnetic tunnel junction (MTJ) located between a top-side and a bottom-side electrode. The bottom-side electrode is coupled to the stacked interconnect layers via a bottom-side electrode via, while the top-side electrode is coupled to the stacked interconnect layers via a top-side electrode via.

[0012] MRAM cells can be fabricated by forming an inter-level dielectric (ILD) over magnetic tunnel junctions (MTJs), followed by a chemical machining (CMP) process to provide a flat surface. The top-end electrode via is then formed by etching the ILD to create an opening over the top electrode of each MRAM cell. This opening is subsequently filled with one or more conductive materials. A CMP process is then performed to remove any excess conductive material, thus forming the top-end electrode via. A bit line is placed over the top-end electrode via. One bit line is placed over each row of MRAM cells.

[0013] It is known that the topography of MTJs can cause the ILD to have sidewalls and a top surface that define a recess between each pair of MRAM cells. The conductive materials used to form the top-side vias can also fill the recess within the ILD layer, so that after performing the CMP process to form the top-side vias, conductive material is present in the recess defined by the ILD. The presence of conductive material at the same level as the top-side vias between MRAM cells in the embedded memory area can cause performance issues.For example, the conductive material within the recess can shorten the distance between adjacent top-side electrode vias, leading to time-dependent dielectric breakdown (TDDB), and / or the conductive material within the recess can cause bit-to-bit short-circuit problems between successive rows of the MRAM cell array, resulting in yield loss and power failures.

[0014] The present disclosure relates, in some embodiments, to a method for constructing a memory device with two or more MRAM cells which, at an upper level of the top-side electrode vias, have no conductive material between corresponding top-side electrode vias of the MRAM cells. The absence of conductive material prevents power failures in the memory device, for example, due to a short circuit between successive bit lines.

[0015] Referring to Fig. Figure 1 provides a cross-sectional view of a storage device 100 according to some embodiments.

[0016] The storage device 100 comprises a first inter-level dielectric (ILD) layer 106 arranged over a substrate 101. Several transistors 102 are located within the substrate 101 and the first ILD layer 106. A first magnetoresistive random-access memory (MRAM) cell 134 is connected to one of the several transistors 102 via a conductive contact 104 and a connecting wire 108. A second MRAM cell 136 is connected to a second of the several transistors 102 via a conductive contact 104 and a connecting wire 108.

[0017] The first MRAM cell 134 and the second MRAM cell 136 each comprise a lower electrode 120 arranged above a bottom electrode via 119, which includes a lower metal layer 116 and a diffusion barrier 118. The diffusion barrier 118 covers the lower metal layer 116. The first MRAM cell 134 and the second MRAM cell 136 each further comprise an upper electrode 130, which is separated from the lower electrode 120 by a magnetic tunnel junction (MTJ) 122. The diffusion barrier 118 and the lower metal layer 116 are arranged within a first lower dielectric layer 110 and a second lower dielectric layer 112. In some embodiments, a center of the diffusion barrier 118 and a center of the lower metal layer 116 are aligned with a center of the MTJ 122. The lower electrode 120 is arranged within a third lower dielectric layer 114.A top-side electrode via 138 is arranged above the top electrode 130. A first sidewall spacer 128 surrounds the first MRAM cell 134 and the second MRAM cell 136. A second sidewall spacer 132 surrounds a section of the top electrode 130 and the top-side electrode via 138. In some embodiments, the bottom electrode 120 and the top electrode 130 may comprise copper, aluminum, titanium, tantalum, or the like. In some embodiments, the bottom electrode 120 may have a thickness in a range between approximately 5.0 nm and approximately 50.0 nm. In some embodiments, the top electrode 130 may have a thickness in a range between approximately 10.0 nm and approximately 60.0 nm and a width in a range between approximately 30.0 nm and approximately 100.0 nm.

[0018] A second ILD layer 140 surrounds the first MRAM cell 134, the second MRAM cell 136, and the top-side electrode via 138. The second ILD layer 140 comprises sidewalls that define a well 141 (e.g., a rhombus well) between the first MRAM cell 134 and the second MRAM cell 136. In some embodiments, the well 141 contains one or more dielectric materials. For example, the well 141 may include a first upper dielectric layer 142 arranged over a portion of the second ILD layer 140, and / or a second upper dielectric layer 144 arranged over the first upper dielectric layer 142. An upper surface of the second ILD layer 140, which defines the well 141, is in contact with a lower surface of the portion of the first upper dielectric layer 142. In some embodiments, the one or more dielectric materials completely fill the well 141.In some embodiments, the one or more dielectric materials have a planar top surface that is aligned with a top surface of the second ILD layer 140 and extends continuously between the side walls of the second ILD layer 140. In some embodiments, the well 141 does not contain any conductive (e.g., metallic) materials. Top surfaces of the one or more dielectric materials and a top surface of the top electrode via 138 are defined by a horizontal line. In some embodiments, the horizontal line is substantially straight. The top surface of the second ILD layer 140, which defines the well 141, is located above a top surface of the first MRAM cell 134 and a top surface of the second MRAM cell 136.In some embodiments, a top surface of the second ILD layer 140 is located below a top surface of the second upper dielectric layer 144.

[0019] The MTJ 122 comprises a lower ferromagnetic electrode 124 and an upper ferromagnetic electrode 126, separated from each other by a tunnel barrier layer 125. In some embodiments, the lower ferromagnetic electrode 124 may have a fixed or "determined" magnetic orientation, while the upper ferromagnetic electrode 126 may have a variable or "free" magnetic orientation that can be switched between two or more different magnetic polarities, each representing a different data state, such as a different binary state. In other realizations, however, the MTJ 122 may be vertically "tilted" such that the lower ferromagnetic electrode 124 has a "free" magnetic orientation, while the upper ferromagnetic electrode 126 has a "determined" magnetic orientation.

[0020] In some embodiments, the upper ferromagnetic electrode 126 comprises iron, cobalt, nickel, iron-cobalt, nickel-cobalt, cobalt-iron boride, iron boride, iron-platinum, iron-palladium, or the like. In some embodiments, the upper ferromagnetic electrode 126 has a thickness in the range of approximately 5.0 nm to approximately 20.0 nm and a width in the range of approximately 50.0 nm to 130.0 nm. In some embodiments, the tunnel barrier layer 125 provides electrical insulation between the upper ferromagnetic electrode 126 and the lower ferromagnetic electrode 124, while still allowing electrons to pass through the tunnel barrier layer 125 under suitable conditions. The tunnel barrier layer 125 can, for example, comprise magnesium oxide (MgO), aluminum oxide (e.g. Al2O3), nickel oxide, gadolinium oxide, tantalum oxide, molybdenum oxide, titanium oxide, tungsten oxide or the like.In some embodiments, the tunnel barrier layer 125 has a thickness in a range between approximately 0.5 nm and approximately 5.0 nm and a width in a range between approximately 50.0 nm and 130.0 nm. In some embodiments, the lower ferromagnetic electrode 127 has a thickness in a range between approximately 5.0 nm and approximately 20.0 nm and a width in a range between approximately 50.0 nm and 130.0 nm.

[0021] A third ILD layer 146 is arranged above the second ILD layer 140, the first upper dielectric layer 142, the second upper dielectric layer 144, and the top-side electrode via 138. The top surface of one or more dielectric materials within the well 141 is in contact with a bottom surface of the third ILD layer 146. In some embodiments, one or more dielectric materials and no metallic material are present from the top surface of the second ILD layer 140, which defines the well 141, to the bottom surface of the third ILD layer 146. A second conductive via 148 is arranged above the top-side electrode via 138. In some embodiments, the second conductive via 148 may, for example, comprise copper or aluminum. A second conductive wire 150 is arranged above the second conductive via 148.In some embodiments, the second conductive wire 150 can, for example, comprise copper or aluminum. The third ILD layer 146 surrounds the second conductive via 148 and the second conductive wire 150. The second conductive wire 150 extends beyond the sidewalls of the second conductive via 148.

[0022] Because the well 141 contains one or more dielectric materials, residual metal from the formation of the top-side electrode via 138 cannot fill the well 141. The absence of metal material between the top-side electrode via 138 of the first MRAM cell 134 and the top-side electrode via 138 of the second MRAM cell 136 prevents short-circuiting between bit lines arranged above the first MRAM cell 134 and the second MRAM cell 136. This increases the yield of an array of multiple MRAM cells in which the MRAM cells are arranged in rows and columns, with a bit line positioned above each row of the array.

[0023] Fig. Figure 2 shows a cross-sectional view of some additional embodiments of a storage device 200.

[0024] The memory device 200 comprises an embedded memory area 201a and a logic area 201b. The multiple transistors 102 are located within the substrate 101 and the first ILD layer 106. The substrate 101 can be, for example, a solid substrate (e.g., a solid silicon substrate) or a silicon-on-insulator (SOI) substrate. Each of the multiple transistors 102 comprises a gate electrode 206, transistor sidewall spacers 205, a gate dielectric 204, and source / drain areas 202. A connecting wire 108 is connected to one of the multiple transistors 102 via a conductive contact 104. In some embodiments, the connecting wire 108 can comprise, for example, copper or aluminum.

[0025] The first lower dielectric layer 110 is arranged above the connecting wire 108 and the first ILD layer 106. In some embodiments, the first lower dielectric layer 110 may comprise silicon carbide (SiC), silicon oxycarbide, silicon nitride, silicon oxide, or the like, with a thickness in the range of approximately 15.0 nm to approximately 35.0 nm. The second lower dielectric layer 112 is arranged above the first lower dielectric layer 110. In some embodiments, the second lower dielectric layer 112 may comprise silicon-rich oxide, silicon oxide, or the like, with a thickness in the range of approximately 10.0 nm to approximately 30.0 nm.

[0026] In logic area 201b, a fourth lower dielectric layer 214 is arranged above the second lower dielectric layer 112. In some embodiments, the fourth lower dielectric layer 214 may comprise tetraethyl orthosilicate (TEOS) (e.g., plasma-enhanced TEOS, particle-free TEOS, etc.), an oxide (e.g., silicon oxide, silicon dioxide, etc.), a nitride, or the like. In some embodiments, the fourth lower dielectric layer 214 may have a thickness in the range of approximately 5.0 nm to approximately 25.0 nm. A first conductive via 208 is arranged above the connecting wire 108 within logic area 201b. In some embodiments, the first conductive via 208 may comprise, for example, copper or aluminum. A second conductive wire 150 is arranged above the first conductive via 208.In some embodiments, the second conductive wire 150 may, for example, comprise copper or aluminum. The third ILD layer 146 surrounds the first conductive via 208 and the second conductive wire 150. In some embodiments, the third ILD layer 146 may comprise a low k-value dielectric, silicon dioxide, carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), boron phosphosilicate glass (BPSG), fluorosilicate glass (FSG), a porous dielectric material, or the like. The second conductive wire 150 extends beyond the sidewalls of the first conductive via 208.

[0027] In the embedded memory region 201a, the third lower dielectric layer 114 is arranged above the second lower dielectric layer 112. In some embodiments, the third lower dielectric layer 114 has a greater thickness than the fourth lower dielectric layer 214. In some embodiments, the third lower dielectric layer 114 may comprise silicon oxycarbide (SiOC), silicon carbide, silicon nitride, silicon oxide, or the like. In some embodiments, the third lower dielectric layer 114 may have a thickness in the range of approximately 20.0 nm to approximately 40.0 nm.

[0028] A bottom-side electrode via 119 is arranged above the connecting wire 108. The bottom-side electrode via 119 comprises a diffusion barrier 118 and a bottom metal layer 116. In some embodiments, the bottom-side electrode via 119 has a thickness in a range between approximately 30.0 nm and approximately 110.0 nm and a width in a range between approximately 20.0 nm and approximately 190.0 nm. The diffusion barrier 118 is in contact with side walls, a bottom surface, and a top surface of the bottom metal layer 116. A top surface of the diffusion barrier 118 is located above a top surface of the second lower dielectric layer 112. The top surface of the diffusion barrier 118 is in direct contact with a bottom surface of the lower electrode 120.In some embodiments, the center of the diffusion barrier 118 and the center of the lower metal layer 116 are offset to the left or right relative to the center of the MTJ 122. In some embodiments, a conductive element 207 (e.g., a sub-resolution assist feature - SRAF) is arranged between the connecting wire 108 located below the first MRAM cell 134 and the connecting wire 108 located below the second MRAM cell 136. In some embodiments, the well 141 is located directly above the conductive element 207, and outer sidewalls of the conductive element 207 extend beyond the sidewalls of the well 141.

[0029] The second ILD layer 140 is arranged above the third lower dielectric layer 114, the first MRAM cell 134, and the second MRAM cell 136. In some embodiments, the second ILD layer 140 may comprise a low k-value dielectric, silicon dioxide, carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), boron phosphosilicate glass (BPSG), fluorosilicate glass (FSG), a porous dielectric material, or the like. In some embodiments, the second ILD layer 140 may have a thickness in the range of approximately 70.0 nm to approximately 130.0 nm. The first upper dielectric layer 142 is arranged above the second ILD layer 140. In some embodiments, the first upper dielectric layer 142 may comprise silicon oxynitride (SiON), silicon carbide, silicon nitride, silicon oxide or the like.In some embodiments, the first upper dielectric layer 142 can have a thickness in the range of approximately 10.0 nm to approximately 30.0 nm. The second upper dielectric layer 144 is arranged above the first upper dielectric layer 142 and the second ILD layer 140. In some embodiments, the second upper dielectric layer 144 can comprise tetraethyl orthosilicate (TEOS) (e.g., plasma-enhanced TEOS, particle-free TEOS, etc.), an oxide (e.g., silicon dioxide, silicon dioxide, etc.), a nitride, or the like. In some embodiments, the second upper dielectric layer 144 can have a thickness in the range of approximately 10.0 nm to approximately 50.0 nm. In some embodiments, the second upper dielectric layer 144 includes a projection that extends into the well 141 within the second ILD layer 140.

[0030] The third ILD layer 146 is arranged above the second upper dielectric layer 144. A second conductive wire 150 is arranged above the top-side electrode via 138. In some embodiments, the second conductive wire 150 may, for example, comprise copper or aluminum. The third ILD layer 146 surrounds the second conductive wire 150. The second conductive wire 150 extends beyond the sidewalls of the top-side electrode via 138. In some embodiments, the top-side electrode via 138 may comprise copper, aluminum, titanium, tantalum, or the like. In some embodiments, the top-side electrode via 138 may have a thickness in a range between approximately 30.0 nm and approximately 95.0 nm and a width in a range between approximately 25.0 nm and approximately 130.0 nm.

[0031] A dashed line 212 is aligned with a top surface of the second ILD layer 140 within the embedded memory area 201a. Within the logic area 201b, the dashed line 212 crosses the first conductive via 208 and the third ILD layer 146.

[0032] A height h1 is defined between a bottom surface of the first upper dielectric layer 142 within the well 141 and a top surface of the second ILD layer 140. The height h1 lies in a range of approximately 0.5 nm to 7.5 nm. The width of the first upper dielectric layer 142 within the well 141 lies in a range of approximately 5.0 nm to approximately 25.0 nm. A height h2 is defined between a bottom surface of the second upper dielectric layer 144 within the well 141 and the top surface of the second ILD layer 140. The height h2 lies in a range of approximately 0.1 nm to 4.0 nm. The width of the second upper dielectric layer 144 within the well 141 lies in a range of approximately 2.0 nm to approximately 15.0 nm. A height h3 is defined between a bottom surface of the third lower dielectric layer 114 and the top surface of the second ILD layer 140.The height h3 lies in a range of approximately 80.0 nm to 180.0 nm. A width w1 is defined between the center of the upper electrode 130 of the MRAM cell 134 and the center of the upper electrode 130 of the MRAM cell 136. The width w1 lies in a range of approximately 250.0 nm to 600.0 nm.

[0033] Fig. Figure 3A shows a top view of some additional embodiments of a storage device 300a.

[0034] The storage device 300a comprises an embedded memory area 201a and a logic area 201b. The dashed line 212 from Fig. Figure 2 shows the location of the top-view section. The embedded memory region 201a comprises an array of MRAM cells arranged in rows and columns. It is understood that memory arrays can comprise any number of MRAM cell pairs and Fig. Figure 3A is therefore only an example. The top-side electrode via 138 is arranged centrally between four wells 141. The well 141 is filled with the first upper dielectric layer 142 and the second upper dielectric layer 144. The second upper dielectric layer 144 is separated from the second ILD layer 140 by the first upper dielectric layer 142. The first upper dielectric layer 142 extends continuously between corresponding columns and rows of the arrangement. The second upper dielectric layer 144 also extends continuously on a top surface of the dashed line 212 between corresponding columns and rows of the arrangement. A bottom surface of the second upper dielectric layer 144 includes a projection, and a bottom surface of the projection is in direct contact with a top surface of the first upper dielectric layer 142, which defines the well 141.

[0035] Fig. Figure 3B shows a top view of some additional embodiments of a storage device 300b.

[0036] The storage device 300b comprises an embedded memory area 201a and a logic area 201b. The dashed line 212 from Fig. Figure 2 shows the location of the top-view section. The embedded memory region 201a comprises an array of MRAM cells arranged in rows and columns. It is understood that memory arrays can comprise any number of MRAM cell pairs and Fig. Figure 3b is therefore only an example. The first upper dielectric layer 142 extends continuously along a top surface of the dashed line 212 between corresponding columns and rows of the arrangement. The second upper dielectric layer 144 comprises discrete segments separated from each other in a first direction and in a second direction perpendicular to the first direction.

[0037] Fig. Figures 4-14 represent cross-sectional views 400-1400 of some embodiments of a method for forming a memory device comprising an embedded memory area including a pair of MRAM cells and a logic area, according to the present disclosure. Even if the in Fig. Sectional views 400-1400 shown in 4-14 are described with reference to a method; it is understood that the in Fig. The structures shown in 4-14 are not limited to the procedure, but rather can stand on their own, separate from the procedure. Even if Fig. Since the actions described in Figures 4-14 are a series, it is understood that these actions are not restrictive, insofar as the sequence of the actions can be changed in other embodiments and the disclosed methods are also applicable to other structures. In other embodiments, some of the actions shown and / or described may be omitted entirely or partially.

[0038] As shown in the cross-sectional view 400 of Fig. As shown in Figure 4, a first lower dielectric layer 110 is formed over a connecting wire 108 and a first ILD layer 106 on a substrate (not shown). In some embodiments, the first lower dielectric layer 110 may comprise a silicon carbide (SiC) layer. A second lower dielectric layer 112 is formed over the first lower dielectric layer 110. In some embodiments, the second lower dielectric layer 112 may comprise a silicon-rich oxide layer. A bottom-side electrode via 119, comprising a diffusion barrier 118 and a bottom metal layer 116, is formed within the first lower dielectric layer 110 and the second lower dielectric layer 112. A third lower dielectric layer 114 is formed over the second lower dielectric layer 112.In some embodiments, the third lower dielectric layer 114 may comprise a silicon oxycarbide (SiOC) layer.

[0039] Within the embedded memory area 201a, a first MRAM cell 134 and a second MRAM cell 136 are formed, each above the connecting wire 108. The first MRAM cell 134 and the second MRAM cell 136 each comprise a lower electrode 120, which is formed above the diffusion barrier 118 and the lower metal layer 116. The first MRAM cell 134 and the second MRAM cell 136 also each comprise an upper electrode 130, which is separated from the lower electrode 120 by a magnetic tunnel junction (MTJ) 122. A first sidewall spacer 128 is formed along the sidewalls of the first MRAM cell 134 and the second MRAM cell 136. A second side wall spacer 132 is designed to surround a top surface of the upper electrode 130.

[0040] As shown in the cross-sectional view 500 of Fig. As shown in Figure 5, a second ILD layer 502 is formed above the embedded memory area 201a and the logic area 201b. In some embodiments, the second ILD layer 502 can comprise silicon dioxide, carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), boron phosphosilicate glass (BPSG), fluorosilicate glass (FSG), a porous dielectric material, or the like. Due to the topography of the first MRAM cell 134 and the second MRAM cell 136, the second ILD layer 502 comprises side walls and a bottom surface that define a well 141 between the first MRAM cell 134 and the second MRAM cell 136. In some embodiments, an upper surface of the second ILD layer 502, which defines the well 141, is located above a top surface of the first MRAM cell 134 and the second MRAM cell 136. A first dielectric 504 is formed above the second ILD layer 502.In some embodiments, the first dielectric 504 may, for example, comprise a silicon oxynitride (SiON) layer. The first dielectric 504 fills a section of the well 141. A bottom surface of the first dielectric 504 is in direct contact with a top surface of the second ILD layer 502, which defines the well 141. In some embodiments, the second ILD layer 502 is formed with a thickness of 80.0 nm or in a range of approximately 65.0 nm to 95.0 nm. In some embodiments, the first dielectric 504 is formed with a thickness of 20.0 nm or in a range of approximately 15.0 nm to 25.0 nm.

[0041] Fig. Figures 6A-6C represent cross-sectional views 600a-600c, which show a first embodiment of the method. Fig. Figures 7A-7B represent cross-sectional views 700a-700b, which correspond to an alternative second embodiment of the method.

[0042] As shown in cross-sectional view 600a, a second dielectric 602 is formed over the first dielectric 504. In some embodiments, the second dielectric 602 may comprise a tetraethyl orthosilicate (TEOS) layer formed with a thickness of 15.0 nm, 20.0 nm, or in a range between approximately 15.0 nm and approximately 25.0 nm. The second dielectric 602 fills a portion of the well 141. A planarization layer 604 is formed over the second dielectric 602. The planarization layer 604 fills the remaining open space in the well 141. In some embodiments, the planarization layer 604 may comprise an anti-reflective coating (ARC). In some embodiments, the planarization layer 604 is formed with a thickness of 88.0 nm or in a range of approximately 70.0 nm and 110.0 nm.

[0043] As shown in cross-sectional view 600b of Fig. As shown in Figure 6B, an etching process is performed to etch the second ILD layer 502, the first dielectric 504, the second dielectric 602, and the planarization layer 604. In some embodiments, the planarization layer 604 may have a different etch selectivity than the first dielectric 504 and / or the second dielectric 602, such that the etching process spares the planarization layer 604 below top surfaces of the first dielectric 504 and / or the second dielectric 602. In some embodiments, the etching process may completely remove the planarization layer 604 from the embedded memory area 201a and the logic area 201b. In other embodiments, a separate etching process may be performed to remove the planarization layer 604 from the embedded memory area 201a and the logic area 201b.In some embodiments, the etching process reduces the thickness of the second dielectric 602, such that the second dielectric 602 has a thickness of 5.0 nm or in a range between approximately 2.0 nm and approximately 8.0 nm. In some embodiments, the etching process can be carried out by forming a masking layer (not shown) over the planarization layer 604 and subsequently allowing an etchant 606 to act on unmasked areas of the planarization layer 604. In some embodiments, the etching process includes performing a back-etching process to remove the planarization layer 604.

[0044] As shown in the cross-sectional view 600c of Fig. As shown in Figure 6C, the thickness of the second dielectric 602 is increased. The thickness of the second dielectric layer is increased by forming an additional material onto the second dielectric 602. The additional material is the same as a material used to form the second dielectric 602. In some embodiments, the additional material may comprise tetraethyl orthosilicate (TEOS). In some embodiments, the additional material causes the second dielectric 602 to have a thickness of 35.0 nm or in the range between approximately 30.0 nm and approximately 40.0 nm. The additional material fills the open space in the well 141. A bottom surface of the second dielectric 602 is located above a top surface of the second ILD layer 502 and the first dielectric 504. The second dielectric 602 comprises side walls and a bottom surface that defines a second well 610.An upper surface of the second dielectric 602, which defines the second well 610, is located above the uppermost surface of the second ILD layer 502 and the first dielectric 504.

[0045] Alternatively, as shown in cross-sectional view 700a of Fig. As shown in Figure 7A, a second dielectric 602 is formed above the first dielectric 504. In some embodiments, the second dielectric 602 may comprise a tetraethyl orthosilicate (TEOS) layer formed with a thickness of 45.0 nm or in a range between approximately 40.0 nm and approximately 50.0 nm. The second dielectric 602 fills the remaining open section of the well 141. A planarization layer 604 is formed above the second dielectric 602. In some embodiments, the planarization layer 604 may comprise an anti-reflective coating (ARC). The second dielectric 602 comprises sidewalls and a bottom surface that define a second well 610. In some embodiments, the planarization layer 604 is formed with a thickness of 88.0 nm or in a range between approximately 70.0 nm and 110.0 nm.

[0046] As shown in cross-sectional view 700b of Fig. As shown in Figure 7B, an etching process is performed to etch the second ILD layer 502, the first dielectric 504, the second dielectric 602, and the planarization layer 604. The planarization layer 604 is removed from the embedded memory area 201a and the logic area 201b. The etching process removes the second well 610. In some embodiments, the etching process reduces the thickness of the second dielectric 602, such that the second dielectric 602 has a thickness of 5.0 nm or in a range between approximately 2.0 nm and approximately 40.0 nm. In some embodiments, the etching process can be performed by forming a masking layer (not shown) over the planarization layer 604 and subsequently allowing an etchant 702 to act on unmasked areas of the planarization layer 604. In some embodiments, the etching process includes performing a reverse etching process to remove the planarization layer 604.

[0047] As shown in the cross-sectional view 800 of Fig. As shown in Figure 8, a chemical-mechanical planarization (CMP) process is carried out along line 802. In the first embodiment of the method, which is shown in Figure 8, a chemical-mechanical planarization (CMP) process is carried out. Fig. As shown in Figures 6A-6C, the CMP process removes the second vat 610, a section of the second ILD layer 502, the first dielectric 504 and the second dielectric 602 (e.g., 610, 502, 504 and 602 of Fig. 6C) and defines a first upper dielectric layer 142 and a second upper dielectric layer 144. In the second embodiment of the method, which is described in Fig. As shown in Figures 7A-7B, the CMP process removes a section of the second ILD layer 502, the first dielectric 504 and the second dielectric 602 (e.g., 502, 504 and 602 of Fig. 7b) and defines a first upper dielectric layer 142 and a second upper dielectric layer 144. Within logic area 201b, the second dielectric 602 is removed, exposing a top surface of the first upper dielectric layer 142. In some embodiments, the second upper dielectric layer 144 has a thickness of 3.5 nm or in a range of approximately 1.0 nm to 7.0 nm. In some embodiments, the CMP process can reduce the thickness of the first upper dielectric layer 142. For example, the CMP process can reduce the thickness of the first upper dielectric layer 142 by approximately 25% or more (e.g., from a thickness of 20.0 nm to a thickness of 15.0 nm). After the CMP process, the first upper dielectric layer 142 can have a thickness in a range of approximately 7.5 nm to 22.5 nm.

[0048] As shown in the cross-sectional view 900 of Fig. As shown in Figure 9, an etching process is carried out to create the second ILD layer (502 of Fig. 8) to etch and thus define a second ILD layer 140. The etching process defines a hole 902 directly above the top electrode 130, which is defined by sidewalls of a top-electrode via within the second ILD layer 140. In some embodiments, the etching process can be carried out by forming a masking layer (not shown) over the second ILD layer 140 and subsequently allowing an etchant 904 to act on unmasked areas of the second ILD layer 140. In some embodiments, the etching process can reduce the thickness of the first top dielectric layer 142. For example, the etching process can reduce the thickness of the first top dielectric layer 142 by approximately 33% or more (e.g., from approximately 15.0 nm to less than 10.0 nm).

[0049] In some embodiments, the masking layer (not shown) comprises a photoresist mask. In other embodiments, the masking layer may comprise a hard mask layer (which may include, for example, a nitride layer). In some embodiments, the masking layer may comprise a multilayer hard mask. For example, in some embodiments, the masking layer may comprise a three-layer resist technology comprising a photoresist over a silicon-containing hard mask over a spin-on carbon.

[0050] As shown in the cross-sectional view 1000 of Fig. As shown in Figure 10, a top-side electrode via layer 1002 is formed over the embedded memory area 201a and the logic area 201b. The top-side electrode via layer 1002 fills the hole (902 of Fig. 9) In some embodiments, the top-side electrode via layer 1002 may comprise a conductive material such as titanium nitride, tantalum nitride, titanium, tantalum or a combination of one or more of the aforementioned.

[0051] As shown in the cross-sectional view 1100 of Fig. As shown in Figure 11, a CMP process is performed along line 1102. The CMP process removes a section of the top-side electrode via layer (1002 of Fig. 10) and thus defines a top-side electrode via 138. A top-side surface of the top-side electrode via 138, the second ILD layer 140, the first top-side dielectric layer 142, and the second top-side dielectric layer 144 are defined along a horizontal line. In some embodiments, the horizontal line is essentially straight. In some embodiments, the top-side surface of the first top-side dielectric layer 142 within the embedded memory region 201a is defined by a second height, and a top-side surface of the first top-side dielectric layer 142 within the logic region 201b is defined by a first height. In some embodiments, the second height is greater than the first height. In some embodiments, the second height is greater than the first height by a range between approximately 90.0 nm and approximately 110.0 nm.In some embodiments, the CMP process can reduce the thickness of the second upper dielectric layer 144. For example, after the CMP process, the second upper dielectric layer 144 can have a thickness of 2.0 nm or in the range of approximately 0.5 nm to 7.0 nm.

[0052] As shown in the cross-sectional view 1200 of Fig. As shown in Figure 12, an etching process is performed to remove the first upper dielectric layer 142, the second ILD layer 140, and the third lower dielectric layer 114 within the logic area 201b. The etching process involves applying an etchant 1202 to the first upper dielectric layer 142, the second ILD layer 140, and the third lower dielectric layer 114 within the logic area 201b. In some embodiments, a masking layer is formed over the embedded memory area 201a before the etching process is performed (not shown).

[0053] As shown in the cross-sectional view 1300 of Fig. As shown in Figure 13, a fourth lower dielectric layer 214 is formed above the second lower dielectric layer 112. Additional dielectric material is formed above the second upper dielectric layer 144 to increase its thickness. In some embodiments, the additional dielectric material comprises the same material as the second upper dielectric layer 144 and increases its thickness by a range of 5.0 nm to 25.0 nm. A third ILD layer 146 is formed above the fourth lower dielectric layer 214 and the second upper dielectric layer 144.

[0054] As shown in the cross-sectional view 1400 of Fig. As shown in Figure 14, a first conductive via 208 is formed above the connecting wire 108 within the logic area 201b and extends through the first lower dielectric layer 110, the second lower dielectric layer 112, the fourth lower dielectric layer 214, and a portion of the third ILD layer 146. A second conductive wire 150 is formed above the first conductive via 208 within the logic area 201b and above the top-side electrode via 138. The second conductive wire 150 is surrounded by the third ILD layer 146. Within the embedded memory area 201a, the second conductive wire 150 extends through the second upper dielectric layer 144.

[0055] Fig. Document 15 presents a method 1500 for constructing a storage device according to some embodiments. Although the method 1500 is presented and / or described as a series of actions or events, it is understood that the method is not limited to the sequence or actions presented. Thus, in some embodiments, the actions may be performed in a different sequence than presented and / or simultaneously. Furthermore, in some embodiments, the presented actions or events may be subdivided into several actions or events that may be performed at separate times or simultaneously with other actions or sub-actions. In some embodiments, some presented actions or events may be omitted and other, not presented, actions or events may be included.

[0056] In 1502, a first and second MRAM cell are formed above a first ILD layer over a substrate. Fig. Figure 4 shows a cross-sectional view 400, which corresponds to some embodiments of Act 1502.

[0057] In 1504, a second ILD layer is formed above the first ILD layer, with the second ILD layer including side walls that define a first well between the first and second MRAM cells. Fig. Figure 5 shows a cross-sectional view 500, which corresponds to some embodiments of Act 1504.

[0058] At 1506, a first dielectric is formed above the second ILD layer. Fig. Figure 5 shows a cross-sectional view 500, which corresponds to some embodiments of Act 1506.

[0059] In 1508a, a second dielectric is formed above the first dielectric, with the second dielectric filling a section of an open section of the first well. Fig. Figure 6A represents a cross-sectional view 600a, which corresponds to some embodiments of Act 1508a.

[0060] In 1508b, sections of the second ILD layer, the first dielectric and the second dielectric are removed. Fig. Figure 6B represents a cross-sectional view 600b, which corresponds to some embodiments of Act 1508b.

[0061] In 1508c, the thickness of the second dielectric is increased. This increase in thickness causes the second dielectric to have sidewalls that define a second well above the first. Fig. Figure 6C represents a cross-sectional view 600c, which corresponds to some embodiments of Act 1508c.

[0062] In 1510a, a second dielectric is formed above the first dielectric, wherein the second dielectric completely fills an open section of the first well and includes side walls that define a second well above the first well. Fig. Figure 7A represents a cross-sectional view 700a, which corresponds to some embodiments of Act 1510a.

[0063] At 1510b, the second well and sections of the second ILD layer, the first dielectric and the second dielectric are removed. Fig. Figure 7B shows a cross-sectional view 700b, which corresponds to some embodiments of Act 1510b.

[0064] In 1512, a planarization process was carried out to remove sections of the second ILD layer, the first dielectric, and the second dielectric, with the planarization process removing the second well in some embodiments. Fig. Figure 8 shows a cross-sectional view 800, which corresponds to some embodiments of Act 1512.

[0065] At 1514, a via opening is formed within the second ILD layer, above the first and second MRAM cells, and a top electrode via is formed within the via opening. Fig. 9 and Fig. Figure 11 shows cross-sectional views 900 and 1100, which correspond to some embodiments of Act 1514.

[0066] Accordingly, in some embodiments, the present disclosure relates to a method for forming a pair of MRAM cells, comprising forming an ILD between the cells, wherein the ILD comprises side walls defining a well, the well containing one or more dielectric materials and no metal material.

[0067] In some embodiments, the present disclosure relates to a storage device. The storage device comprises a first magnetoresistive random-access memory (MRAM) cell arranged above a substrate; a second MRAM cell arranged above the substrate; an inter-level dielectric (ILD) layer arranged above the substrate, the ILD layer comprising sidewalls defining a well between the first MRAM cell and the second MRAM cell; and a dielectric layer arranged above the ILD layer, the dielectric layer filling the well.

[0068] In other embodiments, the present disclosure relates to a storage device. The storage device comprises a first magnetoresistive random-access memory (MRAM) cell arranged over a substrate; a second MRAM cell arranged over the substrate; an inter-level dielectric (ILD) layer arranged over the first MRAM cell and the second MRAM cell, wherein the ILD layer defines a recess between the first MRAM cell and the second MRAM cell and the ILD layer comprises a first material; a dielectric layer arranged over the ILD layer, wherein a bottom surface of the dielectric layer is in direct contact with a top surface of the ILD layer that defines the recess and the dielectric layer comprises a second material;a second ILD layer arranged above the dielectric layer, wherein the recess between a lower surface of the recess and a lower surface of the second ILD layer comprises the first and second material.

[0069] In other embodiments, the present disclosure relates to a method for manufacturing a storage device.The method comprises forming a first magnetoresistive random-access memory (MRAM) cell over a substrate; forming a second MRAM cell over the substrate; forming an inter-level dielectric (ILD) layer over the substrate, wherein the ILD layer comprises sidewalls defining a first well between the first MRAM cell and the second MRAM cell; forming a dielectric layer over the ILD layer, wherein the dielectric layer comprises sidewalls defining a second well directly above the first well; removing the second well, a portion of the ILD layer, and a portion of the dielectric layer, wherein an upper surface of the ILD layer and an upper surface of the dielectric layer meet along a horizontal line, and the horizontal line is substantially straight.

Claims

[1] Method for manufacturing a storage device, comprising: Formation of a first magnetoresistive random access memory cell, MRAM cell (134), over a substrate; Formation of a second MRAM cell (136) above the substrate; Forming an intermediate dielectric layer, ILD layer (140), over the substrate, wherein the ILD layer (140, 502) comprises side walls that define a first well (141) between the first MRAM cell (134) and the second MRAM cell (136); Forming a dielectric layer (142, 144, 504, 602) over the ILD layer (140, 502) wherein the dielectric layer (142, 144, 504, 602) comprises sidewalls that define a second well (610) directly above the first well (141); and Removing the second well (610), a section of the ILD layer (140, 502) and a section of the dielectric layer (142, 144, 504, 602), wherein an upper surface of the ILD layer (140, 502) and an upper surface of the dielectric layer (142, 144, 504, 602) meet at a horizontal line, wherein the horizontal line is substantially straight, the procedure, prior to the removal of the second tub (610), further comprises: Performing a first etching process to remove a section of the ILD layer (140, 502) and a section of the dielectric layer (142, 144, 504, 602), wherein the first etching process defines a second top surface of the ILD layer (140, 502) and a second top surface of the dielectric layer (142, 144, 504, 602); and Filling the second vat (610) with a first material, wherein the first material is the same material as a material comprising the dielectric layer (142, 144, 504, 602), wherein an upper surface of the first material is located above the second upper surface of the ILD layer (140, 502) and the second upper surface of the dielectric layer (142, 144, 504, 602). [2] Method according to claim 1, wherein the ILD layer (140, 502) comprises a first dielectric material, wherein the dielectric layer (142, 144, 504, 602) comprises a second dielectric material and wherein the first dielectric material is a different material than the second dielectric material. [3] Method according to one of the preceding claims 1 or 2, further comprising: performing a first etching process to define a first via opening directly above the first MRAM cell (134) and a second via opening directly above the second MRAM cell (136); Forming a top-side electrode through-hole layer over the first (134) and second MRAM cell (136); and Performing a second planarization process that removes a section of the top-side electrode via layer and defining a first top-side electrode via (138) above the first MRAM cell (134) and a second top-side electrode via (138) above the second MRAM cell (136), wherein no section of the top-side electrode via layer is present above a top-side surface of the first well (141). [4] Method according to claim 3, wherein outer side walls of the first top-side electrode via are located within outer side walls of the first MRAM cell (134), wherein outer side walls of the second top-side electrode via are located within outer side walls of the second MRAM cell (136). [5] Method according to one of the preceding claims, wherein an upper surface of the ILD layer (140, 502) defining the first well (141) is located above a top surface of the first MRAM cell (134) and the second MRAM cell (136). [6] Method according to any of the preceding claims, wherein a top surface of the ILD layer (140, 502) is located below a top surface of the dielectric layer (142, 144, 504, 602). [7] Method according to any of the preceding claims, wherein the first MRAM cell (134) comprises a first set of outer side walls and the second MRAM cell (136) comprises a second set of outer side walls, wherein the dielectric layer (142, 144, 504, 602) is spaced laterally between the first set of outer side walls and the second set of outer side walls. [8] Method according to any of the preceding claims, wherein the dielectric layer comprises (142, 144, 504, 602) tetraethyl orthosilicate and silicon oxynitride. [9] Method according to any one of the preceding claims, wherein the first MRAM cell (134) and the second MRAM cell (136) each have one include a magnetic tunnel contact (MTJ) arranged between a lower electrode and an upper electrode; and wherein a top electrode via (138) is arranged above the top electrode and within the ILD layer (140, 502). [10] Method according to any of the preceding claims, wherein the dielectric layer (142, 144, 504, 602) comprises a first dielectric material and a second dielectric material, wherein the first dielectric material is located below the second dielectric material.

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