NOVEL RESTRICTIVE DIRECT ACCESS STORAGE DEVICES

Abstract

Storage device comprising the following: a first conductor (228, 802-1) which extends substantially along a first axis (Y); a first selector material (224-1) comprising a U-shaped profile with a first section (224-1S1) extending along a first side wall of the first conductor (228); a second selector material (224-2) comprising a U-shaped profile with a first section (224-2S1) extending along the first side wall of the first conductor (228), wherein the U-shaped profile of the second selector material (224-2) partially surrounds the first conductor (228) and the U-shaped profile of the first selector material (224-1) partially surrounds the second selector material (224-2); a first variable resistive material (210) comprising a section extending along the first side wall of the first conductor (228); and a second conductor (220-1, 804-1) extending parallel to a second axis (Z) substantially perpendicular to the first axis (Y), wherein the first section (224-1S1) of the first selector material (224-1), the first section (224-2S1) of the second selector material (224-2) and the section of the first variable resistive material (210) are stacked along a first direction parallel to a third axis (X) that is substantially perpendicular to the first axis (Y) and the second axis (Z).

Description

BACKGROUND

[0001] In recent years, unconventional non-volatile memory (NVM) devices, such as ferroelectric random access memory (FRAM), phase-change random access memory (PRAM), and resistive random access memory (RRAM), have entered the market. More specifically, RRAM devices, which exhibit switching behavior between a high resistance state (HRS) and a low resistance state (LRS), offer several advantages over conventional NVM devices. These advantages include, for example, compatibility with complementary metal oxide semiconductor (CMOS) technologies, cost-effective manufacturing, a compact structure, flexible scalability, fast switching, high integration density, and more.

[0002] In general, an RRAM bit cell of the RRAM device contains a lower electrode (for example, an anode) and an upper electrode (for example, a cathode) with a variable resistive material layer placed between them to form an RRAM resistor, and a transistor (for example, a metal-oxide-semiconductor field-effect transistor (MOSFET), a bipolar transistor (BJT), etc.) connected in series with the RRAM resistor, which is usually referred to as a "one-transistor-one-resistor (1T1R)" configuration.To further increase the integration density of the RRAM bit cells in the RRAM device, it has been proposed to design the RRAM bit cells as a crossing point arrangement, in which the RRAM bit cells are each arranged at a crossing of one of several conductors extending along a first horizontal direction (for example, word lines (WLs)) and one of several conductors extending along a second horizontal direction (for example, bit lines (BLs)).

[0003] However, the use of the 1T1R configuration cannot effectively integrate the RRAM bit cells into a high-density crossover array, partly due to the additional area required to accommodate the transistors. In this respect, a variety of other devices have been proposed to replace the transistors, for example, unipolar or bipolar selector devices (such as diodes). Forming the RRAM bit cell by coupling a selector device with a corresponding RRAM resistor is generally referred to as a "one-selector-one-resistor (1S1R)" configuration.However, forming the intersection point arrangement by integrating the RRAM bit cells, each formed using the 1S1R configuration, can still reach a limit that prevents further increases in integration density, partly because the BLs and WLs are still restricted to extending horizontally (i.e., in the plane), and / or because respective layers of selector devices can only be formed along one direction essentially perpendicular to the directions in which the BLs and WLs respectively extend.

[0004] Therefore, the existing RRAM devices and methods for their manufacture are not entirely satisfactory.

[0005] Corresponding devices are known from the publications US 2017 / 0148851A1, US 2016 / 0087197A1, US 2014 / 0361239A1 and US 2017 / 0263683A1.

[0006] The task is to improve the corresponding RRAM devices accordingly.

[0007] The problem is solved by the storage devices according to claims 1, 9 and 17. Further embodiments are described in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Aspects of this disclosure are best understood with reference to the following detailed description, when read in conjunction with the accompanying figures. It should be noted that, in accordance with common industry practice, various features are not drawn to scale. The dimensions of the various features may be enlarged or reduced as necessary for the sake of clarity in this discussion. Fig. 1A and Fig. Figure 1B illustrates a flowchart of an exemplary method for forming a semiconductor device according to some embodiments. Fig. 2A, Fig. 2B, Fig. 2C, Fig. 2D, Fig. 2E, Fig. 2F, Fig. 2G, Fig. 2H, Fig. 2I, Fig. 2 years Fig. 2K, Fig. 2L and Fig. 2M illustrate respective cross-sectional views of an exemplary semiconductor device during various manufacturing stages, which are achieved through the process of Fig. 1A-1B is manufactured according to some embodiments. Fig. Figure 3 illustrates a perspective view of an exemplary semiconductor device containing multiple layer levels, according to some embodiments. Fig. 4A and Fig. Figure 4B illustrates a flowchart of another exemplary method for forming a semiconductor device according to some embodiments. Fig. 5A, Fig. 5B, Fig. 5C, Fig. 5D, Fig. 5E, Fig. 5F, Fig. 5G, Fig. 5H, Fig. 5I and Fig. Figure 5J illustrates respective top views of an exemplary semiconductor device during various manufacturing stages, which are achieved through the process of Fig. 4A-4B is manufactured according to some embodiments. Fig. 6A, Fig. 6B, Fig. 6C, Fig. 6D, Fig. 6E, Fig. 6F, Fig. 6G, Fig. 6H, Fig. 6I, Fig. 6 years Fig. 6K and Fig. Figure 6L illustrates corresponding cross-sectional views of the Fig. 5A, Fig. 5B, Fig. 5C, Fig. 5D, Fig. 5E, Fig. 5F, Fig. 5G, Fig. 5H, Fig. 5I and Fig. 5J along line AA. Fig. Figure 7 illustrates a flowchart of an exemplary procedure for operating a semiconductor device using the method of Fig. 1A-1B or 4A-4B is manufactured according to some embodiments. Fig. Figure 8 illustrates a diagram of a semiconductor device produced by the process of Fig. 1A-1B or 4A-4B is manufactured according to some embodiments. DETAILED DESCRIPTION OF EXAMPLE EXECUTIONS

[0009] The following disclosure describes various exemplary embodiments for implementing different features of the subject matter discussed herein. Specific examples of components and arrangements are described to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. For example, the formation of a first structural element above or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements, so that the first and second structural elements are not necessarily in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves for simplicity and clarity and does not automatically create a relationship between the various designs and / or configurations discussed.

[0010] Furthermore, spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, may be used in this text to simplify the description and to describe the relationship of one element or structural element to one or more other elements or structural elements, as illustrated in the figures. These spatially relative terms are intended to encompass not only the orientation shown in the figures but also other orientations of the device during use or operation. The device may also be oriented differently (rotated 90 degrees or otherwise), and the spatially relative descriptors used in this text may be interpreted accordingly.

[0011] The present disclosure provides various embodiments of a novel resistive random-access memory (RRAM) device and methods for its fabrication. In some embodiments, the disclosed RRAM device comprises an array of RRAM bit cells integrated by multiple horizontally extending bit lines (BLs) and multiple vertically extending word lines (WLs). More precisely, the RRAM bit cells of the array, each containing an RRAM resistor and a selector device connected in series, are configured as multiple strips extending along a first horizontal direction.The BLs extending along a second horizontal direction cross respective strips that are to be positioned between two adjacent RRAM bit cells at their respective first ends; and the WLs extending along a vertical direction (for example, out of a plane defined by the first and second horizontal directions) also cross the respective strips to form multiple pairs that accommodate two adjacent RRAM bit cells (with an interposed BL) at their respective second ends. Thus, the RRAM bit cells of the disclosed RRAM device can be integrated more densely (i.e., with a greatly increased integration density) than existing RRAM devices, partly because the RRAM bit cells can be formed horizontally in a plane and the BLs and WLs can extend in different planes.

[0012] Fig. 1A and Fig. Figure 1B illustrates a flowchart of a method 100 for forming a semiconductor device according to one or more embodiments of the present disclosure. It should be noted that method 100 is merely an example and is not intended to limit the present disclosure. In some embodiments, the semiconductor device is an RRAM device or at least part thereof. For the purposes of the present disclosure, “RRAM device” refers to any device that contains a variable resistive material layer. It should be noted that method 100 of the Fig. 1A and Fig. 1B does not provide a finished RRAM device. A finished RRAM device can be manufactured using complementary metal oxide semiconductor (CMOS) technology processing. Accordingly, it is understood that additional operations before, during, and after procedure 100 of the Fig. 1A and Fig. 1B can be provided and that some other operations may only be briefly described in this text. In some other embodiments, the method can be used to form any of a variety of different non-volatile memory (NVM) devices, such as ferroelectric random-access memory (FRAM) devices, phase-change random-access memory (PRAM) devices, magnetoresistive random-access memory (MRAM) devices, etc.

[0013] We turn first Fig. 1A. In some embodiments, the method 100 begins with operation 102, in which a substrate is provided. The method 100 proceeds to operation 104, in which several dummy structures are formed over the substrate. In some embodiments, the several dummy structures are laterally spaced apart, and each is formed as a recessed region extending through a dielectric layer formed in the same material as the dummy structures. The method 100 proceeds to operation 106, in which a first capping material, a variable resistive material, and a second capping material are formed over the several dummy structures.Method 100 proceeds to Operation 108, in which the first capping material, the variable resistive material, and the second capping material are etched to form multiple stacked resistive films, each extending along a side wall of each of the multiple dummy structures. Each stacked resistive film is formed by the respective remaining portions (after etching) of the first capping material, the variable resistive material, and the second capping material. In some embodiments, after the stacked resistive films are formed, multiple word-line (WL) openings, which are discussed below, are formed between the multiple dummy structures, spaced laterally apart. Method 100 proceeds to Operation 110, in which a word-line (WL) metal material is formed over the multiple dummy structures. In some embodiments, the WL metal material can fill multiple WL openings.Method 100 proceeds to operation 112, in which a first polishing process is performed. In some embodiments, the first polishing process is performed at least on the WL metal material to expose the multiple dummy structures and form multiple WLs.

[0014] We now turn Fig. 1B, where the method 100 continues to operation 114, in which the multiple dummy structures are removed to form multiple openings. Since the dummy structures are laterally spaced after removal, the openings in some embodiments each have a U-shaped profile. The method 100 continues to operation 116, in which at least first and second selector materials at least partially fill multiple openings. In some embodiments, the at least first and second selector materials, which are formed one above the other, are configured together to provide a "selection" or "steering" function, which is discussed in more detail below. The method 100 continues to operation 118, in which a bitline (BL) metal material is formed over the first and second selector materials.Since the first and second selector materials are each formed to be substantially thin and conformal, the respective U-shaped profiles of the openings may still be present along a portion of an upper boundary of the upper selector material (for example, the second selector material) in some embodiments. The BL metal material is formed to fill at least such U-shaped profiles that are present in the second selector material. Method 100 proceeds to Operation 120, in which a second polishing process is performed to form multiple BLs. In some embodiments, the second polishing process is performed at least on the BL metal material and the first and second selector materials until the respective upper boundaries of the WLs are again exposed, while the U-shaped profiles of the second selector material are kept filled with the BL metal material.In some embodiments, after forming the BLs, several RRAM bit cells can be formed as a strip extending along a first lateral direction, with the multiple BLs passing through the strip along a second lateral direction, and the multiple WLs passing through the strip along a vertical direction. Furthermore, the strip can be said to be formed on a first layering plane. Such a strip is shown and discussed below. Method 100 proceeds to Operation 122, in which Operations 104 to 120 are repeated. In some embodiments, after forming the strip on the first layering plane, an iteration of performing Operations 104 to 120 can form at least one strip on a layering plane above the first layering plane.

[0015] In some embodiments, operations of the method 100 can be linked to cross-sectional views of a semiconductor device 200 at different manufacturing stages, as in the Fig. 2A, Fig. 2B, Fig. 2C, Fig. 2D, Fig. 2E, Fig. 2F, Fig. 2G, Fig. 2H, Fig. 2I, Fig. 2J or 2K are shown. In some embodiments, the semiconductor device 200 can be an RRAM device. The RRAM device 200 can be contained in a microprocessor, a memory cell, and / or another integrated circuit (IC). Furthermore, the Fig. Figures 2A to 2K have been simplified for a better understanding of the concepts of this disclosure. For example, although the figures illustrate the RRAM device 200, it is understood that the IC in which the RRAM device 200 is formed may also contain a number of other devices, such as resistors, capacitors, inductors, fuses, etc., which are described in the Fig. 2A to 2K are not shown for the sake of clarity.

[0016] According to Operation 102 of Fig. 1A is Fig. Figure 2A shows a cross-sectional view of the RRAM device 200 containing a substrate 202 provided at one of the various fabrication stages, according to some embodiments. In some embodiments, the substrate 202 contains a semiconductor material, for example, silicon. Alternatively, the substrate 202 may contain another elemental semiconductor material, such as germanium. The substrate 202 may also contain a compound semiconductor, such as silicon carbide, gallium arsenide, indium arsenide, and indium phosphide. The substrate 202 may contain an alloy semiconductor, such as silicon-germanium, silicon-germanium carbide, gallium arsenic phosphide, and gallium indium phosphide. In one embodiment, the substrate 202 contains an epitaxial layer. For example, the substrate may have an epitaxial layer overlying a bulk semiconductor.Furthermore, the substrate 202 can contain a semiconductor-on-insulator (SOI) structure. For example, the substrate can contain a buried oxide (BOX) layer formed by a process such as separation by implanted oxygen (SIMOX) or another suitable technique, such as wafer bonding and looping.

[0017] In some other embodiments, the substrate has a dielectric material layer 202 formed over various device structure elements (for example, a source, drain, or gate electrode of a transistor). Such a dielectric material layer 202 can contain at least one of the following: silicon dioxide, a material with a low dielectric constant (low k-value), another suitable dielectric material, or a combination thereof. The low k-value material can contain: fluorinated silicon dioxide glass (FSG), phosphosilicate glass (PSG), boron phosphosilicate glass (BPSG), carbon-doped silicon dioxide (SiO₂). x C y), Black Diamond™, Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, BCB (bis-benzocyclobutene), SiLK™, polyimide, and / or other low k-value dielectric materials developed in the future. In such an embodiment, where the substrate 202 contains a dielectric material, the layer 202 may comprise one or more conductive structural elements. Typically, the layer 202 may be referred to as an “initial intermetal dielectric (IMD) layer” or an “initial layering plane”.

[0018] According to Operation 104 of Fig. 1A is Fig. Figure 2B shows a cross-sectional view of the RRAM device 200, which contains several dummy structures 204-1, 204-2, and 204-3 formed at one of the various manufacturing stages, according to some embodiments. As shown, the dummy structures 204-1 to 204-3 are laterally spaced apart from one another, creating several openings 205 between them. According to some embodiments, such openings 205 can be used to form RRAM resistors and WLs of the disclosed RRAM device 200, which will be discussed in detail below.

[0019] Although in the illustrated embodiment of Fig. Since only three dummy structures are shown in Figure 2B (and in the following figures), it is understood that any desired number of dummy structures can be formed over the substrate 202. In some embodiments, hard mask layers 206-1, 206-2, and 206-3 are placed over the dummy structures 204-1, 204-2, and 204-3, respectively. In some embodiments, the dummy structures 204-1 to 204-3 can each be a thin film comprising silicon oxide, formed, for example, by a thermal oxidation process. In some embodiments, the dummy structures 204-1 to 204-3 are used to provide a self-adjusting function while the aforementioned RRAM resistors are formed, which will be discussed further below.In some embodiments, the hard mask layers 206-1 to 206-3 are formed from silicon nitride, for example, using low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD). The hard mask layers 206-1 to 206-3 are each used as a hard mask during subsequent photolithography processes.

[0020] According to Operation 106 of Fig. 1A is Fig. Figure 2C shows a cross-sectional view of the RRAM device 200, which includes a first capping material 208, a variable resistive material 210, and a second capping material 212, formed at one of the various manufacturing stages according to some embodiments. As shown, the first capping material 208 lies over several dummy structures 204-1 to 204-3 (and the corresponding openings 205), the variable resistive material 210 further lies over the first capping material 208, and the second capping material 212 further lies over the variable resistive material 210.Since each of the first capping material 208, the variable resistive material 210 and the second capping material 212 is formed as an essentially thin and conformal layer (for example, about 2.0 to 10.0 nm in thickness), the respective U-shaped profile of each of the openings 205 can still be present through the second capping material 212 after the first capping material 208, the variable resistive material 210 and the second capping material 212 have been formed over the openings 205.

[0021] In some embodiments, the first capping material 208, which forms the “inner electrode” around the WL, can comprise an electrically conductive material selected from the group consisting of: gold (Au), platinum (Pt), ruthenium (Ru), iridium (Ir), titanium (Ti), aluminum (Al), copper (Cu), tantalum (Ta), tungsten (W), iridium-tantalum alloy (Ir-Ta), indium tin oxide (ITO), or any alloy, oxide, nitride, fluoride, carbide, boride, or silicide thereof, such as TaN, TiN, TiAlN, TiW, or a combination thereof. Although the first capping material 208 in the illustrated embodiment of Fig. While Figure 2C (and the following figures) shows the first capping material 208 as a single layer, it should be noted that the first capping material 208 can contain multiple layers formed as a stack, each of the multiple layers being formed from one of the materials described above, for example, TaN, TiN, etc. In some embodiments, the first capping material 208 is formed using chemical vapor deposition (CVD), plasma-enhanced (PE) CVD, high-density plasma (HDP) CVD, inductively coupled plasma (ICP) CVD, physical vapor deposition (PVD), spin deposition, and / or other suitable techniques to deposit the at least one of the described materials over the substrate 202 and the dummy structures 204-1 to 204-3.

[0022] In some embodiments, the variable resistive material 210 has a resistance conversion property (for example, a variable resistance). Or, in other words: The variable resistive material 210 contains material characterized in that it exhibits a reversible resistance variance according to the polarity and / or amplitude of an applied electrical pulse. The variable resistive material 210 contains a dielectric layer. The variable resistive material 210 can change to a conductor or an insulator based on the polarity and / or magnitude of the electrical signal.

[0023] In one embodiment, the variable resistive material 210 can contain a transition metal oxide. The transition metal oxide can be M x O yThe variable resistive material 210 is denoted by the , where M is a transition metal, O is oxygen, x is the transition metal composition, and y is the oxygen composition. In one embodiment, the variable resistive material 210 contains ZrO₂. Examples of other materials suitable for the variable resistive material 210 are: NiO, TiO₂, HfO, ZrO, ZnO, WO₃, CoO, Nb₂O₅, Fe₂O₃, CuO, CrO₂, SrZrO₃ (Nb-doped), and / or other materials. In another embodiment, the variable resistive material 210 may contain a colossal magnetoresistence (CMR)-based material, such as Pr₂. 0,7 Approx 0,3 , MnO3 etc.

[0024] In another embodiment, the variable resistive material 210 can contain a polymer material, such as polyvinylidene fluoride and poly[(vinylidene fluoride co-trifluoroethylene] (P(VDF / TrFE))]. In another embodiment, the variable resistive material 210 can contain a conductive-bridging random access memory (CBRAM) material, such as Ag in GeSe. According to some embodiments, the variable resistive material 210 can contain multiple layers that possess the properties of a resistance-conversion material. A setting stress and / or a reset stress of the variable resistive material 210 can be determined by the composition (including the values ​​of "x" and "y"), the thickness, and / or other factors of the variable resistive material 210 known to those skilled in the art.

[0025] In some embodiments, the variable resistive material 210 can be formed over the first capping material 208 by an atomic layer deposition (ALD) technique using a precursor containing a metal and oxygen. In some embodiments, other chemical vapor deposition (CVD) techniques can be used. In some embodiments, the variable resistive material 210 can be formed by a physical vapor deposition (PVD) technique, such as a sputtering process with a metallic target and with a gas supply of oxygen and optionally nitrogen into the PVD chamber. In some embodiments, the variable resistive material 210 can be formed by an electron beam deposition technique.

[0026] In some embodiments, the second capping material 212 may contain a material substantially similar to that of the first capping material 208. Thus, the second capping material 212 may contain a material selected from the group consisting of: gold (Au), platinum (Pt), ruthenium (Ru), iridium (Ir), titanium (Ti), aluminum (Al), copper (Cu), tantalum (Ta), tungsten (W), iridium-tantalum alloy (Ir-Ta), indium tin oxide (ITO), or any alloy, oxide, nitride, fluoride, carbide, boride, or silicide thereof, such as TaN, TiN, TiAlN, TiW, or a combination thereof. Although the second capping material 212 in the illustrated embodiment of Fig. In Figure 2C (and the following figures) shown as a single layer, it should be noted that the second capping material 212 can contain multiple layers formed as a stack, each of the multiple layers being formed from one of the materials described above, for example, TaN, TiN, etc. In some embodiments, the second capping material 212 is formed using chemical vapor deposition (CVD), plasma-enhanced (PE) CVD, high-density plasma (HDP) CVD, inductively coupled plasma (ICP) CVD, physical vapor deposition (PVD), spin deposition, and / or other suitable techniques to deposit the at least one of the materials described above onto the variable resistive material 210.

[0027] According to Operation 108 of Fig. 1A is Fig. Figure 2D shows a cross-sectional view of the RRAM device 200, which contains several stacked resistive film segments 214-1, 214-2, 214-3, 214-5, and 214-6 formed at one of the various fabrication stages, according to some embodiments. In some embodiments, the stacked resistive films 214-1 to 214-6 are formed by performing at least one anisotropic etching process 215 (for example, a reactive ion etching (RIE) process) on the first capping material 208, the variable resistive material 210, and the second capping material 212.Accordingly, respective sections of the first capping material 208, the variable resistive material 210, and the second capping material 212 that were deposited above the upper limits of the hard mask layers 206-1 to 206-3, and partial sections of the first capping material 208, the variable resistive material 210, and the second capping material 212 that were deposited above an upper limit 202U of layer 202, are removed. For clarity, such removed sections of the first capping material 208, the variable resistive material 210, and the second capping material 212 are outlined in dashed lines, as shown in . Fig. 2D shown. Thus, each of the stacked resistive films 214-1 to 214-6, which extends along a side wall of a respective dummy structure (204-1, 204-2 or 204-3), is formed according to some embodiments by respective remaining sections of the first capping material 208, the variable resistive material 210 and the second capping material 212.

[0028] More precisely, the stacked resistive film 214-1 extends along the side wall 204-1S1 of the dummy structure 204-1; the stacked resistive film 214-2 extends along the side wall 204-1S2 of the dummy structure 204-1; the stacked resistive film 214-3 extends along the side wall 204-2S1 of the dummy structure 204-2; the stacked resistive film 214-4 extends along the side wall 204-2S2 of the dummy structure 204-2; the stacked resistive film 214-5 extends along the side wall 204-3S1 of the dummy structure 204-3; and the stacked resistive film 214-6 extends along the side wall 204-2S2 of the dummy structure 204-3. Furthermore, after forming the stacked resistive films 214-1 to 214-6, a portion of the openings 205 (i.e., a portion of the upper boundary 202U) can be re-exposed according to some embodiments.Such newly exposed sections of the openings 205 can be used to form multiple WLs, which will be discussed below.

[0029] As mentioned above, in some embodiments, each of the stacked resistive films 214-1 to 214-6 is formed by the remaining first capping material 208, variable resistive material 210, and second capping material 212. Using the stacked resistive film 214-1 as a representative example, the remaining first capping material 208, in particular, can have an L-shaped profile having a first leg extending along the side wall 204-1S1 and a second leg extending along an upper boundary 202U of the substrate and away from the dummy structure 204-1. The remaining variable resistive material 210 can also have an L-shaped profile substantially similar to that of the remaining first capping material 208; and the remaining second capping material 212 can optionally have such an L-shaped profile. For example, in the illustrated embodiments of Fig. In Figure 2D (and the following figures), the remaining second capping material 212 in the stacked resistive film 214-1 does not have the L-shaped profile, but it is understood that in some other embodiments the remaining second capping material 212 may have a similar L-shaped profile. Each of the remaining first capping material 208, variable resistive material 210, and second capping material 212 of other stacked resistive films 214-2 to 214-6 has essentially similar profiles, which is why the discussions are not repeated.

[0030] Fig. Figure 2E is a cross-sectional view of the RRAM device 200, which contains an insulating layer 216 formed at one of the various fabrication stages according to some embodiments. As shown, the insulating layer 216 is formed over the substrate 202, the dummy structures 204-1 to 204-3, and the stacked resistive films 214-2 to 214-6. In some embodiments, the insulating layer 216 at this stage may be a film containing an oxide material. The insulating layer 216 may be formed using CVD, PVD, E-Gun, and / or other suitable techniques for depositing the oxide material.

[0031] Fig. Figure 2F is a cross-sectional view of the RRAM device 200, which contains several insulating segments 216 formed at one of the various manufacturing stages, according to some embodiments. In some embodiments, the several insulating segments 216 are formed by performing at least one anisotropic etching process 217 (for example, a reactive ion etching (RIE) process) on the insulating layer 216 to expose lower sections of the openings or trenches 205, top surfaces of the stacked resistive films 214-1 to 214-6, and upper sections of the inner electrodes 212 containing the second capping material. Thus, each of the insulating segments 216, which extends along a side wall of a respective stacked resistive film (214-1 to 214-6), is formed by respective remaining sections of the insulating layer 216 and can insulate the inner electrode 212 from the outer electrode 208.

[0032] According to Operation 110 of Fig. 1A is Fig. Figure 2G shows a cross-sectional view of the RRAM device 200, which contains a WL metal material 218 formed at one of the various manufacturing stages, according to some embodiments. As shown, the WL metal material 218 is formed over the substrate 202, the insulating segments 216, the dummy structures 204-1 to 204-3, and the stacked resistive films 214-2 to 214-6 with a thickness that is relatively greater than the heights of the dummy structures 204-1 to 204-3, such that the re-exposed sections of the openings 205 can be completely filled. In some embodiments, the WL metal material 218 contains a conductive material, such as copper (Cu), aluminum (Al), tungsten (W), etc. The WL metal material 218 can be formed using CVD, PVD, E-Gun and / or other suitable techniques for depositing the conductive material described above over the dummy structures 204-1 to 204-3.

[0033] According to Operation 112 of Fig. 1A is Fig. Figure 2H shows a cross-sectional view of the RRAM device 200 in which a polishing process 219 is performed on at least the WL metal material 218 (shown in dashed lines) at one of the various manufacturing stages, according to some embodiments. In some embodiments, the polishing process 219 includes a chemical-mechanical polishing (CMP) process, which is performed on the WL metal material 218 until the hard mask layers 206-1 to 206-3 are also polished out. In this respect, in some embodiments, respective upper sections of the stacked resistive films 214-1 to 214-6, which extend above the upper limits of the dummy structures 204-1 to 204-3, can also be polished out.

[0034] In some embodiments, the remaining sections of the WL metal material 218 can form several WLs 220-1, 220-2, 220-3 and 220-4, each of which is arranged between two adjacent stacked resistive films and extends along respective sidewalls of the two adjacent stacked resistive films.For example, the WL 220-1 is positioned between a stacked resistance film not shown and the stacked resistance film 214-1, and extends along the respective side walls of the stacked resistance film not shown and the stacked resistance film 214-1; the WL 220-2 is positioned between the stacked resistance films 214-2 and 214-3, and extends along the respective side walls of the stacked resistance films 214-2 and 214-3; the WL 220-3 is positioned between the stacked resistance films 214-4 and 214-5, and extends along the respective side walls of the stacked resistance films 214-4 and 214-5; and the WL 220-4 is positioned between the stacked resistance film 214-6 and an unseen stacked RRAM resistance film and extends along the respective side walls of the stacked resistance film 214-6 and the unseen stacked RRAM resistance film.

[0035] According to Operation 114 of Fig. 1B is Fig. Figure 2I shows a cross-sectional view of the RRAM device 200 in which the dummy structures 204-1 to 204-3 are removed at one of the various manufacturing stages, according to some embodiments. Since the polishing process 219 removes the hard mask layers 206-1 to 206-3 to expose the respective upper boundaries of the dummy structures 204-1 to 204-3 ( Fig. 2H), in some embodiments the dummy structures 204-1 and 204-3 can be removed by performing at least one isotropic etching process (for example, a wet etching process using an acid-based etchant). After the removal of the dummy structures 204-1 to 204-3, several openings 221 are created, each located between two adjacent stacked resistive films, as in the illustrated embodiment of Fig. 2I shown. Or in other words: After removing the dummy structures 204-1 to 204-3, the respective side walls of the stacked resistor films 214-1 to 214-6, which are opposite those to which the WLs 220-1 to 220-3 are in contact, are exposed.

[0036] According to Operation 116 of Fig. 1B is Fig. Figure 2J shows a cross-sectional view of the RRAM device 200, which contains a first selector material 224-1 and a second selector material 224-2 formed at one of the various fabrication stages, according to some embodiments. As shown, the first and second selector materials 224-1 and 224-2 are arranged to partially fill the openings 221 (created by removing the dummy structures 204-1 to 204-3). Since the first and second selector materials 224-1 and 224-2 are each formed as a substantially thin and conformal layer (about 2.0 to 10 mm thick), the material is viscous and therefore viscous.0 nmm in thickness), the recesses having U-shaped profiles (of the openings 221) can still remain along sections of an upper boundary 224U of the second selector material 224-2, which are located between two adjacent stacked resistive films, for example adjacent stacked resistive films 214-1 and 214-2, adjacent stacked resistive films 214-3 and 214-4 and adjacent stacked resistive films 214-5 and 214-6.

[0037] In some embodiments, each of the selector materials 224-1 and 224-2 contains at least one of the following: an intrinsic semiconductor material (for example, i-Si (silicon)), a weakly or heavily p-type doped semiconductor material (for example, p - Si or p + -Si), a weakly or heavily n-type doped semiconductor material (for example, n - Si or n +-Si), an insulator material (for example, HfO2, Al2O3, TiO2, Ti2O5, etc.), and a metal material (for example, Ni, Ti, TiN, etc.). In one example, the first selector material 224-1 can be configured as an n-type doped Si layer; and the second selector material 224-2 can be configured as a p-type doped Si layer, causing a pn diode (for example, a unipolar selector device) to be connected in series with each of the stacked resistive films 214-1 to 214-6, which will be discussed in more detail below.

[0038] In some other embodiments, one or more additional selector materials, each comprising an intrinsic semiconductor material, a weakly or heavily p-type doped semiconductor material, a weakly or heavily n-type doped semiconductor material, an insulator material, or a metallic material, can be formed over the first and second selector materials 224-1 and 224-2. In one example, a third selector material (not shown) can be formed over the first and second selector materials 224-1 and 224-2, wherein the first selector material 224-1 comprises a metallic material (for example, Ni), the second selector material 224-2 comprises an insulator material (for example, TiO2), and the third selector material (not shown) comprises a metallic material similar to that of the first selector material 224-1. Thus, these three selector materials can form a metal-insulator-metal (MIM) tunnel diode (for example, a bipolar selector device).In another example, the first selector material 224-1 contains a heavily doped n-type or p-type silicon, the second selector material 224-2 contains a lightly doped p-type or n-type silicon, and the third selector material (not shown) contains a heavily doped n-type or p-type silicon (similar to the first selector material 224-1). Thus, these three selector materials can form a punch-through diode (for example, a bipolar selector device).

[0039] More precisely, in some embodiments, each of the first and second selector materials 224-1 and 224-2 between two adjacent stacked resistive films (for example, 214-1 and 214-2) follows the U-shaped profile of the opening 221. Accordingly, the first and second selector materials 224-1 and 224-2 between two adjacent stacked resistive films each comprise a lower section extending along the upper boundary 202U of the substrate 202, and two sidewall sections extending from respective ends of the lower section and along the sidewalls of the two adjacent stacked resistive films.

[0040] For example, the first selector material 224-1, between the stacked resistive films 214-1 and 214-2, contains a lower section 224-1B1 extending along the upper boundary 202U, and two sidewall sections 224-1S1 extending along the sidewalls of the stacked resistive films 214-1 and 214-2 respectively; and the second selector material 224-2, between the stacked resistive films 214-1 and 214-2, also contains a lower section 224-2B1 extending along the upper boundary 202U, and two sidewall sections 224-2S1 extending along the sidewalls of the stacked resistive films 214-1 and 214-2 respectively. The first selector material 224-1, located between the stacked resistive films 214-3 and 214-4, contains a lower section 224-1B2 extending along the upper boundary 202U, and two sidewall sections 224-1S2 extending along the sidewalls of the stacked resistive films 214-1 and 214-4, respectively.214-2 extend, and the second selector material 224-2, between the stacked resistance films 214-3 and 214-4, also contains a lower section 224-2B2 extending along the upper boundary 202U, and two sidewall sections 224-2S2 extending along the sidewalls of the stacked resistance films 214-1 and 214-2 respectively. The first selector material 224-1, located between the stacked resistive films 214-5 and 214-6, contains a lower section 224-1B3 extending along the upper boundary of 202U, and two sidewall sections 224-1S3 extending along the sidewalls of the stacked resistive films 214-1 and 214-2, respectively. The second selector material 224-2, located between the stacked resistive films 214-1 and 214-2, also contains a lower section 224-2B3 extending along the upper boundary of 202U, and two sidewall sections 224-2S3 extending along the sidewalls of the stacked resistive films 214-1 and 214-2, respectively.extend to 214-2.

[0041] According to Operation 118 of Fig. 1B is Fig. Figure 2K shows a cross-sectional view of the RRAM device 200, which contains a bit-line (BL) metal material 226 formed at one of the various fabrication stages according to some embodiments. As shown, the BL metal material 226 is formed to lie over the second selector material 224-2. In some embodiments, the BL metal material 226 is formed to at least fill the U-shaped profiles along the upper boundary 224U. In some embodiments, the BL metal material 226 contains a conductive material, such as copper (Cu), aluminum (Al), tungsten (W), etc. The BL metal material 226 can be formed over the second selector material 224-2 using CVD, PVD, E-Gun, and / or other suitable techniques for depositing the conductive material described above.

[0042] According to operation 120 of Fig. 1B is Fig. 2L a cross-sectional view of the RRAM device 200, which contains several BLs 228-1, 228-2 and 228-3 formed at one of the different manufacturing stages, according to some embodiments. In some embodiments, the BLs 228-1 to 228-3 are formed by performing a polishing process 229 (for example, a chemical-mechanical polishing (CMP) process) at least on the BL metal material 226 and upper sections of the first and second selector materials 224-1 and 224-2, which were deposited above upper limits of the WLs 220-1 to 220-4, until a coplanar boundary 231 is formed which is common to the stacked resistive films 214-1 to 214-6, the WLs 220-1 to 220-3, the remaining first and second selector materials 224-1 and 224-2, and the BLs 228-1 to 228-3.Or to put it another way: The polishing process 229 is carried out on the BL metal material 226 and the upper sections of the first and second selector materials 224-1 and 224-2, which have been arranged over the upper limits of the WLs 220-1 to 220-4, until the respective upper limits of the WLs 220-1 to 220-3 are exposed again, while the U-shaped profiles on the second selector material 224-2 remain filled with the BL metal material 226.

[0043] Thus, the BL 228-1 is partially surrounded by remaining sections of the first and second selector materials 224-1 and 224-2 between the stacked resistive films 214-1 and 214-2, i.e., respective remaining sections of the side wall sections 224-2S1 and the lower section 224-2B1 and respective remaining sections of the side wall sections 224-1S1 and the lower section 224-1B1; BL 228-2 is partially surrounded by remaining sections of the second selector material 224-2 between the stacked resistive films 214-3 and 214-4, i.e., respective remaining sections of the sidewall sections 224-2S2 and the lower section 224-2B2, and respective remaining sections of the sidewall sections 224-1S2 and the lower section 224-1B2; and BL 228-3 is partially surrounded by remaining sections of the second selector material 224-2 that remained between the stacked resistive films 214-5 and 214-6, i.e.,respective remaining sections of the side wall sections 224-2S3 and the lower section 224-2B3 and respective remaining sections of the side wall sections 224-1S3 and the lower section 224-1B3.

[0044] In some embodiments, after forming BLs 228-1 to 228-3, several RRAM bit cells 241-1, 241-2, 241-3, 241-4, 241-5 and 241-6 can be arranged along a first lateral direction (for example, a direction parallel to the one shown in the diagram). Fig. 2L (X-axis shown) are formed, with each RRAM bit cell being formed by an RRAM resistor and a selector device connected in series. Furthermore, each RRAM bit cell is configured with a BL that extends along a second lateral direction (for example, a direction parallel to the Y-axis in 2L). Fig. 2L) extends, and a WL that extends along a vertical direction (for example, a direction parallel to the Z-axis in Fig. 2L) extends, coupled at each of its two ends.

[0045] More precisely, the RRAM bit cell 241-1 contains an RRAM resistor formed by the stacked resistive film 214-1 (hereinafter referred to as "RRAM resistor 241-1R"), and a selector device formed by the remaining side wall sections 224-1S1 and 224-2S1 on the left side of the BL 228-1 (hereinafter referred to as "selector device 241-1S"); and the RRAM bit cell 241-1 is coupled to the BL 228-1 and the WL 220-1 at their respective ends. Similarly, the RRAM bit cell 241-2 contains an RRAM resistor formed by the stacked resistive film 214-2 (hereinafter referred to as "RRAM resistor 241-2R"), and a selector device formed by the remaining side wall sections 224-1S1 and 224-2S1 on the right side of the BL 228-1 (hereinafter referred to as "selector device 241-2S"); and the RRAM bit cell 241-2 is coupled to the BL 228-1 and the WL 220-2 at respective ends.The RRAM bit cell 241-3 contains an RRAM resistor formed by the stacked resistive film 214-3 (hereinafter referred to as "RRAM resistor 241-3R"), and a selector device formed by the remaining side wall sections 224-1S2 and 224-2S2 on the left side of the BL 228-2 (hereinafter referred to as "selector device 241-3S"); and the RRAM bit cell 241-3 is coupled to the BL 228-2 and the WL 220-2 at respective ends. The RRAM bit cell 241-4 contains an RRAM resistor formed by the stacked resistor film 214-4 (hereinafter referred to as "RRAM resistor 214-4R"), and a selector device formed by the remaining side wall sections 224-1S2 and 224-2S2 on the right side of the BL 228-1 (hereinafter referred to as "selector device 241-1S"); and the RRAM bit cell 241-4 is coupled to the BL 228-2 and the WL 220-3 at respective ends.The RRAM bit cell 241-5 contains an RRAM resistor formed by the stacked resistive film 214-5 (hereinafter referred to as "RRAM resistor 241-5R"), and a selector device formed by the remaining side wall sections 224-1S3 and 224-2S3 on the left side of the BL 228-3 (hereinafter referred to as "selector device 241-5S"); and the RRAM bit cell 241-5 is coupled to the BL 228-3 and the WL 220-3 at respective ends. The RRAM bit cell 241-6 contains an RRAM resistor formed by the stacked resistive film 214-6 (hereinafter referred to as "RRAM resistor 241-6R"), and a selector device formed by the remaining side wall sections 224-1S3 and 224-2S3 on the right side of the BL 228-3 (hereinafter referred to as "selector device 241-6S"); and the RRAM bit cell 241-6 is coupled to the BL 228-3 and the WL 220-4 at respective ends.

[0046] In some embodiments, during operation of the RRAM bit cell (for example, 241-1 to 241-6), a current flows from the corresponding BL through the selector device, and if the current is allowed to pass through the selector device (i.e., a forward bias in the designated direction), the current continues through the RRAM resistor to the WL, or vice versa. Thus, it should be noted that, according to some embodiments of the present disclosure, each RRAM bit cell of the disclosed RRAM device 200 has its active interface or active interfaces (i.e., an interface through which a conducted current flows) that are substantially parallel to each other and to a plane defined by the Y-axis and the Z-axis.

[0047] Using the RRAM bit cell 241-1 as a representative example, a current can first flow from the BL 228-1 to the selector device 241-1S (the remaining side wall sections 224-2S1 and 224-1S1), with such a current flowing through a first active interface between the side wall of the BL 228-1 and the remaining side wall section 224-2S1.If the current is allowed to pass through, the current flows in a similar manner through a second active interface between the remaining sidewall sections 224-2S1 and 224-1S1, a third active interface between the remaining sidewall sections 224-1S1 and the variable resistive material of the stacked resistive film 214-1, and a fourth active interface between the variable resistive material of the stacked resistive film 214-1 and the sidewall of the WL 220-1, to the WL 220-1, each of the above-mentioned active interfaces being substantially parallel to the plane defined by the Y-axis and the Z-axis.

[0048] It should be noted that, according to some embodiments, each pair of adjacent RRAM bit cells 241-1 to 241-6 on two opposite sides of one of the BLs 228-1 to 228-3 exhibits symmetry. More precisely, the respective resistors and selector devices of each pair of RRAM bit cells 241-1 to 241-6 across a respective BL are mirror-symmetrical.For example, the selector device 241-1S of the RRAM bit cell 241-1 and the selector device 241-2S ​​of the RRAM bit cell 241-2 are mirror-symmetrical across the BL 228-1, and the resistor 241-1R of the RRAM bit cell 241-1 and the resistor 241-2R of the RRAM bit cell 241-2 are also mirror-symmetrical across the BL 228-1; The selector device 241-3S of the RRAM bit cell 241-3 and the selector device 241-4S of the RRAM bit cell 241-4 are mirror-symmetrical across the BL 228-2, and the resistor 241-3R of the RRAM bit cell 241-3 and the resistor 241-4R of the RRAM bit cell 241-4 are also mirror-symmetrical across the BL 228-2; and the selector device 241-5S of the RRAM bit cell 241-5 and the selector device 241-6S of the RRAM bit cell 241-6 are mirror-symmetrical across the BL 228-3, and the resistor 241-5R of the RRAM bit cell 241-5 and the resistor 241-6R of the RRAM bit cell 241-6s are also mirror-symmetrical across the BL 228-3.

[0049] In some embodiments, the RRAM bit cells 241-1, 241-2, 241-3, 241-4, 241-5, and 241-6 are formed laterally as a strip on the substrate 202 and extend parallel to the X-axis; the BLs 228-1, 228-2, and 228-3 each cross the strip and extend parallel to the Y-axis; and the WLs 220-1, 220-2, 220-3, and 220-4 cross the strip and extend parallel to the Z-axis. It should be noted that any desired number of RRAM bit cells can be formed in such a strip and that any desired number of BLs and WLs can pass through it, as long as the RRAM bit cells and corresponding BLs / WLs are arranged similarly to the illustrated embodiment of Fig. 2L. Furthermore, in some embodiments, several such strips can be formed above the substrate 202, spaced apart from each other and arranged parallel to each other (i.e., parallel to the X-axis), which with reference to Fig. 3 is illustrated and discussed.

[0050] According to Operation 122 of Fig. 1B is Fig. Figure 2M shows a cross-sectional view of the RRAM device 200, which contains several layering levels (1st, 2nd, 3rd layering level, etc.) formed at one of the various manufacturing stages, according to some embodiments. As mentioned above, the substrate 202 is generally referred to as the initial layering level, and accordingly, the layering level containing the RRAM bit cells 241-1 to 241-6, BLs 228-1 to 228-3, and WLs 220-1 to 220-4 is referred to as being formed at a 1st layering level. According to some embodiments of the present disclosure, each of the layering levels formed above the 1st layering level can be formed by repeating operations 104 to 120 of method 100 of Fig. 1 are produced, the embodiments of the 2nd and 3rd layering levels are briefly discussed below.

[0051] In the illustrated embodiment of Fig. 2M contains the second layer of RRAM bit cells 251-1, 251-2, 251-3, 251-4, 251-5, and 251-6 with BLs 258-1, 258-2, and 258-3 and WLs 250-1, 250-2, 250-3, and 250-4, which extend through it in their respective directions. BLs 258-1 to 258-3 extend in a direction parallel to the Y-axis (the same direction as BLs 228-1 to 228-3 on the first layer), and WLs 250-1 to 250-4 extend in a direction parallel to the Z-axis (the same direction as WLs 220-1 to 220-4 on the first layer). In some embodiments, WLs 250-1 to 250-4 on the second layer are each aligned with, and coupled to, WLs 220-1 to 220-4 on the first layer. Similarly, the third layer contains RRAM bit cells 281-1, 281-2, 281-3, 281-4, 281-5, and 281-6 with BLs 288-1, 288-2, and 288-3 and WLs 280-1, 280-2, 280-3, and 280-4 passing through it in their respective directions.BLs 288-1 to 288-3 extend along a direction parallel to the Y-axis (the same direction as BLs 228-1 to 228-3 on the 1st layering plane and BLs 258-1 to 258-3 on the 2nd layering plane), and WLs 280-1 to 280-4 extend along a direction parallel to the Z-axis (the same direction as WLs 220-1 to 220-4 on the 1st layering plane and WLs 250-1 to 250-4 on the 2nd layering plane). In some embodiments, the WLs 280-1 to 280-4 on the 3rd layering level are each aligned with, and coupled to, the WLs 250-1 to 250-4 on the 2nd layering level and WLs 220-1 to 220-4 on the 1st layering level.

[0052] In some embodiments, an insulating layer is formed between each pair of adjacent layering planes. For example, an insulating layer 291 is formed on the first layering plane and beneath the second layering plane; and an insulating layer 292 is formed on the second layering plane and beneath the third layering plane. Each of the insulating layers 291 and 292 may contain oxide material.

[0053] As above with reference to Fig. As discussed in 2L, several strips, each containing several horizontally oriented RRAM bit cells, can be formed over substrate 202, with the BLs and WLs running horizontally and vertically through it, respectively. In some embodiments, such multiple strips and the horizontally oriented BLs can together be referred to as a layering plane. And as discussed above with reference to Fig. As discussed in 2M, by repeating operations 104 to 120 of procedure 100 of Fig. 1 Several layering levels are formed on top of each other, wherein such multiple layering levels are coupled to each other by respective WLs that extend vertically.

[0054] Fig. Figure 3 illustrates a perspective view of an exemplary RRAM device 300 containing several strips 310, 320, 340, 360, and 380, each formed on several layering levels (nth layering level, (n+1)th layering level, etc.), according to various embodiments. Although only two layering levels are shown, and only two strips 310 and 320 are shown on the nth layering level, and three strips 340, 360, and 380 are shown on the (n+1)th layering level, it is understood that the RRAM device 300 can contain any desired number of layering levels, and each layering level can contain any desired number of strips.

[0055] As in the illustrated embodiment of Fig. As shown in Figure 3, strips 310, 320, 340, 360, and 380 are designed to extend parallel to the X-axis. Strips 310 and 320 on the nth layering plane are coupled by BLs 302-1, 302-2, and 302-3 and extend parallel to the Y-axis; and strips 340, 360, and 380 on the (n+1)th layering plane are coupled by BLs 342-1, 342-2, and 342-3 and extend parallel to the Y-axis.Strip 340 on the (n+1)th layering plane and strip 310 on the nth layering plane are coupled by WLs 304-1 and 304-2 and extend parallel to the Z-axis; strip 360 on the (n+1)th layering plane and strip 320 on the nth layering plane are coupled by WLs 304-3 and 304-4 and extend parallel to the Z-axis; and strip 380 on the (n+1)th layering plane and a strip not shown on the nth layering plane are coupled by WLs 304-5 and 304-6 and extend parallel to the Z-axis.

[0056] More precisely, strip 310 contains, at the nth layer level, RRAM bit cells 300-1, 300-2, 300-3, 300-4, 300-5 and 300-6, and strip 320 contains several RRAM bit cells that are essentially similar to RRAM bit cells 300-1 to 300-3; and at the (n+1)th layer level, strip 340 contains RRAM bit cells 340-1, 340-2, 340-3, 340-4, 340-5 and 340-6, and the other strips 360 and 380 each contain several RRAM bit cells that are essentially similar to RRAM bit cells 340-1 to 340-6. Furthermore, on the nth layer level, BL 302-1 is configured to cross strip 310 in order to be coupled between RRAM bit cells 300-1 and 300-2; BL 302-2 is configured to cross strip 310 in order to be coupled between RRAM bit cells 300-3 and 300-4; and BL 302-3 is configured to cross strip 310 in order to be coupled between RRAM bit cells 300-5 and 300-6.Although not shown, it is understood that each of the BLs 302-1 to 302-3 also crosses strip 320 in order to be coupled between respective adjacent RRAM bit cells within it.

[0057] Similarly, BL 342-1 is configured on the (n+1)th layer level to cross strip 340 to be coupled between RRAM bit cells 340-1 and 340-2; BL 342-2 is configured to cross strip 340 to be coupled between RRAM bit cells 340-3 and 340-4; and BL 342-3 is configured to cross strip 340 to be coupled between RRAM bit cells 340-5 and 340-6. Although not shown, it is understood that each of BLs 342-1 to 342-3 also crosses strips 360 and 380 to be coupled between respective adjacent RRAM bit cells within them.

[0058] In some embodiments, the exemplary RRAM device 300 can be formed by a method 400 which is essentially the same as the method 100 of Fig. 1 resembles. Fig. 4A and Fig. Figure 4B illustrates a flowchart of process 400 according to one or more embodiments of the present disclosure. It should be noted that process 400 is merely an example and is not intended to limit the present disclosure. It should be noted that process 400 of the Fig. 4A and Fig. 4B does not provide a finished RRAM device. A finished RRAM device can be manufactured using complementary metal oxide semiconductor (CMOS) technology processing. Accordingly, it is understood that additional operations before, during, and after Procedure 400 of the Fig. 4A and Fig. 4B can be provided and that some other operations may only be briefly described in this text. In some other embodiments, Method 400 can be used to form any of a variety of different non-volatile memory (NVM) devices, such as ferroelectric random-access memory (FRAM) devices, phase-change random-access memory (PRAM) devices, magnetoresistive random-access memory (MRAM) devices, etc.

[0059] We turn first Fig. Method 400 begins with operation 402, in which a substrate overlying a dielectric layer is formed. Method 400 proceeds to operation 404, in which several first recessed regions, each extending through the dielectric layer, are formed. In some embodiments, the several first recessed regions, viewed from above, can be formed as a two-dimensional arrangement. Method 400 proceeds to operation 406, in which a first capping material, a variable resistive material, and a second capping material are each formed over the several first recessed regions. Method 400 proceeds to operation 408, in which several stacked resistive films, each extending along respective sidewalls of each of the several first recessed regions, are formed.Each stacked resistive film is formed by the respective remaining sections (after etching) of the first capping material, the variable resistive material, and the second capping material. In some embodiments, after the stacked resistive films have been formed, several word-lead (WL) openings, which are discussed below, are formed within each of the several first recessed regions. Method 400 proceeds to Operation 410, in which a WL metal material is formed over the several first recessed regions. In some embodiments, the WL metal material may fill the several WL openings. Method 400 proceeds to Operation 412, in which a first polishing process is performed. In some embodiments, the first polishing process is performed at least on the WL metal material to re-expose an upper boundary of the dielectric layer and form several WLs.In some embodiments, viewed from above, the multiple WLs are each surrounded by a stacked resistance film, which will be shown and discussed below.

[0060] We now turn Fig. 4B. Method 400 continues to Operation 414, in which a section of the dielectric layer is removed to form several second recessed regions extending through the dielectric layer. In some embodiments, each of the several second recessed regions includes a vertical section and at least two lateral sections. Viewed from above, each of the lateral sections intersects the vertical section and, in conjunction with, two adjacent stacked resistive films; and, viewed in cross-section, each of the lateral sections exposes respective side walls of the two adjacent stacked resistive films and an upper boundary of the substrate to obtain a U-shaped profile, which is shown and discussed below. Method 400 continues to Operation 416, in which the at least first and second selector materials are formed over the several second recessed regions.Method 100 proceeds to Operation 418, in which a bitline (BL) metal material is formed over the first and second selector materials. Since the first and second selector materials are each formed to be substantially thin and conformal, the respective U-shaped profiles of the second recessed regions may still be present in some embodiments along a portion of an upper boundary of the upper selector material (for example, the second selector material); and the BL metal material is formed to fill at least such U-shaped profiles that are present on the second selector material. Method 100 proceeds to Operation 420, in which a second polishing process is performed to form multiple BLs.In some embodiments, the second polishing process is carried out at least on the BL metal material and the first and second selector materials until the respective upper limits of the WLs are again exposed, while the U-shaped profiles of the second selector material are kept filled with the BL metal material.

[0061] In some embodiments, after the BLs are formed, several first RRAM bit cells can be used as a first strip (for example, strip 310 of Fig. 3) be formed, which is parallel to a first axis (for example, the X-axis of Fig. 3) extends, and several second RRAM bit cells can be considered as a second strip (for example, strip 320 of Fig. 3) be formed, which also extends parallel to the first axis, with the multiple BLs (for example, 302-1, 302-2 and 302-3 of Fig. 3) pass through the first and second stripes, which are parallel to a second axis (for example, the Y-axis of Fig. 3) extend, and wherein the multiple WLs (for example, 304-1, 304-2, 304-3, 304-4, 304-5 and 304-6 of Fig. 3) either pass through the first or the second strip, which runs parallel to a third axis (for example, the Z-axis of Fig. 3) extends. Furthermore, the first and second stripes can be formed on a first layering plane (for example, the nth layering plane of Fig. 3) In some embodiments, method 400 continues to operation 422, in which operations 404 to 420 are repeated. In some embodiments, after forming the strip on the first layering plane, a single iteration of performing operations 404 to 420 can form at least one strip on a layering plane above the first layering plane (for example, the (n+1)th layering plane of Fig. 3) form.

[0062] Operations 402 to 420 of the procedure 400 can be illustrated with top views of a semiconductor device 500 at various stages of manufacture, as in the Fig. 5A, Fig. 5B, Fig. 5C, Fig. 5D, Fig. 5E, Fig. 5F, Fig. 5G, Fig. 5H, Fig. 5I or 5J shown, and corresponding cross-sectional views, as in the Fig. 6A, Fig. 6B, Fig. 6C, Fig. 6D, Fig. 6E, Fig. 6F, Fig. 6G, Fig. 6H, Fig. 6I and Fig. 6J shown, linked. In some embodiments, the semiconductor device 500 may be an RRAM device, which is essentially the RRAM device 300 of Fig. 3 resembles. The RRAM device 500 can be contained within a microprocessor, a memory cell, and / or another integrated circuit (IC). Furthermore, the Fig. Figures 5A to 5J and 6A to 6J have been simplified for a better understanding of the concepts of this disclosure. For example, although the figures illustrate the RRAM device 500, it is understood that the IC in which the RRAM device 500 is formed may also contain a number of other components, such as resistors, capacitors, inductors, fuses, etc., which are described in the Fig. 5A to 5J and 6A to 6J are not shown for the sake of clarity.

[0063] According to Operation 402 of Fig. 4A is Fig. 5A a top view of the RRAM device 500, which contains a substrate 502 over which a dielectric layer 504 is located, and which is provided at one of the various manufacturing stages, according to some embodiments, and Fig. 6A is a corresponding cross-sectional view of Fig. 5A along line AA. In some embodiments, the substrate 502 contains a semiconductor material, for example, silicon. Alternatively, the substrate 502 may contain another elemental semiconductor material, such as germanium. The substrate 502 may also contain a compound semiconductor, such as silicon carbide, gallium arsenide, indium arsenide, and indium phosphide. The substrate 502 may contain an alloy semiconductor, such as silicon-germanium, silicon-germanium carbide, gallium arsenide, and gallium indium phosphide. In one embodiment, the substrate 502 contains an epitaxial layer. For example, the substrate may have an epitaxial layer overlying a bulk semiconductor. Furthermore, the substrate 502 may have a semiconductor-on-insulator (SOI) structure.For example, the substrate may contain a buried oxide (BOX) layer formed by a process such as separation by implanted oxygen (SIMOX) or another suitable technique, such as wafer bonding and grinding.

[0064] In some other embodiments, the substrate 502 is a substrate of dielectric material formed over various device structure elements (for example, a source, drain, or gate electrode of a transistor). Such a substrate 502 of dielectric material can comprise at least one of the following: silicon dioxide, a material with a low dielectric constant (low k-value), another suitable dielectric material, or a combination thereof. The low k-value material can comprise: fluorinated silicon dioxide glass (FSG), phosphosilicate glass (PSG), boron phosphosilicate glass (BPSG), carbon-doped silicon dioxide (SiO₂). x C y), Black Diamond™, Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, BCB (bis-benzocyclobutene), SiLK™, polyimide, and / or other low k-value dielectric materials developed in the future. In such an embodiment, where the substrate 202 contains a dielectric material, the substrate 502 may comprise one or more conductive structural elements. Typically, the substrate 502 may be referred to as an “initial intermetal dielectric (IMD) layer” or an “initial layering plane”.

[0065] In some embodiments, the dielectric layer 504 can be a thin film comprising silicon oxide, formed, for example, by a thermal oxidation process. In some embodiments, a hard mask layer (not shown) formed from silicon nitride, for example, by low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD), can be placed over the dielectric layer 504. The hard mask layer is used as a hard mask during subsequent photolithography processes.

[0066] According to Operation 404 of Fig. 4A is Fig. 5B a top view of the RRAM device 500, which includes several first recessed regions 506-1, 506-2, 506-3 and 506-4 formed at one of the various manufacturing stages, according to some embodiments, and Fig. 6B is a corresponding cross-sectional view of Fig. 5B along line AA. As shown in the cross-sectional view of Fig. As shown in Figure 6B, the first recessed regions 506-1, 506-2, 506-3, and 506-4 each extend through the dielectric layer 504 to expose a respective section of an upper boundary 502U of the substrate 502. Furthermore, as shown in the top view of Fig. Figure 5B shows the first recessed regions 506-1, 506-2, 506-3 and 506-4 spaced laterally apart by a distance, causing a remaining section of the dielectric layer 504 to function as several dummy structures (similar to dummy structures 204-1 to 204-3 of the Fig. 2B-2F). According to some embodiments, such several first recessed regions 506-1, 506-2, 506-3 and 506-4 can be used to form RRAM resistors and WLs of the disclosed RRAM device 500, which will be discussed in detail below.

[0067] Although in the illustrated embodiment of the Fig. In Figure 5B (and the following top-view figures), where only four first recessed regions are shown, it is understood that any desired number of first recessed regions can be formed above the substrate 502. In some embodiments, viewed from above, the first recessed regions 506-1, 506-2, 506-3, and 506-4 can be formed as a two-dimensional arrangement, wherein the first recessed regions 506-1 and 506-2 are arranged along a first row parallel to the X-axis (hereinafter referred to as the "1st row"); the first recessed regions 506-3 and 506-4 are arranged along a second row parallel to the X-axis (hereinafter referred to as the "2nd row"); and the first recessed regions 506-1 and 506-3 are arranged along a first column parallel to the Y-axis (hereinafter referred to as the "1st column"). and the first excluded regions 506-2 and 506-4 are arranged along a second column parallel to the Y-axis (hereinafter referred to as "2nd column").

[0068] According to Operation 406 of Fig. 4A is Fig. 5C a top view of the RRAM device 500, in which a first capping material 508, a variable resistive material 510 and a second capping material 512 are each located over the first recessed regions 506-1 to 506-4 (shown in dashed lines) at one of the various manufacturing stages, according to some embodiments, and Fig. 6C is a corresponding cross-sectional view of Fig. 5C along line AA. As shown in the cross-sectional view of Fig. As shown in Figure 6C, the first capping material 508 lies over the first recessed regions 506-1 and 506-2 (and 506-3 and 506-4, which are shown in Figure 6C). Fig. (Figure 6C not shown), the variable resistive material 510 is further layered over the first capping material 508, and the second capping material 512 is further layered over the variable resistive material 510. Since each of the first capping material 508, the variable resistive material 510, and the second capping material 512 is formed as a substantially thin and conformal layer (for example, about) 2.0 to 10.0 nm thick, after the formation of the first capping material 508, the variable resistive material 510, and the second capping material 512 over the first recessed regions 506-1 to 506-4, the respective U-shaped profiles of the first recessed regions 506-1 to 506-4 can still be present due to the second capping material 512.

[0069] In some embodiments, the first capping material 508 may comprise a material selected from the group consisting of: gold (Au), platinum (Pt), ruthenium (Ru), iridium (Ir), titanium (Ti), aluminum (Al), copper (Cu), tantalum (Ta), tungsten (W), iridium-tantalum alloy (Ir-Ta), indium tin oxide (ITO), or any alloy, oxide, nitride, fluoride, carbide, boride, or silicide thereof, such as TaN, TiN, TiAlN, TiW, or a combination thereof. Although the first capping material 508 in the illustrated embodiment of Fig. While Figure 6C (and the following figures) shows the first capping material 508 as a single layer, it should be noted that the first capping material 508 can contain multiple layers formed as a stack, each of the multiple layers being formed from one of the materials described above, for example, TaN, TiN, etc. In some embodiments, the first capping material 508 is formed using chemical vapor deposition (CVD), plasma-enhanced (PE) CVD, high-density plasma (HDP) CVD, inductively coupled plasma (ICP) CVD, physical vapor deposition (PVD), spin deposition, and / or other suitable techniques to deposit the at least one of the materials described above over the substrate 502 and the first recessed regions 506-1 to 506-4.

[0070] In some embodiments, the variable resistive material 510 has a resistance conversion property (for example, a variable resistance). Or, in other words: The variable resistive material 510 contains material characterized in that it exhibits a reversible resistance variance according to the polarity and / or amplitude of an applied electrical pulse. The variable resistive material 510 contains a dielectric layer. The variable resistive material 510 can change to a conductor or an insulator based on the polarity and / or magnitude of the electrical signal.

[0071] In one embodiment, the variable resistive material 510 can contain a transition metal oxide. The transition metal oxide can be M x O yThe variable resistive material 510 is denoted by the following ΣM, where M is a transition metal, O is oxygen, x is the transition metal composition, and y is the oxygen composition. In one embodiment, the variable resistive material 510 contains ZrO2. Examples of other materials suitable for the variable resistive material 510 include: NiO, TiO2, HfO, ZrO, ZnO, WO3, CoO, Nb2O5, Fe2O3, CuO, CrO2, SrZrO3 (Nb-doped), and / or other materials known to those skilled in the art. In another embodiment, the variable resistive material 510 may contain a colossal magnetoresistence (CMR)-based material, such as Pr2. 0,7C a 0,3 , MnO3 etc.

[0072] In another embodiment, the variable resistive material 510 can contain a polymer material, such as polyvinylidene fluoride and poly[(vinylidene fluoride co-trifluoroethylene] (P(VDF / TrFE))]. In another embodiment, the variable resistive material 510 can contain a conductive-bridging random access memory (CBRAM) material, such as Ag in GeSe. According to some embodiments, the variable resistive material 510 can contain multiple layers that possess the properties of a resistance-conversion material. A setting stress and / or a reset stress of the variable resistive material 510 can be determined by the composition (including the values ​​of "x" and "y"), the thickness, and / or other factors of the variable resistive material 510 known to those skilled in the art.

[0073] In some embodiments, the variable resistive material 510 can be formed over the first capping material 508 by an atomic layer deposition (ALD) technique using a precursor containing a metal and oxygen. In some embodiments, other chemical vapor deposition (CVD) techniques can be used. In some embodiments, the variable resistive material 510 can be formed by a physical vapor deposition (PVD) technique, such as a sputtering process with a metallic target and with a gas supply of oxygen and optionally nitrogen into the PVD chamber. In some embodiments, the variable resistive material 510 can be formed by an electron beam deposition technique.

[0074] In some embodiments, the second capping material 512 may contain a material substantially similar to that of the first capping material 208. Thus, the second capping material 512 may contain a material selected from the group consisting of: gold (Au), platinum (Pt), ruthenium (Ru), iridium (Ir), titanium (Ti), aluminum (Al), copper (Cu), tantalum (Ta), tungsten (W), iridium-tantalum alloy (Ir-Ta), indium tin oxide (ITO), or any alloy, oxide, nitride, fluoride, carbide, boride, or silicide thereof, such as TaN, TiN, TiAlN, TiW, or a combination thereof. Although the second capping material 512 in the illustrated embodiment of Fig. While Figure 6C (and the following figures) shows a single layer, it should be noted that the second capping material 512 can contain multiple layers formed as a stack, each of the multiple layers being formed from one of the materials described above, for example, TaN, TiN, etc. In some embodiments, the second capping material 512 is formed using chemical vapor deposition (CVD), plasma-enhanced (PE) CVD, high-density plasma (HDP) CVD, inductively coupled plasma (ICP) CVD, physical vapor deposition (PVD), spin deposition, and / or other suitable techniques to deposit the at least one of the materials described above over the variable resistive material 510.

[0075] According to Operation 408 of Fig. 4A is Fig. 5D a top view of the RRAM device 500, which contains several stacked resistance films 514-1, 514-2, 514-3 and 514-4 formed at one of the various manufacturing stages, according to some embodiments, and Fig. 6D is a corresponding cross-sectional view of Fig. 5D along line AA. In some embodiments, with reference to the cross-sectional view of Fig. 6D, the stacked resistive films 514-1 to 514-4 are formed by performing at least one anisotropic etching process 515 (for example, a reactive ion etching (RIE) process) on the first capping material 508, the variable resistive material 510, and the second capping material 512. Accordingly, respective sections of the first capping material 508, the variable resistive material 510, and the second capping material 512 that were deposited above an upper boundary of the dielectric layer 504, and partial sections of the first capping material 508, the variable resistive material 510, and the second capping material 512 that were arranged above the upper boundary 502U of the substrate 502, are removed. For the sake of clarity, such removed sections of the first capping material 508, the variable resistive material 510 and the second capping material 512 are shown in Fig. 6D outlined in dashed lines. Thus, according to some embodiments, each of the stacked resistive films 514-1 to 514-4, which extends along four side walls of a respective first recessed region (for example, 506-1, 506-2, 506-3 or 506-4), is formed by respective remaining sections of the first capping material 508, the variable resistive material 510 and the second capping material 512.

[0076] More precisely, as seen from above. Fig. In 5D, where the respective first capping material 508, variable resistive material 510 and second capping material 512 of each of the stacked resist films 514-1 to 514-4 are not shown, the stacked resist film 514-1 extends along four side walls of the first recessed region 506-1; the stacked resist film 514-2 extends along four side walls of the first recessed region 506-2; the stacked resist film 514-3 extends along four side walls of the first recessed region 506-3; and the stacked resist film 514-4 extends along four side walls of the first recessed region 506-4. Furthermore, according to some embodiments, after forming the stacked resistive films 514-1 to 514-6, a part of the first recessed regions 506-1 to 506-4 (i.e., a part of the upper boundary 502U) can be re-exposed.Such newly exposed sections of the first excluded regions 506-1 to 506-4 can be used to form multiple WLs, which will be discussed below.

[0077] More precisely, as seen in the cross-sectional view of Fig. 6D shows the respective remaining sections of the first capping material 508, the variable resistive material 510, and the second capping material 512, which form each of the stacked resistive films 514-1 to 514-2, similar to the remaining first capping material 208 and the remaining variable resistive material 210 shown in Fig. As shown in 2D, the respective remaining sections of the first capping material 508 and the variable resistive material 510 of the stacked resistive films 514-1 and 514-2 also have the L-shaped profiles described above, which will not be discussed again.

[0078] Fig. Figure 6E shows an insulating layer 516 formed over the substrate 502, the dielectric layer 504, and the stacked resistive films 514-1 to 514-2. In some embodiments, the insulating layer 516 can be a thin film containing an oxide material. The insulating layer 516 can be formed using CVD, PVD, E-Gun, and / or other suitable techniques for depositing the oxide material. Fig. Figure 6F shows several insulating segments 516 formed by performing at least one anisotropic etching process 517 (for example, a reactive ion etching (RIE) process) on the insulating layer 516 to expose lower sections of the recessed regions 506-1, 506-2, upper surfaces of the dielectric layer 504, and upper sections of the inner electrodes 512 containing the second capping material. Thus, each of the insulating segments 516, extending along a side wall of a respective stacked resistive film (514-1, 514-2), is formed by respective remaining sections of the insulating layer 516 and can insulate the inner electrode 512 from the outer electrode 508.

[0079] According to Operation 410 of Fig. 4A is Fig. 5E a top view of the RRAM device 500 in which a WL metal material 518 is formed over the first recessed regions 506-1 to 506-4 and the stacked resistive films 514-1 to 514-4 (shown in dashed lines) at one of the various manufacturing stages, according to some embodiments, and Fig. 6G is a corresponding cross-sectional view of Fig. 5E along line AA. As shown in the cross-sectional view of Fig. As shown in Figure 6G, the WL metal material 518 is formed over the substrate 502, the dielectric layer 504, the insulating segments 516, and the stacked resistive films 514-1 to 514-2 with a thickness that is relatively greater than the height of the dielectric layer 504, such that the re-exposed sections of the first recessed regions 506-1 and 506-2 (also 506-3 and 506-4, which are not shown) can be completely filled. In some embodiments, the WL metal material 518 contains a conductive material, such as copper (Cu), aluminum (Al), tungsten (W), etc. The WL metal material 518 can be formed over the dielectric layer 504 using CVD, PVD, E-Gun, and / or other suitable techniques.

[0080] According to Operation 412 of Fig. 4A is Fig. 5F a top view of the RRAM device 500 in which several WLs 520-1, 520-2, 520-3 and 520-4 are formed at one of the various manufacturing stages, according to some embodiments, and Fig. 6H is a corresponding cross-sectional view of Fig. 5F along line AA. In some embodiments, as in Fig. 6H can be seen forming several WLs 520-1, 520-2, 520-3 and 520-4 by performing a polishing process 521 (for example, a chemical-mechanical polishing (CMP) process) on the WL metal material 518 until a coplanar boundary is formed that is common to the dielectric layer 504, the stacked resistive films 514-1 and 514-2 (and the not shown 514-3 and 514-4) and the WLs 520-1 and 520-2 (and the not shown 520-3 and 520-4).

[0081] In some embodiments, the remaining sections of the WL metal material 518 can form the WLs 220-1, 220-2, 220-3, and 220-4, each of which is arranged within a corresponding first recessed region and surrounded by a corresponding stacked resistive film. For example, as shown in the top view of Fig. Figure 5F illustrates, where the respective first capping material 508, variable resistive material 510 and second capping material 512 of each of the stacked resistive films 514-1 to 514-4 are not shown, the WL 220-1 is arranged within the first recessed region 506-1 and surrounded by the stacked resistive film 514-1; the WL 220-2 is arranged within the first recessed region 506-2 and surrounded by the stacked resistive film 514-2; the WL 220-3 is arranged within the first recessed region 506-3 and surrounded by the stacked resistive film 514-3; and the WL 220-4 is arranged within the first recessed region 506-4 and surrounded by the stacked resistive film 514-4.

[0082] According to Operation 414 of Fig. 4B is Fig. 5G a cross-sectional view of the RRAM device 500, which contains a second recessed region 524 and which is formed at one of the various manufacturing stages, according to some embodiments, and Fig. 6I is a corresponding cross-sectional view of Fig. 5G along line AA. As shown in the top view of Fig. 5G or the cross-sectional view of Fig. As shown in Figure 6I, the second recessed region 524 is formed between two adjacent first recessed regions over several rows (for example, between the first recessed regions 506-1 and 506-2, between the first recessed regions 506-3 and 506-4, etc.) and extends through the dielectric layer 504.

[0083] Furthermore, as in Fig. As shown in Figure 5G, according to some embodiments, the second recessed region 524 contains a single vertical section 524-1 extending parallel to the Y-axis and several horizontal sections 524-2 and 524-3 extending parallel to the X-axis. The vertical section 524-1 is arranged between two adjacent columns, for example, the first column formed by the first recessed regions 506-1 and 506-3, and the second column formed by the first recessed regions 506-2 and 506-4. The horizontal sections 524-2 and 524-3 each cross the vertical sections 524-1 and couple respective stacked resistive films formed in the first recessed regions, which are aligned along a specific column and row.For example, the horizontal section 524-2, which crosses the vertical section 524-1, couples the stacked resistive films 514-1 and 514-2, which are arranged in the first recessed region 506-1 at the 1st column and 1st row and the first recessed region 506-2 at the 2nd column and 1st row, respectively; and the horizontal section 524-3, which crosses the vertical section 524-1, couples the stacked resistive films 514-3 and 514-4, which are arranged in the first recessed region 506-3 at the 1st column and 2nd row and the first recessed region 506-4 at the 2nd column and 2nd row, respectively.

[0084] More precisely, after forming the second recessed region 524 – in addition to exposing a section of the upper boundary 502U of the substrate 502 – at least sections of the respective sidewalls of the stacked resistive films 514-1 to 514-4, which are connected to the horizontal sections 524-2 and 524-3, are exposed. For example, as shown in the cross-sectional view of Fig. As illustrated in Figure 6I, a section of the side wall of the stacked resistive film 514-1, which is connected to the horizontal section 524-2, is exposed. Thus, viewed in a cross-sectional view, the horizontal sections 524-2 and 524-3 each have a U-shaped profile.

[0085] In some embodiments, the second recessed region 524 can be formed by performing at least some of the following steps: forming a structured layer (for example, a structured photoresist layer) containing an opening directed towards an area where the second recessed region 524 is to be formed above the dielectric layer 504; performing at least one dry or wet etching process on the dielectric layer 504 while the structured layer is used as a mask; and removing the structured layer.

[0086] According to Operation 416 of Fig. 4B is Fig. 5H a top view of the RRAM device 500 in which a first selector material 528-1 and a second selector material 528-2 are formed over the stacked resistive films 514-1 to 514-4, the WLs 520-1 to 520-4 and the second recessed region 524 (shown in dashed lines) at one of the various manufacturing stages, according to some embodiments, and Fig. 6J is a corresponding cross-sectional view of Fig. 5H along line AA. As shown in the cross-sectional view of Fig. As shown in Figure 6J, the first and second selector materials 528-1 and 528-2 are each configured to follow the U-shaped profile of the horizontal section 524-2 of the second recessed region 524, and since the first and second selector materials 528-1 and 528-2 are each configured as an essentially thin and conformal layer (about 20 to 100 angstroms in thickness), the U-shaped profile can still be maintained along a section of an upper boundary 528U of the second selector material 528-2, which is located between two adjacent first recessed regions 506-1 and 506-2 (i.e., the first row). Although in Fig. Not shown in 6J, it is understood that a similar U-shaped profile may also be present through another section of the upper boundary 528U of the second selector material 528-2, which is located between two adjacent first recessed regions 506-3 and 506-4 (i.e. the 2nd row).

[0087] In some embodiments, each of the selector materials 528-1 and 528-2 contains at least one of the following: an intrinsic semiconductor material (for example, i-Si (silicon)), a weakly or heavily p-type doped semiconductor material (for example, p - Si or p + -Si), a weakly or heavily n-type doped semiconductor material (for example, n - Si or n + -Si), an insulator material (for example, HfO2, Al2O3, TiO2, Ti2O5, etc.), and a metal material (for example, Ni, Ti, TiN, etc.). In one example, the first selector material 528-1 can be configured as an n-type doped Si layer; and the second selector material 528-2 can be configured as a p-type Si layer, which causes a pn diode (for example, a unipolar selector device) to be connected in series with each of the stacked resistive films 514-1 to 514-6, which will be discussed in more detail below.

[0088] In some other embodiments, one or more additional selector materials, each comprising an intrinsic semiconductor material, a weakly or heavily p-type doped semiconductor material, a weakly or heavily n-type doped semiconductor material, an insulator material, or a metallic material, can be formed over the first and second selector materials 528-1 and 528-2. In one example, a third selector material (not shown) can be formed over the first and second selector materials 528-1 and 528-2, wherein the first selector material 528-1 comprises a metallic material (for example, Ni), the second selector material 528-2 comprises an insulator material (for example, TiO2), and the third selector material (not shown) comprises a metallic material similar to that of the first selector material 528-1. Thus, these three selector materials can form a metal-insulator-metal (MIM) tunnel diode (for example, a bipolar selector device).In another example, the first selector material 528-1 contains a heavily doped n-type or p-type silicon, the second selector material 528-2 contains a lightly doped p-type or n-type silicon, and the third selector material (not shown) contains a heavily doped n-type or p-type silicon (similar to the first selector material 528-1). Thus, these three selector materials can form a punch-through diode (for example, a bipolar selector device).

[0089] More precisely, in some embodiments, between two adjacent stacked resistive films (for example, 514-1 and 514-2), each of the first and second selector materials 528-1 and 528-2 follows the U-shaped profile of the horizontal section 524-2 of the second recessed region 524. Accordingly, between two adjacent stacked resistive films, the first and second selector materials 528-1 and 528-2 each include a lower section extending along the upper boundary 502U of the substrate 502, and two sidewall sections extending from respective ends of the lower section and along the exposed sidewalls of the two adjacent stacked resistive films.

[0090] For example, the first selector material 528-1 between the stacked resistive films 514-1 and 514-2 contains a lower section 528-1B extending along the upper boundary 502U, and two sidewall sections 528-1S extending along the exposed sidewalls of the stacked resistive films 514-1 and 514-2, respectively; and the second selector material 528-2 also contains between the stacked resistive films 514-1 and 514-2 a lower section 528-2B extending along the upper boundary 502U, and two sidewall sections 528-2S extending along the exposed sidewalls of the stacked resistive films 514-1 and 514-2, respectively.

[0091] According to Operation 418 of Fig. 4B is Fig. 5I a top view of the RRAM device 500 in which a bit line (BL) metal material 530 is formed over the stacked resistive films 514-1 to 514-4, the WLs 520-1 to 520-4 and the second recessed region 524 (shown in dashed lines) at one of the various manufacturing stages, according to some embodiments, and Fig. 6K is a corresponding cross-sectional view of Fig. 5I along line AA. As shown in the cross-sectional view of Fig. To improve visibility of the 6K, the BL metal material 530 is configured to lie above the second selector material 528-2. In some embodiments, the BL metal material 530 is configured to fill at least the U-shaped profile(s) along the upper boundary 528U. In some embodiments, the BL metal material 530 contains a conductive material, such as copper (Cu), aluminum (Al), tungsten (W), etc. The BL metal material 530 can be formed above the second selector material 528-2 using CVD, PVD, E-Gun, and / or other suitable techniques.

[0092] According to Operation 420 of Fig. 4B is Fig. 5J a top view of the RRAM device 500 containing a BL 532 (filled with diagonal stripes) formed at one of the various manufacturing stages, according to some embodiments, and Fig. 6L is a corresponding cross-sectional view of Fig. 5J along line Aa. As shown in the cross-sectional view of Fig. As shown in Figure 6L, in some embodiments the BL 532 is formed by performing a polishing process 533 (for example, a chemical-mechanical polishing (CMP) process) at least on the BL metal material 530 and upper sections of the first and second selector materials 528-1 and 528-2 deposited above upper limits of the WLs 520-1 and 520-2, until a coplanar boundary 535 is formed which is common to the stacked resistive films 514-1 and 514-2, the WLs 520-1 and 520-2, the remaining first and second selector materials 528-1 and 528-2 and the BL 532.Or to put it another way: The polishing process 533 is carried out on the BL metal material 530 and the upper sections of the first and second selector materials 528-1 and 528-2, which have been arranged over the upper limits of the WLs 520-1 and 520-2, until the respective upper limits of the WLs 520-1 and 520-2 are exposed again, while the U-shaped profile on the second selector material 528-2 is kept filled with the BL metal material 530.

[0093] Thus, between the stacked resistive films 514-1 and 514-2, BL 532 is partially surrounded by remaining sections of the first and second selector materials 528-1 and 528-2, i.e., respective remaining sections of the sidewall sections 528-2S and the lower section 528-2B, and respective remaining sections of the sidewall sections 528-1S and the lower section 528-1B. Although not shown, it is understood that between the stacked resistive films 514-3 and 514-4, BL 532 is also partially surrounded by remaining sections of the first and second selector materials 528-1 and 528-2.

[0094] In some embodiments, after forming the BL 532, several RRAM bit cells 541-1 and 541-2 can be formed along the 1st row, and several RRAM bit cells 541-3 and 541-4 can be formed along the 2nd row (in Fig. (shown in Figure 5J) are formed, with each RRAM bit cell being formed by an RRAM resistor and a selector device connected in series. Furthermore, each RRAM bit cell has a BL parallel to the 1st and 2nd columns and a WL extending along a vertical direction (for example, a direction parallel to the Z-axis in Figure 5J). Fig. 6L) extends, coupled at each of its two ends.

[0095] Using the in Fig. In Figure 6L, the RRAM bit cells 541-1 and 541-2 shown as representative examples contain an RRAM resistor formed by a section of the stacked resistive film 514-1 arranged on the right side of the WL 520-1 (hereinafter referred to as "RRAM resistor 541-1R"), and a selector device formed by the remaining side wall sections 528-1S and 528-2S on the left side of the BL 532 (hereinafter referred to as "selector device 541-1S"); and the RRAM bit cell 541-1 is coupled to the BL 532 and the WL 520-1 at respective ends.Similarly, the RRAM bit cell 541-2 contains an RRAM resistor formed by a section of the stacked resistive film 514-2 on the left side of the WL 520-2 (hereinafter referred to as "RRAM resistor 541-2R"), and a selector device formed by the remaining side wall sections 528-1S and 528-2S on the right side of the BL 532 (hereinafter referred to as "selector device 541-2S"); and the RRAM bit cell 541-2 is coupled to the BL 532 and the WL 520-2 at their respective ends.

[0096] Similarly, each pair of adjacent RRAM bit cells of the RRAM device 200 forms a mirror symmetry over a respective BL (as with reference to Fig. (discussed in 2L), each pair of adjacent RRAM bit cells of the RRAM device 500 also exhibits mirror symmetry across a respective BL. For example, the selector device 541-1S of RRAM bit cell 541-1 and the selector device 541-2S ​​of RRAM bit cell 541-2 are mirror symmetrical across BL 532, and the resistor 541-1R of RRAM bit cell 541-1 and the resistor 541-2R of RRAM bit cell S41-2S ​​are also mirror symmetrical across BL 532.

[0097] In some embodiments, after forming BL 532, the RRAM bit cells 541-1 and 541-2 along the first row can be formed as a first strip parallel to the X-axis; the RRAM bit cells 541-3 and 541-4 along the second row can be formed as a second strip, also parallel to the X-axis, with a main section of BL 532 (extending parallel to the Y-axis) passing through the first and second strips, and with the WLs 520-1 to 520-4 (extending parallel to the Z-axis) passing through either the first or the second strip. As mentioned above, operations 402 to 420 (i.e., operation 422 of Fig. 4) to produce such first and second strips and corresponding BLs and WLs, repeated as often as desired to create a three-dimensional RRAM arrangement, for example the RRAM device 300 from Fig. 3, to produce.

[0098] By forming a three-dimensional RRAM array using disclosed method 100 or 400, the integration density of the RRAM bit cells of the three-dimensional RRAM array can be significantly increased, partly due to the mirror symmetry described above, which each pair of adjacent RRAM bit cells possesses. In addition to the increased integration density, the three-dimensional RRAM array produced by method 100 or 400 has several other advantages over the existing RRAM device. For example, in the existing RRAM device, a problem commonly referred to as "interference noise" occurs when multiple RRAM bit cells of the RRAM device are accessed simultaneously (for example, when they are read at the same time).However, such a problem can be advantageously avoided in the three-dimensional RRAM arrangement produced by method 100 or 400, since the respective selector device of two adjacent RRAM bit cells is formed in a mirror-symmetrical manner over a respective BL.

[0099] To illustrate how multiple RRAM bit cells of a three-dimensional RRAM array fabricated by Method 100 or 400 can be accessed simultaneously, a flowchart of an exemplary Method 700 is provided. In various embodiments, operations of Method 700 are performed by the respective components of the devices described above, for example, the RRAM device 200. Fig. 2A-2M, the RRAM device 300 from Fig. 3, the RRAM device 500 of Fig. 5A-6L, etc. For discussion purposes, the following embodiment of method 700 is shown in conjunction with a diagram of a three-dimensional RRAM arrangement 800 ( Fig. 8) described, which is equivalent to one of the RRAM devices described above (for example, 200, 300, or 500). The illustrated embodiment of method 700 is merely an example. Therefore, it is understood that any operations from a multitude of possibilities can be omitted, rearranged, and / or added.

[0100] We first turn to the diagram of Fig. 8. The three-dimensional RRAM arrangement 800 contains several BLs 802-1, 802-2, 802-3, 802-4, 802-5 and 80-6, several WLs 804-1, 804-2 and 804-3 and several RRAM bit cells 806-1, 806-1, 806-3, 806-4, 806-5, 806-6, 806-7, 806-8, 806-9, 806-10, 806-11 and 806-12, which are coupled between respective BLs and WLs. Although the illustrated embodiment of Fig. Since the RRAM contains 86 BLs, 3 WLs and 12 RRAM bit cells, it is understood that any desired number of BLs, WLs and RRAM bit cells can be contained in the three-dimensional RRAM arrangement 800.

[0101] As described above, in the RRAM device manufactured by the disclosed method 100 / 400 (for example, the RRAM device 200, 300, 500, etc.), several first RRAM bit cells are formed laterally as a first strip in a first layering plane, with several first BLs crossing laterally through it and several first WLs crossing vertically through it; several second RRAM bit cells are formed laterally as a second strip spaced laterally from the first strip on the first layering plane, with the several first BLs crossing laterally through it and several second WLs crossing vertically through it; several third RRAM bit cells are formed laterally as a third strip in a second layering plane, with several second BLs crossing laterally through it and the several first WLs crossing vertically through it;Several fourth RRAM bit cells are formed laterally as a fourth strip spaced laterally from the third strip on the second layering level, with the several second BLs passing laterally through it and the several second WLs passing vertically through it, and so on.

[0102] In some embodiments, the three-dimensional RRAM arrangement 800 illustrates a section of such an RRAM device. For example, the RRAM bit cells 806-1 to 806-6 form the aforementioned lateral first strip on the first layer, and the RRAM bit cells 806-7 to 806-12 form the aforementioned lateral second strip on the second layer, wherein the BLs 802-1 to 802-3 and 802-4 to 802-6 each form the multiple first and second BLs, respectively, and the WLs 804-1 to 804-3 form the multiple first WLs. Furthermore, each RRAM bit cell contains a respective resistor and a respective selector device connected in series.

[0103] For example, the RRAM bit cell 806-1 contains the resistor 806-1R and the selector device 806-1S; the RRAM bit cell 806-1 contains the resistor 806-1R and the selector device 806-1S; the RRAM bit cell 806-2 contains the resistor 806-2R and the selector device 806-2S; the RRAM bit cell 806-3 contains the resistor 806-3R and the selector device 806-3S; the RRAM bit cell 806-4 contains the resistor 806-4R and the selector device 806-4S; the RRAM bit cell 806-5 contains the resistor 806-5R and the selector device 806-5S; The RRAM bit cell 806-6 contains the resistor 806-6R and the selector device 806-6S; the RRAM bit cell 806-7 contains the resistor 806-7R and the selector device 806-7S; the RRAM bit cell 806-8 contains the resistor 806-8R and the selector device 806-8S; the RRAM bit cell 806-9 contains the resistor 806-9R and the selector device 806-9S;The RRAM bit cell 806-10 contains the resistor 806-10R and the selector device 806-10S; the RRAM bit cell 806-11 contains the resistor 806-11R and the selector device 806-11S; and the RRAM bit cell 806-12 contains the resistor 806-12R and the selector device 806-12S.

[0104] More precisely, thanks to the mirror symmetry described above, which each pair of adjacent RRAM bit cells possesses across a respective BL, the respective polarities of the selector device of such two symmetrical adjacent RRAM bit cells can, according to some embodiments, also be symmetrical across the respective BL. In the example where the first selector material (for example, 224-1, 528-1, etc.) is an n-type doped silicon layer and the second selector material (for example, 224-2, 528-2, etc.) is a p-type doped silicon layer, the respective nodes (i.e., the node connected to the p-type doped silicon layer) of the selector devices of such two symmetrical adjacent RRAM bit cells are coupled to the respective BL across which the symmetrical adjacent RRAM bit cells are mirrored, and the respective cathodes (i.e.,the node connected to the n-type doped Si layer) of the selector devices of such two symmetrical adjacent RRAM bit cells are coupled to respective WLs by respective resistors, as illustrated in the embodiment of the diagram of . Fig. 8 is expressed even more clearly.

[0105] Using the RRAM bit cells 806-1 and 806-2, which are symmetrical to each other via the BL 802-1, as representative examples, the respective nodes of the selector device 806-1S of the RRAM bit cell 806-1 and the selector device 806-2S of the RRAM bit cell 806-1 are coupled to the BL 802-1, while the respective cathodes of the selector device 806-1S of the RRAM bit cell 806-1 and the selector device 806-2S of the RRAM bit cell 806-1 are each coupled to the WLs 804-1 and 804-2 by the resistors 806-1R and 806-2R. Such symmetrical polarities of the selector device of each pair of symmetrical adjacent RRAM bit cells can bring advantages, such as the elimination of the problem of interference noise when accessing multiple RRAM bit cells of the disclosed three-dimensional RRAM arrangement 800, which will be discussed below.

[0106] We now turn Fig.7. In some embodiments, Method 700 begins with Operation 702, in which an RRAM device is provided in which at least a subset of the RRAM bit cells are arranged like the RRAM bit cells of RRAM Device 200 / 300 / 500. As mentioned above, the three-dimensional RRAM array 800 can equivalently represent a section of RRAM Device 200, 300, or 500. In the following discussion of Method 700, only the components of the three-dimensional RRAM array 800 are used.

[0107] Procedure 700 proceeds to operation 704, in which a first RRAM bit cell and a second RRAM bit cell are selected for access, with the first and second RRAM bit cells being directly coupled to respective different BLs and WLs. In an example where RRAM bit cell 806-1 is selected as the first RRAM bit cell to be accessed (for example, to be read), since RRAM bit cell 806-1 is directly coupled with BL 802-1 and WL 804-1, any other RRAM bit cell that is not directly coupled with BL 802-1 or WL 804-1 can be selected as the second RRAM bit cell to be accessed, such as RRAM bit cell 806-3, which is directly coupled with BL 802-2 and WL 804-2.

[0108] Procedure 700 proceeds to Operation 706, in which a first bias voltage is applied to the directly coupled BL and WL of the first RRAM bit cell, and a second bias voltage is applied to the directly coupled BL and WL of the second RRAM bit cell. Continuing the example above, to access RRAM bit cell 806-1, a first positive voltage can be applied to BL 802-1, and WL 804-1 can be connected to a ground voltage; and similarly, to access RRAM bit cell 806-3, a second positive voltage can be applied to BL 802-2, and WL 804-2 can be connected to the ground voltage.

[0109] Thus, in the example where the first and second RRAM bit cells 806-1 and 806-3 are accessed for reading, the respective logical states of RRAM bit cells 806-1 and 806-3 can be read simultaneously without causing mutual interference noise, due to the symmetrical polarities of the selector devices. More precisely, if WL 804-1 is connected to ground (i.e., a logical "low") and BLs 802-1 and 802-2 are connected to their respective positive voltages (i.e., a logical "high"), a first current passed from BL 802-1 through selector device 806-1S and resistor 806-1R to WL 804-1 can reflect the logical state of RRAM bit cell 806-1 (i.e.,a resistance state of resistor 806-1R), and simultaneously a second current, which is routed from BL 802-2 through selector device 806-3S and resistor 806-3R to WL 804-2, can reflect the logical state that RRAM bit cell 806-3 possesses (i.e., a resistance state of resistor 806-3R). Since selector devices 806-1S and 806-3S are forward-biased, in some embodiments the first and second currents, respectively, are allowed to flow through them. On the other hand, in some embodiments, an interference current that might have flowed from RRAM bit cells 806-3 to 806-3 can be "blocked" by a high resistance of selector device 806-2S, since selector device 806-2S is backward-biased. Accordingly, the problem of interference noise can be advantageously eliminated.

[0110] In one embodiment, a storage device comprises: a first conductor extending parallel to a first axis; a first selector material comprising a first section extending along a first side wall of the first conductor; a second selector material comprising a first section extending along the first side wall of the first conductor; a first variable resistive material comprising a section extending along the first side wall of the first conductor;and a second conductor extending parallel to a second axis substantially perpendicular to the first axis, wherein the first section of the first selector material, the first section of the second selector material, and the section of the first variable resistive material are arranged along a first direction parallel to a third axis substantially perpendicular to the first and second axes.

[0111] In a further embodiment, a storage device comprises: a first selector material formed on a substrate having a first U-shaped profile; a second selector material formed on the first selector material having a second U-shaped profile; a first conductor extending parallel to a first horizontal axis, the side walls and lower boundary of the first conductor being partially embedded in the second U-shaped profile; a first variable resistive material comprising a section arranged along a first side wall section of the first selector material; a second variable resistive material comprising a section arranged along a second side wall section of the first selector material; and a second conductor arranged along the section of the first variable resistive material extending parallel to a vertical axis.and a third conductor arranged along the section of the second variable resistive material, which also extends parallel to the vertical axis.

[0112] In a further embodiment, a storage device comprises: a first conductor extending parallel to a first axis; a first selector material partially surrounding the first conductor; a second selector material partially surrounding the first selector material; a first variable resistive material comprising a section extending along the respective first sidewall sections of the first and second selector materials; a second variable resistive material comprising a section extending along the respective second sidewall sections of the first and second selector materials; a second conductor extending parallel to a second axis substantially perpendicular to the first axis;and a third conductor, which also extends parallel to the second axis, wherein the first and second sidewall sections of the first selector material, the first and second sections of the second selector material, and the sections of the first and second variable resistive materials above the first conductor are each mirror-symmetric.

Claims

[1] Storage device comprising the following: a first conductor (228, 802-1) which extends substantially along a first axis (Y); a first selector material (224-1) comprising a U-shaped profile with a first section (224-1S1) extending along a first side wall of the first conductor (228); a second selector material (224-2) comprising a U-shaped profile with a first section (224-2S1) extending along the first side wall of the first conductor (228), wherein the U-shaped profile of the second selector material (224-2) partially surrounds the first conductor (228) and the U-shaped profile of the first selector material (224-1) partially surrounds the second selector material (224-2); a first variable resistive material (210) comprising a section extending along the first side wall of the first conductor (228); and a second conductor (220-1, 804-1) extending parallel to a second axis (Z) substantially perpendicular to the first axis (Y), wherein the first section (224-1S1) of the first selector material (224-1), the first section (224-2S1) of the second selector material (224-2) and the section of the first variable resistive material (210) are stacked along a first direction parallel to a third axis (X) that is substantially perpendicular to the first axis (Y) and the second axis (Z). [2] Storage device according to claim 1, wherein at least the first section (224-1S1) of the first selector material (224-1) and the first section (224-2S1) of the second selector material (224-2) form a selector device of a first RRAM bit cell (241-1, 8061) and at least the section of the first variable resistive material (210) forms a resistor (806-7R) of the first RRAM bit cell (241-1) which is connected in series with the selector device (806-7S) of the first RRAM bit cell (241-1, 806-1). [3] Storage device according to claim 2, wherein the first conductor (228) forms a bit line of the first RRAM bit cell (241-1, 806-1) and the second conductor (220-1) forms a word line of the first RRAM bit cell (241-1, 806-1). [4] Storage device according to one of the preceding claims, wherein the first selector material (224-1) further comprises a second section (224-1S2) extending along a second side wall of the first conductor (228), and the second selector material (224-2) further comprises a second section (224-2S2) extending along the second side wall of the first conductor (228). [5] Storage device according to claim 4, further comprising: a second variable resistive material (210) comprising a section extending along the second side wall of the first conductor (228); and a third conductor (220-2) extending parallel to the second axis (Z), wherein the second section (224-1S2) of the first selector material (224-1), the second section (224-2S2) of the second selector material (224-2) and the section of the second variable resistive material (210) are arranged along a second direction that runs parallel to the third axis (X). [6] Storage device according to claim 5, wherein at least the second section (224-1S2) of the first selector material (224-1) and the second section (224-2S2) of the second selector material (224-2) form a selector device (806-8S) of a second RRAM bit cell (241-2, 806-2) and at least the section of the second variable resistive material (210) forms a resistor (806-8R) of the second RRAM bit cell (241-2, 806-2) which is connected in series with the selector device (806-8S) of the second RRAM bit cell (241-2, 806-2). [7] Storage device according to claim 6, wherein the first conductor (228, 802-1) forms a bit line of the second RRAM bit cell (241-2, 806-2) and the third conductor (220-2) forms a word line of the second RRAM bit cell (241-2, 806-2). [8] Storage device according to any one of the preceding claims 5 to 7, wherein the first section (241-1S1) and the second section (241-1S2) of the first selector material (241-1), the first section (241-2S1) and the second section (241-2S2) of the second selector material (241-2) and the sections of the first resistive material (210) and the second variable resistive material (210) are each mirror-symmetric about the first conductor (228). [9] Storage device according to one of the preceding claims, wherein the first conductor (228) is partially embedded in the first selector material (224-1). [10] Storage device comprising the following: a first selector material (224-1) formed on a substrate (202) and having a first U-shaped profile; a second selector material (224-2) formed on the first selector material (224-1) and having a second U-shaped profile; a first conductor (228, 802-1) extending parallel to a first horizontal axis (Y), wherein the second U-shaped profile surrounds side walls and a bottom surface of the first conductor (228, 802-1), the first U-shaped profile partially surrounding the second U-shaped profile; a first variable resistive material (210) comprising a section arranged along a first sidewall section (224-1S1) of the first selector material (224-1); a second variable resistive material (210) comprising a section arranged along a second sidewall section (224-1S1) of the first selector material (224-1); a second conductor (220-1, 804-1) arranged along the section of the first variable resistive material (210) extending parallel to a vertical axis (Z); and a third conductor (220-2, 804-2) arranged along the section of the second variable resistive material (210) which also extends parallel to the vertical axis (Z). [11] Storage device according to claim 10, wherein a first side wall section (224-2S1) of the second selector material (224-2), the first side wall section (224-1S1) of the first selector material (224-1) and the section of the first variable resistive material (210) are arranged parallel to a second horizontal axis (X) which is substantially perpendicular to the first horizontal axis (Y), and a second side wall section (224-2S2) of the second selector material (224-2), the second side wall section (224-1S2) of the first selector material (224-1) and the section of the second variable resistive material (210) are arranged parallel to the second horizontal axis (X). [12] Storage device according to claim 11, wherein at least the first side wall section (224-1S1) of the first selector material (224-1) and the first side wall section (224-2S1) of the second selector material (224-2) form a selector device (806-7S) of a first RRAM bit cell (241-1, 806-1) and at least the section of the first variable resistive material (210) forms a resistor (806-7R) of the first RRAM bit cell (241-1, 806-1). [13] Storage device according to claim 12, wherein the first conductor (228, 802-1) forms a bit line of the first RRAM bit cell (241-1, 806-1) and the second conductor (220-1, 804-1) forms a word line of the first RRAM bit cell (241-1, 806-1). [14] Storage device according to any one of the preceding claims 11 to 13, wherein at least the second side wall section (224-1S2) of the first selector material (224-1) and the second side wall section (224-2S2) of the second selector material (224-2) form a selector device (806-8S) of a second RRAM bit cell (241-2, 806-2) and at least the section of the second variable resistive material (210) forms a resistor (806-8R) of the second RRAM bit cell (241-2, 806-2). [15] Storage device according to claim 14, wherein the first conductor (228, 802-1) forms a bit line of the second RRAM bit cell (241-2, 806-1) and the third conductor (220-2, 804-2) forms a word line of the second RRAM bit cell (241-2, 806-2). [16] Storage device according to any one of the preceding claims 10 to 15, wherein the first variable resistive material (210) and the second variable resistive material (210) each have a variable resistance value. [17] Storage device comprising the following: a first conductor (228, 802-1) extending parallel to a first axis (Y); a selector material (224-1) with a U-shaped profile that partially surrounds the first conductor (228, 802-1); another selector material (224-2) with a U-shaped profile that partially surrounds the selector material (224-1); a first variable resistive material (210) comprising a section extending along a respective first sidewall section (224-1S1, 224-2S1) of the selector material (224-1) and the further selector material (224-2); a second variable resistive material (210) comprising a section extending along a respective second sidewall section (224-1S2, 224-2S2) of the selector material (224-1) and the further selector material (224-2); a second conductor (220-1, 804-1) extending parallel to a second axis (Z) substantially perpendicular to the first axis (Y); and a third conductor (220-2, 804-2), which also extends parallel to the second axis (Z), wherein the first and second sidewall sections (224-1S1, 224-1S2) of the selector material (224-1), the first and second sections (224-2S1, 224-2S2) of the further selector material (224-2) and the sections of the first and second variable resistive materials (210) via the first conductor (228, 802-1) are each mirror-symmetric. [18] Storage device according to claim 17, wherein at least the first side wall section (224-1S1) of the selector material (224-1) and the first side wall section (224-2S1) of the further selector material (224-2) form a selector device (806-7S) of a first RRAM bit cell (241-1, 806-1) and at least the section of the first variable resistive material (210) forms a resistor of the first RRAM bit cell (241-1, 806-1). [19] Storage device according to claim 18, wherein at least the second side wall section (224-1S2) of the selector material (224-1) and the second side wall section (224-2S2) of the further selector material (224-2) form a selector device (806-8S) of a second RRAM bit cell (241-2, 806-2) and at least the section of the second variable resistive material (210) forms a resistor (806-8R) of the second RRAM bit cell (241-2, 806-2). [20] Storage device according to claim 19, wherein the first conductor (228, 802-1) is configured to serve as a bit line for the first RRAM bit cell (241-1, 806-1) and the second RRAM bit cell (241-2, 806-2), and the second conductor (220-1, 804-1) and the third conductor (220-2, 804-2) are configured to serve as word lines for the first RRAM bit cell (241-1, 806-1) and the second RRAM bit cell (241-2, 806-2).

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