HIGH-PERFORMANCE MOSFET

Abstract

Semiconductor design, which includes the following: a fin (805) on a substrate (200), a vertical structure (810) on the substrate (200), wherein the vertical structure (810) comprises the following: a first part with alternating first and second nanosheet layers (505, 510) and a second part with the second nanosheet layers, wherein the second nanosheet layers extend from the first part through the second part, and a gate structure on a part of the fin (805) and the second part of the first vertical structure (810), wherein the gate structure surrounds the second nanosheet layers of the second part of the first vertical structure (810) and a top and side part of the fin (805).

Description

GENERAL STATE OF THE ART

[0001] Integrated circuits (ICs) used in mobile applications (e.g., mobile computing, smartphones, tablets, smart devices (smart gear), etc.) can have strict power and performance requirements. P- and N-type field-effect transistors (FETs) are expected to have balanced switching performance (e.g., similar ON and OFF switching characteristics) in the logic and SRAM (Static Access Memory) regions of the chip. However, due to FET scaling, P- and N-FETs can develop a performance discrepancy. For example, NFETs can become "faster" than PFETs due to different materials used in their manufacturing, different lattice alignments, or different conventional stress conditions acting on their respective channel regions. US 2016 / 0 104 765 A1, US 2018 / 0 151 677 A1 and US 2015 / 0 370 949 A1 describe conventional semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Aspects of the present disclosure can best be understood by studying the following detailed description in conjunction with the accompanying figures. It should be noted that, consistent with industry practice, various structural elements are not drawn to scale. Rather, the dimensions of the various structural elements may be exaggerated or decreased for purposes of illustration. Fig. 1 is a flow diagram for a method of fabricating a gate-all-around nanosheet FET according to some embodiments. The Fig. 2 to 13 are isometric views of a gate-all-around nanosheet FET structure at various stages of fabrication according to some embodiments. Fig. 14 is a cross-sectional view of a gate-all-around nanosheet FET according to some embodiments. Fig. 15 is a cross-sectional view of two gate-all-around nanosheet FETs with different nanosheet layer widths according to some embodiments. Fig. 16 is a cross-sectional view of a hybrid structure including a gate-all-around nanosheet FET and a FinFET, according to some embodiments. Fig. 17 is an isometric view of a gate-all-around nanosheet FET with a fewer number of nanosheet layers according to some embodiments. Fig. 18 is a cross-sectional view of two gate-all-around nanosheet FETs with different numbers of nanosheet layers according to some embodiments. DETAILED DESCRIPTION

[0003] The following disclosure provides many different embodiments or examples of implementing various features of the subject matter. Certain example components and arrangements are described below to simplify the present disclosure. In the following description, forming a first feature on a second feature may include, for example, embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact.

[0004] Spatially relatable terms such as "beneath," "under," "lower," "above," "above," "above," "upper," and the like may also be used herein for convenience in describing the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. The spatially relatable terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation depicted in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relatable descriptors used herein may also be interpreted accordingly.

[0005] The term "nominal" refers to a nominal or target value for a characteristic or parameter of a component or process sequence, which is defined during the design phase of a product or process, along with a range of values ​​above and / or below the nominal value. This range of values ​​is usually due to slight variations in manufacturing processes or tolerances.

[0006] The term "substantially" here indicates the value for a given quantity, which may vary based on a specific technology node associated with the respective semiconductor device. Based on the specific technology node, the term "substantially" may indicate a value for a given quantity that varies, for example, by no more than ±5%.

[0007] The term "approximately" here indicates the value for a given quantity, which may vary based on a specific technology node associated with the respective semiconductor device. Based on the specific technology node, the term "approximately" may indicate a value for a given quantity that varies, for example, by 10 to 30% (e.g., +10%, ±20%, or ±30%).

[0008] The term “vertical” here nominally means perpendicular to the surface of a substrate.

[0009] The term “insulating layer” here refers to a layer that acts as an electrical insulator (e.g. a dielectric layer).

[0010] Integrated circuits (ICs) used in mobile applications (e.g., mobile computing, smartphones, tablets, smart devices (smart gear), etc.) can have strict power and performance requirements. P- and n-type field-effect transistors (FETs) are expected to have balanced switching performance (e.g., ON and OFF switching characteristics) in the logic and static access memory (SRAM) regions of the chip. However, due to FET scaling, p-FETs (PFETs) and n-FETs (NFETs) can develop a performance discrepancy. For example, NFETs can become "weaker" than PFETs due to (i) different materials used in their manufacturing processes, (ii) different lattice alignments, (iii) different conventional stress conditions applied to the FET channel region, or a combination thereof.In addition, dual- or tri-gate FinFETs can suffer from short-channel effects if the gate electrode loses control over the channel region. For example, aggressive scaling in dual- or tri-gate FinFETs can lead to a DIBL (drain-induced barrier lowering) effect, e.g., loss of gate control over the channel due to the drain voltage.

[0011] The embodiments described herein relate to a manufacturing method and structures that provide various types of gate-all-around nanosheet FETs (GAA nanosheet FETs) with tunable / adjustable performance. For example, both n- and p-type tunable GAA nanosheet FETs—also referred to herein as "NSFs" (nanosheet FETs)—can be formed from multilayer nanosheet stacks that alternate pairs of first and second nanosheet layers. The first and second nanosheet layers in the multilayer nanosheet stacks can include, for example, epitaxially grown silicon germanium (SiGe) and silicon (Si) nanosheet layers, respectively. In some embodiments, the n-type NSFs have a channel region with Si nanosheet layers, and the p-type NSFs have a channel region with SiGe nanosheet layers.For each NSF, the dimensions and number of nanosheet layers can be controlled during the initial stages of the NSF fabrication process to produce different types of GAA nanosheet FETs. The dimensions and number of nanosheet layers can also be used to precisely tune the electrical performance of the resulting GAA nanosheet FETs. For example, the resulting GAA nanosheet FETs can exhibit better gate control (e.g., low DIBL) as well as tunable forward current and power consumption. Furthermore, by using the embodiments described here, hybrid devices comprising FinFETs and GAA nanosheet FETs of other types can be formed on the same substrate.

[0012] Fig. 1 is a flow diagram for a manufacturing method 100 according to some embodiments. The manufacturing method 100 describes the formation of GAA nanosheet FETs according to some embodiments. Between the various operations of the method 100, other manufacturing steps may be performed, which may be omitted for clarity only. It is understood that additional operations may be performed. Moreover, not all operations may be required to practice the disclosure provided herein. In addition, some operations may be performed concurrently or in a different order than in Fig. 1. In some embodiments, one or more further steps may be performed in addition to or instead of the steps described herein. The manufacturing method 100 is described for illustrative purposes with reference to the steps shown in the Fig. 2 to 18 are described.

[0013] The method 100 begins with operation 105 and the formation of a multilayer nanosheet stack on a substrate. According to some embodiments, the multilayer nanosheet stack comprises alternating pairs of a first and a second nanosheet layer grown vertically on top of one another. Fig. 2 through 8 are isometric views of partially fabricated structures that can be used to describe the manufacturing stages of operation 105. Fig. For example, FIG. 2 is an isometric view of a portion of a substrate 200 according to some embodiments. The substrate 200 may be a bulk semiconductor wafer or the top semiconductor layer of a semiconductor-on-insulator (SOI) wafer (not shown), such as silicon on insulator. The substrate 200 may further include crystalline silicon, with its top surface 200t parallel to the crystal plane (100) (e.g., xy plane).In some embodiments, the substrate 200 may include another elemental semiconductor such as (i) germanium (Ge), (ii) a compound semiconductor including silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb), (iii) an alloy semiconductor including silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP), or (iv) combinations thereof.

[0014] The substrate 200 in method 100 is described as an example in the context of crystalline silicon, whose upper surface 200t is parallel to the crystal plane (100). Based on the disclosure presented herein, other materials may also be used, as explained above. These materials fall within the spirit and scope of this disclosure.

[0015] In some embodiments, the fabrication of the multilayer nanosheet stack begins with the deposition and patterning of a hard mask layer 300 on the substrate 200, as shown in Fig. 3. Consequently, selected areas of the substrate 200, such as those shown in Fig. 3, the upper surface 200t of the substrate 200 may be exposed. The upper surface 200t of the substrate 200 runs parallel to the crystal plane (100) (e.g., xy plane), as explained above. The hard mask layer 300 may contain, for example, silicon nitride (Si3N4, hereinafter "SiN"), silicon carbon nitride (SiCN), silicon oxide (SiO2), any other suitable material, or any combination thereof. The hard mask layer 300 may be patterned such that the upper surface 200t of the substrate 200 may be exposed at multiple locations. In a subsequent anisotropic dry etching process, the exposed substrate 200 may be etched such that, as shown in Fig. 4, one or more recessed regions 400 may be formed. The depth (e.g., in the z-direction) of the recessed region 400 may be influenced via the dry etching process. In some embodiments, more than one recessed region such as the recessed region 400 may be formed in the substrate 200 according to the patterning design of the hard mask layer 300. The recessed region 400 has a lower horizontal surface 405 and one or more vertical surfaces 410 (e.g., vertical sidewalls). According to some embodiments, the horizontal surface 405 runs parallel to the crystal plane. <100> (e.g. xy-plane), and vertical surfaces 410 run parallel to the crystal plane <110> (e.g., yz-plane). The area of ​​the recessed region 400 (e.g., the area of ​​the horizontal surface 405) may be approximately 500 × 0.1 µm 2(e.g., x- or y-direction), with a depth in the vertical z-direction being between about 100 nm and about 200 nm. However, the above dimensions are not limiting, and the recessed area 400 may be smaller or larger than these.

[0016] Next, to form a multilayer nanosheet stack filling the recessed region 400, alternating pairs of a first and a second nanosheet layer may be grown in the recessed region 400. In some embodiments, the first and second nanosheet layers may be epitaxially grown in the recessed region 400 using the exposed horizontal surfaces 405 (e.g., xy-plane) as a seed surface. Exposed horizontal surfaces 405, as explained above, are parallel to the top surface of the substrate 200 and therefore have the same crystal orientation (e.g., parallel to the crystal plane (100), xy-plane). Consequently, the epitaxial layers formed on exposed horizontal surfaces 405 have the same crystal orientation as if they were deposited on the (in Fig. 2) of the substrate 200. Nanosheet layers may not be able to grow on areas of the substrate 200 that are covered with the hard mask layer 300. Therefore, in some embodiments, the growth of nanosheet layers is limited to the exposed surfaces of recessed areas 400. In some embodiments, the vertical surfaces 410 of the recessed area 400 may be covered with a hard mask layer to prevent the growth of a nanosheet layer. In some embodiments, the epitaxial growth of nanosheet layers preferably occurs on the crystal plane (100) (e.g., the exposed horizontal surface 405) rather than the crystal plane <110> (e.g. the vertical surfaces 410).

[0017] In some embodiments, the first and second nanosheet layers contain SiGe and Si, respectively. Alternatively, first nanosheet layers may contain III-V compound semiconductors such as GaAs, InP, GaP, GaN, etc. The multilayer nanosheet stack in method 100 will now be described, as an example, in the context of alternating SiGe and Si nanosheet epitaxial layers. Based on the disclosure presented herein, other materials may also be used, as explained above. These materials fall within the spirit and scope of this disclosure.

[0018] Precursor gases that can be used to grow the SiGe and Si nanosheet layers include, but are not limited to, monosilane (SiH4), disilane (Si2H6), monogermane (GeH4), digermane (Ge2H6), dichlorosilane (SiH2Cl2), any other suitable gas, or combinations thereof. According to some embodiments, Fig. 5 is an isometric view of substrate 200 after forming the multilayer nanosheet stack 500 in the recessed region 400. The multilayer nanosheet stack 500 may include, among other things, alternating pairs of a SiGe nanosheet layer 505 (bottom layer) and a Si nanosheet layer 510 (top layer). SiGe nanosheet layers 505 may contain from about 10% to about 50% Ge (e.g., 15%, 20%, 30%, 40%, etc.). The presence of Ge in SiGe nanosheet layers increases the residual stress in the SiGe nanosheet layers and improves hole mobility for p-type NSF. A Ge concentration below 10% can provide limited improvement in hole mobility, and a Ge concentration above 50% can lead to stacking faults and defects in the SiGe nanosheet layers. Defects in SiGe nanosheet stacks can adversely affect the performance of p-type NSFs because they can increase channel resistance.In some embodiments, as in . Fig. 5, the upper layer of the multilayer nanosheet stack is a Si nanosheet layer 510 and the lower layer is a SiGe nanosheet layer 505.

[0019] In some embodiments, the thickness of the Si nanosheet layers 510 can influence the distance (or gap) between each two SiGe nanosheet layers 505, and similarly, the thickness of the SiGe nanosheet layers 505 can influence the distance (or gap) between two Si nanosheet layers 510. The thickness 510t of the Si nanosheet layer 510 in Fig. 6, which is an enlarged view of section 515 in Fig. 5, can be used, for example, to define the spacing 505p for the SiGe nanosheet layers 505. At this manufacturing stage, the spacing of nanosheet layers of similar types is defined. Furthermore, each of the nanosheet layers (e.g., SiGe or Si) may have the same or a different thickness. In some embodiments, the thickness of each SiGe nanosheet layer 505 and Si nanosheet layer 510 may be about 5 nm to about 20 nm (e.g., 5 nm to 10 nm, 10 nm to 15 nm, 5 nm to 15 nm, 10 nm to 20 nm, etc.). Since the SiGe and Si nanosheet layers are grown individually, the SiGe nanosheet layers 505 and the Si nanosheet layers 510 may have the same or different thicknesses. Furthermore, the SiGe nanosheet layers may have the same or different thicknesses, and the Si nanosheet layers may equally have the same or different thicknesses.

[0020] In some embodiments, the multilayer nanosheet stack 500 may comprise a total of up to about 10 to 12 nanosheet layers (e.g., about 5 to 6 pairs of SiGe / Si nanosheet layers). However, more or fewer nanosheet layers are possible depending on the design of the resulting NSF. In some embodiments, the depth of the Fig. 4 can be adjusted to accommodate a greater or fewer number of SiGe and Si nanosheet layers. In some embodiments, the height (in the vertical z-direction) of the multilayer nanosheet stack 500 can be between about 100 nm and about 200 nm (e.g., between 100 nm and 150 nm, 140 nm and 180 nm, 160 nm and 200 nm, etc.). The height of the multilayer nanosheet stack 500 can further correspond to the depth of the recessed region 400 such that the top surface of the multilayer nanosheet stack is substantially coplanar with a top surface of the non-recessed regions of the substrate 200. However, this is not a limitation, and fewer or taller multilayer nanosheet stacks 500 are possible. Furthermore, the above-mentioned thicknesses for each nanosheet layer and each multilayer nanosheet stack do not represent a limitation.

[0021] After forming the multilayer nanosheet stack 500, the (in Fig. 5 not shown) hard mask layer 300 is removed (e.g., by wet cleaning). Subsequently, as shown in Fig. As shown in Figure 5, an oxide 520 and a cap layer 525 are grown on the non-recessed areas of the substrate 200 and the multilayer nanosheet stack 500. In some embodiments, the oxide 520 includes a SiO2 layer, and the cap layer 525 includes a nitride layer such as SiN.

[0022] The procedure 100 from Fig. 1 continues with step 110 and the formation of vertical structures by selectively removing parts of the Fig. 5 shown multilayer nanosheet stack 500. In Fig. 7, for example, a photoresist layer can be spun onto the cover layer 525 and then patterned to form patterned photoresist structures 700. In some embodiments, the photoresist structures 700 are as shown in Fig. 7 shown on the y-axis or in the direction <110> aligned. Patterned photoresist structures 700 can be used as an etching mask in a subsequent etching process. During the etching process, parts of the multilayer nanosheet stack 500 that are not masked with the patterned photoresist structures 700 are removed, so that vertical structures with multilayer nanosheet stacks are created that are aligned along the y-axis or the direction <110> In some designs, the vertical structures are deliberately aligned in the direction <110> aligned so that the channel regions of the resulting nanosheet FETs are directed towards <110> This means that the current flow in the resulting NSF is directed <110> A current flow in the direction <110> is beneficial to electron mobility in the NFET.

[0023] Photoresist structures 700 on the substrate 200 can also be used to form fins made of the substrate material. The single-material fins (hereinafter "fins") can be used to form dual- or tri-gate FinFETs on the substrate 200.

[0024] Accordingly, the width 700w of the patterned photoresist structures 700 can determine the width of the vertical structures, which subsequently determine the width of the channel region in the nanosheet FET. According to some embodiments, the width of the channel region in a FET can determine the amount of current flowing through the channel region. For example, a wide channel region can carry a higher current density than a narrow channel region. However, a narrow channel region can enable better gate control than a wide channel region. Therefore, the width of each vertical structure with a multilayer nanosheet stack can be adjusted to balance current density and gate control over the channel region. Furthermore, by influencing the width 700w of each patterned photoresist structure 700, vertical structures of different widths can be formed on the substrate 200.In other words, nanosheet FETs with different nanosheet layer widths can be built at any location on the substrate.

[0025] Fig. 8 shows the structures resulting from the etching process described above, e.g., the fin 805 and the vertical structure 810 with the multilayer nanosheet stack 500. The fin 805 is made of substrate material as explained above, e.g., Si or another elemental semiconductor such as (i) Ge, (ii) a compound semiconductor including silicon carbide, GaAs, GaP, InP, InAs and / or InSb, (iii) an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP, or (iv) combinations thereof.

[0026] In some embodiments, the width 805w of the fin 805 is in a range of about 4 nm to about 15 nm (e.g., from 4 nm to 10 nm, 8 nm to 12 nm, 10 nm to 15 nm, etc.), and the width 810w of the vertical structure 810 with the multilayer nanosheet stack 500 is in a range of about 4 nm to about 50 nm (e.g., from 4 nm to 10 nm, 8 nm to 15 nm, 10 nm to 25 nm, 15 nm to 30 nm, 20 nm to 50 nm, etc.). Consequently, the vertical structure 810 with the multilayer nanosheet stack 500 can be formed wider than the fin 805.

[0027] The configuration from Fig. 8 is described here as a “hybrid” conference iguration in which vertical structures with multilayer nanosheet stacks are formed simultaneously with fins on the substrate 200. According to some embodiments, nanosheet FETs are formed on the multilayer vertical nanosheet structure 810, and FinFETs are formed on the fins 805. As explained above, various arrangements of fins 805 and vertical structures 810 are possible on the substrate 200, such as a matrix of multilayer vertical nanosheet structures 805, a matrix of Si fins 805, or combinations thereof. Consequently, combinations of nanosheet FETs and FinFETs are possible on the substrate 200.

[0028] Furthermore, multilayer vertical nanosheet structures 810 can be formed in various widths 810w. Therefore, the formation of nanosheet FETs in a range of nanosheet widths (e.g., channel widths) on the substrate 200 is possible.

[0029] In some embodiments, the height 805h of fin 805 is the same as or different from the height 810h of vertical structure 810. For example, 805h may be higher or lower than 810h. In some embodiments, 810h may range from about 100 nm to about 200 nm (e.g., 100 nm to 150 nm, 140 nm to 180 nm, 160 nm to 200 nm, etc.).

[0030] The procedure 100 from Fig. 1 proceeds with operation 115 and the formation of a sacrificial gate structure on the vertical structures 810 with the multilayer nanosheet stack 500. In some embodiments, sacrificial gate structures may also be formed on the fins 805 simultaneously according to operation 115. Operation 115 will now be described as an example of sacrificial gate structures formed on vertical structures 810 with multilayer nanosheet stacks 500. Based on the disclosure provided herein, operation 115 may be used, as explained above, to form sacrificial gate structures on fins 805 and vertical structures 810 with multilayer nanosheet stacks 500.

[0031] Fig. 9 is an isometric view of a sacrificial gate structure 900 formed on two vertical structures 810, each containing a multilayer nanosheet stack. The sacrificial gate structure 900 is formed along the x-axis (e.g., perpendicular to the length of the vertical structures 810). In some embodiments, Fig. 9 compared to Fig. 8 in a later “production stage”, and therefore Fig. 9 additional structural elements such as a liner 905, an insulating layer 910, gate spacers 915, a cap layer 920 and an oxide layer 925.

[0032] In some embodiments, the sacrificial gate layer 900 includes a sacrificial gate electrode 930 and a sacrificial gate dielectric 935. The sacrificial gate dielectric 935 is deposited, for example, prior to the sacrificial gate electrode 930 and is disposed between the vertical structures 810 and the sacrificial gate electrode 930, among other things. According to some embodiments, the sacrificial gate dielectric 935 includes SiO2 or silicon oxynitride (SiON) and may be replaced with a high-k dielectric in a subsequent gate structure replacement step. The sacrificial gate electrode 930 may further include polycrystalline silicon (polysilicon) and may be replaced with a gate metal electrode stack in a subsequent gate structure replacement step.The gate sacrificial dielectric 935 and the gate sacrificial electrode 930 may, for example, be deposited as blanket layers and patterned by photolithography and etching steps such that the gate sacrificial structure 900 is formed on the multilayer vertical structures 810 and the insulating layer 910.

[0033] It should be noted that additional gate structures (such as the sacrificial gate structure 900) may be formed parallel to the sacrificial gate structure 900 and perpendicular to a projection of the vertical structures 810 along the y-axis. Therefore, Fig. 9 additional gate sacrificial structures 900 which run parallel to each other on vertical structures 810.

[0034] In some embodiments, the insulating layer 910 may be an isolation structure such as a shallow trench isolation (STI) including SiO2, SiN, SiON, fluorine-doped silicate glass (FSG), a low-k dielectric material (e.g., with a k value below about 3.9), and / or another suitable dielectric material with appropriate fill properties. The liner 905 may be a nitride such as SiN.

[0035] The gate spacers 915 (or spacers 915) may serve as alignment masks during an ion implantation operation for forming the source-drain junctions on the vertical structures 810. The spacers 915 may, for example, be deposited as a blanket overlay, which may be etched using an etch-back process to form spacers 915 on the sidewalls of the sacrificial gate structure 900. In some embodiments, the etch-back process is an anisotropic etch, in which the spacer material is removed faster on horizontal surfaces (e.g., in the xy plane) than on vertical surfaces (e.g., in the yz or xz plane). Because the spacer material is blanket deposited, it may coat the exposed surfaces of the vertical structures 810. In a sidewall recession process, the spacer material may be removed from the sidewall surfaces of the vertical structure.

[0036] In some embodiments, spacers 915 may include a dielectric material such as SiO2, SiON, SiCN, silicon oxycarbide (SiOC), or SiN. In some embodiments, the thickness of spacers 915 may range from about 2 nm to about 5 nm. Spacers 915 may be a stack of one or more layers containing the same or different materials. According to some embodiments, spacers 915 are not removed during the gate metal removal process and may serve as structural elements for the gate metal structure replacing sacrificial gate structure 900.

[0037] In Fig. 10, a source / drain (S / D) epitaxial stack 1000 may be grown on each of the vertical structures 810 as well as adjacent to the sacrificial gate structure 900. In some embodiments, the epitaxial stacks 1000 may be boron-doped SiGe stacks suitable for p-type NSFs or phosphorus-doped Si layers suitable for n-type NSFs. Epitaxial stacks 1000 are described, as an example, in the context of phosphorus (P)-doped Si layers for n-type NSFs. Based on the disclosure presented herein, boron (B)-doped silicon (SiGe) stacks may also be grown for p-type NSFs. These S / D epitaxial stacks fall within the spirit and scope of this disclosure. Since n- and p-NSFs can be formed on a single substrate, B-doped SiGe stacks and P-doped Si layers can be grown on the substrate 200 to desired vertical structures 810.

[0038] In some embodiments, p-doped (n-) Si S / D layers can be epitaxially grown using a silane precursor (SiH4 precursor). During the growth process, a phosphorus-containing dopant can be introduced into the epitaxially grown Si layer. In some embodiments, the phosphorus concentration can be in the range of about 10 21 atoms / cm 3 up to about 8×10 21 atoms / cm 3 It should be noted that the above-mentioned dopant concentration ranges are not limiting, and other dopant concentration ranges are within the spirit and scope of this disclosure.

[0039] In some embodiments, a B-doped (p-) SiGe-S / D may be an epitaxial stack comprising two or more (in Fig. 10 (not shown) may contain successively grown epitaxial layers and may have a different mole fraction of germanium (Ge) and different B dopant concentrations. The first layer may, for example, have, among other things, a mole fraction of Ge in the range of 0 to about 40% and a B dopant concentration in the range of about 5×10 19 atoms / cm 3 up to about 1×10 21 atoms / cm 3 The second epitaxial layer may, for example, have, among other things, a mole fraction of Ge in the range of about 20% to about 80% and a B dopant concentration in the range of about 3×10 20 atoms / cm 3 up to about 5×10 21 atoms / cm 3Finally, the third epitaxial layer can be a capping layer that can have a similar mole fraction of Ge and similar B dopant concentrations as the first layer (e.g. 0 to about 40% Ge and about 5×10 19 atoms / cm 3 up to about 1×10 21 atoms / cm 3 B dopant). The thickness of these layers can vary depending on the performance requirements of the device. For example, the first epitaxial layer can have a thickness in the range of about 10 nm to about 20 nm, the second epitaxial layer can have a thickness in the range of about 30 nm to about 60 nm, and the third epitaxial layer (cap layer) can have a thickness in the range of 0 to about 10 nm. It should be noted that the above-mentioned thicknesses and dopant concentrations are not limiting, and other thicknesses and dopant concentrations are within the spirit and scope of this disclosure.

[0040] After forming the epitaxial stack, a nitride protection layer 1005 may be deposited on the epitaxial stacks 1000, the insulating layer 910, and the spacers 915. In some embodiments, the thickness of the nitride protection layer 1005 may range from about 3 nm to about 5 nm. The nitride protection layer 1005 may be deposited, for example, via a conformal deposition process such as atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), or any other suitable deposition method, among others. The nitride protection layer 1005 may be deposited, for example, via an ALD process at about 500°C. According to some embodiments, the nitride protection layer 1005 may be used for a subsequent etching process in forming (in Fig. 10 not shown) contact openings on the S / D epitaxial stacks 1000 serve as an etch stop layer (ESL).

[0041] The procedure 100 from Fig. 1 and Fig. 10 continues with operation 120 and the formation of an insulation layer 1010 on the vertical structures 810 such that it surrounds the sacrificial gate structure 900. According to some embodiments, the insulation layer 1010 is an interlayer dielectric (ILD) comprising SiO2, SiOC, SiON, silicon oxycarbon nitride (SiOCN), or SiCN, which may be deposited via CVD, physical vapor deposition (PVD), a thermal growth process, or any other suitable deposition technique. In some embodiments, the deposited insulation layer 1010 may be located on the sacrificial gate structures 900. In a chemical mechanical polishing (CMP) process, the insulation material may be polished down from the top of the sacrificial gate structures 900 (e.g.,removed and planarized) such that the upper surface of the insulation layer 1010 and the upper surface of the sacrificial gate structure 900 are substantially coplanar. According to some embodiments, FIG. Fig. 10 shows the insulation layer 1010 after the above-mentioned CMP process. It should be noted that the insulation layer 1010 may extend between adjacent gate sacrificial structures 900 and provide electrical isolation of the structural elements it surrounds, such as the gate sacrificial structure 900, the S / D epitaxial stack 1000, and the S / D metal contacts formed adjacent to the gate structures. In some embodiments, an optional cap layer or hard mask layer (in Fig. 10 not shown) may be grown on the insulating layer 1010, which protects the insulating layer 1010 from being etched during a gate replacement process (e.g., during etching of the sacrificial gate dielectric 935).

[0042] At step 125 in Fig. 1 can the (in Fig. 10) gate sacrificial structure 900 for forming a Fig. 11 may be removed. In some embodiments, operation 120 may comprise a double wet etch process in which the sacrificial gate electrode 930 and the sacrificial gate dielectric 935 are removed sequentially. The sacrificial gate structure 900 may be removed, for example, via a first wet etch process designed to be selective to the polysilicon material of the sacrificial gate electrode 930. The selectivity of the first wet etch chemical may, for example, be higher than about 1000:1 (e.g., 10000:1), such that the gate spacers 915, the sacrificial gate dielectric 935, and the insulating layer 1010 are not removed in the first wet etch process.It should be noted that the gate sacrificial dielectric 935, since it is disposed between the vertical structures 810 and the gate sacrificial electrode 930, can protect the SiGe / Si nanosheet layers 505 / 510 of the vertical structures 810 from being etched during the first wet etching process. In . Fig. 11, in a subsequent second wet etching process, the sacrificial gate dielectric 935 may be removed without etching the gate spacers 915, the insulation layer 1010, and the vertical structures 810. The second wet etching chemical may, for example, be selective with respect to the sacrificial gate dielectric 935, such that surrounding materials such as the gate spacers 915 and first and second nanosheet layers of the multilayer nanosheet stack and the insulation layer 1010 are not removed. If the second etching chemical can etch the insulation layer 1010, a cap layer or a hard mask may be formed on the insulation layer 1010 after step 120, as already explained, to protect the insulation layer 1010 prior to the second wet etching process.In some embodiments, after operation 125 and removal of the sacrificial gate structure 900, the SiGe and Si nanosheet layers of the vertical structures 810 in the opening 1015 are exposed, while the SiGe and Si nanosheet layers of the vertical structures 810 outside the opening 1015 are overcoated with S / D epitaxial stacks 1000, nitride protection layer 1005, and insulation layer 1010.

[0043] In operation 130 of the method 100, the SiGe nanosheet layers 505 in the opening 1015 may be removed so that n-type NSFs can be formed thereon. In some embodiments, when the S / D epitaxial stacks 1000 are B-doped SiGe stacks (e.g., instead of P-doped Si layers), the Si nanosheet layers in the opening 1015 may be removed instead of the SiGe nanosheet layers 505 to form p-type NSFs. In other words, at operation 130, provided that the appropriate type of S / D epitaxial stack 1000 (e.g., SiGe or P-doped Si) has been grown on the vertical structures 810, either the Si or the SiGe nanosheet layers in the opening 1015 may be removed. Furthermore, at some locations on the substrate 200, Si nanosheet layers 510 may be removed to form n-NSF Si nanosheet layers, while at other locations on the substrate 200, SiGe nanosheet layers 505 may be removed to form p-NSF SiGe nanosheet layers.The n- and p-NSFs can be formed sequentially, for example. The vertical structures 810 intended for p-NSFs can be coated, for example, with a hard mask, a photoresist, or the gate sacrificial structure 900, while SiGe nanosheet layers are removed from the vertical structures 810 intended for n-NSFs.

[0044] As an example, operation 130 will now be described, in which the SiGe nanosheet layers 505 are removed from the vertical structures 810 to form n-type NSF. Based on the disclosure presented herein, the Si nanosheet layers 510 may alternatively be removed to form p-type NSF, as explained above. Therefore, removing Si nanosheet layers 510 in the opening 1015 falls within the spirit and scope of this disclosure.

[0045] The removal of SiGe nanosheet layers 505 in the opening 1015 can be achieved, for example, using a dry etching process that is selective towards SiGe. Halogen-based chemistries, for example, can have an etch selectivity that is high towards Ge and low towards Si. Therefore, halogen gases can etch Ge faster than Si. Furthermore, halogen gases can etch SiGe faster than Si. In some embodiments, the halogen-based chemistries include fluorine- and / or chlorine-based gases. Alternatively, a wet etching chemistry with high selectivity towards SiGe can be used. A wet etching chemistry can include, for example, a mixture of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) (SPM) or a mixture of ammonium hydroxide with H2O2 and water (APM), among others. As a result of operation 130, the Si nanosheet layers 510 in the opening 1015 hang separated between the spacers 915.

[0046] Since the dry or wet etching process of step 130 is designed so that the Si nanosheet layers 510 of the vertical structures 810 (and thus Si material in general) are not etched, the (in Fig. 8) that may have been formed at other locations on the substrate 200 are not affected by the dry or wet etching process.

[0047] In some embodiments, a gate metal structure may be formed on the Fig. 12 shown exposed Si nanosheet layers 510 are formed in the opening 1015. Fig. 12 is an isometric view of the device shown in Fig. 11 shown structure. In Fig. 13, the gate metal structure 1300, which (i) has a (in Fig. 13 not shown) interface layer, (ii) a high-k dielectric (e.g. with a k value of more than 3.9) 1305 and (iii) a gate metal electrode stack 1310, for example in the opening 1015 of Fig. 12 formed. Fig. 13 includes selected portions of a semiconductor structure for illustrative purposes and may include other portions (not shown). For example, the interface layer and the one or more layers of the gate metal electrode stack 1310 may be included.

[0048] In some embodiments, the high-k dielectric 1305 may be hafnium oxide (HfO2), a hafnium silicate-based material, or another suitable dielectric with a k value greater than 3.9—the dielectric constant of stoichiometric SiO2, which is used as a reference. The gate electrode stack 1310 may further include a cap layer on the gate dielectric, one or more metal layers, a work function metal (WFM) stack, and a metal fill layer. The number and type of metal layers in the gate electrode stack may depend on the threshold voltage requirements of the FinFET. Example metal layers in the gate electrode stack may include a bottom tantalum nitride (TaN) layer and one or more titanium nitride (TiN) layers.In some embodiments, titanium / aluminum (Ti / Al) bilayers or a titanium-aluminum (Ti-Al) alloy may be included in the WFM stack. The WFM stack may finely tune the work function of the gate metal electrode stack 1310 and influence the threshold voltage of the resulting FinFET. The thickness and number of the one or more TiN layers, together with the WFM stack, may determine the threshold voltage of the FinFET. In some embodiments, the metal fill layer may include a TiN barrier layer and a tungsten (W) metal stack. The high-k dielectric 1305 and the gate electrode stack 1310 are not limited to the material combinations described above. Therefore, other materials may be used and are within the spirit and scope of this disclosure.

[0049] According to some embodiments, an interface layer is an oxide that naturally forms during the deposition of the high-k dielectric 1305. The interface layer and the high-k dielectric 1305 are deposited directly on the exposed surfaces of the second Si nanosheet layers 510 in the (in Fig. 12). To complete the formation of the n-nanosheet FET or nanosheet NFET, the gate metal electrode stack 1310 can then be deposited on the high-k dielectric 1305 in the opening 1015. Fig. 14 is a cross-sectional view of the vertical structure 810 between the gate spacers 915 along line 1315 in Fig. 13. According to some embodiments, Fig. 14 shows a cross-sectional view of a GAA nanosheet NFET structure with multiple Si nanosheet layers surrounded by at least the high-k dielectric 1305 and the gate metal electrode stack 1310. When the GAA nanosheet NFET is turned on, current flows in the direction of <110> (e.g. along the y-axis) and parallel to the crystal plane (100) (e.g. xy-plane).

[0050] The Si nanosheet layers 510 in the vertical structures 810 are in Fig. 14 with a thickness of 510t and a width of 510w, which essentially corresponds to the width 810w of the Fig. 8 shown vertical structures 810. The width 810w of the Si nanosheet layers 510 can, as already explained, be determined via the width 700w of the Fig. 7. By adjusting the width 700w of the patterned photoresist structures 700, the width 510w of the Si nanosheet layers 510 can be adjusted. Consequently, multilayer vertical structures of different widths can be formed on the substrate 200. According to some embodiments, on the substrate 200, as shown in Fig. 15, for example, vertical structures 810 of different widths 510w1 and 510w2 are formed. In the example of Fig. 15, 510w1 is larger than 510w2. The nanosheet FETs built on the vertical structures 810 and comprising nanosheet layers (Si or SiGe) of different widths 510w1 and 510w2 may exhibit different forward current capabilities and DIBL behavior. Therefore, according to some embodiments, it is possible to individually tune the nanosheet FETs in desired areas of the substrate by influencing the width of their nanosheet layers.

[0051] Furthermore, as with Fig. 6, the thickness 510t of the Si nanosheet layers 510 in the Fig. 14 and Fig. 15 during the growth of the Si nanosheet layers. In addition, as with Fig. 6, the distance 510p of the Si nanosheet layers 510 in the Fig. 14 and Fig. 15 by the thickness of the SiGe nanosheet layers 505.

[0052] Based on the above, vertical structures 810 with Si nanosheet layers 510 of different dimensions may be formed on the substrate 200. Similarly, according to some embodiments, vertical structures 810 with SiGe nanosheet layers 505 of different dimensions may be formed on the substrate 200.

[0053] Fig. 16 shows a hybrid structure in which, according to some embodiments, fin 805 is formed adjacent to a vertical structure 810. Accordingly, gate electrode stack 1310 may be shared by the structures forming a nanosheet GAA NFET on vertical structure 810 and an n-type FinFET on fin 805. The width 510w of Si nanosheet layers 510 may, as previously explained, be larger than the width 805w of fin 805. According to some embodiments, the nanosheet GAA NFET formed on vertical structure 810 has better gate control over its channel region compared to the n-type FinFET formed on fin 805. GAA nanosheet NFETs and PFETs may equally be formed adjacent to p-type and n-type FinFETs. Furthermore, certain regions of the substrate 200 may be configured to include exclusively nanosheet GAA NFETs or PFETs, p- and n-FinFETs, or combinations thereof.

[0054] On the gate metal electrode stack 1310 in Fig. 13, a nitride cap layer 1320 may be formed. In some embodiments, this is followed by the formation of source / drain contacts, wherein contacts on (in Fig. 13 not shown) S / D epitaxial stacks 1000 extending vertically through the insulation layer 1010.

[0055] The procedure 100 from Fig. 1 may also include an optional operation 140 in which a portion of the gate metal electrode stack 1310 of the gate metal structure 1300 is removed or recessed such that a maximum of half of the Si nanosheet layers 510 of the vertical structures 810 are removed. In the optional operation 140, among other things, one to three Si nanosheet layers 510 may be removed, for example, to form a nanosheet NFET with six Si nanosheet layers. According to some embodiments, removing (e.g., "cutting") a portion of the gate electrode stack 1310 and a corresponding number of Si nanosheet layers 510 may reduce the power consumption of the GAA nanosheet NFET. The optional operation 140 can be performed selectively on one or more GAA nanosheet NFETs on the substrate 200 to adjust the forward current and power consumption of the GAA nanosheet NFETs.Accordingly, according to some embodiments, operation 140 may be applied to GAA nanosheet PFETs.

[0056] Fig. 17 is, for example, a cross-sectional view of Fig. 13 along the yz-plane after the optional step 140 of the method 100. A portion of the gate metal structure 1300 has been removed, as explained above, or recessed such that a maximum of half of the Si nanosheet layers 510 have been removed from the top of the vertical structure. In some embodiments, the substrate 200 may comprise a plurality of GAA-NSFs with modified gate electrode structures 1300. After the optional step 140, a Fig. 17 not shown nitride layer (e.g. similar to the nitride layer 1320) may be grown on the modified gate metal structure 1300.

[0057] Fig. 18 is a cross-sectional view of a structure according to another embodiment of this disclosure, showing a cross-section of two GAA nanosheet NFETs on different vertical structures 810 and 810'. The vertical structures 810 and 810' each have a different Si nanosheet layer width (e.g., 510w1 and 510w2) and a different number of Si nanosheet layers 510 as a result of operation 140. In the example of Fig.18, 510w1 is wider than 510w2. However, this is not a limitation, and 510w1 may have a width corresponding to 510w2 or be narrower. Furthermore, the thickness of the Si nanosheet layers 510t1 and 510t2 may be the same or different. For example, 510t1 ≥ 510t2 or 510t1 ≤ 510t2. In some embodiments, the GAA nanosheet NFET on the vertical structure 810' may be a low-power NSF with a lower forward current capability than the GAA nanosheet NFET on the vertical structure 810. Furthermore, 810 and 810' may be located in the same area or in different areas on the substrate 200. For example, the vertical structures 810 and 810' may not be adjacent to each other.

[0058] In some embodiments, step 140 of method 100 occurs after replacing sacrificial gate structure 900 and before forming S / D contacts on S / D epitaxial stacks 1000.

[0059] The embodiments described herein relate to a method for forming GAA nanosheet NFETs and PFETs with tunable performance (e.g., tunable forward current and power consumption). In some embodiments, the channel region of a tunable n- and / or p-type NSF may be formed from vertical structures comprising alternating pairs of first and second nanosheet layers stacked one upon another. The GAA nanosheet NFET may comprise, for example, Si nanosheet layers, and the nanosheet GAA PFET may comprise SiGe nanosheet layers, among others. In some embodiments, the number, width, thickness, and spacing of the nanosheet layers in each GAA NSF may be controlled during the initial stages of the fabrication process and used to precisely tune the electrical properties and performance of the resulting GAA NSF.Due to targeted processing, hybrid structures with FinFETs and GAA-NSFs can be formed simultaneously on the same substrate. Furthermore, according to some embodiments, GAA-NSFs with nanosheets of different widths, numbers, thicknesses, and electrical properties can be formed on the same substrate. The resulting GAA-nanosheet FETs can exhibit improved DIBL behavior compared to FinFETs.

[0060] In some embodiments, a semiconductor structure includes a fin and a vertical structure on a substrate. The vertical structure further includes a first portion with alternating first and second nanosheet layers and a second portion with the second nanosheet layers, wherein the second nanosheet layers extend from the first portion through the second portion. The semiconductor structure further includes a gate structure on a portion of the fin and the second portion of the first vertical structure, wherein the gate structure surrounds the second nanosheet layers of the second portion of the first vertical structure and a top and a side portion of the fin.

[0061] In some embodiments, a semiconductor structure comprises a vertical structure on a substrate, the vertical structure comprising a first portion with alternating first and second nanosheet layers and a second portion without the first nanosheet layers and with a different number of second nanosheet layers than the first portion. The semiconductor structure also comprises: a fin on the substrate, a first gate structure surrounding the top, bottom, and side surfaces of each of the second nanosheet layers of the second portion of the vertical structure, and a second gate structure surrounding a portion of the fin, the second gate structure being taller than the first gate structure.

[0062] In some embodiments, the method comprises arranging a first and a second vertical structure on a substrate, wherein the first and second vertical structures are separated by a first dielectric. Furthermore, the first and second vertical structures have different widths and an upper portion above the first insulation layer comprising a multilayer nanosheet stack with alternating first and second nanosheet layers.The method also includes: disposing a sacrificial gate structure on the upper part of the first and second vertical structures and on a part of the first insulating layer, depositing a second insulating layer on the first and second vertical structures and the first insulating layer such that the second insulating layer surrounds a sidewall of the sacrificial gate structure, etching the sacrificial gate structure to expose each multilayer nanosheet stack of the first and second vertical structures, removing the first nanosheet layers from each exposed multilayer nanosheet stack to form pending second nanosheet layers, and forming a gate metal structure to surround the pending second nanosheet layers.

Claims

[1] Semiconductor construction comprising: a fin (805) on a substrate (200), a vertical structure (810) on the substrate (200), the vertical structure (810) comprising: a first part with alternating first and second nanosheet layers (505, 510) and a second part with the second nanosheet layers, wherein the second nanosheet layers extend from the first part through the second part, and a gate structure on a part of the fin (805) and the second part of the first vertical structure (810), the gate structure surrounding the second nanosheet layers of the second part of the first vertical structure (810) and a top and a side part of the fin (805). [2] The semiconductor structure of claim 1, further comprising: a source / drain epitaxial stack (1000) on the first part of the vertical structure (810) and next to the gate structure and another source / drain epitaxial stack (1000) on the fin (805) and next to the gate structure. [3] The semiconductor structure of claim 1 or 2, wherein a width of the vertical structure (810) corresponds to at least a width of the fin (805). [4] The semiconductor structure of claim 3, wherein the width of the vertical structure (810) corresponds to a width of the second nanosheet layers and is in the range of 4 nm to 50 nm. [5] A semiconductor structure according to claim 4, further comprising: a further vertical structure on the substrate (200), the further vertical structure comprising: a first part with alternating first and second nanosheet layers (505, 510) and a second part with the second nanosheet layers of the further vertical structure, wherein a width of the second nanosheet layers of the further vertical structure differs from the width of the second nanosheet layers of the vertical structure (810). [6] A semiconductor structure according to any one of the preceding claims, wherein a spacing of the first nanosheet layers is based on a thickness of the second nanosheet layers and a spacing of the second nanosheet layers is based on a thickness of the first nanosheet layers. [7] A semiconductor structure according to any one of the preceding claims, wherein the first nanosheet layers comprise silicon germanium and the second nanosheet layers comprise silicon. [8] A semiconductor structure according to any one of the preceding claims 1 to 6, wherein the first nanosheet layers comprise silicon and the second nanosheet layers comprise silicon-germanium. [9] A semiconductor structure according to any one of the preceding claims, wherein the first and second nanosheet layers comprise different epitaxially grown materials. [10] Semiconductor structure according to one of the preceding claims, wherein an upper surface of the first and second nanosheet layers (505, 510) is parallel to a crystal plane <100> runs. [11] Semiconductor construction comprising: a vertical structure (810) on a substrate (200), the vertical structure (810) comprising: a first part with alternating first and second nanosheet layers (505, 510) and a second part without the first nanosheet layers and with a different number of second nanosheet layers than the first part, a fin (805) on the substrate (200), a first gate structure surrounding the top, bottom and side surfaces of each of the second nanosheet layers of the second part of the vertical structure (810), and a second gate structure surrounding a portion of the fin (805), the second gate structure being higher than the first gate structure. [12] A semiconductor structure according to claim 11, further comprising: a source / drain epitaxial stack (1000) on the first part of the vertical structure (810) and adjacent to the first gate structure and another source / drain epitaxial stack (1000) on the fin (805) and next to the second gate structure. [13] A semiconductor structure according to claim 11 or 12, further comprising: a further vertical structure (810) on the substrate (200), the further vertical structure (810) comprising: a first part with alternating first and second nanosheet layers (505, 510) and a second part without the first nanosheet layers (505, 510) and with the same number of second nanosheet layers as the first part, and a third gate structure surrounding each of the second nanosheet layers of the second part of the further vertical structure, the third gate structure being higher than the first gate structure. [14] The semiconductor structure of claim 13, wherein a width of the second vertical structure is equal to or different from the width of the first vertical structure. [15] The semiconductor structure of claim 14, wherein the width of the first and second vertical structures determines the respective width of the first and second nanosheet layers (505, 510). [16] Semiconductor structure according to one of the preceding claims 13 to 15, wherein the second part of the vertical structure has fewer second nanosheet layers than the second part of the further vertical structure. [17] A semiconductor structure according to any one of the preceding claims 11 to 16, wherein the first nanosheet layers comprise silicon and the second nanosheet layers comprise silicon-germanium. [18] A semiconductor structure according to any one of the preceding claims 11 to 17, wherein each of the first and second nanosheet layers (505, 510) has a thickness in the range of 5 nm to 20 nm. [19] Procedure comprising: Arranging a first and a second vertical structure (810) on a substrate (200), wherein the first and the second vertical structure (810) are separated by a first dielectric and the first and the second vertical structure (810) each have a different width and an upper part above the first insulation layer comprises a multilayer nanosheet stack with alternating first and second nanosheet layers (505, 510), Arranging a gate sacrificial structure (900) on the upper part of the first and second vertical structures (810) and on a part of the first insulation layer, depositing a second insulation layer on the first and second vertical structures (810) and the first insulation layer such that the second insulation layer surrounds a sidewall of the sacrificial gate structure (900), Etching the gate sacrificial structure (900) to expose each multilayer nanosheet stack of the first and second vertical structures (810), Removing the first nanosheet layers from each exposed multilayer nanosheet stack to form hanging second nanosheet layers and forming a gate metal structure (1300) such that it surrounds the suspended second nanosheet layers. [20] The method of claim 19, further comprising: Etching the gate metal structure (1300) to remove one or more of the second nanosheet layers of the first vertical structure and Depositing a nitride layer on the gate metal structure (1300).

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