PLATFORM FOR ELIMINATING SCAN DESIGN BASED ON MACHINE LEARNING

Abstract

Computer system (500) for grouping and sequencing a plurality of scan flip-flops within an electronic circuit of an electronic device, wherein the computer system (500) comprises: a memory that stores one or more instructions; and a processor (504) that is configured to execute the one or more instructions, wherein the one or more instructions, when executed by the processor (504), configure the processor (504): to perform a cluster analysis of the multitude of scan flip-flops in order to group the multitude of scan flip-flops into a multitude of scan chains; to perform a routing analysis of the scan flip-flops within each scan chain of the multitude of scan chains in order to determine a multitude of routing sequences for the multitude of scan flip-flops; to perform a statistical cost analysis of a multitude of properties, parameters or attributes of a multitude of electrical connections between the multitude of scan flip-flops in order to identify a non-optimal electrical connection among the multitude of electrical connections (402, 404); to identify a scan flip-flop among the multitude of scan flip-flops that corresponds to the non-optimal electrical connection, wherein the identified scan flip-flop is from a first group of scan flip-flops of the multitude of scan flip-flops that are grouped to form a first scan chain among the multitude of scan chains (406, 408); and to move the identified scan flip-flop from the first group of scan flip-flops to a second group of scan flip-flops of the multitude of scan flip-flops that are grouped together to form a second scan chain of the multitude of scan chains (410), including the multitude of properties, parameters or attributes of the multitude of electrical connections: a multitude of lengths (L) of a multitude of scan wires between the multitude of scan flip-flops; a multitude of distances (D) between the multitude of scan flip-flops; or a number of metal layers (M) required to manufacture the multitude of scan chains, the statistical cost analysis includes: a manufacturing / distribution cost analysis; or an M / L cost analysis.

Description

BACKGROUND

[0001] Advances in technology and engineering have enabled developers and manufacturers to offer consumers a wider range of electronic devices. Scan chain testing (DFT) is a design for a testability mechanism used to detect faults within the various combinational logic circuits of these electronic devices. Scan chain testing involves grouping numerous scan flip-flops into numerous scan chains and placing these scan chains within the electronic devices to detect the faults. In some situations, scan chains conventionally occupy between 10 and 40 percent of the available space allocated to these electronic devices.

[0002] US 2010 / 0169727A1 describes an EDA tool. A module for deriving the expected value determines the expected value of each FF by calculating the probability propagation or by logic simulation. A grouping module groups each FF to be tested into multiple groups based on the determined expected value. A scan chain configuration module pairs two groups whose acquisition frequencies are opposite to the logical value 1, performs a logic inversion for one group, and configures a scan chain.

[0003] CUI, Aijiao et al.: An improved scan design for minimization of test power under routing constraint. In: 2015 IEEE international symposium on circuits and systems, May 24-27, 2015, pp. 629-632, describes a method for arranging scan cells in integrated circuits, in which the scan cells are first grouped into clusters using a K-means algorithm to comply with routing constraints. The arrangement and connection of the scan cells within and between the clusters is performed taking into account the bit transitions and the total length of the connections.

[0004] US 2016 / 0253445A1 describes an electronic circuit design system. A server for a CAD environment is connected to the internet and contains a machine learning program. The machine learning program includes a netlist analysis program, a database, and a classifier and predictor program. The netlist analysis program receives a circuit netlist for a designed circuit from the user, characterizes it, and sends characterization data to the database. Characterization data from multiple users for multiple designed circuits is stored in the database. The system uses design target data, the characterization data from multiple designed circuits, and simulation results to calculate and generate predictions and suggestions for the user.

[0005] RÜLLING, Wolfgang: Design for testability. In: The electronic design automation handbook. New York: Springer Science+Business Media, 2003, pp. 339-381, describes technical methods and circuits for the testability of integrated circuits. It covers fault and test pattern models, methods for automatic test pattern generation, scan-path and boundary-scan techniques, special test structures such as signature analysis and on-chip test pattern generators, as well as circuits for self-testing and fault-tolerant systems. SUMMARY

[0006] The present invention relates to a computer system according to claim 1, a computer system according to claim 11, and a method according to claim 15. Claims 2 to 10 describe particularly advantageous implementations of the computer system according to claim 1. Claims 12 to 14 describe particularly advantageous implementations of the computer system according to claim 11. Claims 16 to 18 describe particularly advantageous implementations of the method according to claim 15. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of this disclosure are best understood from the detailed description below when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, several features are not drawn to scale. In fact, the dimensions of the various features may have been enlarged or reduced as desired for clarity. Fig. Figure 1 illustrates a block diagram of an electronic design platform of the exemplary design environment according to an exemplary embodiment of the present disclosure; Fig. 2 illustrates a flowchart of an exemplary operation of the electronic design platform in the grouping and / or sequencing of scan flip-flops within scan chains according to an exemplary embodiment of the present disclosure; Fig. Figure 3 illustrates a flowchart of an exemplary operation of the electronic design platform when generating high-level software layer descriptions of scan flip-flops within scan chains according to an exemplary embodiment of the present disclosure; Fig. Figure 4 illustrates a flowchart of an exemplary operation of the electronic design platform when filtering outlier scan flip-flops within the scan chains according to an exemplary embodiment of the present disclosure; and Fig. Figure 5 illustrates a block diagram of an exemplary computer system for implementing the exemplary design environment according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0008] The following disclosure provides many different embodiments or examples of the implementation of various features of the presented subject matter. Specific examples of the components and arrangements are described below to simplify the present disclosure. For example, the formation of a first element over a second element in the following description may include embodiments in which the first and second elements are in direct contact, and may also include embodiments in which additional elements are formed between the first and second elements, so that the first and second elements may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition does not in itself dictate a relationship between the various embodiments and / or configurations discussed. OVERVIEW

[0009] The electronic design automation (EDA) of the present disclosure optimizes, in various embodiments, the design, simulation, analysis, and verification of electronic circuits for an electronic device. The electronic device includes scan flip-flops for autonomous testing of the electronic circuit for various manufacturing defects. The EDA of the present disclosure groups the scan flip-flops into scan chains such that scan flip-flops within each scan chain share similar properties, parameters, or attributes. Subsequently, the EDA of the present disclosure intelligently orders the scan flip-flop sequence within each scan chain to optimize the performance, power, and / or area of ​​the electronic circuit. EXEMPLARY ELECTRONIC DESIGN PLATFORM

[0010] Fig. Figure 1 illustrates a block diagram of an electronic design platform of the exemplary design environment according to an exemplary embodiment of the present disclosure. As in Fig. As illustrated in Figure 1, the Electronic Design Platform 100 represents a design workflow, including one or more electronic design software tools for designing, simulating, analyzing, and / or verifying one or more electronic architectural design layouts for electronic circuits of an electronic device. In the Fig. In the illustrated embodiment of Figure 1, the electronic device includes one or more scan chains for testing the electronic circuit for various manufacturing defects, such as stuck defects. The one or more electronic architecture design layouts represent one or more images and / or one or more data-based representations of geometric shapes that describe the electronic circuit, the positions of the geometric shapes, and / or the connections between the geometric shapes. As explained in more detail below, the electronic design platform 100 performs an iterative sequence of operations to optimize the placement of the one or more scan chains within the one or more electronic architecture design layouts in order to conserve resources, such as performance and / or space, to name just a few examples, of the electronic device.In some situations, this iterative sequence of operations can itself be repeated iteratively to optimize the placement of one or more scan chains within one or more electronic architecture design layouts. This iterative sequence of operations can, for example, be iterative itself if one or more electronic architecture design layouts are irregular.

[0011] In the Fig. In the illustrated embodiment of Figure 1, the electronic design platform 100 includes a synthesis tool 102, a placement and routing tool 104, a machine learning (ML) design-for-test (DFT) solution tool 106, a DFT specification tool 108, a design engineering change order (ECO) tool 110, an outlier filtering tool 112, a simulation tool 114, and a verification tool 116. These various tools, which will be described in more detail below, represent one or more electronic design software tools which, when executed by one or more computing devices, processors, controllers, or other devices that are apparent to a person skilled in the art without departing from the spirit and scope of this disclosure, can design, simulate, analyze, and / or verify one or more electronic architectural design layouts.Embodiments of the disclosure may be implemented in hardware, firmware, software, or any combination thereof. Embodiments of the disclosure may also be implemented as instructions stored on a machine-readable medium that can be read and executed by one or more processors. A machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computing device). A machine-readable medium may include, for example, read-only memory (ROM); random-access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustic, or other forms of propagating signals (e.g., carrier waves, infrared signals, digital signals, etc.); and other such media.Furthermore, firmware, software, routines, and instructions may be described herein as performing specific actions. However, it should be noted that such descriptions serve only for clarity, and that such actions actually result from computing devices, processors, controllers, or other devices that execute the firmware, software, routines, instructions, etc.

[0012] The synthesis tool 102 translates one or more properties, parameters or attributes of the electronic circuit into one or more logic operations, one or more arithmetic operations, one or more control operations and / or any other suitable operations which will be obvious to the person skilled in the art without departing from the spirit and scope of the present disclosure, into one or more high-level software descriptions of the electronic circuit.In one exemplary embodiment, the one or more high-level software-level descriptions can represent a textual representation of the electronic circuit, such as a netlist; a high-level software model of the electronic circuit using a high-level software language, such as a graphical design tool, for example, C, System C, C++, LabVIEW, and / or MATLAB; a universal system design language, such as SysML, SMDL, and / or SSDL; or a high-level software format, such as Common Power Format (CPF) or Unified Power Format (UPF); or an image-based representation of the electronic circuit, such as a computer-aided design (CAD) model, to name one example. In the [reference to be added]... Fig. In the exemplary embodiment illustrated in Figure 1, the synthesis tool 102 can generate a scan chain report, such as a text file, that describes the scan chains used to test the electronic circuit for various manufacturing defects, such as stuck defects. In this exemplary embodiment, the scan chain report represents a report on the number of scan chains within the electronic circuit, a cumulative number of scan flip-flops within each of the scan chains, and / or a cumulative number of scan flip-flops within the electronic circuit as a whole.

[0013] The Placement and Routing Tool 104 defines the one or more logic operations, the one or more arithmetic operations, the one or more control operations, and / or the other suitable operation from the Synthesis Tool 102 with respect to various geometric shapes corresponding to diffusion layers, polysilicon layers, and / or metal layers, as well as connections between these layers, to provide the one or more electronic architecture design layouts. The Placement and Routing Tool 104 places various electrical, mechanical, and / or electromechanical components of the electronic circuit, as described by the one or more high-level software descriptions of the electronic circuit, onto an electronic design surface to provide one or more electronic architecture design placements for the electronic circuit.The placement and routing tool then assigns 104 geometric shapes to the various electrical, mechanical and / or electromechanical components of the electronic circuit, assigns positions for the geometric shapes within the electronic design area and / or routes connections between the geometric shapes to provide one or more electronic architectural design layouts.In an exemplary embodiment, the placement and routing tool 104 uses a textual or image-based netlist describing the electronic circuit, a technology library for fabricating the electronic device, a semiconductor foundry for fabricating the electronic device, and / or a semiconductor technology node for fabricating the electronic device to place the various electrical, mechanical, and / or electromechanical components, to assign the geometric shapes to the various electrical, mechanical, and / or electromechanical components of the electronic circuit, to assign positions for the geometric shapes within the electronic design area, and / or to route the connections between the geometric shapes.

[0014] The machine learning (ML) design-for-test (DFT) solution tool 106 groups and orders the scan flip-flops within the scan chains. The ML-DFT solution tool 106 receives the scan chain report, which describes the scan chains, from the synthesis tool 102 and the one or more electronic architecture design placements and / or the one or more electronic architecture design layouts from the placement and routing tool 104. The ML-DFT solution tool 106 uses one or more electronic architecture design placements and / or the one or more electronic architecture design layouts to extract the positions of the scan flip-flops.The ML-DFT solution tool 106 performs a mathematical cluster analysis of the scan flip-flops, such as connectivity-based clustering, also known as hierarchical clustering (e.g., agglomerative clustering); centroid-based clustering (e.g., k-mean clustering); distribution-based clustering; and / or density-based clustering, to name a few examples. The mathematical cluster analysis groups the scan flip-flops such that scan flip-flops within each scan chain share similar properties, parameters, or attributes compared to other scan flip-flops within other scan chains.The properties, parameters, or attributes can include distances between scan flip-flops within the scan chains, the density of scan flip-flops within the scan chains, and / or statistical distributions, such as mean distances, for example, between the scan flip-flops within the scan chains. In one exemplary embodiment, the number of scan chains and the number of scan flip-flops for each scan chain are identified in the scan chain report.

[0015] After arranging the scan flip-flops into scan chains, the ML-DFT solution tool 106 performs a mathematical routing analysis, such as a shortest path problem (e.g., a Traveling Salesman Problem - TSP), on the scan flip-flops within each scan chain to determine a routing order. The mathematical routing analysis iteratively establishes a sequence or order for the scan flip-flops within each scan chain to optimize one or more routing parameters of the electronic architecture design placements and / or layouts (e.g., wire length).Mathematical routing analysis can, for example, configure the sequence of a scan chain such that it consists of a first sequence of a first scan flip-flop, a second scan flip-flop, a third scan flip-flop derived from a second sequence of the first scan flip-flop, and the third scan flip-flop and the second scan flip-flop if the wire length of the first sequence is smaller than the wire length of the second sequence. The mathematical routing analysis further orders the sequence or order of the scan flip-flops until one or more routing parameters are optimized. In an exemplary embodiment, the ML-DFT solution tool 106 provides a scan cluster report representing a textual or image-based netlist that describes the grouping of scan flip-flops within the scan chains and the routing order for the scan flip-flops within each scan chain.

[0016] In some situations, the grouping and / or sequencing of scan flip-flops within scan chains may be subject to one or more electronic design constraints. In an exemplary embodiment, the one or more electronic design constraints may be specified in an electronic design specification for the electronic circuit. For example, the one or more electronic design constraints may specify a cumulative number of flip-flops within one or more of the scan chains, a predetermined grouping of scan flip-flops within one or more of the scan chains, and / or a predetermined routing order for the scan flip-flops within one or more of the scan chains. As described in Fig. As illustrated in Figure 1, the electronic design platform 100 includes the DFT specification tool 108 for receiving these electronic design restrictions. In one exemplary embodiment, the DFT specification tool 108 can receive a report on the electronic design restrictions, such as a text file, for example, describing one or more electronic design restrictions. However, other mechanisms for receiving the one or more electronic design restrictions are also possible, such as manual input via a peripheral device, like a keyboard, without departing from the spirit and scope of this disclosure.

[0017] The Design-Engineering-Change-Order (ECO) Tool 110 provides the one or more high-level software-level descriptions of the electronic circuit, supplied by the Synthesis Tool 102, according to the grouping and sequencing of the scan flip-flops supplied by the ML-DFT Solution Tool 106. As described above, the Synthesis Tool 102 translates the one or more properties, parameters, or attributes of the electronic circuit into the one or more logic operations, arithmetic operations, control operations, and / or other suitable operations in the one or more high-level software-level descriptions of the electronic circuit. In the Fig. In the exemplary embodiment illustrated in Figure 1, the Design-ECO-Tool 110 removes the grouping and sequencing of the scan flip-flops from the one or more high-level software descriptions of the electronic circuit provided by the Synthesis-Tool 102. Subsequently, in this exemplary embodiment, the Design-ECO-Tool 110 extends the one or more high-level software descriptions of the electronic circuit with the grouping and sequencing of the scan flip-flops provided by the ML-DFT Solution-Tool 106.Next, the Placement and Routing Tool 104 extends the one or more placements of the electronic architecture design and / or the one or more electronic architecture design layouts according to the grouping and sequencing of the scan flip-flops provided by the ML-DFT Solution Tool 106, as described by the one or more high-level software descriptions of the electronic circuit provided by the Design-ECO Tool 110. In some situations, the grouping and / or sequencing of the scan flip-flops within the scan chains may be subject to the one or more constraints of the electronic design, as described above. In these situations, the scan flip-flops and / or scan chains that exhibit the one or more constraints of the electronic design may be removed from consideration by the Design-ECO Tool 110.In these situations, the grouping and / or sequencing of these scan flip-flops and / or scan chains, which exhibit one or more constraints of the electronic design, remain within the high-level software-level descriptions of the electronic circuit provided by the synthesis tool 102.

[0018] The outlier filter tool 112 performs a statistical cost analysis of the scan flip-flops within the scan chains to identify whether one or more non-optimal scan flip-flops, referred to as outliers, are present in the scan chains. In the Fig. In the exemplary embodiment illustrated in Figure 1, the outlier filter tool 112 analyzes the one or more architectural design placements and / or the one or more electronic architectural design layouts from the placement and routing tool 104 for one or more properties, parameters, or attributes of the electrical connections between the scan flip-flops within the scan chains. In an exemplary embodiment, the one or more properties, parameters, or attributes may include the length (L) of the scan wires between the scan flip-flops, the distances (D) between the scan flip-flops, and the number of metal layers (M) required to construct the scan chains.The outlier filter tool 112 then performs a statistical cost analysis of one or more properties, parameters, or attributes, such as an L / D cost analysis, an M / D cost analysis, and / or an M / L cost analysis, to name a few examples, in order to identify one or more suboptimal electrical connections between the scan flip-flops within the scan chains. The outlier filter tool 112 identifies these electrical connections, whose statistical cost analyses are greater than or equal to a blocking threshold, such as two standard deviations from the mean of the statistical cost analysis, four standard deviations from the mean of the statistical cost analysis, and / or six standard deviations from the mean of the statistical cost analysis, for example, as the suboptimal electrical connections.Next, the outlier filter tool 112 locates scan flip-flops, designated as non-optimal scan flip-flops, within the scan chains that correspond, for example, to these non-optimal electrical connections as being closest. Then, the outlier filter tool 112 sets the grouping and / or reordering of these non-optimal scan flip-flops within the scan chains. The outlier filter tool 112 can, for example, move these non-optimal scan flip-flops to different scan chains than those provided by the ML-DFT solution tool 106. Then, the design ECO tool 110 extends the [database / process / etc.] in [the context of the previous sentence]. Fig. Figure 1 illustrates the embodiment in which one or more high-level software descriptions of the electronic circuit are provided by the outlier filter tool 112, grouping and sequencing the scan flip-flops. Next, the placement and routing tool 104 extends the one or more electronic architecture design placements and / or the one or more electronic architecture design layouts according to the grouping and sequencing of the scan flip-flops provided by the outlier filter tool 112, as described by the one or more high-level software descriptions of the electronic circuit provided by the design ECO tool 110. In an exemplary embodiment, the placement and routing tool 104 extends the one or more electronic architecture design placements for large-format scan chains.Otherwise, in this exemplary embodiment, the placement and routing tool 104 extends the one or more electronic architecture layouts for smaller scan chains. In some situations, the synthesis tool 102 can extend the one or more high-level software descriptions of the electronic circuit according to the grouping and sequencing of the scan flip-flops provided by the outlier filter tool 112.

[0019] The simulation tool 114 simulates the geometric shapes, the positions of the geometric shapes, and / or the connections between the geometric shapes, as described by the one or more electronic architectural design layouts, in order to reproduce the one or more properties, parameters, or attributes of the geometric shapes, the positions of the geometric shapes, and / or the connections between the geometric shapes. In an exemplary embodiment, the simulation tool 114 can perform a statistical timing analysis (STA), a voltage drop analysis (also known as an IREM analysis), a clock domain crossing verification (CDC check), a formal verification (also known as model checking), equivalence checking, or any other suitable analyses, as will be apparent to the person skilled in the art, without departing from the spirit and scope of the present disclosure.In another exemplary embodiment, the simulation tool 114 can perform an AC analysis, such as a linear small-signal frequency domain analysis, and / or a DC analysis, such as a non-linear equilibrium point calculation or a sequence of non-linear operating points calculated while a voltage, current and / or parameter is traversed to perform the STA, IREM analysis or other suitable analyses.

[0020] Verification Tool 116 validates whether one or more properties, parameters, or attributes of the geometric shapes, their positions, and / or the connections between them, as reproduced by Simulation Tool 114, meet the electronic design specification. Verification Tool 116 can also perform a physical verification, also known as a Design Rule Check (DRC), to check whether the geometric shapes, their positions, and / or the connections between them, assigned by Placement and Routing Tool 104, meet a set of recommended parameters, known as design rules, as defined by a semiconductor foundry and / or semiconductor technology node for manufacturing the electronic device. EXAMPLE GROUPING AND / OR SEQUENCE DETERMINATION OF SCAN FLIP-FLOPS WITHIN THE SCAN CHAINS

[0021] Fig. Figure 2 illustrates a flowchart of an exemplary operation of the electronic design platform for grouping and / or sequencing scan flip-flops within scan chains according to an exemplary embodiment of the present disclosure. The disclosure is not limited to this description of operation. Rather, it will be apparent to those skilled in the art that other operational control sequences fall within the scope and spirit of the present invention. The following discussion describes an exemplary operational control sequence 200 for grouping and / or sequencing the scan flip-flops within the scan chains within the electronic circuit of the electronic device. In some situations, the exemplary operational control sequence 200 can be repeated iteratively to optimize the grouping and / or sequencing of the scan flip-flops within the scan chains within the electronic circuit of the electronic device.The operational control process 200 can be an exemplary operation for the machine learning (ML) design-for-test (DFT) solution tool 106 when determining the grouping and / or sequencing of scan flip-flops within the scan chains, as above in . Fig. 1 described, represent.

[0022] In process 202, the exemplary operating control sequence 200 determines the number of scan flip-flops and the number of scan chains of the electronic circuit. In one exemplary embodiment, the exemplary operating control sequence 200 receives a scan chain report, such as a text file, for example, that describes the scan chains. In this exemplary embodiment, the scan chain report represents a report on the number of scan chains of the electronic circuit, a cumulative number of scan flip-flops within each of the scan chains, and / or a cumulative number of scan flip-flops within the electronic circuit as a whole. However, other mechanisms for determining the number of scan flip-flops and the number of scan chains of the electronic device are also possible, such as manual entry via a peripheral device, such as a keyboard, without departing from the spirit and scope of the present disclosure.

[0023] In process 204, the exemplary operational control sequence extracts 200 scan flip-flop positions within one or more electronic architecture design layouts. The one or more electronic architecture design layouts represent one or more images and / or one or more data-based representations of geometric shapes that describe the electronic circuitry, the positions of the geometric shapes, and / or the connections between the geometric shapes. The one or more electronic architecture design layouts can represent one or more Design Exchange Format (DEF) files, one or more Library Exchange Format (LEF) files, one or more JPEG (Joint Photographic Experts Group) images, JPEG File Interchange Format (JIFF) images, Exchangeable Image File (Exif) images, Tagged Image File Format (TIFF) images, Graphics Interchange Format (GIF) images, Windows Bitmap (BMP) images, and / or Portable Network Graphic (PNG) images.that correspond to the electronic circuit, and / or one or more Gerber data files, AutoCAD Drawing Exchange Format (DXF) data files, Portable Document Format (PDF) data files, Electronic Design Interchange Format (EDIF) data files, ODB++ data files, one or more Association Connecting Electronics Industries (IPC) data files, such as IPC-2511A, IPC-2511B or IPC-2581 for example, one or more International Organization for Standardization (ISO) data files, such as ISO 10303-210 for example, that correspond to the electronic circuit.

[0024] In process 206, the exemplary operational control sequence 200 determines whether a number of scan chains within the electronic circuit needs to be optimized. In some situations, the exemplary operational control sequence 200 can autonomously determine to optimize the number of scan chains within the electronic circuit by evaluating the efficiency, performance, and / or area of ​​the scan chains within the electronic circuit from one or more electronic architecture design layouts and comparing these efficiency, performance, and / or area properties, parameters, or attributes of the scan chains with corresponding properties, parameters, or attributes for efficiency, performance, and / or area listed in an electronic design specification.In one exemplary embodiment, the exemplary operating control sequence 200 can reduce the performance, power, and / or area of ​​the scan chains within the electronic circuit by optimizing the number of scan chains within the electronic circuit. In some other situations, the grouping and / or sequencing of the scan flip-flops within the scan chains may be subject to one or more of the constraints of the electronic design, as described above in . Fig. 1 described. In the Fig. In the exemplary embodiment illustrated in Figure 2, one or more constraints of the electronic design may include a requirement to optimize the number of scan chains within the electronic circuit. The operating control sequence 200 proceeds to step 208 to optimize the number of scan chains within the electronic circuit. Otherwise, the operating control sequence 200 proceeds to step 210 to determine the grouping of the scan flip-flops within the scan chains.

[0025] In process 208, the exemplary operational control sequence 200 determines an optimal number of scan chains for the electronic circuit. The exemplary operational control sequence 200 performs the mathematical cluster analysis of the scan flip-flops to assign the scan flip-flops to the scan chains within the electronic circuit, as described above. Fig. As described in section 1, the system groups the scan flip-flops. Following this, the exemplary operational control sequence 200 performs a mathematical consistency analysis of the scan flip-flops, such as silhouette clustering, to interpret and / or validate the consistency of the scan flip-flop grouping within the scan chains. In the section described in Fig. In the exemplary embodiment illustrated in Figure 2, the mathematical consistency analysis uses a distance metric, such as a Euclidean distance or a Manhattan distance, to name just a few examples, to determine distances between the scan flip-flops within the scan chains. The mathematical consistency analysis provides a consistency coefficient, such as a silhouette value, which represents a measure of the similarity between the scan flip-flops within their own scan chains, known as cohesion, compared to scan flip-flops in other scan chains, known as separation.Exemplary operational control sequence 200 iteratively repeats the mathematical cluster analysis to determine different groupings of the scan flip-flops into different numbers of scan chains and the mathematical consistency analysis to interpret and / or validate the consistency of these different groupings. Exemplary operational control sequence 200 then selects the number of scan chains exhibiting the highest consistency coefficient as the optimal number of scan chains for the electronic circuit.

[0026] In process 210, the exemplary operational control sequence performs 200k mean clustering to group the scan flip-flops into the number of scan chains determined in process 208, or as specified in the scan chain report above. Fig. As described in section 1, k-mean clustering was identified. The k-mean clustering initializes random centroids within the area for the electronic circuit design. Each of these random centroids corresponds to one of the scan chains identified in the scan chain report. The k-mean clustering then assigns scan flip-flops to the random centroids also identified in the scan chain report. For example, the k-mean clustering assigns each scan flip-flop to the random centroid with the nearest mean. Next, the k-mean clustering determines new centroids for the scan chains from each of the previously assigned scan flip-flops within each scan chain. The k-mean clustering then assigns the scan flip-flops to these new centroids also identified in the scan chain report.This process of determining new centroids for the scan chains and assigning the scan flip-flops to the new centroids is repeated iteratively until the k-mean clustering assignments converge such that each scan flip-flop belongs to the scan chain with the nearest mean. In some situations, the grouping and / or ordering of the scan flip-flops within the scan chains may be subject to one or more electronic design constraints, as described above. Fig. 1 described. In these situations, the exemplary operational control sequence 200, based on the proximity to the centroids, can further redistribute the grouping of the scan flip-flops within the scan chains, as determined by the k-mean clustering, in order to generate approximately equally sized clusters for the scan chains in order to compensate for the length of the scan chains.

[0027] In process 212, the exemplary operational control sequence 200 performs the Traveling Salesman Problem (TSP) of the scan flip-flops within each of the scan chains to determine a routing order for the scan flip-flops, as described above in Fig. As described in section 1, the TSP iteratively arranges a sequence or order for the scan flip-flops within each scan chain to optimize one or more routing parameters, such as wire length, from one or more of the electronic architecture design placements and / or the one or more electronic architecture design layouts to determine the routing order for the scan flip-flops. For example, the TSP can set the sequence of a scan chain to be the first sequence of a first scan flip-flop, a second scan flip-flop, a third scan flip-flop from a second sequence of the first scan flip-flop, the third scan flip-flop, and the second scan flip-flop if the wire length of the first sequence is smaller than the wire length of the second sequence. The TSP continues to arrange the sequence or order for the scan flip-flops until the one or more routing parameters are optimized.

[0028] In Operation 214, Exemplary Operational Control Sequence 200 generates an Engineering Change Order (ECO) for the one or more electronic architecture design placements and / or the one or more architecture design layouts. In an exemplary embodiment, the ECO represents a textual listing and / or a graphical representation of the changes required to the one or more electronic architecture design placements and / or the one or more electronic architecture design layouts so that the grouping and sequencing of the scan flip-flops within the one or more electronic architecture design placements and / or the one or more electronic architecture design layouts conforms to the grouping and sequencing of the scan flip-flops as determined by Operation 210 and Operation 212. EXAMPLE SOFTWARE LEVEL DESCRIPTIONS OF HIGH-LEVEL SCAN FLIP-FLOPS WITHIN THE SCAN CHAINS

[0029] Fig. Figure 3 illustrates a flowchart of an exemplary operation of the electronic design platform when generating high-level software descriptions of scan flip-flops within scan chains according to an exemplary embodiment of the present disclosure. The disclosure is not limited to this operation description. Rather, it will be apparent to those skilled in the art that other operational control sequences fall within the scope and spirit of the present invention. The following discussion describes an exemplary operational control sequence 300 for generating a high-level software description of the scan flip-flops within the scan chains within the electronic circuit of the electronic device.The operational control sequence 300 can be an exemplary operation for the Design-Engineering-Change-Order (ECO) Tool 110 when generating the one or more high-level software-level descriptions of the electronic circuit according to the grouping and sequencing of the scan flip-flops provided by the ML-DFT solution tool 106 as described above. Fig. 1 described above, and / or the operating tax process 200, as described above in Fig. 2 described.

[0030] In process 320, the operating control sequence 300 identifies the scan flip-flops within the electronic circuit of the electronic device. In the Fig. In the exemplary embodiment illustrated in section 3, the operating control sequence 300 identifies the scan flip-flops from the one or more high-level software layer descriptions, the one or more electronic architecture design placements, and / or the one or more architecture design layouts, as described above. Fig. 1 described. In an exemplary embodiment, the one or more high-level software layer descriptions, the one or more electronic architecture design placements, and / or the one or more electronic architecture design layouts can represent a textual representation of the electronic circuit, such as a netlist; a high-level software model of the electronic circuit using a high-level software language, such as a graphical design tool, for example C, System C, C++, LabVIEW, and / or MATLAB; a universal system design language, such as SysML, SMDL, and / or SSDL; or a high-level software format, such as Common Power Format (CPF) or Unified Power Format (UPF); or an image-based representation of the electronic circuit, such as a computer-aided design (CAD) model, to give an example.

[0031] In operation 304, the operational control sequence 300 eliminates circuit connections, referred to as legacy circuit connections, for the scan flip-flops identified in operation 320. In general, operational control sequence 300 removes the scan flip-flop sequence from the one or more high-level software layer descriptions, the one or more electronic architecture design placements, and / or the one or more architecture design layouts, as described above in Fig. 1 described. In the Fig. In the exemplary embodiment illustrated in Figure 3, the operational control process 300 removes the grouping and sequencing of the scan flip-flops identified in process 302 within the one or more high-level software descriptions of the electronic circuit provided by the synthesis tool 102.

[0032] In operation 306, the operational control sequence creates 300 new circuit connections for the scan flip-flops identified in operation 302, in one or more high-level software layer descriptions, one or more electronic architecture design placements, and / or one or more architecture design layouts, as described above in Fig. 1 described, according to the grouping and / or sequencing of the scan flip-flops provided by the ML-DFT solution tool 106 and / or the outlier filter tool 112, as described above in Fig. 1 described, provided, and / or the operating tax process 200, as above in Fig. 2 described. In some situations, the operational control sequence 300 can verify the new circuit connections for the scan flip-flops identified in operation 302. In an exemplary embodiment, the operational control sequence 300 verifies the new circuit connections by tracing the new circuit connections for the scan flip-flops identified in operation 302 from the one or more software layer descriptions, the one or more electronic architecture design placements, and / or the one or more architecture design layouts. EXEMPLARY FILTERING OF OUTLIERS - SCAN FLIP-FLOPS WITHIN THE SCAN CHAINS

[0033] Fig. Figure 4 illustrates a flowchart of an exemplary operation of the electronic design platform when filtering outlier scan flip-flops within the scan chains according to an exemplary embodiment of the present disclosure. The disclosure is not limited to this description of operation. Rather, it will be apparent to those skilled in the art that other operational control sequences fall within the scope and spirit of the present invention. The following discussion describes an exemplary operational control sequence 400 for identifying one or more suboptimal scan flip-flops, referred to as outliers, within the scan chains of the electronic circuit of the electronic device.The operational control process 400 can be an exemplary process for the outlier filter tool 112 in performing the statistical cost analysis of electrical connections between the scan flip-flops within the scan chains to identify one or more non-optimal scan flip-flops, referred to as outliers, within the scan chains, as described above in . Fig. 1 described.

[0034] In process 402, the operational control process 400 selects a statistical cost function from among an L / D cost function, an M / D cost function, and / or an M / L cost function, to name a few examples, to evaluate electrical connections between the scan flip-flops within the scan chains in order to identify one or more non-optimal scan flip-flops, which are referred to as outliers. In the Fig. In the exemplary embodiment illustrated in Figure 4, the statistical cost function analyzes the lengths (L) of the scan wires between the scan flip-flops, the distances (D) between the scan flip-flops, and the number of metal layers (M) required to fabricate the scan chains. The L / D cost function represents the ratio of a scan wire length (L) between scan flip-flops to a distance (D) between scan flip-flops. The M / D cost function represents the ratio of the number of metal layers (M) required to fabricate the scan chains to a distance (D) between scan flip-flops. The M / L cost function represents the ratio of the number of metal layers (M) required to fabricate the scan chains to a scan wire length (L) between scan flip-flops.

[0035] In process 404, the operational control process 400 calculates a cost metric for the electrical connections between the scan flip-flops within the scan chains according to the statistical cost function selected in process 402. In the Fig. In the exemplary embodiment illustrated in Figure 4, after the operating control process 400 has calculated the cost metrics for the electrical connections between the scan flip-flops within a first scan chain, it proceeds to calculate the cost metrics for the electrical connections between the scan flip-flops within a second scan chain.

[0036] In process 406, the operational control sequence 400 identifies one or more suboptimal electrical connections between the scan flip-flops within the scan chains. In the Fig. In the exemplary embodiment illustrated in Figure 4, the operational control sequence 400 compares the cost metrics for the electrical connections with a blocking threshold to identify the one or more suboptimal electrical connections between the scan flip-flops within the scan chains. In one exemplary embodiment, the blocking threshold represents one or more standard deviations from the mean of the cost metrics. For example, the blocking threshold can represent two, four, or six standard deviations from the mean cost metric for the scan flip-flops. The operational control sequence 400 identifies the electrical connections as the one or more suboptimal electrical connections if their corresponding cost metric is greater than the blocking threshold.

[0037] In process 408, the operational control sequence 400 identifies one or more scan flip-flops, referred to as non-optimal scan flip-flops, within the scan chains corresponding to the electrical connections identified in process 406. In the Fig. In the exemplary embodiment illustrated in Figure 4, the operational control sequence 400 identifies scan flip-flops, referred to as non-optimal scan flip-flops, within the scan chains that are, for example, closest in distance to the non-optimal connections identified in Procedure 406 from the one or more electronic architecture design placements and / or the one or more electronic architecture design layouts. The operational control sequence 400 can use a distance metric, such as a Euclidean distance or a Manhattan distance, to name just a few examples, to determine distances between the scan flip-flops within the scan chains and the non-optimal electrical connections.

[0038] In step 410, the operational control flow 400 sets the grouping of scan flip-flops from the one or more electronic architecture design placements and / or the one or more architecture design layouts. For example, operational control flow 400 can group the scan flip-flops identified in process 408 such that these suboptimal scan flip-flops share similar properties, parameters, or attributes as other scan flip-flops within their respective scan chains. These properties, parameters, or attributes can include distances between scan flip-flops within the scan chains, density of scan flip-flops within the scan chains, and / or statistical distributions, such as mean distances, for example, of the scan flip-flops within the scan chains. EXEMPLARY COMPUTER SYSTEM FOR IMPLEMENTING THE EXEMPLARY DESIGN ENVIRONMENT

[0039] Fig. Figure 5 illustrates a block diagram of an exemplary computer system for implementing the exemplary design environment according to an exemplary embodiment of the present disclosure. It can be a computer system 500 for implementing the electronic design platform 100, as described above in Figure 5. Fig. The electronic design platform 100 can be used as described in section 1. However, in some situations, more than one computer system 500 can be used for the electronic design platform 100. After reading this description, it will be obvious to the person skilled in the art how embodiments can be implemented using other computer systems and / or computer architectures.

[0040] The computer system 500 contains one or more processors 504, also called central processing units (CPUs), to run the synthesis tool 102, the placement and routing tool 104, the machine learning (ML) design-for-test (DFT) solution tool 106, the DFT specification tool 108, the design engineering change order (ECO) tool 110, the outlier filtering tool 112, the simulation tool 114, and / or the verification tool 116, as described above in Fig. 1 described, to execute. The one or more processors 504 can be connected to a communication infrastructure or bus 506. In an exemplary embodiment, one or more of the one or more processors 504 can be implemented as a graphics processing unit (GPU). The GPU represents a specialized electronic circuit designed to rapidly process mathematically intensive applications on electronic devices. The GPU can have a highly parallel structure that is efficient for parallel processing of large blocks of data, such as mathematically intensive data commonly used in computer graphics applications, images, and videos.

[0041] The computer system 500 also includes user input / output device(s) 503, such as monitors, keyboards, pointing devices, etc., which communicate with communication infrastructure 506 via user input / output interface(s) 502.

[0042] The Computer System 500 also includes a main or primary memory 508, such as random access memory (RAM). The main memory 508 can contain one or more intermediate memory levels. Control logic (i.e., computer software) and / or data are stored in the main memory 508, such as the Synthesis Tool 102, the Placement and Routing Tool 104, the Machine Learning (ML) Design-for-Test (DFT) Solution Tool 106, the DFT Specification Tool 108, the Design Engineering Change Order (ECO) Tool 110, the Outlier Filter Tool 112, the Simulation Tool 114, and / or the Verification Tool 116.

[0043] The computer system 500 may also include one or more secondary storage devices or memory 510 to store the synthesis tool 102, the placement and routing tool 104, the machine learning (ML) design-for-test (DFT) solution tool 106, the DFT specification tool 108, the design engineering change order (ECO) tool 110, the outlier filtering tool 112, the simulation tool 114, and / or the verification tool 116. The one or more secondary storage devices or memory 510 may, for example, include a hard disk drive and / or a removable storage drive or drive 514. The removable storage drive 514 may be a floppy disk drive, a magnetic tape drive, a compact disk drive, an optical storage device, a tape backup device, and / or another storage device / drive. The removable storage drive 514 can interact with a removable storage unit 518.The removable storage unit 518 contains a computer-usable or -readable storage device with computer software (control logic) and / or data stored on it. The removable storage unit 518 can be a floppy disk, magnetic tape, compact disk, DVD, optical storage disk, and / or other storage device for computer data. The removable storage drive 514 reads from and / or writes to the removable storage unit 518 in a well-known manner.

[0044] According to one exemplary embodiment, the one or more secondary storage devices or memory 510 may include other means, instrumentation, or other approaches that enable computer systems 500 to access computer programs and / or other instructions and / or data. Such means, instrumentation, or other approaches may, for example, include a removable storage unit 522 and an interface. Examples of the removable storage unit 522 and the interface 520 may include a program cartridge and cartridge interface (such as those found in video game devices), a removable memory chip (such as an EPROM or PROM) and associated socket, a memory stick and USB port, a memory card and associated memory card slot, and / or other removable storage units and associated interfaces.

[0045] The computer system 500 may further include a communication or network interface 524. The communication or network interface 524 enables the computer system 500 to communicate and interact with any combination of distributed devices, distributed networks, distributed entities, etc. (referenced individually or collectively by reference numeral 528). For example, the communication or network interface 524 may enable the computer system 500 to communicate with the distributed devices 528 via a communication path 526, which may be wired and / or wireless and may include any combination of LANs, WANs, the Internet, etc. Control logic and / or data may be transmitted to and from the computer system 500 via the communication path 526.

[0046] In one embodiment, a tangible device or manufactured article comprising a tangible computer-usable or -readable medium with control logic (software) stored thereon is also referred to herein as a computer program product or program storage device. This includes, but is not limited to, the computer system 500, the main memory 508, the secondary memory 510, and the removable storage units 518 and 522, as well as tangible manufactured articles embodying any combination of the foregoing. Such control logic, when executed by one or more data processing devices (such as computer system 500), causes these data processing devices to operate as described herein.

[0047] Based on the teachings contained in this disclosure, it is obvious to a person skilled in the art how the disclosure can be adapted using data processing devices, computer systems and / or computer architectures other than those described in Fig. 5 shown, can be manufactured and used. In particular, embodiments can operate with different software, hardware and / or operating system implementations than those described herein. CONCLUSION

[0048] The foregoing detailed description discloses a computer system for grouping and ordering scan flip-flops within an electronic circuit of an electronic device. The computer system includes a memory and a processor. The memory stores one or more instructions. The processor executes the one or more instructions, and when executed by the processor, the one or more instructions configure the processor to: perform a cluster analysis of the scan flip-flops to group the scan flip-flops into scan chains; and perform a routing analysis of the scan flip-flops within each scan chain to determine routing orders for the scan flip-flops.

[0049] The foregoing detailed description further discloses a computer system for optimizing a grouping of scan flip-flops in scan chains within an electronic circuit of an electronic device. The computer system includes a memory and a processor. The memory stores one or more instructions. The processor executes the one or more instructions, wherein the one or more instructions, when executed by the processor, configure the processor.Configure: to perform a statistical cost analysis of the properties, parameters, or attributes of electrical connections between the scan flip-flops to identify a non-optimal electrical connection among the electrical connections; to identify a scan flip-flop among the scan flip-flops that corresponds to the non-optimal electrical connection, wherein the scan flip-flop is taken from a first group of scan flip-flops among the scan flip-flops that are grouped to form a first scan chain among the scan chains; to move the scan flip-flop from the first group of scan flip-flops to a second group of scan flip-flops among the scan flip-flops that are grouped to form a second scan chain from the scan chains.

[0050] The foregoing detailed description further discloses a method for grouping and ordering scan flip-flops within an electronic circuit of an electronic device. The method includes: performing a cluster analysis of the scan flip-flops to group the scan flip-flops into scan chains; performing a routing analysis of the scan flip-flops within each scan chain among the scan chains to determine electrical connections for the scan flip-flops; and performing a statistical cost analysis of the properties, parameters, or attributes of the electrical connections between the scan flip-flops to identify a suboptimal electrical connection among the electrical connections.Identifying a scan flip-flop among the scan flip-flops that corresponds to the non-optimal electrical connection, wherein the scan flip-flop is taken from a first group of scan flip-flops among the scan flip-flops that are grouped to form a first scan chain among the scan chains; and moving the scan flip-flop from the first group of scan flip-flops to a second group of scan flip-flops among the scan flip-flops that are grouped to form a second scan chain among the scan chains.

Claims

[1] Computer system (500) for grouping and sequencing a plurality of scan flip-flops within an electronic circuit of an electronic device, wherein the computer system (500) comprises: a memory that stores one or more instructions; and a processor (504) that is configured to execute the one or more instructions, wherein the one or more instructions, when executed by the processor (504), configure the processor (504): to perform a cluster analysis of the multitude of scan flip-flops in order to group the multitude of scan flip-flops into a multitude of scan chains; to perform a routing analysis of the scan flip-flops within each scan chain of the multitude of scan chains in order to determine a multitude of routing sequences for the multitude of scan flip-flops; to perform a statistical cost analysis of a multitude of properties, parameters or attributes of a multitude of electrical connections between the multitude of scan flip-flops in order to identify a non-optimal electrical connection among the multitude of electrical connections (402, 404); to identify a scan flip-flop among the multitude of scan flip-flops that corresponds to the non-optimal electrical connection, wherein the identified scan flip-flop is from a first group of scan flip-flops of the multitude of scan flip-flops that are grouped to form a first scan chain among the multitude of scan chains (406, 408); and to move the identified scan flip-flop from the first group of scan flip-flops to a second group of scan flip-flops of the multitude of scan flip-flops that are grouped together to form a second scan chain of the multitude of scan chains (410), including the multitude of properties, parameters or attributes of the multitude of electrical connections: a multitude of lengths (L) of a multitude of scan wires between the multitude of scan flip-flops; a multitude of distances (D) between the multitude of scan flip-flops; or a number of metal layers (M) required to manufacture the multitude of scan chains, the statistical cost analysis includes: a manufacturing / distribution cost analysis; or an M / L cost analysis. [2] Computer system (500) according to claim 1, wherein the one or more instructions, when executed by the processor (504), further configure the processor (504) to extract a plurality of positions of the plurality of scan flip-flops from an electronic architecture design placement for the electronic circuit or an electronic architecture design layout of the electronic circuit. [3] Computer system according to claim 1 or 2, wherein the cluster analysis is configured to group the plurality of scan flip-flops such that scan flip-flops within each scan chain of the plurality of scan flip-flops have similar properties, parameters or attributes compared to properties, parameters or attributes of scan flip-flops within other scan chains of the plurality of scan chains. [4] Computer system (500) according to any one of the preceding claims, wherein the features, parameters or attributes comprise: a multitude of distances between the multitude of scan flip-flops within the multitude of scan chains; a multitude of scan flip-flop densities within the multitude of scan flip-flops within the multitude of scan chains, or a multitude of statistical distributions of scan flip-flops within the multitude of scan flip-flops within the multitude of scan chains. [5] Computer system (500) according to any of the preceding claims, wherein the one or more instructions, when executed by the processor (504), further configure the processor (504) to receive a scan chain report that identifies: a number of scan chains within the multitude of scan chains; and a number of scan flip-flops for scan chains from the multitude of scan chains. [6] Computer system (500) according to any one of the preceding claims, wherein the cluster analysis comprises: a connectivity-based clustering; a centroid-based clustering; a distribution-based clustering; or density-based clustering. [7] Computer system (500) according to one of the preceding claims, wherein the routing analysis comprises a shortest path problem. [8] Computer system (500) according to one of the preceding claims, wherein the routing analysis is configured to arrange a sequence for scan flip-flops within each scan chain of the plurality of scan chains in order to optimize one or more routing parameters for each scan chain among the plurality of scan chains. [9] Computer system (500) according to claim 8, wherein one or more routing parameters comprise: a wire length between scan flip-flops within each scan chain of the multitude of scan chains. [10] Computer system (500) according to one of the preceding claims, wherein the one or more instructions, when executed by the processor (504), further configure the processor (504) to provide a scan cluster report that describes a grouping of the plurality of scan flip-flops into the plurality of scan chains and routing sequences for the plurality of scan flip-flops within each scan chain of the plurality of scan chains. [11] Computer system (500) for optimizing a grouping of a plurality of scan flip-flops into a plurality of scan chains within an electronic circuit of an electronic device, wherein the computer system (500) comprises: a memory that stores one or more instructions; and a processor (504) that is configured to execute the one or more instructions, wherein the one or more instructions, when executed by the processor (504), configure the processor (504): to perform a statistical cost analysis of a multitude of properties, parameters or attributes of a multitude of electrical connections between the multitude of scan flip-flops in order to identify a non-optimal electrical connection among the multitude of electrical connections (402, 404); to identify a scan flip-flop among the multitude of scan flip-flops that corresponds to the non-optimal electrical connection, wherein the identified scan flip-flop is from a first group of scan flip-flops of the multitude of scan flip-flops that are grouped to form a first scan chain among the multitude of scan chains (406, 408); and to move the identified scan flip-flop from the first group of scan flip-flops to a second group of scan flip-flops of the multitude of scan flip-flops that are grouped together to form a second scan chain of the multitude of scan chains (410), including the multitude of properties, parameters or attributes of the multitude of electrical connections: a multitude of lengths (L) of a multitude of scan wires between the multitude of scan flip-flops; a multitude of distances (D) between the multitude of scan flip-flops; or a number of metal layers (M) required to manufacture the multitude of scan chains, the statistical cost analysis includes: a manufacturing / distribution cost analysis; or an M / L cost analysis. [12] Computer system (500) according to claim 11, wherein the one or more instructions, when executed by the processor (504), configure the processor (504) to compare the statistical cost analysis of the plurality of properties, parameters or attributes with a blocking threshold and to identify the non-optimal electrical connection whose statistical cost analysis is greater than or equal to the blocking threshold. [13] Computer system (500) according to claim 12, wherein the blocking threshold corresponds to one or more standard deviations from a mean of the statistical cost analysis of the plurality of properties, parameters or attributes. [14] Computer system (500) according to one of claims 11 to 13, wherein the one or more instructions, when executed by the processor (504), further configure the processor (504) to receive an electronic architecture design placement for the plurality of scan flip-flops, wherein the electronic architecture design placement represents a logical placement of the plurality of scan flip-flops on an electronic design surface. [15] Method for grouping and sequencing a plurality of scan flip-flops within an electronic circuit of an electronic device, the method comprising: Performing a cluster analysis of the multitude of scan flip-flops to group the multitude of scan flip-flops into a multitude of scan chains; Performing a routing analysis of scan flip-flops within each scan chain of the multitude of scan chains to determine a multitude of electrical connections for the multitude of scan flip-flops; Performing a statistical cost analysis of a multitude of properties, parameters, or attributes of the multitude of electrical connections between the multitude of scan flip-flops to identify a suboptimal connection among the multitude of electrical connections (402, 404); Identifying a scan flip-flop among the multitude of scan flip-flops that corresponds to the non-optimal electrical connection, wherein the identified scan flip-flop is from a first group of scan flip-flops of the multitude of scan flip-flops that are grouped to form a first scan chain of the multitude of scan chains (406, 408); and Moving the identified scan flip-flop from the first group of scan flip-flops to a second group of scan flip-flops of the plurality of scan flip-flops that are grouped to form a second scan chain of the plurality of scan chains (410), including the multitude of properties, parameters or attributes of the multitude of electrical connections: a multitude of lengths (L) of a multitude of scan wires between the multitude of scan flip-flops; a multitude of distances (D) between the multitude of scan flip-flops; or a number of metal layers (M) required to manufacture the multitude of scan chains, the statistical cost analysis includes: a manufacturing / distribution cost analysis; or an M / L cost analysis. [16] The method of claim 15, wherein performing the cluster analysis comprises: Grouping the multitude of scan flip-flops such that scan flip-flops within each scan chain of the multitude of scan chains have similar properties, parameters, or attributes compared to properties, parameters, or attributes of scan flip-flops within other scan chains of the multitude of scan chains. [17] Method according to claim 15 or 16, wherein performing the routing analysis comprises: Arranging a sequence for scan flip-flops within each scan chain of the multitude of scan chains to optimize one or more routing parameters for each scan chain of the multitude of scan chains. [18] Method according to any one of claims 15 to 17, wherein the identification comprises: Comparing the statistical cost analysis of a multitude of properties, parameters, or attributes with a blocking threshold; and Identifying the suboptimal electrical connection whose statistical cost analysis is greater than or equal to the blocking threshold.

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