Power semiconductor device and method

Abstract

Power semiconductor device (1) comprising the following: - a semiconductor body (10) having a front (10-1) and a back (10-2) and configured to conduct a load current between the front (10-1) and the back (10-2); and - several control cells (14) configured to control the load current, wherein each control cell (14) is at least partially contained in the semiconductor body (10) on the front side (10-1) and comprises a gate electrode (143) electrically insulated from the semiconductor body (10) by means of a gate insulating layer (144), wherein the gate insulating layer (144) comprises a first boron nitride layer (1443); and wherein an interlayer dielectric structure (13) is arranged at least partially between the gate electrode (143) and a front-side metallization (11) of the power semiconductor device (1), wherein the interlayer dielectric structure (13) is or comprises at least a second boron nitride layer (1331).

Description

TECHNICAL AREA

[0001] This patent specification relates to embodiments of a power semiconductor device and to embodiments of a method for forming a power semiconductor device. In particular, this patent specification refers to a vertical power semiconductor device comprising several control cells, each having a gate electrode and a gate insulating layer. BACKGROUND

[0002] Many functions of modern devices in automotive, consumer, and industrial applications, such as converting electrical energy and driving an electric motor or machine, depend on power semiconductor devices. Insulated-gate bipolar transistors (IGBTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), and diodes, to name just a few, are used in a wide variety of applications, including, among others, switches in power supplies and power converters.

[0003] A power semiconductor device typically comprises a semiconductor body configured to conduct a load current along a load current path between two load terminals of the device. For example, in the case of a vertical power semiconductor device, the load current can flow between a front and a back side of the semiconductor body.

[0004] Furthermore, the power semiconductor device can comprise multiple control cells, which may be arranged in a so-called active (cell) region of the power semiconductor device. For example, a load current path can be controlled by means of an insulated electrode, commonly referred to as a control electrode or gate electrode. Such a gate electrode can be located in each of the control cells. For example, upon receiving a corresponding control signal, e.g., from a driver unit, the gate electrode can switch the power semiconductor device into a conducting or a blocking state. In some cases, the gate electrode may have a planar shape, extending mainly in a plane parallel to a front surface of the semiconductor body.In other variants, the gate electrode can be contained within a trench that extends vertically from the front surface into the semiconductor body, with the trench having, for example, a stripe configuration or a needle configuration.

[0005] A general challenge in the design of such power semiconductor devices is to provide sufficient heat dissipation, for example, from locations within the device where relatively high current densities (and therefore heat production) occur during operation. For instance, the creation of hotspots that could cause self-heating effects and ultimately lead to device failure should generally be avoided.

[0006] US 2018 / 0226480A1 describes a semiconductor device comprising a semiconductor layer of a first conductivity type with a main surface in which a trench is formed, a gate insulating layer formed along a side wall of the trench, a gate electrode embedded in the trench, between which the gate insulating layer is arranged, and with an upper surface located below the main surface of the semiconductor layer, a region of the second conductivity type formed in a surface layer section of the main surface of the semiconductor layer and facing the gate electrode, with the gate insulating layer in between.

[0007] US Patent 2019 / 0115443A1 describes a heterostructured semiconductor device comprising a first active layer and a second active layer arranged on top of the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. A dielectric sandwich-gate layer structure is arranged on top of the second active layer. A passivation layer is placed over the dielectric sandwich-gate structure. A gate extends through the passivation layer to the dielectric sandwich-gate structure. A first and second ohmic contacts are electrically connected to the second active layer. The first and second ohmic contacts are laterally spaced apart, with the gate located between them.

[0008] US Patent 2006 / 0175672A1 discloses a semiconductor device comprising a semiconductor substrate and a gate insulating film of a p-channel MOS transistor formed on the semiconductor substrate. The gate insulating film has an oxide film and a diffusion barrier film containing boron and nitrogen atoms.

[0009] JP 2015 128 082 A describes a semiconductor device comprising a semiconductor body in which a gate electrode with a trench structure is embedded. A gate insulating layer can be formed using hexagonal boron nitride (H-BN).

[0010] CN 109 686 667 A describes a SiC-based MOS device comprising a two-dimensional high-mobility electrical transport layer made of BN (boron nitride) between a substrate layer of SiC epitaxy material and a gate electrode layer. SUMMARY

[0011] The aspects described here concern a special novel design of a gate insulation layer of a power semiconductor device, which can, for example, provide improved thermal performance.

[0012] The subject matter of the independent claims is proposed. Features of some embodiments are specified in the dependent claims.

[0013] It should be noted that in some embodiments, the boron nitride layers mentioned above and below are structured in a horizontal plane, i.e., when viewed from above. In other words, the respective boron nitride layer does not necessarily have to extend continuously in the horizontal plane, but may be interrupted.

[0014] Additional features and advantages will become apparent to a specialist upon reading the following detailed description and examining the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The parts in the figures are not necessarily to scale. Instead, the emphasis is on illustrating the principles of the invention. Furthermore, identical reference numerals in the figures denote corresponding parts. The following applies to the drawings: Fig. Figure 1 schematically and exemplarily illustrates a section of a vertical cross-section of a power semiconductor device according to one or more examples; Fig. Figure 2 illustrates heat conduction paths during the operation of the semiconductor device. Fig. 1 schematic and exemplary; Fig. Figure 3 schematically and exemplarily illustrates a section of a vertical cross-section of a power semiconductor device according to one or more examples; Fig. Figure 4 schematically and exemplarily illustrates a section of a vertical cross-section of a power semiconductor device according to one or more examples; Fig. Figure 5 schematically and exemplarily illustrates a section of a vertical cross-section of a power semiconductor device according to one or more embodiments; Fig. Figure 6A schematically and exemplarily illustrates a section of a vertical cross-section of a power semiconductor device according to one or more embodiments; Fig. Figure 6B schematically and exemplarily illustrates a section of a vertical cross-section of a power semiconductor device according to one or more embodiments, including heat conduction paths during operation; and Fig. 7A-H each schematically and exemplarily illustrates the steps of a procedure for forming a power semiconductor device according to one or more examples. DETAILED DESCRIPTION

[0016] The following detailed description refers to the accompanying drawings, which form a part thereof and in which special embodiments are shown as illustrations in which the invention can be practiced.

[0017] In this respect, directional terminology such as "above," "below," "below," "in front of," "behind," "back," "leading," "following," "above," etc., may be used with reference to the orientation of the described figures. Because parts of embodiments may be positioned in a number of different orientations, the directional terminology is used for illustrative purposes and is in no way limiting. It is understood that other embodiments may be used and structural or logical modifications may be made without deviating from the scope of protection of the present invention. The following detailed description is therefore not to be understood in a limiting sense, and the scope of protection of the present invention is defined by the accompanying claims.

[0018] The following detailed reference is made to different embodiments, one or more examples of which are illustrated in the figures. Each example is provided as an explanation and is not intended to limit the invention. For example, features illustrated or described as part of one embodiment can be applied to or combined with other embodiments to obtain yet another embodiment. The present invention is intended to include such modifications and variations. The drawings are not to scale and are for illustrative purposes only. For clarity, the same elements or manufacturing steps have been designated with the same reference numerals in the various drawings, unless otherwise indicated.

[0019] The term "horizontal," as used in this description, is intended to describe an orientation essentially parallel to a horizontal surface of a semiconductor substrate or structure. This could be, for example, the surface of a semiconductor wafer, die, or chip. Both the first lateral (or horizontal) direction X mentioned below and / or shown in the figures, and the second lateral (or horizontal) direction Y mentioned below and / or shown in the figures, can, for example, be horizontal directions, with the first lateral direction X and the second lateral direction Y being perpendicular to each other.

[0020] The term "vertical," as used in this description, is intended to describe an orientation that is essentially perpendicular to the horizontal surface, i.e., parallel to the normal direction of the semiconductor wafer / chip / die surface. The vertical direction Z mentioned below and / or shown in the figures, for example, can be a direction perpendicular to both the first lateral direction X and the second lateral direction Y.

[0021] In this description, n-doped materials are generally referred to as a "first conductivity type," whereas p-doped materials are referred to as a "second conductivity type." Alternatively, reverse doping relationships can be used, so that the first conductivity type can be p-doped and the second conductivity type n-doped.

[0022] In the context of this description, the terms "in ohmic contact," "in electrical contact," "in ohmic connection," and "electrically connected" are intended to describe the existence of a low-resistance electrical connection or current path between two regions, sections, zones, portions, or parts of a semiconductor device, or between different terminals of one or more devices, or between a terminal, metallization, or electrode and a portion or part of a semiconductor device. Furthermore, the term "in contact" in the context of this description is intended to describe the existence of a direct physical connection between two elements of the semiconductor device in question; for example, a junction between two elements in contact may not include any further intermediate element or the like.

[0023] Additionally, in the context of this description, the term "electrical isolation" is used in its generally accepted sense, unless otherwise specified, and thus describes a situation where two or more components are positioned separately and there is no ohmic connection connecting them. However, components that are electrically isolated from each other may still be coupled, for example, mechanically coupled and / or capacitively coupled and / or inductively coupled. To give an example, two electrodes of a capacitor may be electrically isolated from each other and may simultaneously be mechanically and capacitively coupled, for example, by means of insulation such as a dielectric.

[0024] Specific embodiments described in this description relate, but are not limited to, a power semiconductor device having a single-cell, strip-cell, or cellular (also referred to as a "needle" or "column" cell) cell configuration, e.g., a power semiconductor device that can be used within a power converter or power supply. Accordingly, in one embodiment, such a device may be configured to carry a load current, which is to be supplied to a load and / or which is provided by a power supply. For example, the power semiconductor device may comprise one or more active power semiconductor cells, such as a monolithically integrated diode cell, a derivative of a monolithically integrated diode cell (e.g., a diode), or a diode cell.A monolithically integrated cell consisting of two anti-series connected diodes, a monolithically integrated transistor cell (e.g., a monolithically integrated IGBT or MOSFET cell), and / or derivatives thereof. Such diode / transistor cells can be integrated into a power semiconductor module. Several such power cells can form a cell array arranged with an active region of the power semiconductor device.

[0025] The term "power semiconductor device," as used in this description, is intended to describe a semiconductor device on a single chip with high voltage blocking and / or high current carrying capabilities. In other words, such a power semiconductor device is designed to handle high currents, typically in the ampere range, e.g., up to several tens or hundreds of amperes, and / or high blocking voltages, typically above 15 V, such as above 40 V, typically 100 V and above, e.g., up to at least 400 V or even above, e.g., up to at least 3 kV or even up to 6 kV or above.

[0026] For example, the power semiconductor device described below can be a single semiconductor chip having a striped cell configuration or a cellular cell configuration, and can be configured to be used as a power component in a low, medium and / or high voltage application.

[0027] For example, the term "power semiconductor device" as used in this patent specification does not refer to logic semiconductor devices used, for example, for storing data, calculating data and / or for other types of semiconductor-based data processing.

[0028] Fig. Figure 1A schematically and exemplarily shows a section of a vertical cross-section of a power semiconductor device 1 according to one or more examples. The power semiconductor device 1 comprises a semiconductor body 10 with a front face 10-1 and a back face 10-2. For example, the semiconductor body 10 may comprise or consist of a silicon-based substrate, a silicon carbide-based substrate, a gallium-based substrate, or, for example, another wide-bandgap semiconductor substrate.

[0029] The power semiconductor device 1 of the illustrated embodiment can be configured to conduct a load current between the front side 10-1 and the back side 10-2. In other words, the power semiconductor device 1 can be configured as a vertical power semiconductor device 1. For example, the power semiconductor device 1 can have an IGBT configuration or a MOSFET configuration. More generally, the power semiconductor device can also have a JFET configuration or a diode configuration (not illustrated in the figures).

[0030] According to the in Fig. In the illustrated embodiment 1, the front side 10-1 can be coupled to a first load connection structure 11 and the back side 10-2 can be coupled to a second load connection structure 12, so that the load current can flow between the first load connection structure 11 and the second load connection structure 12. Fig. Figure 1 shows, for example, an exemplary front face metallization 11, which can form at least part of the first load connection structure 11, and a back face metallization 12, which can form at least part of the second load connection structure 12.

[0031] Furthermore, the semiconductor body 10 can include a drift region 100 of a first conductivity type (e.g., n-type). The drift region 100 can be configured to conduct the load current between the first load terminal structure 11 and the second load terminal structure 12, the load current path being able to include additional semiconductor regions 141, 142, 103 besides the drift region 100, as will be explained further below.

[0032] To control the load current, several control cells 14 can be provided, for example, in an active cell region of the power semiconductor device 1. The section of the in Fig. The cross-section shown in Figure 1 schematically illustrates only one such control cell 14 as an example. However, it is understood that the power semiconductor device 1 can comprise several, such as hundreds or even thousands, of such control cells 14, which can be electrically connected in parallel so that they jointly conduct and control the load current.

[0033] For example, as in Fig. Figure 1 schematically and exemplarily illustrates that each control cell 14 is at least partially contained in the semiconductor body 10 on the front face 10-1. Each control cell 14 can comprise at least one source region 141 of the first conductivity type, wherein the source region 141 is contained in the semiconductor body 10 and is electrically connected to the first load connection structure 11.

[0034] Furthermore, each control cell can have at least one body region 142 of a second conductivity type (e.g. p-type) that is complementary to the first conductivity type, wherein the body region 142 is contained in the semiconductor body 10 and separates the source region 141 from the drift region 100.

[0035] In the example from Fig. In Figure 1, the control cell 14 comprises two such source regions 141 and two corresponding body regions 142, which share a common gate electrode 143. In this example, the gate electrode 143 has a planar arrangement and extends mainly parallel to a front surface of the semiconductor body 10 (i.e., parallel to the horizontal plane XY in Figure 1). Fig. 1) In other embodiments, the gate electrode 143 can be arranged in a vertical gate groove, as shown below with reference to Fig. 6A is explained further.

[0036] The gate electrode 143 can be configured to induce a conduction channel in the body region(s) 142 depending on a control signal, the conduction channel extending from the source region(s) 141 to the drift region 100. For example, the power semiconductor device 1 can include a gate terminal (not illustrated) for receiving such a control signal from outside the power semiconductor device 1, e.g., in the form of a gate voltage, the gate terminal being electrically connected to the gate electrode 143.

[0037] For example, the gate electrode 143 can be made of or comprise polysilicon. Alternatively, the gate electrode 143 can be made of or comprise a metal.

[0038] The gate electrode 143 can be electrically isolated from the semiconductor body 10, such as the source region(s) 141, the body region(s) 142, and the drift region 100, by a gate insulating layer 144 comprising a first boron nitride layer 1443. It should be noted that in some embodiments, the gate insulating layer 144 can be a stack of layers that may include the first boron nitride layer 1443 in addition to further layers.

[0039] For example, in one embodiment, the first boron nitride layer 1443 can consist of or comprise hexagonal boron nitride (hBN). In another embodiment, the first boron nitride layer 1443 can consist of or comprise cubic boron nitride (cBN).

[0040] According to the in Fig. In the example shown, the gate insulating layer 144 can be provided in the form of a stack of, for example, three layers 1441, 1443, 1442, wherein the first dielectric layer 1441 can be arranged on a front surface of the semiconductor body 10, the first boron nitride layer 1443 can be arranged on the first dielectric layer 1441, and a second dielectric layer 1442 can be arranged on the first boron nitride layer 1443. In other words, and more generally, in one embodiment, the first boron nitride layer 1443 can be sandwiched (or embedded) between two other dielectric layers 1441, 1442.

[0041] For example, the other dielectric layers 1441, 1442, such as the first dielectric layer 1441 and the second dielectric layer 1442, which are in Fig. The oxide layers shown in 1 are shown.

[0042] More generally, according to one or more examples, the gate insulating layer 144 can further comprise a first dielectric layer 1441, which is arranged at least partially between the first boron nitride layer 1443 and the semiconductor body 10, and / or a second dielectric layer 1442, which is arranged at least partially between the first boron nitride layer 1443 and the gate electrode 143.

[0043] Regarding dimensions and further with reference to the exemplary embodiment from Fig. 1. The thickness T1 (e.g., measured along the vertical direction Z) of the gate insulating layer 144 can, for example, be in the range of 50 nm to 120 nm. Furthermore, the first dielectric layer 1441 can, in one example, have a thickness T1 (e.g., vertical) in the range of, for example, 5 nm to 10 nm.

[0044] For example according to Fig. 1. The horizontal extent W of the gate insulation layer can, for example, be in the range of 6 µm to 10 µm, such as e.g. 8 µm.

[0045] Furthermore, in one example, the vertical extent t3 of the planar gate electrode 143 can be in the range of 100 nm to 500 nm.

[0046] In an example, as exemplary and schematic in Fig. As illustrated in Figure 1, the power semiconductor device 1 can further comprise an interlayer dielectric (ILD) structure 13, which is at least partially located between the gate electrode 143 and the front face metallization 11. The ILD structure 13 can be configured to insulate the gate electrode 143 from the front face metallization 11. For example, the interlayer dielectric structure 13 can comprise one or more dielectric layers, such as one or more oxide layers. The ILD structure 13 can be configured as an intermediate oxide 13. A vertical layer thickness t4 of the interlayer dielectric structure 13 (as measured in a portion extending above the gate electrode 143) can, for example, be in the range of 0.5 µm to 1.0 µm.

[0047] Furthermore, with reference to Fig. In one example, the semiconductor body 10 may comprise a back-side emitter region 103 of either the first conductivity type or the second conductivity type. For example, if the power semiconductor device 1 has an IGBT configuration, a back-side emitter region 103 of the second conductivity type may be provided, wherein the back-side emitter region 103 may be located on the back side 10-2 of the semiconductor body 10 in contact with the back-side metallization 12. If the power semiconductor device 1 has, for example, a MOSFET configuration, the back-side emitter region 103 may be a region containing dopants of the first conductivity type with a higher dopant concentration than the drift region 100. A person skilled in the art is well familiar with the design of such back-side emitter regions 103. Since such back-side structures are not a focus of the present invention, they are not described in more detail here.

[0048] It should be noted that the boron nitride layer(s) 1443 mentioned above and below is structured in a horizontal plane, i.e., when viewed from above, in some embodiments. In other words, the respective boron nitride layer 1443 does not necessarily extend continuously in the horizontal plane, but may be interrupted.

[0049] In this case, it can be provided that the boron nitride layer 1443 extends at least to a position where it makes contact with the front face metallization 11, such as in a contact hole, so that it is able to efficiently dissipate heat via the metal 11.

[0050] Furthermore, in one embodiment, the boron nitride layer 1443 can have small holes or depressions (not illustrated), so that the boron nitride layer 1443 is wedged between the dielectric layers 1441, 1442. As a result, the cohesion of the layer stack 1441, 1442, 1443 can be improved.

[0051] Fig. Figure 2 illustrates heat conduction paths during the operation of semiconductor device 1. Fig. 1. Schematic and exemplary. For example, during operation, heat is generated by a current density that can be relatively high in an area directly below the gate insulation layer 144. For example, a significant amount of heat can be generated at a central position (with respect to the first horizontal direction X) below the first dielectric layer 1441, as well as at an interface between the first dielectric layer 1441 and the body region 142, where an inversion channel can form during operation. Such areas can also be referred to as hotspots.

[0052] A resulting heat profile H is schematically represented in Fig. Figure 2 shows that a high density of horizontal lines indicates high heat, and vice versa. The thin arrows in Fig. Figure 2 indicates paths along which heat is dissipated, e.g., through part of the semiconductor body 10. The thick arrows indicate additional heat dissipation paths provided by the first boron nitride layer 1443. As illustrated by example, the area of ​​highest temperature (hotspot) may be one layer below 1441, with lateral spreading into body regions 142.

[0053] Due to the very small thickness T1 of the first dielectric layer 1441, the boron nitride layer 1443 can be located very close to the hotspot, for example, at a distance of only 5–10 nm. The boron nitride layer 1443 can dissipate heat to the front face metallization 11, acting as a heat spreader. For example, the boron nitride layer 1443 can be 10 nm thick. In some variants, the thickness of the boron nitride layer can be greater and can, for example, be the full thickness T0 of the gate insulating layer 144. This is discussed below with reference to Fig. 3 explained.

[0054] Accordingly, the first boron nitride layer 1443 can serve as a heat distributor, conducting heat generated in the semiconductor body 10, e.g., in the center of a control cell 14, to a metal, such as the front-side metallization 11, so that the heat can be dissipated more easily. It should be noted in this context that in the embodiment consisting of Fig. 1 and Fig. 2 the first boron nitride layer 1443 (lateral) is in contact with the front face metallization 10, which can further promote heat dissipation to the metal 11.

[0055] Now, with reference to Fig. In one embodiment of the power semiconductor device 1, the gate insulation layer 144 can consist entirely of the first boron nitride layer 1443. Therefore, in this example, the first boron nitride layer 1443 can be in contact with the semiconductor body 10 (such as the source region(s) 141, the body region(s) 142, and the drift region 100) as well as the gate electrode 143. Obviously, in this example, the first boron nitride layer 1443 can also be in contact with the front-side metallization 11. Regarding possible dimensions, reference is made to what was stated above, e.g., concerning the (vertical) layer thickness T0 of the gate insulation layer 144.

[0056] Fig. Figure 4 schematically illustrates another embodiment. In this case, the gate insulating layer 144 comprises the first boron nitride layer 1443, which is in contact with the semiconductor body 10, and a second dielectric layer 1442, which is arranged on top of the first boron nitride layer 1443. For example, heat dissipation during operation can be very efficient due to the direct contact of the first boron nitride layer 1443 with a hotspot in the semiconductor body 10. The second dielectric layer 1442 can separate the first boron nitride layer 1443 from the gate electrode 143 and the ILD structure 13, as illustrated. For example, the thermal conductivity of the gate insulating layer 144 can be primarily defined by the thickness of the boron nitride layer 1443. Furthermore, the dielectric strength of the gate insulating layer 144 can be primarily defined by the thickness of the second dielectric layer 1442.In principle, the dielectric strength of the gate insulating layer 144 can be improved by the second dielectric layer 1442 (if the boron nitride layer has a lower dielectric strength than the material of the second dielectric layer, e.g., silicon dioxide). In this variant as well, the first boron nitride layer 1443 can be in contact with the front face metallization 11, as illustrated.

[0057] For example, the exemplary embodiment avoids Fig. 5 from the above with reference to Fig. The semiconductor device 1 described only with respect to the design of the ILD structure 13. As illustrated, for example, one or more second boron nitride layers 1331 can be embedded in the ILD structure 13. For example, the second boron nitride layer(s) 1331 can extend mainly in a horizontal plane XY, such as substantially parallel to the front surface of the semiconductor body 10. Furthermore, it should be noted that the second boron nitride layer(s) 1331 can be arranged in contact with the front metallization 11, as illustrated.

[0058] In one embodiment, at least two such second boron nitride layers 1331, such as three second boron nitride layers 1331, as exemplified in Fig. Figure 5 illustrates how this can be provided as part of the ILD structure 13. For example, each of the second boron nitride layers 1331 can be sandwiched between other dielectric layers 1332, 1333 of the ILD structure 13, such as oxide layers 1332, 1333. For example, such a further dielectric layer 1333 can be arranged between the at least two second boron nitride layers 1331, as shown in Figure 5. Fig. 5 is illustrated.

[0059] In yet another embodiment, the entire ILD structure 13 can consist of boron nitride. For example, such a configuration can have a horizontal cross-section, as in one of the Fig. 1-4 illustrates, exhibiting the ILD structure 13 being entirely formed by a boron nitride layer.

[0060] The in Fig. The illustrated embodiment in 6A differs from the one above with reference to Fig. The main difference in the examples discussed in 1-5 is that the gate electrode 143 does not have a planar configuration, but is arranged within a gate trench that extends vertically from the front surface 10-1 into the semiconductor body 10. The gate trench can, for example, exhibit a striped configuration or a cellular configuration with several separate trench cells having a rectangular or square outline.

[0061] A gate insulation stack 144 comprising a first boron nitride layer 1443, similar to the one described above with reference to Fig. The embodiment described in section 1 is arranged on the underside of the trench and on the trench side walls. In the illustrated embodiment from Fig. 6A A part of the gate insulation stack 144 extends above the gate electrode 143 and above a part of the front surface of the semiconductor body 10. For example, a (e.g. lateral) contact between the first boron nitride layer 1443 and the front metallization 11 can be established accordingly, as illustrated.

[0062] In one (not illustrated) embodiment, the power semiconductor device 1 can have a trench-gate configuration, as shown in Fig. Figure 6A illustrates the gate isolation layer 144 being similar to the one above with reference to Fig. The example described in point 3 can consist entirely of the first boron nitride layer 1443.

[0063] In another (not illustrated) variant, the power semiconductor device 1 can have a trench-gate configuration, as shown in Fig. Figure 6A illustrates the gate insulating layer 144 comprising the first boron nitride layer 1443, which is in contact with the semiconductor body 10, and a second dielectric layer 1442, which separates the first boron nitride layer 1443 from the gate electrode 143 and the ILD structure 13, similar to the one above with reference to Fig. The example described in section 4 can include.

[0064] Furthermore, as in Fig. As shown by way of example in Figure 6A, an ILD structure 13 may be arranged on the part of the gate insulation stack 144 that extends above the gate electrode. For example, one or more (such as at least two) second boron nitride layers 1331 may be integrated into the ILD structure 13, as shown above with reference to Fig. 5 was explained and in Fig. 6A is illustrated by way of example.

[0065] Fig. Figure 6B schematically and exemplarily illustrates a section of a vertical cross-section of a power semiconductor transistor 1 with a gate-trough configuration according to one or more further embodiments. Furthermore, some exemplary heat conduction paths during operation of the power semiconductor device 1 are shown. Thin arrows in Fig. Figure 6B indicates conventional heat dissipation paths through part of the semiconductor body 10. The thick arrows indicate additional heat dissipation paths provided by the boron nitride layer 1443.

[0066] At the in Fig. In the embodiment illustrated in Figure 6B, a portion of the boron nitride 1443 is arranged above the front surface 10-1, thus functionally replacing part of the ILD structure 13. As schematically illustrated by thick arrows, this can contribute to improved heat dissipation generated during operation at a hotspot H, which may be located adjacent to the gate trench at an interface between the first dielectric layer 1441 and the body region 142.

[0067] The following are exemplary examples of a method for forming a power semiconductor device comprising a gate insulation layer 144 which includes the first boron nitride layer 1443, with reference to Fig. 7A-H explained.

[0068] Embodiments of the method may correspond to the embodiments of the power semiconductor device 1 described above with reference to Fig. 1-6 was explained. Therefore, what was stated above can be applied equally / analogously to the power semiconductor device 1 and the method for forming a power semiconductor device 1 to form further embodiments.

[0069] Starting with Fig. In a first step, a semiconductor body 10 with a front side 10-1 and a back side 10-2 can be provided. For example, the semiconductor body 10 can be provided in the form of a wafer, such as a silicon or silicon carbide wafer substrate. The substrate 10 can have a base doping, such as an n - -base doping. For example, a part of the semiconductor body 10 may later form a drift region 100 of the processed power semiconductor device 1, wherein the drift region 100 may have the base doping.

[0070] In the next step ( Fig. 7B) A first dielectric layer 1441 can be deposited on a front surface of the semiconductor body 10. For example, the first dielectric layer 1441 can be formed by oxide deposition on the front surface.

[0071] Then a first boron nitride layer 1443 can be deposited on the first dielectric layer 1441 ( Fig. 7C). For example, the first boron nitride layer 1443 can include or consist of cubic boron nitride (cBN) and hexagonal boron nitride (hBN).

[0072] Both species of boron nitride, i.e., hBN and cBN, exhibit relatively high thermal conductivity. For example, cBN can have high thermal conductivity in all directions (i.e., isotropic), whereas hBN has very high thermal conductivity specifically for heat propagation within the layer, i.e., along a principal expansion direction X, Y of the first boron nitride layer 1443, and a somewhat lower thermal conductivity perpendicular to the principal expansion directions X, Y of the first boron nitride layer 1443 (i.e., along the vertical direction Z in the Fig. 7C). For example, these properties of hBN and / or cBN can be used to control the direction of heat flow. With state-of-the-art processes, cBN can be deposited more easily than hBN in trench structures.

[0073] For example, in one embodiment, cBN can be deposited using one or more of the following processes: a sputtering process using a boron or boron nitride target; a chemical vapor deposition (CVD) process using different gases; an atomic layer deposition (ALD) process.

[0074] In another embodiment, hBN can be deposited directly onto the first dielectric layer 1441, which may be an oxide, by means of a sputtering process using a boron or boron nitride target or by means of a CVD process. Alternatively, an auxiliary substrate, such as a metal foil, can be provided, and an hBN layer can be grown on the auxiliary substrate by means of a CVD process (not illustrated). The hBN layer can then be deposited onto the first dielectric layer 1441 or, if no first dielectric layer 1441 is provided (compare, for example, the examples from [reference]), Fig. 3 and Fig. 4) are transferred to the front surface of the semiconductor body 10.

[0075] Another variant for producing the first boron nitride layer 1443 in the form of an hBN layer is now described with reference to Fig. 7C(a)-7C(c) explained: First, a metal layer 2 is deposited on an oxide layer, such as the first dielectric layer 1441, see Fig. 7C(a). Then an hBN layer 1443 can be grown by means of a CVD process at an interface between the metal layer 2 and the oxide layer 1441, whereby another (upper) hBN layer 1444 can also be produced on the metal layer 2 during the CVD process step, see Fig. 7C(b). Subsequently, the metal layer 2 (as well as the upper hBN layer 1444 formed on the metal layer 2) can be removed, so that the hBN layer is exposed, which forms the first boron nitride layer 1443, see Fig. 7C(c).

[0076] It should be noted that in some embodiments, the boron nitride layer 1443 is structured in a horizontal plane XY, i.e., when viewed from above. In other words, the boron nitride layer 1443 does not have to extend continuously in the horizontal plane but may be interrupted. Furthermore, in one embodiment, the boron nitride layer 1443 may be formed such that it has small holes or depressions (not illustrated), so that the boron nitride layer 1443 is wedged between the dielectric layers 1441, 1442. As a result, the cohesion of the layer stack 1441, 1442, 1443 can be improved.

[0077] In a further step, as schematically shown in Fig. Figure 7D illustrates an example where a second dielectric layer 1442 can be formed on the first boron nitride layer 1443. For example, this step can be carried out by oxide deposition.

[0078] Then a gate electrode 143 can be formed on the stack of dielectric layers 1441, 1442, 1443. However, it should be noted that not all of the layers 1441, 1442, 1443 are necessarily required (see, for example, the examples according to Fig. 3 and Fig. 4) The production of the gate electrode 143 can, for example, involve the deposition and subsequent structuring of a polysilicon layer, as is generally well known in engineering.

[0079] In a further step, one or more dielectric layers can be deposited and then structured by means of an etching process to form the ILD structure 13 ( Fig. 7F-G). It should be noted that parts of the first boron nitride layer 1443 and (if present) of the first and second dielectric layers 1441, 1442 may also be removed from the semiconductor front surface during the etching process (or during one or more further etching processes) and that as a result, a (e.g. lateral) part of the first boron nitride layer may be exposed.

[0080] Furthermore, as in Fig. Figure 7H illustrates how the body regions 142 and the source regions 141 in the semiconductor layer 10 are generated by means of respective (masked) doping implantation steps. For example, in the case of a silicon-based power semiconductor device 1, such implantation steps can be performed after the formation of the ILD structure 13 according to Fig. 7G-H. However, in the case of a silicon carbide-based power semiconductor device 1, such implantation steps can be carried out in an earlier phase.

[0081] Finally, a metal can be deposited, forming the front face metallization 11, which may be in contact with, for example, the source regions 141, the body regions 142, and the first boron nitride layer 1443, see Fig. 1.

[0082] It should be noted that a power semiconductor device 1 with a trench-gate configuration, as exemplified in Fig. 6A-B is shown, with similar process steps to those above, with reference to Fig.7A-H illustrated. For example, in this case, the method can further comprise an initial etching process to form trenches in the semiconductor body 10. Then, a gate insulating layer 144, comprising or consisting of a first boron nitride layer 1443, can be deposited at least on the trench bottoms and trench sidewalls before the trenches are filled with a gate electrode material, such as polysilicon or metal, to form the gate electrode 143.

[0083] Above, embodiments relating to power semiconductor devices and corresponding processing methods have been explained.

[0084] These semiconductor devices are based, for example, on silicon (Si). Accordingly, a monocrystalline semiconductor region or layer, e.g., the semiconductor body 10 and its regions / zones, can be a monocrystalline Si region or Si layer. In other embodiments, polycrystalline or amorphous silicon can be used.

[0085] However, it is understood that the semiconductor body 10 and its regions / zones can be made of any semiconductor material suitable for manufacturing a semiconductor device. Examples of such materials include elemental semiconductor materials, such as silicon (Si) or germanium (Ge); group IV compound semiconductor materials, such as silicon carbide (SiC) or silicon germanium (SiGe); binary, ternary, or quaternary III-V semiconductor materials, such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN), or indium gallium arsenide phosphide (InGaAsP); and binary or ternary II-VI semiconductor materials, such as cadmium telluride (CdTe) and mercury cadmium telluride. (HgCdTe), to name just a few.The semiconductor materials mentioned above are also referred to as "homojunction semiconductor materials." When two different semiconductor materials are combined, a heterojunction semiconductor material is formed. Examples of heterojunction semiconductor materials include aluminum gallium nitride (AlGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminum gallium nitride (AlGaN), silicon-silicon carbide (Si. x C 1-x ) and silicon-SiGe heterojunction semiconductor materials. Si, SiC, GaAs, and GaN materials are currently the most commonly used for power semiconductor switching applications.

[0086] Spatially relative terms such as "under," "below," "lower," "above," "upper," and the like are used for the sake of simplicity to explain the positioning of one element relative to another. These terms are intended to encompass various orientations of the corresponding device, in addition to the different orientations depicted in the figures. Furthermore, expressions such as "first," "second," and the like are also used to describe different elements, areas, sections, etc., and these are likewise not intended to be restrictive. Throughout the description, identical terms refer to identical features.

[0087] As used here, the terms “indicating”, “containing”, “encompassing”, “showing”, and the like are open expressions that indicate the presence of the specified elements or features, but do not exclude any additional elements or features.

Claims

[1] Power semiconductor device (1) comprising the following: - a semiconductor body (10) having a front (10-1) and a back (10-2) and configured to conduct a load current between the front (10-1) and the back (10-2); and - several control cells (14) configured to control the load current, wherein each control cell (14) is at least partially contained in the semiconductor body (10) on the front side (10-1) and comprises a gate electrode (143) electrically insulated from the semiconductor body (10) by means of a gate insulating layer (144), wherein the gate insulating layer (144) comprises a first boron nitride layer (1443); and wherein an interlayer dielectric structure (13) is arranged at least partially between the gate electrode (143) and a front-side metallization (11) of the power semiconductor device (1), wherein the interlayer dielectric structure (13) is or comprises at least a second boron nitride layer (1331). [2] Power semiconductor device (1) according to claim 1, wherein the first boron nitride layer (1443) comprises cubic boron nitride and / or hexagonal boron nitride. [3] Power semiconductor device (1) according to one of the preceding claims, wherein the first boron nitride layer (1443) is arranged in contact with the semiconductor body (10). [4] Power semiconductor device (1) according to one of the preceding claims, wherein the first boron nitride layer (1443) is arranged in contact with the gate electrode (143). [5] Power semiconductor device (1) according to one of the preceding claims, wherein the first boron nitride layer (1443) is arranged in contact with a metal (11). [6] Power semiconductor device (1) according to one of the preceding claims, wherein the gate insulating layer (144) comprises a first dielectric layer (1441) which is arranged at least partially between the first boron nitride layer (1443) and the semiconductor body (10). [7] Power semiconductor device (1) according to claim 5, wherein a layer thickness (T1) of the first dielectric layer (1441) is in the range of 5 nm to 10 nm. [8] Power semiconductor device (1) according to one of the preceding claims, wherein the gate insulating layer (144) comprises a second dielectric layer (1442) which is arranged at least partially between the first boron nitride layer (1443) and the gate electrode (143). [9] Power semiconductor device (1) according to one of the preceding claims, wherein a layer thickness (T0) of the gate insulation layer (144) is in the range of 50 nm to 120 nm. [10] Power semiconductor device (1) according to claim 1, wherein the at least one second boron nitride layer (1.331) is arranged in contact with the front face metallization (11). [11] Power semiconductor device (1) according to one of the preceding claims, wherein the at least one second boron nitride layer (1331) extends mainly in a horizontal plane (XY). [12] Power semiconductor device (1) according to one of the preceding claims, wherein the interlayer dielectric structure (13) comprises at least two second boron nitride layers (1331), wherein another dielectric layer (1333) is arranged between the two second boron nitride layers (1331). [13] Power semiconductor device (1) according to any of the preceding claims, wherein the power semiconductor device (1) is or comprises an IGBT and / or a MOSFET. [14] Power semiconductor device (1) according to one of the preceding claims, wherein the semiconductor body (10) comprises silicon carbide. [15] Power semiconductor device (1) according to any of the preceding claims, wherein - the front (10-1) is coupled to a first load connection structure (11) and the back (10-2) is coupled to a second load connection structure (12); - the semiconductor body (10) includes a drift region (100) of a first conductivity type, wherein the drift region (100) is configured to conduct the load current between the first load terminal structure (11) and the second load terminal structure (12); and - each control cell (14) includes the following: ◯ a source region (141) of the first conductivity type, wherein the source region (141) is contained in the semiconductor body (10) and is electrically connected to the first load connection structure (11); ◯ a body region (142) of a second conductivity type, wherein the body region (142) is contained in the semiconductor body (10) and separates the source region (141) from the drift region (100); wherein the gate electrode (143) is configured to induce a conduction channel in the body region (142) depending on a control signal, the conduction channel extending from the source region (141) to the drift region (100). [16] Method for forming a power semiconductor device (1), wherein the power semiconductor device (1) comprises: - a semiconductor body (10) having a front (10-1) and a back (10-2) and configured to conduct a load current between the front (10-1) and the back (10-2); and - several control cells (14) configured to control the load current, each control cell (14) being at least partially contained in the semiconductor body (10) on the front side (10-1) and comprising a gate electrode (143) electrically insulated from the semiconductor body (10) by means of a gate insulating layer (144), wherein the gate insulating layer (144) is or comprises a first boron nitride layer (1443); wherein the process includes forming the first boron nitride layer (1443) by means of a deposition process, wherein an interlayer dielectric structure (13) is arranged at least partially between the gate electrode (143) and a front face metallization (11) of the power semiconductor device (1), wherein the interlayer dielectric structure (13) is or comprises at least a second boron nitride layer (1331). [17] Method according to claim 16, wherein the formation of the first boron nitride layer (1443) comprises at least one of the following: a chemical vapor deposition process; a sputtering process; an atomic layer deposition process. [18] Method according to claim 17, wherein forming the first boron nitride layer (1443) comprises: - Deposition of a metal layer (2) on an oxide layer (1441); - Growth, by means of a chemical vapor deposition process, of a hexagonal boron nitride layer (1443) at an interface between the metal layer (2) and the oxide layer (1441); and - Removal of the metal layer (2) so that the hexagonal boron nitride layer (1443) is exposed. [19] Method according to claim 17 or 18, wherein forming the first boron nitride layer (1443) comprises: - Providing an auxiliary substrate; - Growth of a hexagonal boron nitride layer (1443) on the auxiliary substrate by means of a chemical vapor deposition process; and - Transferring the hexagonal boron nitride layer (1443) to the semiconductor body (10) or to a dielectric layer (1441) formed on the semiconductor body (10).

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