TRANSISTORS WITH SEMICONDUCTOR STACKS AS CHANNELS AND MANUFACTURING METHODS

Abstract

A method for manufacturing a semiconductor device, comprising the steps of: depositing a first p-type semiconductor layer (34B) over a portion of a semiconductor substrate (20); depositing a first semiconductor layer (34C) over the first p-type semiconductor layer (34B), the first semiconductor layer (34C) not comprising any p-type dopants; forming a gate stack (68) directly over a first portion of the first semiconductor layer (34C); etching a second portion of the first semiconductor layer (34C) to create a trench (50) extending into the first semiconductor layer (34C), exposing at least a surface of the first p-type semiconductor layer (34B) to the trench;and forming a source / drain region (54) in the trench, the source / drain region (54) being n-type, the method comprising depositing a second semiconductor layer (34A) over the portion of the semiconductor substrate (20), the second semiconductor layer (34A) also not comprising p-type dopants, the second semiconductor layer (34A) being disposed beneath and in contact with the first p-type semiconductor layer (34B), and the etching further etching through the first p-type semiconductor layer (34B) and exposing a top surface of the second semiconductor layer (34A) to the trench (50);

Description

BackgroundAs integrated circuits continue to develop, the density of integrated circuit (IC) devices, such as transistors, is becoming higher and higher, and the devices are becoming smaller and smaller. This places higher demands on the performance of the IC devices. For example, leakage currents must be lower and drive currents must be higher.US 2017 / 0 098 692 A1 discloses a FinFET comprising a substrate, at least one fin and at least one gate, wherein the at least one fin comprises a seed layer, a stress relaxation layer and a channel layer from bottom to top, and wherein the at least one gate is arranged over the at least one fin. The document US 2014 / 0 008 700 A1 discloses a semiconductor device having active germanium layers which comprise underlying diffusion barrier layers. US 2012 / 0 056 275 A1 discloses a method for forming a semiconductor device, wherein a heavily doped region is formed in a substrate and an undoped or lightly doped intermediate layer is formed in recesses next to a channel and the heavily doped region. Source and drain regions are formed on the intermediate layer such that they are spaced from the heavily doped region by the intermediate layer. The document US 2014 / 0 001 571 A1 discloses a semiconductor structure including a first, second and third transistor element each having a first shielding region. A second shield region is formed in the second and third transistor elements, and at least one characteristic of the shield region in the second transistor element is different from that in the third transistor element. The properties include, for example, the doping concentration and the depth of the implantation.The invention is defined in the claims.Brief Description of the DrawingsAspects of the present invention can best be understood from the following detailed description taken in conjunction with the accompanying drawings. It should be noted that, in accordance with common practice in the industry, various elements are not drawn to scale. Rather, for clarity of discussion, the dimensions of the various elements may be arbitrarily increased or decreased.FIGS. 1-3, 4A, 4B, 5A, 5B, 6A, 6B, 7A, 7B, 8, 9, 10A, 10B, 11, 12A, and 12B are perspective and sectional views of the fabrication of transistors in accordance with some embodiments. FIG. 13 illustrates a process flow for manufacturing a transistor, in accordance with some embodiments.Detailed DescriptionThe following description provides many different embodiments or examples for implementing different features of the invention. Specific examples of components and arrangements will be described below to simplify the present invention. For example, the formation of a first element over or on a second element in the description below may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements are not in direct contact. Moreover, in the present invention, reference numerals and / or letters may be repeated in the various examples. This repetition is for convenience and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.Moreover, spatially relative terms such as "lower", "lower", "lower(r)" / "lower", "higher", "upper(r)" / "upper" and the like may be used herein to easily describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in another orientation) and the spatially relative descriptors used herein may also be interpreted accordingly.A transistor and a method for manufacturing the same are provided according to various embodiments. The intermediate stages in the fabrication of the transistor will be explained in accordance with some embodiments. In addition, some modifications of some embodiments are discussed. In all illustrations and illustrative embodiments, similar reference numerals are used to designate similar elements. In some embodiments of the present invention, a transistor includes one or more stacked silicon layers and p-type semiconductor layers, such as silicon-boron (SiB) layers, used to form a channel region of a corresponding transistor, such that leakage between a source region and a drain region is reduced. It should be understood that the fabrication of a fin field effect transistor is used merely as an example for explaining the principle of the present invention. Embodiments of the present invention may also be readily used for other types of transistors, such as planar transistors, gate-all-around (GAA) transistors, and the like. Although n-type transistors are discussed in the examples of embodiments, it should be appreciated that p-type transistors may also be fabricated by applying the principles of the present invention. The p-type transistors may be similar to the n-type transistors except that the p-type semiconductor layers in the semiconductor stack layers of the n-type transistors are replaced with n-type semiconductor layers, the p-type well region is replaced with an n-type well region, and n-type source / drain regions are replaced with p-type source / drain regions.FIGS. 1-3, 4A, 4B, 5A, 5B, 6A, 6B, 7A, 7B, 8, 9, 10A, 10B, 11, 12A, and 12B are perspective and cross-sectional views of fabricating n-type transistors, in accordance with some embodiments. The corresponding steps are also schematically indicated in the process flow 200 shown in FIG. 13.In FIG. 1, a substrate 20 is provided. The substrate 20 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p- or an n-dopant) or undoped. The semiconductor substrate 20 may be a part of a wafer 10, such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is provided on a substrate, usually a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, may also be used. In some embodiments, the semiconductor material of the semiconductor substrate 20 may include silicon; germanium; a compound semiconductor such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.Referring to FIG. 1, a well region 22 is formed in the substrate 20. The corresponding step is indicated as a step 202 in the process flow 200 shown in FIG. 13. In some embodiments of the present invention, well region 22 is a p-well region formed by implanting a p-type dopant such as boron, indium, or the like. The resulting well region 22 may extend from a top surface of the substrate 20. The p-type doping concentration may be equal to or less than 10 18 cm -3 and may be about 10 17 cm -3 to about 10 18 cm -3.In FIG. 2, isolation regions 24 are formed to extend from the top surface of the substrate 20 into the substrate 20. Isolation regions 24 are alternatively referred to below as shallow trench isolation (STI) regions. The corresponding step is indicated as a step 204 in the process flow 200 shown in FIG. 13. The portions of the substrate 20 between adjacent STI regions 24 are referred to as semiconductor strips 26. To form the STI regions 24, a pad oxide layer 28 and a hard mask layer 30 are formed on the semiconductor substrate 20, which are subsequently patterned. The pad oxide layer 28 may be a thin layer including silicon oxide. In some embodiments of the present invention, the pad oxide layer 28 is formed in a thermal oxidation process in which a surface layer of the semiconductor substrate 20 is oxidized. The pad oxide layer 28 functions as an adhesion layer between the semiconductor substrate 20 and the hard mask layer 30. the pad oxide layer 28 may also function as an etch stop layer for etching the hard mask layer 30. In some embodiments of the present invention, the hard mask layer 30 is formed of silicon nitride, for example, by low pressure chemical vapor deposition (LPCVD). In other embodiments of the present invention, the hard mask layer 30 is formed by thermal nitriding of silicon or by plasma enhanced chemical vapor deposition (PECVD). A patterned photoresist (not shown) is formed on the hard mask layer 30. Then, the hard mask layer 30 is patterned using the patterned photoresist as an etching mask to form patterned hard masks 30, as shown in FIG. 2.Then, the patterned hard mask layer 30 is used as an etch mask for etching the pad oxide layer 28 and the substrate 20, and then the resulting trenches in the substrate 20 are filled with one or more dielectric materials. A planarization process, such as a chemical mechanical polishing (CMP) process or a mechanical grinding process, is then performed to remove excess portions of the dielectric materials, and the remaining portions of the dielectric materials are the STI regions 24. The dielectric liner may also be a deposited silicon oxide layer, silicon nitride layer, or the like, formed by atomic layer deposition (ALD), high density plasma chemical vapor deposition (HDP-CVD), or chemical vapor deposition (CVD), for example. The STI regions 24 may also include a dielectric material over the oxide liner, where the dielectric material may be deposited by flowable chemical vapor deposition (FCVD), spin coating, or the like. In some embodiments, the dielectric material over the dielectric liner may be silicon oxide.In some embodiments of the present invention, bottom portions of well region 22 are lower than bottom surfaces of STI regions 24, and thus semiconductor strips 26 are portions of well region 22 and are doped with the p-type dopant to form well region 22.In a later process, the pad oxide layer 28 and the hard mask layer 30 are removed. As shown in FIG. 3, the semiconductor strips 26 are then recessed, resulting in trenches 32 between adjacent STI regions 24. The corresponding step is indicated as a step 206 in the process flow shown in FIG. 13. In some embodiments of the present invention, the recessing is performed by dry etching. The dry etching may be performed using an etching gas selected from the group consisting of C 2 F 6, CF 4, SO 2, a mixture of HBr, Cl 2 and O 2, a mixture of HBr, Cl 2 and O 2 or a mixture of HBr, Cl 2, O 2 and CF2, or the like. In alternative embodiments, the etch is performed with a wet etching process using KOH, tetramethylammonium hydroxide (TMAH), CH 3 COOH, NH 4 OH, H 2 O 2, isopropanol (IPA), a solution of HF, HNO 3 and H 2 O, or the like as the etchant. In some embodiments, the bottom portions of the trenches 32 are higher than the bottom surfaces of the STI regions 24.FIG. 4A illustrates the formation of semiconductor stack layers 34 (details of which are shown in FIG. 4B ) formed by selective epitaxial growth (SEG). The semiconductor stack layers 34 are formed in the trenches 32 as shown in FIG. 3. The corresponding step is indicated as a step 208 in the process flow shown in FIG. 13. In some embodiments of the present invention, the semiconductor stack layers 34 include a plurality of stack layers including at least two and optionally more silicon layers and at least one and optionally more p-type epitaxial layers (such as SiB layers) discussed with reference to FIG. 4B. The epitaxially grown semiconductor layers may be grown to a level higher than the tops of the STI regions 24. In a later step, a planarization process, such as a CMP process or a mechanical grinding process, is performed to remove excess portions of the grown semiconductor materials, forming the structure shown in FIGS. 4A and 4B.FIG. 4B shows the reference cross-section 4B- 4B of FIG. 4A, except that the details of the semiconductor stack layers 34 are shown. In some embodiments of the present invention, a silicon layer 34A is first epitaxially grown. The thickness of the silicon layer 34A may be about 1 nm to about 5 nm. In some embodiments of the present invention, silicon layer 34A is an intrinsic layer that is intentionally doped with neither a p-type dopant nor an n-type dopant. In alternative embodiments of the present invention, silicon layer 34A is doped with a p-type dopant, such as boron, indium, or the like, at a dopant concentration that is at least one order of magnitude, or two or more orders of magnitude lower than the p-type dopant concentration of an overlying p-type semiconductor layer 34B. Accordingly, silicon layer 34A, when doped with a p-type dopant, may have a doping concentration that is less than about 10 17 cm -3 or less than about 10 16 cm -3 or even less. In other embodiments, layer 34A may be made of other semiconductor materials, such as silicon germanium, silicon carbon, or the like, which may be intrinsic layers that are undoped or lightly doped with p- or n-type dopants.The p-type semiconductor epitaxial layer 34B is epitaxially grown on the silicon layer 34A. In some embodiments of the present invention, the p-type semiconductor layer 34B includes silicon and a p-type dopant such as boron, indium, or the like. The p-type semiconductor layer 34B may be, for example, a silicon boron (SiB) layer. The p-type dopant is doped in situ with the progress of epitaxy of the p-type semiconductor layer 34B. The concentration of the p-type dopant in the p-type semiconductor layer 34B may not be too high, as this may result in the p-type dopant being undesirably diffused into the underlying silicon layer 34A and an overlying silicon layer 34C, which would result in an undesirable degradation in the ability to prevent leakage. The p-type doping concentration in the p-type semiconductor layer 34B may be lower than about 5×10 20 cm -3 or lower than about 1×10 19 cm -3. However, the p-type impurity concentration in the p-type semiconductor layer 34B may not be too low because the p-type impurity in the p-type semiconductor layer 34B generates holes, and if the p-type impurity concentration is too low, the number of holes generated becomes too low, which would again result in undesirable deterioration of leakage prevention performance. The p-type doping concentration in the p-type semiconductor layer 34B may be, for example, about 5×10 17 cm -3 to about 5×10 20 cm -3 or about 1×10 18 cm -3 to about 1×10 19 cm -3. In some embodiments, the p-type semiconductor layer 34B does not include germanium, carbon, or the like. In alternative embodiments, the p-type semiconductor layer 34B includes silicon and an element selected from the group consisting of germanium, carbon, or the like. The thickness of the p-type semiconductor layer 34B may be about 1 nm to about 15 nm.Over the p-type semiconductor layer 34B, another silicon layer 34C is epitaxially grown. In some embodiments of the present invention, silicon layer 34C is an intrinsic layer that is intentionally doped with neither a p-type dopant nor an n-type dopant. In alternative embodiments of the present invention, silicon layer 34C is doped with a p-type dopant, such as boron, indium, or the like, at a dopant concentration that is at least one order of magnitude, or two or more orders of magnitude lower than the p-type dopant concentration of underlying p-type semiconductor layer 34B. Accordingly, silicon layer 34C, when doped with a p-type dopant, may have a doping concentration that is less than about 10 17 cm -3 or less than about 10 16 cm -3 or even less. Depending on whether or not further semiconductor epitaxial layers 34D and 34E are formed over the silicon layer 34C, the thickness of the silicon layer 34C may be about 14 nm to about 51 nm.In some embodiments of the present invention, the epitaxial process is terminated after the formation of the silicon layer 34C, and no further semiconductor layer is epitaxially grown over the silicon layer 34C. In alternative embodiments of the present invention, a p-type semiconductor epitaxial layer 34D continues to be grown over the silicon layer 34C, but no further semiconductor layer is epitaxially grown over the p-type semiconductor epitaxial layer 34D. In still further alternative embodiments of the present invention, a p-type semiconductor epitaxial layer 34D is grown over the silicon layer 34C, and a silicon layer 34E is further grown over the p-type semiconductor epitaxial layer 34D. Accordingly, the p-type semiconductor epitaxial layer 34D and the silicon layer 34E are illustrated with broken lines to indicate that they may or may not be formed.The p-type semiconductor epitaxial layer 34D (if formed) is epitaxially grown on the silicon layer 34C. In some embodiments of the present invention, the p-type semiconductor epitaxial layer 34D includes silicon and a p-type dopant, such as boron, indium, or the like. The p-type semiconductor epitaxial layer 34D may be, for example, a SiB layer. The p-type dopant is doped in situ with the progress of epitaxy of the p-type semiconductor epitaxial layer 34D. Here too, the concentration of the p-type dopant in the p-type semiconductor layer 34D may not be too high or too low. Otherwise, the electron-hole recombination function of the p-type semiconductor epitaxial layer is impaired. In some embodiments of the present invention, the p-type doping concentration in the p-type semiconductor layer 34D is about 5×10 17 cm -3 to about 5×10 20 cm -3 or about 1×10 18 cm -3 to about 1×10 19 cm -3. In some embodiments, the p-type semiconductor layer 34D does not include germanium, carbon, or the like. The thickness of the p-type semiconductor layer 34D may be about 1 nm to about 15 nm.Over the p-type semiconductor epitaxial layer 34D, another silicon layer 34E may be epitaxially grown, or the formation of the silicon layer 34E may be omitted. In some embodiments of the present invention, silicon layer 34E is an intrinsic layer that is intentionally doped neither with a p-type dopant nor with an n-type dopant. In alternative embodiments of the present invention, silicon layer 34E is doped with a p-type dopant, such as boron, indium, or the like, at a dopant concentration that is at least one order of magnitude, or two or more orders of magnitude lower than the p-type dopant concentration of underlying p-type semiconductor epitaxial layers 34B and 34D. Accordingly, silicon layer 34E, when doped with a p-type dopant, may have a doping concentration that is less than about 10 17 cm -3 or less than about 10 16 cm -3 or even less. The silicon layer 34E (if formed) may be used as a buffer layer for the planarization process (FIG. 4A ) and to protect the underlying p-type semiconductor epitaxial layer 34D from planarization. The thickness of the silicon layer 34E may be small, and may be set as small as possible as long as it can protect the p-type semiconductor epitaxial layer 34D with a corresponding process margin from being planarized. In some embodiments of the present invention, the thickness of the silicon layer 34E is about 1 nm to about 5 nm.In FIG. 5A, the STI regions 24 are then recessed such that at least the top portions of the semiconductor stack layers 34 protrude above top surfaces of adjacent STI regions 24. The corresponding step is indicated as a step 210 in the process flow shown in FIG. 13. Additionally, the STI regions 24 may have a planar top surface as shown, a convex top surface, a concave top surface (such as dishing), or a combination thereof. The top surfaces of the STI regions 24 may be formed planar, convex, and / or concave with a corresponding etch. The STI regions 24 may be recessed with a suitable etching process using an etchant that attacks the STI regions 24, but not the semiconductor layers 34. For example, if wet etching is used, the etchant may be dilute hydrofluoric acid (dHF acid). When dry etching is used, a mixture of NF 3- and NH 3- gases or a mixture of HF and NH 3- gases may be used. Those portions of the semiconductor material that are higher than the tops of the STI regions 24 are referred to as protruding fins 36.FIG. 5B shows the reference cross-section 5B- 5B of FIG. 5A, except that the details of the semiconductor stack layers 34 are shown. Since the STI regions 24 are not in the plane shown, they are not shown in FIG. 5B. The levels of tops 24A and bottoms 24B of STI regions 24 are shown to show the level of STI regions 24. In some embodiments of the present invention, the top surfaces 24A of the STI regions 24 are at an intermediate level between the top and bottom surfaces of the silicon layer 34A. In alternative embodiments, the top surfaces 24A of the STI regions 24 are level with the top surface of the silicon layer 34A. The top surfaces 24A of the STI regions 24 may also be level with and lower than the bottom surface of the silicon layer 34A.In the embodiments discussed above, the fins may be formed using any suitable method. For example, the fins may be patterned using one or more photolithography processes, such as dual-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes that can produce patterns having, for example, pitch spacings that are less than those that can otherwise be achieved with a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate, which is then patterned using a photolithography process. Spacers are produced along the structured sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers, or mandrels, may then be used to pattern the fins.In FIG. 6A, dummy gate stacks 38 are formed to extend on top and sidewalls of (protruding) fins 36. The corresponding step is indicated as a step 212 in the process flow shown in FIG. 13. Dummy gate stacks 38 may include dummy gate dielectrics 40 and dummy gate electrodes 42 over dummy gate dielectrics 40. Dummy gate electrodes 42 may be formed using polysilicon, for example, but other materials may be used. The dummy gate stacks 38 may each include one or more hard mask layers 44 over the dummy gate electrodes 42. The hard mask layers 44 may be made of silicon nitride, silicon oxide, silicon carbonitride, or multilayers thereof. Dummy gate stacks 38 may traverse one or more protruding fins 36 and / or STI regions 24. The dummy gate stacks 38 may also have longitudinal directions that are perpendicular to the longitudinal directions of the protruding fins 36.Then, gate spacers 46 are formed on the sidewalls of the dummy gate stacks 38. The corresponding step is also indicated as the step 212 in the process flow shown in FIG. 13. In some embodiments of the present invention, the gate spacers 46 are made of one or more dielectric materials such as silicon nitride, silicon carbonitride, or the like, and may have a single-layer or a multilayer structure including a plurality of dielectric layers. FIG. 6B shows the reference cross section 6B- 6B of FIG. 6A. It should be appreciated that layers 34D and 34E may or may not be formed and gate stack 38 may have a bottom surface contacting the top surface of silicon layer 34E, p-type semiconductor epitaxial layer 34D, or silicon layer 34C.Then, an etching process is performed to recess the portions of the semiconductor stack layers 34 not covered by the dummy gate stacks 38 and the gate spacers 46, thereby forming the structure shown in FIG. 7A. The corresponding step is indicated as a step 214 in the process flow shown in FIG. 13. The recessing may be anisotropic, and thereby the portions of the fins 36 directly below the dummy gate stacks 38 and the gate spacers 46 are protected and are not etched. The tops of the recessed semiconductor stack layers 34 may be lower than the tops 24A of the STI regions 24 in some embodiments. Thereby, recesses 50 are formed. the recesses 50 include portions located on opposite sides of the dummy gate stacks 38 and portions between remaining portions of the protruding fins 36.FIG. 7B shows the reference cross section 7B- 7B of FIG. 7A. In some embodiments of the present invention, the lower parts of the recesses 50 are at the bottom level of the p-type semiconductor epitaxial layer 34B, and thus the recesses 50 penetrate the p-type semiconductor epitaxial layer 34B. The sidewalls of the remaining portions of the p-type semiconductor epitaxial layer 34B are exposed to the recesses 50. In alternative embodiments, the bottom portions of the recesses 50 are at the top level of the p-type semiconductor epitaxial layer 34B, and the top of the p-type semiconductor epitaxial layer 34B is exposed. In further alternative embodiments, the bottom portions of the recesses 50 are at a level between the top level and the bottom level of the p-type semiconductor epitaxial layer 34B. Additionally, the bottom surfaces of the recesses 50 may be at a level between the top surfaces and the bottom surfaces of the STI regions 24. The bottom surfaces of the recesses 50 may also be higher or lower than the top surfaces of the STI regions 24. Dashed lines 52 indicate the likely positions of the bottom surfaces of the recesses 50. Preferably, the recesses 50 should not penetrate through the silicon layer 34A such that the implanted well region 22 is not exposed to the recesses 50, and the later-formed source / drain regions 54 (FIG. 8 ) should be spaced apart from the implanted well region 22 that has more defects than the semiconductor epitaxial layers 34 and thus has a higher junction creep current.Then, an epitaxial process is performed to form epitaxial regions 54 that are selectively grown by the recesses 50, thereby forming the structure shown in FIG. 8. The corresponding step is indicated as a step 216 in the process flow shown in FIG. 13. In some embodiments, the epitaxial regions 54 include SiP, SiCP, SiC, or the like, and may have a lattice constant smaller than that of silicon. In some embodiments of the present invention, an n-type dopant such as phosphorus, indium, antimony, or the like is in situ doped into the epitaxy regions 54 as epitaxy proceeds. After the epitaxy regions 54 completely fill the recesses 50, the epitaxy regions 54 begin to expand horizontally and slopes may be formed. Adjacent epitaxial regions 54 begin to merge with each other. This creates an integrated epitaxial region 54. the top side of the source / drain regions 54 may be higher than the bottom sides of the gate spacers 46.Cavities (air gaps) 56 may be created. In some embodiments of the present invention, the formation of the epitaxy regions 54 is terminated when the tops of the epitaxy regions 54 are still wavy (FIG. 8 ) or when the tops of the merged epitaxy regions 54 have become planar (FIG. 9 ), which is achieved by further growth on the epitaxy regions 54 as shown in FIG. 8. After the epitaxy regions 54 are formed, an implantation process may be performed to implant an n-type dopant into the epitaxy regions 54 to form source / drain regions, also referred to as source / drain regions 54. In alternative embodiments where an n-type dopant has been implanted in situ, the implantation process is omitted.FIG. 10A is a perspective view of the structure after formation of a contact etch stop layer (CESL) 58 and an interlayer dielectric (ILD) 60 The corresponding step is indicated as a step 218 in the process flow shown in FIG. 13. The CESL 58 may be made of silicon oxide, silicon nitride, silicon carbonitride, or the like by CVD, ALD, or the like. The ILD 60 may be a dielectric material formed by, for example, FCVD, spin coating, CVD, or other deposition process. The ILD 60 may be made of an oxygen-containing dielectric material, which may be a silicon oxide-based material, such as a TEOS (tetraethyl orthosilicate) oxide, a PECVD (SiO 2), phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), or the like. A planarization process, such as a CMP process or a mechanical grinding process, may be performed to level the tops of the ILD 60, the dummy gate stacks 38, and the gate spacers 46 with each other.FIG. 10B shows the reference cross section 10B- 10B of FIG. 10A. As shown in FIG. 10B, the source / drain regions 54 are in contact with at least the p-type semiconductor epitaxial layer 34B. For example, depending on whether or not the source / drain regions 54 penetrate the p-type semiconductor epitaxial layer 34B, the source / drain regions 54 may be in contact with the top surface and / or the sidewall of the p-type semiconductor epitaxial layer 34B. The source / drain regions 54 may also be in contact with the sidewalls of the silicon layer 34C, and may be in contact with the sidewalls of the p-type semiconductor epitaxial layer 34D and the silicon layer 34E, if formed. The source / drain regions 54 may be in contact with and may or may not extend into the silicon layer 34A. As the source / drain regions 54 extend into the silicon layer 34A, they cannot penetrate through the silicon layer 34A.In some embodiments, the p-type semiconductor epitaxial layer 34B is close to the bottom of the source / drain regions 54. for example, a depth D 1 of the top of the p-type semiconductor epitaxial layer 34B may be greater than about 80% of a depth D 2 of the source / drain regions 54, where the depths D 1 and D 2 are measured from the bottom of the gate spacers 46. A ratio D 1 / D 2 may be up to 100%, which means that the bottom surfaces of the source / drain regions 54 are in contact with the top surface of the p-type semiconductor epitaxial layer 34B. Disposing the p-type semiconductor epitaxial layer 34B close to the bottom surfaces of the source / drain regions 54 has a higher effect in improving the DIBL (Drain-Induced Barrier Sinking) behavior of the respective transistor than disposing the p-type semiconductor epitaxial layer 34B at a higher position.Then, the dummy gate stacks 38 including the hard mask layers 44, the dummy gate electrodes 42, and the dummy gate dielectrics 40 are replaced with replacement gate stacks 68 (see FIG. 11 ) including metal gates 66 and gate dielectrics 64. The corresponding step is indicated as a step 220 in the process flow shown in FIG. 13. When the replacement gate stacks 68 are formed, the hard mask layers 44, dummy gate electrodes 42, and dummy gate dielectrics 40 shown in FIGS. 10A and 10B are first removed in one or more etch steps, forming trenches / openings between the gate spacers 46. The upper surfaces and the side walls of the protruding semiconductor fins 36 are exposed to the resultant trenches.As shown in FIG. 10B, after exposing the dummy gate stacks 38, the semiconductor stack layers 34 are exposed to the resulting trenches. In some cases, the removal of the dummy gate stacks 38 may not end on top of the top silicon layer [ 34E (if manufactured), or 34C if 34E and 34D are not manufactured]. When this occurs, the resulting recess in the semiconductor layers 34 may extend laterally to the source / drain regions 54, so that there is a risk that gate electrodes 66 produced later may be electrically short-circuited to the source / drain regions 54 or high leakage currents may occur between them. This effect is referred to as metal gate extrusion, which may cause device failure. The p-type semiconductor epitaxial layer 34D formed close to the top surface of the semiconductor stack layers 34 may function as an etch stop layer when the silicon layer 34E is etched through, because the etch rate of the p-type semiconductor epitaxial layer 34D is lower than the etch rate of the silicon layer 34E when a suitable etchant is used.After the dummy gate stacks 38 are removed, dielectric (replacement) gate layers 64 are formed that extend into the trenches between the gate spacers 46. In some embodiments of the present invention, the gate dielectric layers 64 each have an interfacial layer (IL) as its lower portion contacting the exposed surfaces of the corresponding protruding fins 36. The IL may be an oxide layer, such as a silicon oxide layer, formed by thermal oxidation of the protruding fins 36, a chemical oxidation process, or a deposition process. The gate dielectric layer 64 may also be a high-k dielectric layer formed over the IL. The high-k dielectric layer may include a high-k dielectric material, such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, silicon nitride, or the like. The dielectric constant (k-value) of the high-k dielectric material is higher than 3.9 and may be higher than about 7.0. The high-k dielectric layer is formed as a conformal layer and extends on the sidewalls of the protruding fins 36 and the sidewalls of the gate spacers 46.In FIG. 11, gate electrodes 66 are formed over the gate dielectrics 64, the gate electrodes 66 having conductive sub-layers. The sub-layers are not shown individually, but they are distinguishable from each other. The deposition of the sub-layers can be carried out using a conformal deposition method such as ALD or CVD.The conductive stack layers may include a diffusion barrier layer and one or more work function layers over the diffusion barrier layer. The diffusion barrier layer may be made of titanium nitride (TiN), which may (or may not) be doped with silicon. The work function layer (schematically illustrated as 66A in FIG. 12B ) determines the work function of the gate and includes at least one layer or a plurality of layers made of different materials. The work function layer 66A may be a titanium aluminum (TiAl) layer. After the deposition of the one or more work function layers, a barrier layer is formed, which may be another TiN layer.The gate dielectric layers and conductive layers to be deposited are formed as conformal layers that extend into the trenches between the gate spacers 46, and have some portions over the ILD 60. Then, a metallic material is deposited to fill the remaining trenches between the gate spacers 46. The metallic material may be, for example, tungsten or cobalt. In a later step, planarization, such as a CMP process or a mechanical grinding process, is performed to remove the portions of the gate dielectric layers, the conductive sub-layers, and the metallic material that are over the ILD 60. This results in the metal gate electrodes 66 and the gate dielectrics 64 The gate electrodes 66 and the gate dielectrics 64 are collectively referred to as replacement gate stacks 68. At this time, the tops of the replacement gate stacks 68, the gate spacers 46, the CESL 58, and the ILD 60 may be substantially coplanar.FIG. 11 also illustrates the formation of hard masks 70 in accordance with some embodiments. The formation of the hard masks 70 may include the steps of: performing an etching step to recess the replacement gate stacks 68 to form recesses between the gate spacers 46; filling the recesses with a conductive material; and subsequently performing a planarization process, such as a CMP process or a mechanical grinding process, to remove excess portions of the dielectric material. The hard masks 70 may be made of silicon nitride, silicon oxynitride, silicon oxycarbonitride, or the like.FIG. 12A illustrates the formation of source / drain pins 72. The formation of the source / drain contact pins 72 includes etching the ILD 60 to expose the underlying portions of the CESL 58 and then etching the exposed portions of the CESL 58 to expose the epitaxy regions 54. In a subsequent process, a metal layer (such as a Ti layer) is deposited to extend into the contact openings. In addition, a metal nitride capping layer may be formed. Then, an annealing process is performed to react the metal layer with the upper portion of the source / drain regions 54 to form silicide regions 74, as shown in FIGS. 12A and 12B. Then, the previously prepared metal nitride layer either remains, or is removed, and a new metal nitride layer (such as a titanium nitride layer) is deposited. Then, a metallic filler material such as tungsten, cobalt, or the like is filled into the contact holes, followed by planarization to remove excess materials, thereby forming the source / drain contact pins 72. Accordingly, the source / drain contact pins 72 include the remaining portions of the metal layer, the metal nitride layer, and the metal fill material. In addition, gate contact pins (not shown) are formed to penetrate a part of each of the hard masks 70 to contact the gate electrodes 66. This results in FinFETs 78, which may be connected in parallel as a single FinFET.FIG. 12B shows the reference cross section 12B- 12B of FIG. 12A. As shown in FIG. 12B, gate stacks 68 are disposed over the semiconductor stack layers 34, functioning as channels of the FinFET 78. Currents can flow in the semiconductor stack layers 34, both in the p-type semiconductor epitaxial layers (34B and 34D) and in the silicon layers (34A, 34C and 34E). Depending on whether or not the p-type semiconductor epitaxial layer 34D and the silicon layer 34E are formed, the gate stacks 68 may be in contact with the silicon layer 34C, the p-type semiconductor epitaxial layer 34D, or the silicon layer 34E.The embodiments of the present invention have several advantages. By forming a p-type semiconductor epitaxial layer at a level near the bottom level of source / drain regions, electrons leaking between source and drain regions can recombine with holes of the p-type semiconductor epitaxial layer, so that leakage loss is reduced and DIBL performance is improved. By forming a p-type semiconductor epitaxial layer at a level near the top level of source / drain regions, the p-type semiconductor epitaxial layer can function as an etch stop layer and has a function of preventing metal gate extrusion. This improves the production yield.

Claims

A method of manufacturing a semiconductor device, comprising: depositing a first p-type semiconductor layer (34B) over a portion of a semiconductor substrate (20); depositing a first semiconductor layer (34C) over the first p-type semiconductor layer (34B), the first semiconductor layer (34C) having no p-type dopants; forming a gate stack (68) directly over a first portion of the first semiconductor layer (34C); etching a second portion of the first semiconductor layer (34C) to create a trench (50) extending into the first semiconductor layer (34C), at least a surface of the first p-type semiconductor layer (34B) being exposed to the trench; and forming a source / drain region (54) in the trench, wherein the source / drain region (54) is n-type, the method comprising depositing a second semiconductor layer (34A) over the portion of the semiconductor substrate (20), wherein the second semiconductor layer (34A) also does not comprise p-dopants and the second semiconductor layer (34A) is arranged under and in contact with the first p-semiconductor layer (34B), and wherein in the etching the first p-semiconductor layer (34B) is further etched through and a top surface of the second semiconductor layer (34A) is exposed to the trench (50).The method of claim 1, wherein the first p-type semiconductor layer (34B) comprises a silicon-boron layer, hereinafter referred to as a SiB layerThe method of claim 2, wherein a p-type doping concentration in the p-type semiconductor layer (34B) is about 5×10 17 cm -3 to about 5×10 20 cm -3 or about 1×10 18 cm -3 to about 1×10 19 cm -3.The method of claim 2 or 3, wherein a bottom surface of the trench (50) is higher than a bottom surface of the second semiconductor layer (34A).The method of any preceding claim, wherein the etching terminates on a top surface of the first p-type semiconductor layer (34B).The method of any preceding claim, further comprising depositing a second p-type semiconductor layer (34D) over the first semiconductor layer (34C).The method of claim 6, further comprising depositing a second semiconductor layer (34E) over the second p-type semiconductor layer (34D), wherein the second semiconductor layer (34E) does not have p-type dopants.The method of claim 7, further comprising forming a gate dielectric (64) over and in contact with the second semiconductor layer (34E).The method of claim 7 or 8, further comprising etching a dummy gate stack (38) over the second semiconductor layer (34E), wherein the second semiconductor layer (34E) is etched through and the etching ends on a top surface of the second p-type semiconductor layer (34D).The method of any preceding claim, wherein the first p-type semiconductor layer (34B) further does not include n-type dopants.A method of manufacturing a semiconductor device, comprising the steps of: forming isolation regions (24) to extend into a semiconductor substrate (20); etching to remove a portion of the semiconductor substrate (20) between the isolation regions (24) to create a trench (32); performing a first epitaxy to grow a first semiconductor layer (34A) in the trench (32), the first semiconductor layer (34A) having no p-type dopants and no n-type dopants; performing a second epitaxy to grow a first SiB layer (34B) over and in contact with the first semiconductor layer (34A); Performing a third epitaxy to grow a second semiconductor layer (34C) over the first SiB layer (34B), wherein the second semiconductor layer (34C) does not include p-type dopants and n-type dopants; and recess the isolation regions (24) such that the second semiconductor layer (34C) and a portion of the first SiB layer (34B) are higher than tops of the isolation regions (24) to form a semiconductor fin (36).The method of claim 11, wherein in the recessing of the isolation regions (24), a first portion of the first semiconductor layer (34A) is higher than the tops of the isolation regions (24) to form a portion of the semiconductor fin (36).The method of claim 11 or 12, wherein in the recessing of the isolation regions (24), a second portion of the first semiconductor layer (34A) is lower than the tops of the isolation regions (24).The method of any of claims 11 to 13, the method further comprising: forming a gate stack (68) to cover a first portion of the first semiconductor layer (34A); performing an etching process using the gate stack (68) as a portion of an etch mask to form a further trench (50), wherein the etching process includes etching through the second semiconductor layer (34C) and exposing a surface of the first SiB layer (34B) to the further trench (50); and forming a source / drain region (54) in the further trench (50), wherein the source / drain region (54) is n-type.The method of any of claims 11 to 14, further comprising: performing a fourth epitaxy to grow a second SiB layer (34D) over the second semiconductor layer (34C); and performing a fifth epitaxy to grow a third semiconductor layer (34E) over the second SiB layer (34D), wherein the third semiconductor layer (34E) does not have p-type dopants and n-type dopants.A semiconductor device comprising: isolation regions (24) extending into a semiconductor substrate (20); a semiconductor fin (36) between the isolation regions (24), the semiconductor fin (36) being higher than tops of the isolation regions (24), and comprising: a first semiconductor layer (34A), the first semiconductor layer (34A) having no p-type dopants, and a first p-type semiconductor layer (34B) over and in contact with the first semiconductor layer (34A); a further semiconductor layer (34C) over the first p-type semiconductor layer (34B); a gate stack (68) on the semiconductor fin (36); and a source / drain region (54) extending into the semiconductor fin (36), the source / drain region (54) contacting the first p-type semiconductor layer (34B) and being an n-type region, the source / drain region (54) penetrating the first p-type semiconductor layer (34B), and the source / drain region (54) contacting a sidewall of the first p-type semiconductor layer (34B).The semiconductor device of claim 16, wherein the source / drain region (54) has a bottom surface contacting a top surface of the first p-type semiconductor layer (34B).The semiconductor device according to claim 16 or 17, wherein the first p-type semiconductor layer (34B) comprises a silicon-boron layer, hereinafter referred to as a SiB layerThe semiconductor device of any of claims 16 to 18, wherein the semiconductor fin (36) further comprises a second semiconductor layer (34C) over and in contact with the first p-type semiconductor layer (34B), wherein the second semiconductor layer (34C) does not comprise p-type dopants and n-type dopants.The semiconductor device of claim 19, wherein the semiconductor fin (36) further comprises: a second p-type semiconductor layer (34D) over and in contact with the second semiconductor layer (34C); and a third semiconductor layer (34E) over and in contact with the second p-type semiconductor layer (34E), wherein the third semiconductor layer (34E) does not comprise p-type dopants and n-type dopants.

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