Integrated chip and method of forming an integrated chip

Abstract

Integrated chip (100) comprising: a plurality of lower interconnect layers (108) disposed within a lower dielectric structure (106) over a substrate (102); a lower insulating structure (110) disposed over the lower dielectric structure (106) and having sidewalls (110s) extending through the lower insulating structure (110); a lower electrode (114) disposed along the sidewalls and an upper surface of the lower insulating structure (110), the upper surface of the lower insulating structure extending past outermost sidewalls of the lower electrode (114); a data storage structure (116) disposed on the lower electrode (114), the data storage structure (116) comprising a ferroelectric material and configured to store a data state; an upper electrode (118) disposed on the data storage structure (116); and a hard mask (120) disposed over the upper electrode (118), and an upper interconnect structure (128) extending through the hard mask (120) to the upper electrode (118), wherein the lower electrode (114) has inner sidewalls (114s) coupled to a horizontally extending surface for defining a cutout (115) within an upper surface (114u) of the lower electrode (114), the horizontally extending surface (114h) of the lower electrode (114) underlying the upper surface (110u) of the lower insulating structure (110); wherein the upper electrode (118) has inner sidewalls coupled to a horizontally extending surface for defining a second cutout within an upper surface of the upper electrode (120), wherein the hard mask (120) is arranged along the inner side walls, the horizontally extending surface and the uppermost surface of the upper electrode (120), wherein the upper interconnect structure (128) contacts the upper electrode (118) at a position laterally spanning an outer edge of the upper surface (114u) of the lower electrode (114).

Description

GENERAL STATE OF THE ART

[0001] Many modern electronic devices include electronic memory configured to store data. Electronic memory can be volatile memory or non-volatile memory. Volatile memory stores data when powered, while non-volatile memory is capable of storing data even when the power supply is disconnected. Ferroelectric random access memory (FeRAM) devices are a promising candidate for next-generation non-volatile memory technologies. This is because FeRAM devices offer many advantages, including fast writing, high robustness, low power consumption, and low susceptibility to radiation damage.

[0002] US 6 777 739 B2 relates to a capacitor comprising an electrode having at least one layer comprising a platinum-rhodium material and at least one non-oxide layer comprising a platinum material on and in direct contact with the platinum-rhodium layer.

[0003] EP 2 903 025 A1 relates to a semiconductor device comprising a semiconductor substrate having an impurity region, an interlayer insulating film formed on top of the semiconductor substrate, and a conductive plug formed through the interlayer insulating film and electrically connected to the impurity region.

[0004] US 2007 / 0 221 974 A1 relates to a ferroelectric memory cell comprising a dielectric layer having a top surface forming a plane; a metal contact formed in the dielectric layer; and a ferroelectric capacitor formed over the metal contact.

[0005] US 7 642 099 B2 relates to a manufacturing method for a ferroelectric memory device, comprising forming a ferroelectric capacitor on a substrate, the ferroelectric capacitor having a lower electrode, a ferroelectric film and an upper electrode, and forming a first hydrogen barrier film covering the ferroelectric capacitor.

[0006] US 2018 / 0 375 022 A1 discloses an RRAM device comprising a bottom electrode disposed over a conductive bottom interconnect layer; a top electrode over the bottom electrode; a multilayer data storage structure between the bottom and top electrodes; and a hard mask over the top electrode. An interconnect structure extends through the hard mask to the top electrode.

[0007] Further prior art relating to the subject matter of the invention can be found, for example, in the documents DE 10 2018 126 665 A1, US 2015 / 0 255 713 A1, US 2011 / 0 272 664 A1, US 2015 / 0 090 949 A1, US 2015 / 0 262 864 A1 and US 2015 / 0 295 172 A1.

[0008] The invention provides an integrated chip according to claim 1, an integrated chip according to claim 10, and a method for forming an integrated chip according to claim 17. Embodiments are specified in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Aspects of the present disclosure can best be understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of the various features may be exaggerated or reduced as desired for clarity of explanation. Fig. 1 illustrates a cross-sectional view of some embodiments of an integrated chip having a memory device including a bottom electrode having a top surface with a cutout. Fig. 2A illustrates a cross-sectional view of some embodiments of an integrated chip having a ferroelectric random access memory (FeRAM) device including a bottom electrode having a top surface with a cutout. Fig. 2B illustrates a top view of some embodiments of the integrated chip of Fig. 2A. Fig. 3 illustrates a cross-sectional view of some further embodiments of an integrated chip having a FeRAM device including a bottom electrode having a top surface with a cutout. Fig. 4A to 4B illustrate cross-sectional views of some further embodiments of integrated chips having a FeRAM device including a bottom electrode having a top surface with a cutout. Fig. 5 illustrates a cross-sectional view of some further embodiments of an integrated chip having a FeRAM device including a bottom electrode having a top surface with a cutout. Fig. 6 illustrates a cross-sectional view of some further embodiments of an integrated chip having a FeRAM device including a bottom electrode having a top surface with a cutout. Fig. 7 to 17 illustrate cross-sectional views of some embodiments of a method of forming an integrated chip including a FeRAM device without using a planarization process to define a bottom electrode of the FeRAM device. Fig. 18 illustrates a flow diagram of some embodiments of a method of forming an integrated chip including a FeRAM device without using a planarization process to define a bottom electrode of the FeRAM device. DETAILED DESCRIPTION

[0010] The invention is as defined in the independent claims. The dependent claims relate to corresponding developments. The following disclosure provides many different embodiments or examples for implementing various functions of the presented content. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. For example, the formation of a first feature or a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which further features may be formed between the first and second features such that the first and second features need not be in direct contact.Furthermore, the present disclosure may repeat reference numbers and / or letters throughout the various examples. This repetition is for simplicity and clarity and does not, in itself, dictate a relationship between the various embodiments and / or configurations discussed.

[0011] Furthermore, spatially relative terms such as "beneath," "underneath," "lower," "above," "upper," and the like may be used herein for ease of description to describe the relationship of one element or feature to one or more other elements or features as illustrated in the FIGS. The spatially relative terms are intended to encompass various orientations of the device in use or operation, in addition to the orientation illustrated in the FIGS. The device may be oriented differently (rotated 90 degrees or in other orientations), and the spatially relative designators used herein may also be interpreted accordingly.

[0012] Ferroelectric random access memory (FeRAM) devices have a bottom electrode separated from a top electrode by a ferroelectric material. The ferroelectric material has an intrinsic electric dipole that can be switched between opposite polarities by applying an external electric field. The different polarities provide the FeRAM device with different capacitances representative of different data states (e.g., a logical '0' or '1'), allowing the FeRAM device to digitally store data. During a read operation, the different capacitances can be detected by a voltage on a bitline attached to a FeRAM device to output a data state stored by the FeRAM device.

[0013] FeRAM devices are typically formed by depositing a less insulating structure over a dielectric structure surrounding multiple interconnect layers. The lower insulating structure is patterned to form an opening exposing one or more of the multiple interconnect layers. A bottom electrode layer is formed within the opening and over the less insulating structure. A chemical mechanical planarization (CMP) process is subsequently performed on the bottom electrode layer to define a substantially planar top surface. A ferroelectric layer is formed over the substantially planar top surface of the bottom electrode layer, and a top electrode layer is formed over the ferroelectric layer.A first patterning process is performed on the top electrode layer and the ferroelectric layer to define a top electrode and ferroelectric structure. Sidewall spacers are then formed along the sides of the top electrode, followed by a second patterning process to define a bottom electrode.

[0014] The cost of using a CMP process to form the bottom electrode significantly increases the cost of forming a FeRAM device, as CMP processes are relatively expensive. Furthermore, it has been recognized that a residue of slurry used by the CMP process may remain on a substrate after the CMP process is complete. The slurry residue may accumulate over alignment marks used during subsequent lithographic processes, thereby obscuring the alignment marks. Obscuring the alignment marks reduces a photolithography process window of overlying layers, resulting in lower yield and / or lower reliability of the FeRAM devices.

[0015] This disclosure, in some embodiments, relates to a method of forming a FeRAM device that does not use a CMP process to form a bottom electrode. By not using a CMP process to form the bottom electrode, the cost of forming the FeRAM device may be reduced and a photolithography process window of overlying layers may be improved. In some embodiments, the resulting FeRAM device includes a bottom electrode generally corresponding to sidewalls and a top surface of an underlying less insulating structure, a ferroelectric material disposed over the bottom electrode, and a top electrode over the ferroelectric material.Because the bottom electrode is formed without using a CMP process, the bottom electrode has inner sidewalls defining a first cutout disposed within an upper surface of the bottom electrode. The ferroelectric material and / or the top electrode are disposed within the first cutout and may also have inner sidewalls defining further cutouts.

[0016] Fig. 1 illustrates a cross-sectional view of some embodiments of an integrated chip 100 having a memory device including a bottom electrode having a top surface with a cutout.

[0017] The integrated chip 100 includes an access device 104 disposed within a substrate 102. In some embodiments, the access device 104 may comprise a transistor device (e.g., a MOSFET, a bipolar junction transistor (BJT), a high electron mobility transistor (HEMT), or the like). In some embodiments, the substrate 102 may comprise a semiconductor material (e.g., silicon, germanium, or the like). A lower dielectric structure 106 is disposed over the substrate 102 and surrounds the access device 104. The lower dielectric structure 106 further surrounds a plurality of lower interconnect layers 108 that are electrically coupled to the access device 104. A lower insulating structure 110 is disposed over the lower dielectric structure 106.The lower insulating structure 110 includes sidewalls 110s that define an opening above an interconnect structure 108a of the plurality of lower interconnect layers 108.

[0018] A memory device 112 is disposed within the opening and above an upper surface 110u of the lower insulating structure 110. The memory device 112 includes a data storage structure 116 disposed between a lower electrode 114 and an upper electrode 118. The data storage structure 116 is configured to store either a first data state (e.g., a '0') or a second data state (e.g., a '1') depending on pre-emergence voltages applied to the lower electrode 114 and the upper electrode 118. For example, to store the first data state within the data storage structure 116, a first set of pre-emergence conditions may be applied to the lower electrode 114 and the upper electrode 118.Alternatively, to store the second data state within the data storage structure 116, a second set of pre-emergence conditions may be applied to the lower electrode 114 and the upper electrode 118.

[0019] The bottom electrode 114 includes a conductive material that generally corresponds to a top surface of the interconnect structure 108a, the sidewalls 110s of the bottom insulating structure 110, and a top surface of the bottom insulating structure 110. Because the conductive material of the bottom electrode 114 generally corresponds to underlying layers, the bottom electrode 114 has inner sidewalls 114s and a horizontally extending surface 114h that define a first cutout 115 within a top surface 114u of the bottom electrode 114. The data storage structure 116 and / or the top electrode 118 are disposed within the first cutout 115. In some embodiments, the data storage structure 116 and / or the top electrode 118 may also have inner sidewalls that define further cutouts.

[0020] A hard mask 120 is disposed over the memory device 112, and sidewall spacers 122 extend along outermost sidewalls of the top electrode 118 and the hard mask 120. A protective layer 124 covers the hard mask 120, the sidewall spacers 122, and the bottom insulating structure 110. In some embodiments, the hard mask 120 and the protective layer 124 may also include inner sidewalls defining further cutouts. A top interconnect structure 128 is disposed within a top dielectric structure 126 above the protective layer 124. The top interconnect structure 128 extends from a top surface of the top dielectric structure 126 to the top electrode 118.

[0021] The first cutout 115 within the top surface or bottom electrode 114 indicates that the bottom electrode 114 was formed without using a planarization process (e.g., a CMP process). By forming the bottom electrode 114 without using a planarization process, the bottom electrode 114 can be formed at a lower cost than processes that use a CMP process to form a bottom electrode. Furthermore, a photolithography process window of overlying layers can also be improved compared to processes that use a CMP process to form a bottom electrode.

[0022] Fig. 2A illustrates a cross-sectional view 200A of some embodiments of an integrated chip having a ferroelectric (FeRAM) device including a bottom electrode having a top surface with a cutout.

[0023] As seen in cross-sectional view 200A, the integrated chip includes a bottom dielectric structure 106 disposed over a substrate 102. The bottom dielectric structure 106 includes a plurality of bottom interlayer dielectric (ILD) layers 106a-106c stacked on top of each other and separated by etch stop layers 107a-107b. In some embodiments, the plurality of bottom ILD layers 106a-106c may include one or more of silicon dioxide, doped silicon dioxide (e.g., carbon-doped silicon dioxide), silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), or the like. In some embodiments, the etch stop layers 107a to 107b may comprise silicon carbide, silicon nitride, titanium nitride, tantalum nitride, or the like.

[0024] A plurality of lower interconnect layers 108 are disposed within the lower dielectric structure 106. The plurality of lower interconnect layers 108 include conductive contacts 202, interconnect wires 204, and interconnect vias 206, each surrounded by one or more lower ILD layers 106a-106c. For example, the conductive contact 202 may be surrounded by a first lower ILD layer 106a, a first of the interconnect wires 204 may be surrounded by a second lower ILD layer 106b, etc. In some embodiments, the interconnect wires 204 and the interconnect vias 206 each include a diffusion barrier layer surrounding a metal core. In some embodiments, the metal core may comprise copper, tungsten, aluminum, or the like. In some embodiments, the diffusion barrier layer may comprise titanium nitride, tantalum nitride, or the like.In some embodiments, the metal core and the diffusion barrier layer may have top surfaces that are substantially coplanar. In other embodiments, the diffusion barrier layer may extend vertically over outer edges of the metal core.

[0025] A lower insulating structure 110 may be disposed over the plurality of lower ILD layers 106a-106c. In some embodiments, the lower insulating structure 110 may have a thickness in a range between about 200 angstroms and about 400 angstroms. In other embodiments, the lower insulating structure 110 may have a thickness in a range between about 225 angstroms and about 325 angstroms. The lower insulating structure 110 includes sidewalls 110s defining an opening extending through the lower insulating structure 110. In some embodiments, the sidewalls 110s may be oriented at an acute angle α measured with respect to a lower surface of the lower insulating structure 110.In some embodiments, a line extending between each of the upper and lower sidewalls 110s may be oriented at an acute angle α measured with respect to a lower surface of the lower insulating structure 110. In some embodiments, the acute angle α ranges between approximately 40° and approximately 50°. In such embodiments, the acute angle α may limit gap-filling issues during fabrication of an overlying memory device. Furthermore, the acute angle α ensures good uniformity of the overlying layers, resulting in consistent performance of an overlying memory device. In various embodiments, the lower insulating structure 110 may comprise one or more of silicon oxynitride, silicon dioxide, silicon carbide, silicon nitride, tetraethyl orthosilicate (TEOS), a low-kappa dielectric, or the like.

[0026] A FeRAM device 208 is disposed over the lower insulating structure 110. The FeRAM device 208 includes a ferroelectric material 210 disposed between a lower electrode 114 and a top electrode 118. The lower electrode 114, the ferroelectric material 210, and the top electrode 118 each have an inner region 212 laterally surrounded by an outer region 214. Layers within the inner region 212 each have a recessed, horizontally extending surface laterally disposed between and vertically below upper surfaces of a corresponding layer within the outer region 214. For example, the lower electrode 114 utilizes a horizontally extending surface within the inner region 212 that is laterally disposed between and vertically below upper surfaces of the lower electrode 114 within the outer region 214.

[0027] In some embodiments, shown in plan view 200B in Fig. 2B (taken along line AA' of Fig. 2A), the outer region 214 may extend continuously in an unbroken ring around the inner region 212 when viewed in a top view of the FeRAM device 208. In some embodiments, the upper surface of the bottom electrode 114 extends in opposite directions along opposite edges of the inner region 212 by substantially equal distances d1 and d2. In some such embodiments, the bottom electrode 114 is substantially symmetric about a line 220 that bisects the lowermost surface of the bottom electrode 114. In other embodiments, the distances d1 and d2 may be different, such that the bottom electrode 114 is asymmetric about line 220.

[0028] Again with reference to cross-sectional view 200A from Fig. 2A (carried out along line BB' from Fig. 2B), the bottom electrode 114 extends continuously from a bottommost surface 114b, directly overlying the plurality of bottom interconnect layers 108, to line the sidewalls 110s and to a top surface 110u of the bottom insulating structure 110. The bottom electrode 114 has inner sidewalls disposed over the bottommost surface 114b. The inner sidewalls are coupled to the horizontally extending surface to define a first cutout within an upper surface of the bottom electrode 114. The ferroelectric material 210 is disposed within the first cutout and lines the inner sidewalls and the top surface of the bottom electrode 114. The ferroelectric material 210 has inner sidewalls disposed over the bottommost surface of the bottom electrode 114 and defining a second cutout within the top surface of the ferroelectric material 210.The upper electrode 118 is disposed within the second cutout and lines the inner sidewalls and the upper surface of the ferroelectric material 210. In some embodiments, the upper electrode 118 has inner sidewalls disposed above the lowermost surface of the lower electrode 114 and defining a third cutout within the upper surface of the upper electrode 118.

[0029] In some embodiments, the bottom electrode 114 and the top electrode 118 may comprise one or more of titanium, tantalum, tungsten, tantalum nitride, titanium nitride, or the like. In some embodiments, the ferroelectric material 210 may comprise a metal, a metal oxynitride, or a compound metal oxide. For example, in various embodiments, the ferroelectric material 210 may comprise lead titanate, lead zirconate titanate (PZT), lead lanthanum zirconate titanate, strontium bismuth tantalate (SBT), bismuth lanthanum titanate (BLT), and bismuth neodymium titanate (BNT), or the like.

[0030] In some embodiments, the bottom electrode 114, the ferroelectric material 210, and / or the top electrode 118 may each have a thickness ranging between about 50 angstroms and about 150 angstroms. In other embodiments, the bottom electrode 114, the ferroelectric material 210, and / or the top electrode 118 may each have a thickness equal to about 100 angstroms. The specified thicknesses of the bottom electrode 114, the ferroelectric material 210, and / or the top electrode 118 prevent an overall height of the FeRAM device 208 from becoming large enough to cause process issues within other regions of an integrated chip (e.g., within a logic region) and / or within overlying layers of an integrated chip.In some embodiments, the bottom electrode 114, the ferroelectric material 210, and / or the top electrode 118 may each have a substantially equal thickness between outermost sidewalls. In some alternative embodiments, the inner region 212 of the bottom electrode 114, the ferroelectric material 210, and / or the top electrode 118 may have a first thickness, and the outer region 214 of the bottom electrode 114, the ferroelectric material 210, and / or the top electrode 118 may have a second thickness that is less than the first thickness.

[0031] A hard mask 120 is disposed over the top electrode 118. Sidewall spacers 122 are disposed along opposite sides of the top electrode 118 and the hard mask 120. In some embodiments, the sidewall spacer 122 may comprise the same material as the hard mask 120. For example, in some embodiments, the hard mask 120 and the sidewall spacers 122 may comprise a carbide (e.g., silicon carbide), a nitride (e.g., silicon nitride), an oxide (e.g., silicon oxynitride), or the like. In other embodiments, the sidewall spacers 122 may comprise a different material than the hard mask 120. In some such embodiments, the sidewall spacers 122 and the hard mask 120 may extend to different heights (e.g., the hard mask 120 may have a top surface recessed below a top surface of the sidewall spacers 122, or vice versa).

[0032] A protective layer 124 is disposed over the sidewall spacers 122 and the hard mask 120. The protective layer 124 extends continuously from above the hard mask 120 to the lower insulating structure 110. In some embodiments, the protective layer 124 may comprise a carbide, an oxide, a nitride, TEOS (tetraethyl orthosilicate), or the like. In some embodiments, the hard mask 120 and the protective layer 124 may each have a thickness ranging between approximately 50 angstroms and approximately 150 angstroms. In other embodiments, the hard mask 120 and the protective layer 124 may each have a thickness equal to approximately 100 angstroms.

[0033] A top dielectric structure 126 is disposed over the protective layer 124. The top dielectric structure 126 may extend within a cutout defined by sidewalls of the protective layer 124. A top interconnect structure 128 is disposed within the top dielectric structure 126. The top interconnect structure 128 extends from a top surface of the top dielectric structure 126 to the top electrode 118. In some embodiments, the dielectric structure 126 may comprise silicon dioxide, carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), a porous dielectric, or the like. In various embodiments, the top interconnect structure 128 may comprise an interconnect via 216 and / or an interconnect wire 218.In some embodiments, the upper interconnect structure 128 may comprise a conductive material such as copper, tungsten, and / or aluminum.

[0034] During operation, pre-bias voltages may be applied to the bottom electrode 114 and / or the top electrode 118. For example, during a write operation, one or more pre-bias voltages may be applied to cause charge carriers (e.g., electrons and / or holes) to accumulate in the bottom electrode 114 and / or the top electrode 118. The charge carriers generate electric fields that extend through the ferroelectric material 210. The electric fields are configured to change the positions of the electric dipoles within the ferroelectric material 210 depending on the pre-bias voltages. When the positions of the electric dipoles within the ferroelectric material 210 define a first polarization, the FeRAM device 208 digitally stores data as a first bit value (e.g., a logic "0").Alternatively, if the positions of the electric dipoles within the ferroelectric material 210 define a second polarization, the FeRAM device 208 digitally stores data as a second bit value (e.g., a logical "1").

[0035] Fig. 3 illustrates a cross-sectional view of some embodiments of an integrated chip 300 having a FeRAM device including a bottom electrode having a top surface with a cutout.

[0036] The integrated chip 300 includes a FeRAM device 208 disposed over a lower insulating structure 110 above a substrate 102. The FeRAM device 208 includes a ferroelectric material 210 disposed between a lower electrode 114 and a top electrode 118. In some embodiments, the lower electrode 114 includes a liner 302 and a conductive layer 304 disposed over the liner 302. The liner 302 extends along sidewalls and a top surface of the lower insulating structure 110. In some embodiments, the liner 302 may comprise titanium nitride, tantalum nitride, or the like. In some embodiments, the conductive layer 304 may comprise titanium, tantalum, or the like.

[0037] The bottom electrode 114 has inner sidewalls disposed above a lowermost surface of the bottom electrode 114. The inner sidewalls are coupled between a horizontally extending surface of the bottom electrode 114 and a top surface of the bottom electrode 114. In some embodiments, the horizontally extending surface of the bottom electrode 114 extends along a first horizontal plane 306 that intersects sidewalls 110s of the bottom insulating structure 110. In some embodiments, the ferroelectric material 210 and the top electrode 118 extend continuously from directly above the bottom insulating structure 110 to positions below a second horizontal plane 308 that extends along a top surface 110u of the bottom insulating structure 110.By keeping the ferroelectric material 210 and the top electrode 118 below the second horizontal plane 308, a height of the FeRAM device 208 can be kept relatively low, thereby reducing process issues for layers overlying the FeRAM device.

[0038] A hard mask 120 is disposed over the top electrode 118. The hard mask 120 includes inner sidewalls coupled to a horizontally extending surface. In some embodiments, the horizontally extending surface extends along a third horizontal plane 310 that lies below lower surfaces of the top electrode 118. In other embodiments (not shown), the third horizontal plane 310 may lie above an upper surface of the top electrode 118.

[0039] Fig. 4A to 4B illustrate cross-sectional views of some embodiments of integrated chips having a FeRAM device including a bottom electrode having a top surface with a cutout.

[0040] As in Fig. 4A, an integrated chip 400 includes a first access device 104a and a second access device 104b disposed within a substrate 102. A first FeRAM device 208a is coupled to the first access device 104a, and a second FeRAM device 208b is coupled to the second access device 104b. The first FeRAM device 208a and the second FeRAM device 208b each include a ferroelectric material 210 disposed between a bottom electrode 114 and a top electrode 118. The bottom electrode 114 has sidewalls defining a first cutout within a top surface of the bottom electrode 114. The ferroelectric material 210 has sidewalls defining a second cutout within a top surface of the ferroelectric material 210. The upper electrode 118 is arranged within the second cutout and completely fills the second cutout.The upper electrode 118 has a top surface that lies entirely over the ferroelectric material 210. In some embodiments, the upper electrode 118 has a substantially flat top surface that extends continuously across the second cutout.

[0041] A top interconnect structure 128 extends through a top dielectric structure 126 disposed over the first FeRAM device 208a to contact the top electrode 118. In some embodiments, the top interconnect structure 128 may contact the top electrode 118 in a position directly overlying a top surface 114u of the bottom electrode 114. In some further embodiments, the top interconnect structure 128 may contact the top electrode 118 in a position laterally spanning an outer edge of the top surface 114u of the bottom electrode 114. In still other embodiments, Fig. 4B, an integrated chip 402 includes the upper interconnect structure 128 contacting the upper electrode 118 in a position directly above the cutout within the lower electrode 114. It should be understood that contact between the upper interconnect structure 128 and the upper electrode 118 in a position directly above the cutout within the lower electrode may reduce the risks associated with overlay defects during lithographic processes used to form the upper interconnect structure 128.

[0042] Fig. 5 illustrates a cross-sectional view of some embodiments of an integrated chip 500 having a FeRAM device including a bottom electrode having a top surface with a cutout.

[0043] The integrated chip 500 includes FeRAM devices 208a-208b, each including a ferroelectric material 210 disposed between a bottom electrode 114 and a top electrode 118. A hard mask 120 and a protective layer 124 are disposed over the FeRAM devices 208a-208b.

[0044] The upper electrode 118 has an upper surface 118u that extends laterally from directly above a top surface 210u of the ferroelectric material 210 to directly above the lowermost surface 114b of the lower electrode 114. In some embodiments, the upper surface 118u of the upper electrode 118 is disposed entirely above a top surface of the lower electrode 114. In some further embodiments, the upper surface 118u of the upper electrode 118 may also be disposed entirely above a top surface of the ferroelectric material 210. In such embodiments, the upper electrode 118 fills a cutout within the top surface 210u of the ferroelectric material 210. In some embodiments, the upper surface 118u of the upper electrode 118 is a curved (bent) surface.

[0045] A top interconnect structure 128 extends through the hard mask 120 and the protective layer 124 to contact the top electrode 118. In some embodiments, the top interconnect structure 128 may contact the top electrode 118 at a location directly above a bottom surface 114b of the bottom electrode 114. In such embodiments, the top surface 118u of the top electrode 118 may be tilted to intersect sidewalls of the top electrode 118 at a non-zero angle measured with respect to a horizontal plane. In some embodiments, the hard mask 120 and the protective layer 124 may also have top surfaces curved (bent) to intersect the sidewalls of the top electrode 118 at non-zero angles measured with respect to horizontal planes.In other embodiments (not shown), the upper interconnect structure 128 may contact the upper electrode 118 at a position that is laterally displaced from a lowermost point along the upper surface 118u of the upper electrode 118.

[0046] Fig. 6 illustrates a cross-sectional view of some embodiments of an integrated chip 600 having a FeRAM device including a bottom electrode having a top surface with a cutout.

[0047] The integrated chip 600 includes a substrate 102 including an embedded memory region 602 and a logic region 604. Within the embedded memory region 602, a plurality of lower interconnect layers 108 are disposed within a lower dielectric structure 106. The plurality of lower interconnect layers 108 are coupled between access devices 104a-104b disposed within the substrate 102 and FeRAM devices 208a-208b disposed over a lower insulating structure 110. The FeRAM devices 208a-208b each include a ferroelectric material 210 disposed between a lower electrode 114 and a top electrode 118.

[0048] In some embodiments, access devices 104a-104b each include a gate electrode 104g disposed vertically above substrate 102 and laterally between a source region 104s and a drain region 104d. Gate electrode 104g may be coupled to a word line, WL, or WL2, while source region 104s may be coupled to a source line SL. Drain region 104d is coupled to one of FeRAM devices 208a or 208b, which is further coupled to a bit line, BL1 or BL2.

[0049] Within the logic region 604, one or more further interconnect layers 608-612 are disposed within the lower dielectric structure 106 above the substrate 102. The one or more further interconnect layers 608-612 include a conductive contact 608, an interconnect wire 610, and an interconnect via 612. The one or more further interconnect layers 608-612 are coupled to a logic device 606 disposed within the substrate 102. In some embodiments, the logic device 606 may include a transistor device (e.g., a MOSFET, a bipolar junction transistor (BJT), a high electron mobility transistor (HEMT), or the like).

[0050] Fig. 7 to 17 illustrate cross-sectional views 700 to 1700 of some embodiments of a method of forming an integrated chip including a FeRAM device without using a planarization process to define a bottom electrode of the FeRAM device. Although Fig. 7 to 17 with respect to a method, it is to be understood that the structures described in Fig. 7 to 17 are not limited to a method, but can be seen separately as structures independent of the method.

[0051] As shown in the cross-sectional view 700 of Fig. 7, a substrate 102 is provided. The substrate 102 includes an embedded memory region 602 and a logic region 604. An access device 104 is formed within the embedded memory region 602 of the substrate 102, and a logic device 606 is formed within the logic region 604 of the substrate 102. In various embodiments, the substrate 102 may be any type of semiconductor body (e.g., silicon, SiGe, SOI, etc.), such as a semiconductor wafer and / or one or more dies on a wafer, as well as any other type of semiconductor and / or epitaxial layers associated therewith. In some embodiments, the access device 104 and / or the logic device 606 may include a transistor. In some such embodiments, the access device 104 and / or the logic device 606 may be formed by depositing a gate dielectric film and a gate electrode film over the substrate 102.The gate dielectric film and the gate electrode film are subsequently patterned to form a gate dielectric (e.g., 104g) and a gate electrode (e.g., 104e). The substrate 102 may subsequently be implanted to form a source region (e.g., 104s) and a drain region (e.g., 104d) within the substrate 102 on opposite sides of the gate electrode (e.g., 104e).

[0052] As shown in cross-sectional view 800 from Fig. 8, a plurality of lower interconnect layers 108 are formed within a lower dielectric structure 106, comprising one or more lower interlayer dielectric (ILD) layers 106a and 106b above the substrate 102. In some embodiments, the one or more lower ILD layers 106a-106b may comprise a first lower ILD layer 106a and a second lower ILD layer 106b separated by a first etch stop layer 107a. In some embodiments, the plurality of lower interconnect layers 108 may comprise a conductive contact 202 and an interconnect wire 204. In some other embodiments (not shown), the plurality of lower interconnect layers 108 may further comprise an interconnect via. The plurality of lower interconnect layers 108 may be formed by forming one or more lower ILD layers 106a to 106b (e.g.an oxide, a low-k dielectric, or an ultra-low-k dielectric) over the substrate 102, selectively etching the lower ILD layer to define a via hole and / or a trench within the lower ILD layer, forming a conductive material (e.g., copper, aluminum, etc.) within the via hole and / or a trench, and performing a planarization process (e.g., a chemical-mechanical planarization process).

[0053] As shown in cross-sectional view 900 from Fig. 9, a lower insulating structure 110 is formed over the lower dielectric structure 106. In some embodiments, the lower insulating structure 110 may comprise one or more of an oxide, silicon nitride, silicon carbide, silicon oxynitride, TEOS, or the like. In some embodiments, the lower insulating structure 110 may be formed by one or more different deposition processes (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), PE-CVD, atomic layer deposition (ALD), sputtering, etc.) to a thickness in a range between about 200 angstroms and about 400 angstroms.

[0054] As shown in cross-sectional view 1000 from Fig. 10, the lower insulating structure 110 is selectively patterned to define a plurality of openings 1002 extending through the lower insulating structure 110. The plurality of openings 1002 expose an interconnect structure 108a of the plurality of lower interconnect layers 108. In some embodiments, the lower insulating structure 110 may be selectively patterned by exposing the lower insulating structure 110 to an etchant 1004 after a patterned masking layer 1006 disposed on the lower insulating structure 110. In some embodiments, the patterned masking layer 1006 may comprise a photoresist material, a hard mask, or the like. In some embodiments, the etchant 1004 may comprise a dry etchant (e.g., comprising fluorine or chlorine).

[0055] As shown in cross-sectional view 1100A of Fig. 11A, a bottom electrode layer 1102 is formed over the bottom insulating structure 110 and within the openings 1002. The bottom electrode layer 1102 extends through the bottom insulating structure 110 to the interconnect structure 108a. The bottom electrode layer 1102 has sidewalls 1102s and a horizontally extending surface 1102h that define a cutout 115 within a top surface 1102u of the bottom electrode layer 1102. The cutout 115 is located directly above a bottommost surface 1102b of the bottom electrode layer 1102. In some embodiments, the bottom electrode layer 1102 may be formed by deposition of a liner followed by deposition of a conductive material.In various embodiments, the liner may comprise an adhesive layer configured to increase the bonding between adjacent layers and / or a diffusion barrier layer configured to prevent diffusion between adjacent layers.

[0056] As shown in cross-sectional view 1100B of Fig. 11B, a ferroelectric layer 1104 is formed over the lower electrode layer 1102 and within the first cutout (115 of Fig. 11A). The ferroelectric layer 1104 has sidewalls 1104s and a horizontally extending surface 1104h that define a second cutout 1106 within a top surface 1104u of the ferroelectric layer 1104 and directly above the bottommost surface 1102b of the bottom electrode layer 1102.

[0057] As shown in cross-sectional view 1100C from Fig. 11C, an upper electrode layer 1108 is formed over the ferroelectric layer 1104 and within the second cutout (1106 of Fig. 11B). The upper electrode layer 1108 has sidewalls 1108s and a horizontally extending surface 1108h that define a cutout 1110 within an upper surface 1108u of the upper electrode layer 1108 and directly above the lowermost surface 1102b of the lower electrode layer 1102.

[0058] As shown in cross-sectional view 1100D from Fig. 11D, a hard mask layer 1112 is deposited over the top electrode layer 1108 and within the third cutout (1110 of Fig. 11C). The hard mask layer 1112 has sidewalls 1112s and a horizontally extending surface 1112h defining a fourth cutout 1114 within a top surface 1112u of the hard mask layer 1112 and directly above the bottommost surface 1102b of the bottom electrode layer 1102.

[0059] As shown in the cross-sectional view 1200 from Fig. 12, a first patterning process is performed to define a top electrode 118 and a hard mask 120. The first patterning process selectively lays out the hard mask layer (1112 of Fig. 11D) and the upper electrode layer (1108 of Fig. 11D) for an etchant 1204 after a masking layer 1202 (e.g., a photoresist material, a hard mask, or the like) to define the top electrode 118 and the hard mask 120.

[0060] As shown in cross-sectional view 1300 from Fig. 13, sidewall spacers 122 are formed along sidewalls of the top electrode 118 and the hard mask 120. In some embodiments, the sidewall spacer 122 may completely cover sidewalls of the top electrode 118 and / or the hard mask 120. In various embodiments, the sidewall spacers 122 may comprise silicon nitride, a silicon dioxide, silicon oxynitride, or the like. In some embodiments, the sidewall spacers 122 may be formed by forming a spacer layer over the substrate. In some embodiments, the spacer layer may be formed using a deposition technique (e.g., PVD, CVD, PE-CVD, ALD, sputtering, etc.). The spacer layer is subsequently exposed to an etchant (e.g., a dry etchant) that removes the spacer layer from horizontal surfaces.Removing the spacer layer from horizontal surfaces leaves a portion of the spacer layer along opposite sides of the top electrode 118 and the hard mask 120 as the sidewall spacers 122.

[0061] As shown in the cross-sectional view 1400 from Fig. 14, a second patterning process is performed to define a first FeRAM device 208a and a second FeRAM device 208b, each comprising a ferroelectric material 210 disposed between a bottom electrode 114 and the top electrode 118. The second patterning process selectively deposits the ferroelectric layer (1104 of Fig. 13) and the lower electrode layers (1102 of Fig. 13) is open to an etchant 1402 to define the ferroelectric material 210 and the bottom electrode 114. In some embodiments, the second patterning process may further etch the bottom insulating structure 110 to cause the bottom insulating structure 110 to have a smaller thickness laterally outside the bottom electrode 114 than directly below the bottom electrode 114.

[0062] As shown in the cross-sectional view 1500 from Fig. 15, a protection layer 124 is formed over the first FeRAM device 208a and the second FeRAM device 208b. The protection layer 124 has sidewalls 124s and a horizontally extending surface 124h that define a fifth cutout 1502 located within a top surface 124u of the protection layer 124 and directly above a bottom surface 114b of the bottom electrode 114. In some embodiments, the protection layer 124 may be formed using a deposition technique (e.g., PVD, CVD, PE-CVD, ALD, sputtering, etc.). In various embodiments, the protection layer 124 may comprise one or more of silicon carbides, tetraethyl orthosilicate (TEOS), or the like.

[0063] As shown in the cross-sectional view 1600 from Fig. 16, a top dielectric structure 126 is formed over the protection layer 124. The top dielectric structure 126 is formed to cover the first FeRAM device 208a and the second FeRAM device 208b. In some embodiments, the top dielectric structure 126 may be formed by a deposition process (e.g., PVD, CVD, PE-CVD, ALD, or the like). In various embodiments, the top dielectric structure 126 may comprise silicon dioxide, carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), a porous dielectric, or the like.

[0064] As shown in cross-sectional view 1700 from Fig. 17, an upper interconnect structure 128 is formed in the upper dielectric structure 126 within the embedded memory region 602, and one or more further interconnect layers 610-612 are formed in the upper dielectric structure 126 within the logic region 604. In some embodiments, the upper interconnect structure 128 may include an interconnect via 216 and an interconnect wire 218. In some embodiments, the one or more further interconnect layers 610-612 may include an interconnect via 612 and an interconnect wire 610.

[0065] The upper interconnect structure 128 and the one or more further interconnect layers 610-612 may be formed simultaneously by selectively etching the upper dielectric structure 126 to define via holes and / or trenches within the upper dielectric structure 126, forming a conductive material (e.g., copper, aluminum, etc.) within the via holes and / or trenches, and performing a planarization process (e.g., a chemical mechanical planarization process). In some embodiments, the planarization process may include a chemical mechanical planarization (CMP) process.

[0066] Fig. 18 illustrates a flow diagram of some embodiments of a method 1800 for forming an integrated chip including a FeRAM device without using a planarization process to define a bottom electrode of the FeRAM device.

[0067] While method 1800 is illustrated and described herein as a series of acts or events, it is to be understood that the illustrated order of those acts or events is not to be construed as limiting. For example, some acts may occur in different orders and / or concurrently with other acts or events except those illustrated and / or described herein. Furthermore, not all of the illustrated acts may be required to practice one or more aspects or embodiments of the description herein. Further, one or more of the acts depicted herein may be performed in one or more separate acts and / or phases.

[0068] In 1802, an access device is formed within a substrate. Fig. 7 illustrates a cross-sectional view 700 of some embodiments corresponding to act 1802.

[0069] In 1804, multiple lower interconnect layers are formed within a lower dielectric structure over the substrate. Fig. 8 illustrates a cross-sectional view 800 of some embodiments corresponding to act 1804.

[0070] In 1806, a lower insulating structure is formed over the lower dielectric structure. The lower insulating structure is formed to have openings overlying an interconnect structure of the plurality of lower interconnect layers. Fig. 9 to 10 illustrate cross-sectional views 900 to 1000 of some embodiments corresponding to act 1806.

[0071] In 1808, a lower electrode layer, a ferroelectric layer, an upper electrode layer, and a hard mask layer are sequentially formed over the lower insulating structure. Fig. 11A to 11D illustrate cross-sectional views 1100A to 1100D of some embodiments, the act 1808.

[0072] In 1810, a first patterning process is performed on the top electrode layer and the hard mask layer to define a top electrode and a hard mask. Fig. 12 illustrates a cross-sectional view 1200 of some embodiments corresponding to act 1810.

[0073] In 1812, sidewall spacers are formed along sidewalls of the top electrode and hard mask. Fig. 13 illustrates a cross-sectional view 1300 of some embodiments corresponding to act 1812.

[0074] In 1814, a second patterning process is formed on the ferroelectric layer and the bottom electrode layer to define a first FeRAM device and a second FeRAM device, each having a ferroelectric material disposed between a bottom electrode and the top electrode. Fig. 14 illustrates a cross-sectional view 1400 of some embodiments corresponding to act 1814.

[0075] In 1816, a protective layer is formed over the first FeRAM device and the second FeRAM device. Fig. 15 illustrates a cross-sectional view 1500 of some embodiments corresponding to act 1816.

[0076] In 1818, an upper interconnect structure is formed within an upper dielectric structure disposed over the protective layer. Fig.16 to 17 illustrate cross-sectional views 1600 to 1700 of some alternative embodiments corresponding to act 1818.

[0077] Accordingly, in some embodiments, this disclosure relates to a method of forming a FeRAM device that does not use a planarization process to define a bottom electrode. The resulting FeRAM device includes a bottom electrode having a top surface with a cutout.

Claims

[1] Integrated chip (100) comprising: a plurality of lower interconnect layers (108) disposed within a lower dielectric structure (106) over a substrate (102); a lower insulating structure (110) disposed over the lower dielectric structure (106) and having sidewalls (110s) extending through the lower insulating structure (110); a lower electrode (114) disposed along the sidewalls and an upper surface of the lower insulating structure (110), the upper surface of the lower insulating structure extending past outermost sidewalls of the lower electrode (114); a data storage structure (116) disposed on the lower electrode (114), the data storage structure (116) comprising a ferroelectric material and configured to store a data state; an upper electrode (118) disposed on the data storage structure (116); and a hard mask (120) disposed over the upper electrode (118), and an upper interconnect structure (128) extending through the hard mask (120) to the upper electrode (118), wherein the lower electrode (114) has inner sidewalls (114s) coupled to a horizontally extending surface for defining a cutout (115) within an upper surface (114u) of the lower electrode (114), the horizontally extending surface (114h) of the lower electrode (114) underlying the upper surface (110u) of the lower insulating structure (110); wherein the upper electrode (118) has inner sidewalls coupled to a horizontally extending surface for defining a second cutout within an upper surface of the upper electrode (120), wherein the hard mask (120) is arranged along the inner side walls, the horizontally extending surface and the uppermost surface of the upper electrode (120), wherein the upper interconnect structure (128) contacts the upper electrode (118) at a position laterally spanning an outer edge of the upper surface (114u) of the lower electrode (114). [2] The integrated chip of claim 1, wherein a first horizontal plane (306) extends along the horizontally extending surface (114h) of the lower electrode (114) and through the sidewalls (110s) of the lower insulating structure (110). [3] An integrated chip according to any preceding claim, wherein the lower electrode (114) is substantially symmetrical about a line (220) dividing a lowermost surface of the lower electrode (114) into two. [4] An integrated chip according to any preceding claim, wherein the upper surface 114u of the lower electrode (114) extends in opposite directions by substantially equal distances (214, d1, d2) past the inner sidewalls (114s) of the lower electrode (114). [5] Integrated chip according to one of the preceding claims, further comprising: an upper dielectric structure (126) disposed over the upper electrode (118) and the lower insulating structure (110), wherein the upper interconnect structure (128) extends from an upper surface of the upper dielectric structure (126) to the upper electrode (118). [6] The integrated chip of any preceding claim, wherein the sidewalls (110s) of the lower insulating structure (110) are arranged at an angle of between about 40° and about 50°, measured with respect to a line extending along a bottom of the lower insulating structure (110). [7] Integrated chip according to one of the preceding claims, further comprising: Sidewall spacers (122) disposed over the data storage structure (116) and completely covering the outermost sidewalls of the top electrode (118) and the hard mask (120). [8] Integrated chip according to one of the preceding claims, further comprising: a protective layer (124) disposed over the hard mask (120), the protective layer (124) being disposed along inner sidewalls of the hard mask (120) defining a third cutout within a top surface of the hard mask. [9] The integrated chip of claim 8, wherein the upper dielectric structure (126) is disposed along inner sidewalls of the protective layer (124) defining a fourth cutout within an upper surface of the protective layer (124). [10] Integrated chip comprising: a plurality of lower interconnect layers (108) disposed within a lower dielectric structure (106) over a substrate (102); a lower insulating structure (110) disposed over the lower dielectric structure (106) and having sidewalls (110s) defining an opening (1002); a ferroelectric random access memory device (208), FeRAM device, extending through the opening (1002) to the plurality of lower interconnect layers (108), the FeRAM device (208) comprising: - a lower electrode (114) arranged along the sidewalls and an upper surface of the lower insulating structure (110), the lower electrode (114) having inner sidewalls (114s) coupled to a horizontally extending surface (114h) for defining a first cutout (115) within an upper surface (114u) of the lower electrode (114); - a ferroelectric material (116) disposed on the lower electrode (114); - an upper electrode (118) disposed on the ferroelectric material (116); and - a hard mask (120) disposed on the upper electrode (118), wherein the ferroelectric material (116), the upper electrode (118), and the hard mask (120) each have inner sidewalls and a horizontally extending surface, each of which together defines a cutout (1106, 1110, 1114) disposed directly above the first cutout (115) of the lower electrode (114), the hard mask (120) being disposed along the inner sidewalls, the horizontally extending surface, and the uppermost surface of the upper electrode (120); and an upper interconnect structure (128) extending through the hard mask (120) to the upper electrode (118), the upper interconnect structure (128) contacting the upper electrode (118) at a position laterally spanning an outer edge of the upper surface (114u) of the lower electrode (114). [11] The integrated chip of claim 10, wherein the top electrode (118) has a top surface extending laterally from directly above a top surface of the ferroelectric material (1104) to directly above the bottom surface of the bottom electrode (114), an entirety of the top surface lying vertically above the top surface of the ferroelectric material (1104). [12] The integrated chip of claim 11, wherein the upper surface of the upper electrode (118) is a curved surface. [13] Integrated chip according to one of claims 10 to 12, further comprising: a protective layer (124) disposed on the hard mask (120), the protective layer (124) having sidewalls defining a further cutout disposed over the lowermost surface of the lower electrode (114). [14] The integrated chip of any one of claims 10 to 13, wherein a horizontal plane (308) extending along the upper surface of the lower insulating structure (110) intersects sidewalls of the upper electrode (118). [15] The integrated chip of any one of claims 10 to 14, wherein the sidewalls (110s) of the lower insulating structure (110) are arranged at an angle between about 40° and about 50°, measured with respect to a line extending along a bottom of the lower insulating structure (110). [16] Integrated chip according to one of claims 10 to 15, further comprising: a protective layer (124) disposed over the hard mask (120), the protective layer (124) having sidewalls that intersect the upper interconnect structure (128) at a non-zero angle measured with respect to a horizontal plane extending along a top surface of the protective layer (124). [17] A method of forming an integrated chip, comprising: Forming a lower insulating structure (110) over a plurality of interconnect layers (108) within a lower dielectric structure (106) over a substrate (102); Removing a portion of the lower insulating structure (110) to define openings (1002) extending through the lower insulating structure (110) to the plurality of interconnect layers (108); sequentially depositing a lower electrode layer (1102), a ferroelectric layer (1104), an upper electrode layer (1108), and a hard mask layer (1112) over the lower insulating structure (110), wherein the lower electrode layer (1102), the ferroelectric layer (1104), the upper electrode layer (1108), and the hard mask layer (1112) each have sidewalls and a horizontally extending surface, which together each define a cutout (115, 1106, 1110, 1114) arranged directly above the horizontally extending surface of the lower electrode layer (1102); Patterning the bottom electrode layer (1102), the ferroelectric layer (1104), the top electrode layer (1108), and the hard mask layer (1112) to define a FeRAM device (208) comprising a ferroelectric material (210) disposed between a bottom electrode (114) and a top electrode (118), wherein a hard mask (120) is disposed along the sidewalls, the horizontally extending surface, and the top surface of the top electrode (118); Forming an upper dielectric structure (126) over the hard mask (120) and the lower insulating structure (110); and Forming an upper interconnect structure (128) extending from an upper surface of the upper dielectric structure (126) to the upper electrode (118), the upper interconnect structure (128) contacting the upper electrode (118) at a position laterally spanning an outer edge of the upper surface (114u) of the lower electrode (114). [18] The method of claim 17, further comprising: before forming the upper dielectric structure (126), forming a protective layer (124) over the hard mask (120) and the lower insulating structure (110), wherein the protective layer (124) has sidewalls that intersect the upper interconnect structure (128) at a non-zero angle measured with respect to a horizontal plane extending along a top surface of the protective layer (124).

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