HYBRID DIELECTRIC SCHEME IN PACKAGES

Abstract

Procedure with the following steps: Establishing an initial redistribution line (RDL1); Producing a first polymer layer (DL1) with a first part that encloses the first redistribution line (RDL1) and a second part that covers the first redistribution line (RDL1); Creating a pair of differential transmission lines (SL1, SL2) over and in contact with the first polymer layer (DL1); Establishing a second redistribution line (RDL2) simultaneously with establishing the pair of differential transmission lines (SL1, SL2); Establishing a through-hole connection (V3) across and in contact with the second redistribution line (RDL2); Overmolding the pair of differential transmission lines (SL1, SL2) and the via (V3) with a first molding compound (DL2), wherein the first molding compound has a first part that encloses the pair of differential transmission lines (SL1, SL2) and a second part that covers the pair of differential transmission lines (SL1, SL2) and encloses the via (V3); and Performing a planarization process to bring the top surfaces of the via (V3) and the first molding compound (DL2) to the same level; Establishing an electrical connecting element (62) over and in electrical connection with the pair of differential transmission lines (SL1, SL2).

Description

background

[0001] With the development of semiconductor technologies, semiconductor chips / dies are becoming increasingly smaller. Meanwhile, more functions need to be integrated into the semiconductor dies, which means that other semiconductor dies and the resulting packages are also becoming larger.

[0002] To route energy and signals within the packages, redistribution lines are fabricated in the package substrates. Transmission lines are manufactured as components of these redistribution lines, and they also become very long as the packages grow larger, occasionally reaching several tens of millimeters. These long transmission lines have high resistance values ​​and cause significant insertion loss, especially for high-speed signals. A semiconductor device and a corresponding fabrication method are known from German patent application DE 10 2018 123 492 A1. Ultra-high-density redistribution layer interconnects for integrated fan-out packages (InFO packages) are known from German patent application DE 10 2018 122 358 A1. Brief description of the drawings

[0003] Aspects of the present invention are best understood with reference to the detailed description below in conjunction with the accompanying drawings. It should be noted that, in accordance with common industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of discussion, the dimensions of the various elements may be arbitrarily enlarged or reduced. The Fig. Figures 1 to 15 show sectional views of intermediate stages in the production of a die stack according to some embodiments. The Fig. Figures 16 to 18 show sectional views of packages according to some embodiments. The Fig. 19A, Fig. 19B and Fig. Figure 20 shows two sectional views or a top view of transmission lines according to some embodiments. Fig. Figure 21 shows an enlarged representation of an area in a package according to some embodiments. Fig. Figure 22 shows a process flow for manufacturing a package according to some embodiments. Detailed description

[0004] The present invention relates to a method and a corresponding package comprising the features of the respective independent claims. Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to easily describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. In addition to the orientation shown in the figures, the spatially relative terms are intended to encompass other orientations of the device in use or operation. The device can be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0005] According to some embodiments, a package and a method for its fabrication are provided. Intermediate steps in the fabrication of the package according to some embodiments are explained. Furthermore, some variations of certain embodiments are discussed. In all descriptions and explanatory embodiments, similar reference numerals are used to denote similar components. While some method embodiments may be discussed as being carried out in a specific sequence, other method embodiments may be carried out in any logical order.

[0006] According to some embodiments of the present invention, a package comprises high-speed transmission lines, which may be differential transmission lines. In some embodiments, the transmission line has a higher-level dielectric layer and a lower-level dielectric layer. The higher-level dielectric layer and the lower-level dielectric layer can be made of different materials and by different methods, such that the higher-level layer or the lower-level layer may have a thickness that is significantly greater than that of the other layer. The transmission lines in this structure can have a large line width for reduced insertion loss while maintaining a desired impedance.

[0007] The Fig. Figures 1 to 15 show sectional views of intermediate stages in the manufacture of a package according to some embodiments of the present invention. The corresponding steps are also schematically indicated in the process flow 200, which is presented in Fig. 22 is shown. Fig. 1. A support 20 is provided, and the support 20 is coated with a release layer 22. The support 20 is made of a transparent material and can be a glass support, a ceramic support, an organic support, or the like. The release layer 22 is in physical contact with the top surface of the support 20. The release layer 22 can be made of an LTHC coating material (LTHC: light-heat conversion) applied to the support 20 by coating. In some embodiments of the present invention, the LTHC coating material can be decomposed by the heat of light or radiation (such as lasers), and thereby the support 20 can be detached from the structure on which it is made. As further described in Fig. As shown in Figure 1, in some embodiments a dielectric buffer layer 24 is produced on the LTHC coating material 22. In some embodiments, the dielectric buffer layer 24 is made from a polymer-based material. The dielectric buffer layer 24 can be made, for example, from polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or other suitable polymers.

[0008] The Fig. 2 and Fig. Figure 3 shows the fabrication of redistribution lines (RDLs) 26 on the dielectric buffer layer 24. The corresponding step is indicated as step 202 in the process flow 200, which is described in Fig. 22 is shown. Fig. 2. A metallic seed layer 26A is produced. The metallic seed layer 26A is produced as a protective layer, which in some embodiments may include an adhesive layer and a copper-containing layer. The adhesive layer may be made of titanium, titanium nitride, tantalum, tantalum nitride, or the like. The copper-containing layer may be made of substantially pure copper or a copper alloy. Physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or the like may be used as deposition methods for the materials of the metallic seed layer 26A. Then, a structured plating mask 28, which may be made of a photoresist, is produced over the metallic seed layer 26A. Openings 30 are created to expose some parts of the metallic seed layer 26A.Then, metallic areas (RDLs) 26B are produced in the openings 30, for example, by electrochemical plating. The RDLs 26B can be made of copper or a copper alloy, aluminum, nickel, palladium, alloys thereof, or multiple layers thereof.

[0009] After the fabrication of the RDLs 26B, the plating mask 28 is removed, exposing the underlying portions of the metallic seed layer 26A. The exposed portions of the metallic seed layer 26A are then etched, and the remaining portions are also referred to as the metallic seed layer 26A. The resulting structure is in Fig. 3 shown. Throughout the description, the remaining parts of the metallic seed layer 26A are considered to be parts of the RDLs, and therefore 26A and 26B are collectively referred to as RDLs 26.

[0010] The Fig. Figures 4 to 6 show sectional views of intermediate stages in the fabrication of vias 32 according to some embodiments of the present invention. The corresponding step is indicated as step 204 in the process sequence 200, which is described in Fig. 22 is shown. Fig. 4. A metallic seed layer 32A is produced. The manufacturing processes and materials for the metallic seed layer 32A can be compared to those for the [missing information]. Fig. The metallic seed layer 26A shown in Figure 2 is similar and is therefore not repeated here. The metallic seed layer 32A covers the top and side walls of the RDLs 26 and extends onto the top of the dielectric buffer layer 24. Then, a structured plating mask 34, for example from a photoresist, is fabricated, with openings 36 being created in the plating mask 34 that cover some parts of the RDLs 26.

[0011] Then, as in Fig. As shown in Figure 5, vias 32B are produced, for example, by plating in the openings 36. After the vias 32B are produced, the plating mask 34 is removed, exposing the underlying parts of the metallic seed layer 32A. Then, the exposed parts of the metallic seed layer 32A are etched, and the remaining parts are also designated 32A. The resulting structure is shown in Fig. Figure 6 shows the remaining portions of the metallic seed layer 32A as parts of the RDLs, and the vias 32B and the remaining portions of the metallic seed layer 32A are hereinafter collectively referred to as vias 32. Due to the fabrication process, the edges of the vias 32 are essentially vertical and straight, and they have, for example, an inclination angle α of about 85° to 90° or of about 88° to 90°.

[0012] In Fig. 7 A dielectric layer 38 is produced such that it encapsulates the RDLs 26 and the vias 32. The corresponding step is specified as step 206 in the process flow 200, which is described in Fig. Figure 22 shows that the dielectric layer 38 is filled to a level higher than the tops of the vias 32. In some embodiments, the dielectric layer 38 comprises a molding compound, a mold underfill, an epoxy, and / or a resin. The top of the dielectric layer 38 is higher than the tops of the vias after application. If the dielectric layer 38 is made from a molding compound or a mold underfill, it may consist of a base material, which may be a polymer, a resin, an epoxy, or the like, and filler particles (not shown, see Figure 22). Fig. 21) in the base material. The filler particles can be dielectric particles made of SiO2, Al2O3, silica, or the like, and can be spherical. Furthermore, the spherical filler particles can have several different diameters. Since the dielectric layer can contain 38 different materials, such as the base material and the filler particles, it can be made from one or more heterogeneous materials.

[0013] In alternative embodiments, the dielectric layer 38 is made from a homogeneous material. The homogeneous material can be a photosensitive or a non-photosensitive material. For example, the homogeneous material can be or comprise PBO, polyimide, a resin, an epoxy, or the like. The manufacturing process can include spreading the homogeneous dielectric layer 38 in a flowable form, curing the dielectric layer, and subsequently performing a planarization process to expose the vias 32. The dielectric layer 38 can also be made from an inorganic material, such as silicon oxide, silicon nitride, or the like.

[0014] As in Fig. As shown in Figure 7, a subsequent step involves a planarization process, such as a CMP process (CMP: chemical-mechanical polishing) or a mechanical grinding process, to planarize the dielectric layer 38 until the vias 32 are exposed. Through the planarization process, the top ends of the vias 32 are essentially at the same level (coplanar) with the top surface of the dielectric layer 38.

[0015] Fig. Figure 8 shows the fabrication of RDLs 40, which may comprise a metallic seed layer 40A and a clad metallic area (RDLs) 40B. The corresponding step is indicated as step 208 in process flow 200, which is described in Fig. Figure 22 shows that in some embodiments of the present invention, the fabrication of the RDLs 40 may comprise the following steps: depositing a metallic protective seed layer; fabricating a structured plating mask over the metallic protective seed layer; plating the metallic areas 40B; removing the plating mask; and etching the exposed portions of the metallic seed layer. The materials for the RDLs 40 may be selected from the same group of suitable materials as for fabricating the RDLs 26, and they are not repeated here.

[0016] Fig. Figure 9 shows the application and structuring of a dielectric layer 42. The corresponding step is indicated as step 210 in the process flow 200, which is described in Fig. Figure 22 shows that in some embodiments, the dielectric layer 42 is made of a photosensitive material, which may be or include a polymer such as polyimide, PBO, or the like. The dielectric layer 42 can be applied in a flowable form and is then cured. Due to the coating process, no planarization process is required to flatten the top surface of the dielectric layer 42. The manufacturing processes include applying the dielectric layer 42, performing an exposure process on the dielectric layer 42 (for example, using a structured photolithographic mask), and developing the dielectric layer 42. Some parts of the dielectric layer 42 are removed during the development process to create openings 44. The manufacturing process results in angled and straight edges to the edges of the openings 44.

[0017] In Fig. 10 RDLs 46 are produced, which may comprise a metallic seed layer 46A and clad metallic areas 46B. The corresponding step is specified as step 212 in process flow 200, which is described in Fig. 22 is shown. In some embodiments of the present invention, the manufacture of the RDLs 46 comprises the following steps: depositing a metallic protective seed layer such that it fits into the openings 44 (see Fig. 9) extends into; and fabrication of a structured plating mask (not shown) over the metallic protective seed layer. Then the metallic areas 46B are fabricated, for example, by plating. Subsequently, the plating mask is removed, for example, by a peeling process. The portions of the metallic seed layer that were previously covered by the plating mask are then etched so that the in Fig. The 10 RDLs 46 shown are created. The materials for the RDLs 46 can be chosen from the same group of eligible materials as for the production of the RDLs 26, and they are not repeated here.

[0018] The RDLs 46 comprise conductor parts 46L located above the dielectric layer 42 and via parts 46V extending into the dielectric layer 42. In some embodiments of the present invention, some portions of the top surfaces of the RDLs 46 directly above the via parts 46V can be recessed due to the topology provided by the openings 44. The recessed top surfaces of the RDLs 46 are indicated by dashed lines 47 in some exemplary embodiments. In other embodiments, the plating process is adjusted such that the top surfaces of the conductor parts 46L directly above the via parts 46V are planar with or higher than the top surfaces of the portions of the conductor parts 46L that cover the dielectric layer 42.Due to the manufacturing process, the edges of the vias 46V, for example, are inclined with an inclination angle β that is less than about 85° or less than about 80° or about 75°.

[0019] As in the Fig. 9 and Fig. As shown in Figure 10, since it is made of a homogeneous material, the dielectric layer 42 can be structured to create openings 44 (as in Figure 10). Fig. (as shown in Figure 9). This allows the conductor parts 46L and the via parts 46V to be manufactured in the same process. In contrast, since the dielectric layer 38 can be heterogeneous and the base material and filler particles within it have different etch rates, it is difficult to etch the dielectric layer 38. Accordingly, the vias 32 and the RDLs 40 are manufactured in separate processes, which leads to an increase in manufacturing costs. However, the higher costs are offset by the advantage that the thickness of the dielectric layer 38 can be set to a target value that can be greater than approximately 15 µm and can range from approximately 20 µm to 40 µm. If, on the other hand, the dielectric layer 42 is made of a photosensitive material, the thickness of the dielectric layer 42 is limited, for example, to a value less than approximately 15 µm due to the exposure restrictions.

[0020] Fig. Figure 11 shows the fabrication of vias 50 comprising metallic seed layers 50A and metallic regions (RDLs) 50B. The corresponding step is indicated as step 214 in process flow 200, which is shown in Fig. Figure 22 shows that in some embodiments of the present invention, the fabrication of the vias 50 may comprise the following steps: depositing a metallic protective seed layer; fabricating a structured plating mask (not shown) over the metallic protective seed layer; plating the metallic areas 50B; removing the plating mask; and etching the exposed portions of the metallic seed layer. The materials for the vias 50 may be selected from the same group of suitable materials as for fabricating the vias 32, and they are not repeated here.

[0021] Then a dielectric layer 52 is produced such that it encapsulates the RDL conductor parts 46L and the vias 50. The corresponding step is specified as step 216 in the process flow 200, which is described in Fig. Figure 22 shows that the dielectric layer 52 can be made from a material selected from the same group of suitable materials as those used to make the dielectric layer 38, and it can be made from or have the composition of a molding compound, mold underfill, epoxy, resin, inorganic dielectric material, or the like. A planarization process, such as a CMP process or a mechanical grinding process, is then performed to planarize the dielectric layer 52 until the vias 50 are exposed. The corresponding step is also shown as step 216 in process flow 200, which is shown in Figure 22. Fig. Figure 22 shows that, through the planarization process, the upper ends of the vias 50 are essentially at the same level (coplanar) with a top surface of the dielectric layer 52.

[0022] Fig. Figure 12 shows the fabrication of further structural elements located above, comprising RDLs 56 and a dielectric layer 58. The corresponding step is indicated as step 218 in process flow 200, which is described in Fig. Figure 22 shows that, for example, some of the layers above, represented by dots, can form a multilayer structure similar to the structure comprising the dielectric layers 42 and 52 and the conductive structural elements 40, 46, and 50. In some embodiments, an alternating layout is used for the dielectric layers produced later and the dielectric layers 38, 42, and 52 produced earlier, with some of the layers being made of homogeneous materials and other layers being made of heterogeneous materials.Each layer made of a homogeneous material can be inserted between two layers made of heterogeneous materials in such a way that it contacts these two layers, and vice versa. For example, layers 24, 42, and 58 can be made of homogeneous materials, while layers 38 and 52 can be made of heterogeneous materials. Depending on the materials of the respective dielectric layers, the structures of RDLs 46 and 50 can also be used for the conductive structural elements in the structures above.

[0023] Furthermore, subsurface metallizations (UBMs) 60 and electrical connecting elements 62 are produced. The corresponding steps are specified as steps 220 and 222 in process flow 200, which is described in Fig. Figure 22 shows that the UBMs 60 can be manufactured similarly to the RDLs 46 and can have an adhesive layer (such as a titanium layer) and a copper layer above it. The electrical connecting elements 62 can, for example, be or have solder areas. Throughout this description, structural elements above the release layer 22 are collectively referred to as the composite package substrate 64. The composite package substrate 64 does not contain any component dies or active components.

[0024] In some embodiments of the present invention, the thicknesses T1 of the RDL conductor sections 46L and the RDLs 26, 40, and 56 are approximately 1 µm to approximately 20 µm. The thicknesses T2 of the homogeneous layer 42 (and the homogeneous layers above it) can be approximately 3 µm to approximately 30 µm. The thicknesses T3 of the heterogeneous layers 38 and 52 (and the heterogeneous layers above them) can be approximately 5 µm to approximately 50 µm. The thickness T3 is greater than the thickness T2, and the ratio T3 / T2 can be approximately 1.5 to approximately 3.0. A distance S2 between the conductor sections 46L and the RDLs above them (not shown) can be approximately 5 µm to approximately 40 µm. The ratio S2 / S1 is greater than 1.0 and can be approximately 1.5 to approximately 3.0 in some embodiments.

[0025] Fig. Figure 13 shows the bonding of the package substrate 66 to the composite package substrate 64. The corresponding step is specified as step 224 in the process flow 200, which is described in Fig. Figure 22 shows that only one package substrate 66 is depicted, but there can be multiple identical package substrates 66 bonded to the composite package substrate 64. In some embodiments, the package substrate 66 has a core 68, which in turn has a core dielectric 72, conductive lines 70 penetrating the core dielectric 72, and a dielectric filler 74 within the conductive lines 70. In some embodiments, the core dielectric 72 is made of glass fiber, an epoxy, a resin, prepreg, or the like. The conductive lines 76 and the dielectric layer 78 are produced on opposing layers of the core 68 and can be connected to each other by the conductive lines 70. Bond pads 80 can be connected to the conductive lines 76. A dielectric layer 82 can cover peripheral parts of the bond pads 80, while middle parts of the bond pads 80 remain exposed.The dielectric layer 82 can, for example, be produced from a solder mask.

[0026] In some embodiments, an encapsulation material 84, which may be made from a mold underfill, a molding compound, or the like, is applied such that it encapsulates the package substrate 66. The corresponding step is specified as step 224 in the process flow 200, which is described in Fig. Figure 22 shows the encapsulation material 84 in contact with the sidewalls of the package substrate 66. The structure above the release layer 22 is referred to below as a composite package component 86.

[0027] The composite package component 86 is then detached from the carrier 20, for example by projecting light onto the release layer 22, whereby the light (such as a laser beam) passes through the transparent carrier 20. The corresponding step is specified as step 226 in the process sequence 200, which is described in Fig. 22 is shown. The detachment layer 22 is thereby decomposed, and the composite package component 86 detaches from the support 20. The resulting structure is in Fig. 14 shown. In subsequent steps, the dielectric buffer layer 24 is structured, for example, by laser drilling. Electrical connecting elements 87, which can be solder areas, are manufactured such that they contact the metal pads in the RDLs 26. The corresponding step is specified as step 228 in the process flow 200, which is shown in Fig. 22 is shown.

[0028] The composite package component 86 can then be separated by sawing the encapsulation material 84 and the underlying dielectric layers, resulting in a plurality of identical package substrates. The corresponding step is specified as step 230 in the process flow 200, which is described in Fig. Figure 22 shows one of the isolated package substrates 86'. Fig. Figure 15 shows that the package substrate 86' comprises a package substrate 64' that has been separated from the composite package substrate 64. In some embodiments, the package substrate 86' is bonded to package components 88 and 90, forming a package 92. The corresponding step is specified as step 232 in the process flow 200, which is shown in Fig. Figure 22 is shown. In some embodiments of the present invention, the package component 88 is a device die. In some embodiments of the present invention, the package component 88 comprises an interposer (not shown) and a device die (or a plurality of device dies; not shown) bonded to the interposer, the interposer being directly bonded to the package substrate 64'. In some embodiments of the present invention, the package component 88 is an integrated fan-out package (InFO package) comprising a device die (not shown) encapsulated in an encapsulation material and RDLs fabricated on the encapsulation material and the device die.In further embodiments of the present invention, the package component 88 is a chip-on-wafer-on-substrate (CoWoS) structure comprising a chip bonded to a wafer, which is then sawn off to produce a package, the package being in turn bonded to a package substrate. The package component 90 can, for example, be or comprise a printed circuit board.

[0029] Fig. Figure 19A shows part of the package substrate 64'. In some embodiments, the illustrated structure comprises dielectric layers DL1 to DL9 and further dielectric layers, which are dielectric layers 24, 38, 42, 52, 58 and the like. Fig. 12. Signal transmission lines SL1 to SL6 and grounding plates GPL1 to GPL4 correspond to RDLs 26, 40, 46, 56 and the like, which are shown in Fig. Figure 12 shows the grounding plates GPL1 to GPL4 being electrically grounded. The signal transmission lines SL1 to SL6 run between the corresponding grounding plates GPL1, GPL2, GPL3, and GPL4 and can form a single-line transmission line or differential transmission lines. In some embodiments of the present invention, the transmission lines SL1 and SL2 can form a pair of differential transmission lines, and the transmission lines SL3 and SL4 can also form a pair of differential transmission lines. Furthermore, RDLs RDL1 to RDL10 and vias V1, V2, V3, V4, V5, V6, V7, and the like are shown. The shapes of these vias correspond to the material and manufacturing processes for the corresponding dielectric layers, which are described with reference to the Fig. 2 to 6 as well as 9 and 10 have been discussed.

[0030] The in Fig. The structure shown in 19A may correspond to some parts in the package substrate 64', which is described in Fig. Figure 12 shows that, for example, dielectric layers DL2, DL4 and DL6 can be substituted for dielectric layers 38 and 52 ( Fig. 12) correspond, and they are manufactured with similar materials, similar manufacturing processes, and similar thicknesses to these, which may be larger, and they may be manufactured from a molding compound. The dielectric layers DL1, DL3, and DL5 can correspond to the dielectric layers 42 and 58 ( Fig. 15) correspond, and they are manufactured using similar materials, similar manufacturing processes and similar thicknesses to these, which may be smaller, and they may be made from a photosensitive material, such as polyimide or PBO. Fig. Figure 19A also shows the RDLs with pads and vias for making vertical electrical connections, corresponding to the RDLs and vias shown in Fig. 12 are shown.

[0031] The structure that is in the Fig. 19A and Fig. As shown in Figure 15, it can be used to manufacture high-speed transmission lines (such as differential transmission lines) and can be used for large packages where the transmission lines are long and thus the insertion loss is high. To reduce the insertion loss, the line width W1 ( Fig. 19A) of the transmission lines is preferably increased (for example, so that it is larger than about 15 µm to about 20 µm) so that the resistance of the transmission lines can be reduced. However, increasing the width of the transmission lines adversely reduces the impedance of the transmission lines, resulting in a mismatch of impedance values ​​between different parts of the package. In embodiments of the present invention, the distance S2 ( Fig. 12 and Fig. 19A) between the transmission line (such as SL1 / SL2 / SL3 / SL4) and one of the adjacent grounding plates (such as GPL2) is increased so that when the line width W1 is increased, the impedance is not reduced and can be maintained at a setpoint (for example, 100 Ω). In some embodiments, the distance S1 is not increased. This is because the fabrication of the RDLs in thicker dielectric layers (such as 38 in Fig. 12) with two plating processes (such as in the Fig. 2 to 6) is connected and manufacturing costs are high. If the distance S2 ( Fig. 19A) is small, the dielectric layers (such as DL1, DL3, DL5, etc.) can be manufactured using photosensitive materials, which means that the corresponding vias (such as 46V in Fig. 12) and the corresponding RDL lines (such as 46L in Fig. 12) can be manufactured in the same process and the manufacturing costs of these parts of the RDLs do not increase. Therefore, by using alternating thicker and thinner dielectric layers, the requirement to reduce insertion loss and keep manufacturing costs low can be balanced with the requirement not to decrease the impedance of the transmission lines.

[0032] The in Fig. The embodiment shown in Figure 19A is relatively inexpensive, since some dielectric layers, such as layers DL1, DL3, DL5 and DL7, are made from photosensitive materials and the corresponding RDLs RDL2, RDL4, RDL6, etc. are produced by a single-plating process (as in the Fig. 9 and Fig. 10). In further embodiments of the present invention, which are shown in Fig. As shown in Figure 19B, a high-performance structure is produced using more molding compound layers. Accordingly, the RDLs in the molding compound layers are produced using a manufacturing process with two plating processes (as shown in the Fig. (shown in 2 to 6). For example, in Fig. 19B The dielectric layers DL3 and DL5 (in addition to layers DL2, DL4, and DL6) are manufactured from a molding compound. Accordingly, the spacing S1" can be increased so that it is, for example, in the same range as the spacing S2. The performance of the resulting structure can be further adjusted and improved, but this comes at the expense of cost. This offers a possibility for the manufacture of circuits that require a specific performance level. To adapt to the use of a molding compound for manufacturing the dielectric layers DL3 and DL5, the vias V3, V5, and V7 and their overlying metal conductors RDL3, RDL5, and RDL7 are double-plated (similar to the processes in the Fig. 2 to 6 are similar) manufactured, as indicated by the shapes of the vias V3, V5 and V7. It should be understood that each of the in the Fig. 19A and Fig. The structures shown in 19B can be integrated into each of the embodiments described in the Fig. 15, Fig. 16, Fig. 17 and Fig. 18 are shown.

[0033] In some embodiments, which are in Fig. As shown in Figure 19A, the dielectric layer (DL2, DL4, or DL6) directly above the transmission lines (SL1 / SL2 or SL3 / SL4) is thicker than the dielectric layers (DL1, DL3, or DL5) directly below the transmission lines. In alternative embodiments, the dielectric layer (DL2, DL4, or DL6) directly above the transmission lines (SL1 / SL2 or SL3 / SL4) is thinner than the dielectric layers (DL1, DL3, or DL5) directly below the transmission lines. In these embodiments, the thinner dielectric layers DL2, DL4, and DL6 are produced using (for example) a photosensitive material, while the thicker dielectric layers DL1, DL3, and DL5 are produced using heterogeneous materials, such as a molding compound.

[0034] Fig. Figure 20 shows a schematic top view of the transmission lines SL1 and SL2, with the [unclear] Fig. 19A and Fig. Sectional view shown in Figure 19B of reference cross-section 19 - 19 of Fig. 20 can be obtained. Furthermore, the exemplary shape of the earthing plates GPL1, GLP2, GPL3 and GPL4 is shown using dashed lines.

[0035] Let's return to... Fig. 15. In some embodiments, the package substrate 64' includes horizontal high-speed transmission lines, and therefore the package substrate 64' is used to transmit high-speed signals (such as high-frequency signals). The package substrate 66 can be used to transmit current signals or low-speed signals. Accordingly, the dielectric layers in the package substrate 66 can be thick or thin without affecting the performance of the resulting circuit.

[0036] In some embodiments, some of the RDLs in the package substrate 64' are used to route horizontal high-speed transmission lines, while other RDLs do not have high-speed transmission lines routed horizontally within them. In some embodiments, the dielectric layers (such as layers DL1 to DL6 of Fig. 19A) with horizontal high-speed transmission lines, the alternating scheme is used, while other dielectric layers (such as layers DL7 to DL9 of Fig. 19A), which do not have horizontal high-speed transmission lines, can be manufactured using photosensitive materials, with the scheme of the RDLs manufactured therein being applicable. Fig. 9 and Fig. 10 is used. For example, the multiple RDL layers (such as RDLs 26, 40 and 46 of Fig. 15), which are closer to the package component 88, are used for routing high-speed transmission lines, while the RDL layers above them, up to RDLs 56, can be made with photosensitive materials. Thus, the materials for the dielectric layers are selected accordingly.

[0037] The package manufacturing processes that are used in the Fig. Figures 1 to 15 are referred to as processes with an RDL-first scheme, in which RDLs are produced in the package substrate 64' before the package component 88 is bonded. Fig. Figure 16 shows a package 92 fabricated using an RDL-last scheme. In the fabrication of the package 92, the package component 88 is first provided, on whose surface metal pads 94 are arranged. Then, a package substrate 64 is fabricated layer by layer on the package component 88. For example, a dielectric layer 24' of a photosensitive (homogeneous) material is first fabricated, and RDLs 26' are fabricated to extend into the dielectric layer 24' to contact the metal pads 94. In subsequent processes, the dielectric layers 38, 42, and 52 and the RDLs / vias 32, 40, 46, 50, and 56, etc., are fabricated. The package substrate 66 is then bonded to the package substrate 64 and encapsulated in the encapsulation material 84.The resulting composite package component is then separated, resulting in a plurality of packages 92 that have the package substrate 64'.

[0038] Fig. Figure 17 shows Package 92 according to some embodiments. These embodiments are related to Package 92. Fig. 15 (for which the RDL-first scheme is used) is similar, except that in Fig. The package substrate 66 shown in Figure 15 is not used. Instead, package component 90 is bonded directly to package substrate 64'.

[0039] Fig. Figure 18 shows Package 92 according to some embodiments. These embodiments are those of Fig. 16 (for which the RDL-last scheme is used) is similar, except that package substrate 66 is not used. Instead, package component 90 is bonded directly to package substrate 64'.

[0040] Fig. 21 is an enlarged representation of an area 96 of Fig. Figure 15 shows a portion (of a heterogeneous material, such as) of the dielectric layer 38, a portion of the dielectric layer 42, and a portion of the RDL 40. As explained above, the dielectric layer 38 can comprise a base material 38A, such as an epoxy, resin, polymer, and the like, and spherical particles 38B. Through the planarization process, the upper portions of some of the spherical particles 38B can be removed, resulting in partial particles that have planar top surfaces coplanar with the planar top surface of the base material 38A. The underside of the dielectric layer 42 contacts the planar top surfaces of the partial particles 38B and the base material 38A. However, the dielectric layer 42 can also be homogeneous and contain no particles.

[0041] In the embodiments described above, some processes and structural elements according to some embodiments of the present invention are discussed, which are used to fabricate a three-dimensional (3D) package. Other processes and structural elements may also be used. For example, test structures may be used to support the verification testing of the 3D packaging or 3DIC components. The test structures may include, for example, test pads fabricated in a redistribution layer or on a substrate, which enable the testing of the 3D packaging or 3DIC components, the use of probes and / or probe cards, and the like. The verification testing may be performed on intermediate structures as well as on final structures.Furthermore, the structures and procedures described here can be used in conjunction with testing methodologies that include intermediate verification of proven good dies to increase yield and reduce costs.

[0042] The embodiments of the present invention have several advantages. By using a molding compound or similar material on one side (top or bottom) of transmission lines, the width of the transmission lines can be increased (to reduce resistance) without an undesirable reduction in the impedance of the transmission lines. On the other side (bottom or top), a photosensitive material can be used to reduce manufacturing costs. Thus, in the embodiments of the present invention, the performance of the circuits and the manufacturing costs are balanced.

[0043] In some embodiments of the present invention, a method comprises the following steps: producing a first redistribution line; producing a first polymer layer having a first part enclosing the first redistribution line and a second part covering the first redistribution line; producing a pair of differential transmission lines over and in contact with the first polymer layer; overmolding the pair of differential transmission lines with a first molding compound, the first molding compound having a first part enclosing the pair of differential transmission lines and a second part covering the pair of differential transmission lines; and producing an electrical connecting element over and in electrical connection with the pair of differential transmission lines.In one embodiment, the method further comprises: fabricating a second redistribution line simultaneously with the fabrication of the pair of differential transmission lines; fabricating a via over and in contact with the second redistribution line; and performing a planarization process to bring the top surfaces of the via and the first molding compound to the same level. In one embodiment, fabricating the second redistribution line comprises a first plating process, and fabricating the via comprises a second plating process.In one embodiment, the method further comprises: manufacturing a first grounding plate covered by the pair of differential transmission lines, wherein the pair of differential transmission lines is spaced a first distance from the first grounding plate; and manufacturing a second grounding plate covering the pair of differential transmission lines, wherein the pair of differential transmission lines is spaced a second distance from the second grounding plate, which is greater than the first distance. In one embodiment, the first molding compound comprises a base material and filler particles in the base material, wherein the first polymer layer is made of a homogeneous material.In one embodiment, the method further comprises: bonding a first package substrate to the electrical connecting element; and performing a singulation process to saw the first polymer layer and the first molding compound into a second package substrate. In another embodiment, the method further comprises: producing a second polymer layer over and in contact with the first molding compound; and producing a second molding compound over and in contact with the second polymer layer.

[0044] In some embodiments of the present invention, a method comprises the following steps: producing a plurality of polymer layers; producing a plurality of molding compound layers, wherein the plurality of polymer layers and the plurality of molding compound layers are produced alternately, and each of the plurality of molding compound layers is produced by processes that include distributing a molding compound material and performing a planarization process to flatten a top surface of the molding compound material; producing a first redistribution line in each of the plurality of polymer layers; and producing a second redistribution line in each of the plurality of molding compound layers.In one embodiment, one of the plurality of molding compound layers is thicker than a first and a second polymer layer of the plurality of polymer layers, wherein the first polymer layer is arranged above and in contact with one of the plurality of molding compound layers, and the second polymer layer is arranged below and in contact with one of the plurality of molding compound layers. In one embodiment, the plurality of polymer layers is not planarized by planarization processes. In one embodiment, the method further comprises producing a plurality of vias, each in one of the plurality of molding compound layers, wherein each of the plurality of vias and a corresponding underlying redistribution line are produced in separate processes. In one embodiment, each of the plurality of vias is planarized by a corresponding planarization process.In one embodiment, the method further comprises bonding a package substrate for electrical connection to the first redistribution line. In another embodiment, the method further comprises fabricating a pair of differential transmission lines in one of the plurality of polymer layers and the plurality of molding compound layers. In another embodiment, the method further comprises: fabricating a first grounding plate above the pair of differential transmission lines, wherein the pair of differential transmission lines is spaced a first distance from the first grounding plate; and fabricating a second grounding plate below the pair of differential transmission lines, wherein the pair of differential transmission lines is spaced a second distance from the second grounding plate, which is different from the first distance.In one embodiment, the pair of differential transmission lines is arranged in one of the plurality of molding compound layers, and the first grounding plate and the second grounding plate are arranged in two of the plurality of polymer layers, the first spacing being greater than the second spacing.

[0045] According to some embodiments of the present invention, a package comprises: a plurality of polymer layers, wherein the plurality of polymer layers have first thicknesses; a plurality of molding compound layers, wherein the plurality of polymer layers and the plurality of molding compound layers are arranged alternately and the plurality of molding compound layers have second thicknesses that are greater than the first thicknesses; a first redistribution line in each of the plurality of polymer layers; and a second redistribution line in each of the plurality of molding compound layers. In one embodiment, the package further comprises a pair of differential transmission lines in one of the plurality of polymer layers and in one of the plurality of molding compound layers.In one embodiment, the package further comprises: a first grounding plate above the pair of differential transmission lines, wherein the pair of differential transmission lines is spaced a first distance from the first grounding plate; and a second grounding plate below the pair of differential transmission lines, wherein the pair of differential transmission lines is spaced a second distance from the second grounding plate, which differs from the first distance. In one embodiment, the plurality of polymer layers and the plurality of molding compound layers are part of a first package substrate, wherein the package further comprises a second package substrate bonded to the first package substrate.

Claims

[1] Procedure with the following steps: Establishing an initial redistribution line (RDL1); Producing a first polymer layer (DL1) with a first part that encloses the first redistribution line (RDL1) and a second part that covers the first redistribution line (RDL1); Creating a pair of differential transmission lines (SL1, SL2) over and in contact with the first polymer layer (DL1); Establishing a second redistribution line (RDL2) simultaneously with establishing the pair of differential transmission lines (SL1, SL2); Establishing a through-hole connection (V3) across and in contact with the second redistribution line (RDL2); Overmolding the pair of differential transmission lines (SL1, SL2) and the via (V3) with a first molding compound (DL2), wherein the first molding compound has a first part that encloses the pair of differential transmission lines (SL1, SL2) and a second part that covers the pair of differential transmission lines (SL1, SL2) and encloses the via (V3); and Performing a planarization process to bring the top surfaces of the via (V3) and the first molding compound (DL2) to the same level; Establishing an electrical connecting element (62) over and in electrical connection with the pair of differential transmission lines (SL1, SL2). [2] Method according to claim 1, wherein the production of the second redistribution line (RDL2) comprises a first plating process and the production of the through-hole plating (V3) comprises a second plating process. [3] A method according to any of the preceding claims, further comprising: Establishing a first grounding plate (GPL1) covered by the pair of differential transmission lines (SL1, SL2), wherein the pair of differential transmission lines (SL1, SL2) is spaced a first distance (S1) from the first grounding plate (GPL1); and Producing a second grounding plate (GPL2) that covers the pair of differential transmission lines (SL1, SL2), wherein the pair of differential transmission lines (SL1, SL2) is spaced a second distance (S2) from the second grounding plate (GPL2) which is greater than the first distance (S1). [4] Method according to any of the preceding claims, wherein the first molding compound (DL2) comprises a base material (38A) and filler particles (38B) in the base material (38A) and the first polymer layer (DL1) is produced from a homogeneous material. [5] A method according to any of the preceding claims, further comprising: Bonding of a first package substrate (66) to the electrical connecting element (62); and Performing a singulation process to saw the first polymer layer (DL1) and the first molding compound (DL2) into a second package substrate. [6] A method according to any of the preceding claims, further comprising: Forming a second polymer layer (DL3) over and in contact with the first molding compound (DL2); and Producing a second molding compound (DL4) over and in contact with the second polymer layer (DL3). [7] Procedure with the following steps: Production of multiple polymer layers (DL1, DL3, DL5); Producing a plurality of molding compound layers (DL2, DL4, DL6), wherein the multiple polymer layers (DL1, DL3, DL5) and the multiple molding compound layers (DL2, DL4, DL6) are produced alternately; Establishing a first redistribution line (RDL1, RDL3, RDL5) in each of the plurality of polymer layers (DL1, DL3, DL5); and Creating a second redistribution line (RDL2, RDL4, RDL6) in each of the plurality of molding compound layers (DL2, DL4, DL6), comprising the fabrication of a plurality of vias (V3, V5, V7) each in one of the plurality of molding compound layers (DL2, DL4, DL6), wherein each of the plurality of vias (V3, V5, V7) and a corresponding underlying redistribution line (RDL2, RDL4, RDL6) are fabricated in separate processes; Fabrication of a pair of differential transmission lines (SL1, SL2) in one of the majority of polymer layers (DL1, DL3, DL5) and the majority of molding compound layers (DL2, DL4, DL6); where each of the multiple molding compound layers (DL2, DL4, DL6) is produced using processes that include the following: Distributing a molding compound material (38) such that a first part of the molding compound material (38) surrounds the pair of differential transmission lines (SL1, SL2) and a second part of the molding compound material (38) covers the pair of differential transmission lines (SL1, SL2) and surrounds the respective vias (V3, V5, V7) located in the molding compound layer (DL2, DL4, DL6), and Performing a planarization process to bring the top surfaces of the via and the molding compound material (38) to the same level. [8] Method according to claim 7, wherein one of the plurality of molding compound layers (DL2, DL4, DL6) is thicker than a first and a second polymer layer of the plurality of polymer layers (DL1, DL3, DL5), wherein the first polymer layer is arranged above and in contact with one of the plurality of molding compound layers (DL2, DL4, DL6) and the second polymer layer is arranged below and in contact with one of the plurality of molding compound layers (DL2, DL4, DL6). [9] Method according to claim 7 or 8, wherein the majority of polymer layers (DL1, DL3, DL5) are not planarized by planarization processes. [10] Method according to claim 7, wherein each of the plurality of vias (V3, V5, V7) is planarized by a corresponding planarization process. [11] Method according to any one of claims 7 to 10, further comprising bonding a package substrate (64') for electrical connection to the first redistribution line (RDL1). [12] The method of claim 7, further comprising: Establishing a first grounding plate (GPL2) above the pair of differential transmission lines (SL1, SL2), wherein the pair of differential transmission lines (SL1, SL2) is spaced a first distance (S2) from the first grounding plate (GPL2); and Establishing a second grounding plate (GPL1) under the pair of differential transmission lines (SL1, SL2), wherein the pair of differential transmission lines (SL1, SL2) is spaced a second distance (S1) from the second grounding plate (GPL1) which is different from the first distance (S2). [13] Method according to claim 12, wherein the pair of differential transmission lines (SL1, SL2) is arranged in one of the plurality of molding compound layers (DL2, DL4, DL6) and the first grounding plate (GPL2) and the second grounding plate (GPL1) are arranged in two of the plurality of polymer layers (DL1, DL3, DL5), wherein the first distance (S2) is greater than the second distance (S1). [14] Package (92) containing: a plurality of polymer layers (DL1, DL3, DL5), wherein the multiple polymer layers (DL1, DL3, DL5) have first thicknesses (T2); a plurality of molding compound layers (DL2, DL4, DL6), wherein the multiple polymer layers (DL1, DL3, DL5) and the multiple molding compound layers (DL2, DL4, DL6) are arranged alternately, wherein the multiple molding compound layers (DL2, DL4, DL6) have second thicknesses (T3) that are greater than the first thicknesses (T2); a first redistribution line (RDL1, RDL3, RDL5) in each of the plurality of polymer layers (DL1, DL3, DL5); and a second redistribution line (RDL2, RDL4, RDL6) in each of the plurality of molding compound layers (DL2, DL4, DL6); a through-hole connection (V3, V5, V7) over and in contact with each of the second redistribution lines (RDL2, RDL4, RDL6); a pair of differential transmission lines (SL1, SL2) in one of the majority of polymer layers (DL1, DL3, DL5) and the majority of molding compound layers (DL2, DL4, DL6); wherein each of the plurality of molding compound layers (DL2, DL4, DL6) has a first part that encloses the respective pair of differential transmission lines (SL1, SL2) and a second part that covers the respective pair of differential transmission lines (SL1, SL2) and encloses the respective via (V3, V5, V7), wherein the respective top surfaces of the vias (V3, V5, V7) and the molding compound layers (DL2, DL4, DL6) are at the same level. [15] Package (92) according to claim 14, further comprising: a first grounding plate (GPL2) above the pair of differential transmission lines (SL1, SL2), wherein the pair of differential transmission lines (SL1, SL2) is spaced a first distance (S2) from the first grounding plate (GPL2); and a second grounding plate (GPL1) under the pair of differential transmission lines (SL1, SL2), wherein the pair of differential transmission lines (SL1, SL2) is spaced a second distance (S1) from the second grounding plate (GPL1) which is different from the first distance (S2). [16] Package (92) according to one of claims 14 to 15, wherein the plurality of polymer layers (DL1, DL3, DL5) and the plurality of molding compound layers (DL2, DL4, DL6) are parts of a first package substrate (64') and the package (92) further comprises a second package substrate (66) which is bonded to the first package substrate (64').

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