Measurement, calibration and adjustment of the memory bus duty cycle

Abstract

Storage device (102, 202), comprising: one or more storage devices (110, 203); a controller (106, 230) coupled to one or more storage devices; and a measuring circuit (114, 214, 300) coupled to the controller, the measuring circuit comprising the following: a multitude of successive delay taps (306a - 306n); a plurality of flip-flop registers (302a - 302n), wherein each flip-flop register of the plurality of flip-flop registers has a first input (308) and a second input (310); a first input line (314) that is directly coupled to the first input of each flip-flop register of the plurality of flip-flop registers; a second input line (316) coupled to the second input of each flip-flop register of the plurality of flip-flop registers via successive delay taps of the plurality of successive delay taps, each successive delay tap having a constant delay; and a measurement signal (318) configured to measure a clock duty cycle to enable the measuring circuit; wherein the measuring circuit further comprises a variable delay circuit (322), wherein the second input line is coupled to the successive delay taps via the variable delay circuit; and where the same clock signal (312) is input into both the first input line and the second input line.

Description

BACKGROUND OF REVELATION Area of ​​Revelation

[0001] Embodiments of the present disclosure generally relate to storage devices, such as solid-state drives (SSDs). Description of the state of the art

[0002] During the operation of a data storage device, such as an SSD, data can be communicated between a controller and the device's memory via a parallel, high-speed data bus that connects the controller and the memory. For example, one or more data values ​​can be provided to or received from the data bus at a transfer rate based on the frequency of a clock signal. To illustrate, an initial data value can be provided to the data bus by the controller in response to a rising or falling edge of the clock signal.

[0003] As the device's performance is further increased, the clock frequency requirements may rise, and environmental conditions such as temperature and supply voltage may change. Such changes can degrade bus signal characteristics, such as setup time and hold time. This degradation limits the maximum clock frequency, which in turn limits system performance in some data usage scenarios. Consequently, the device's clock cycle may fall outside of tolerance, necessitating clock cycle calibration to achieve higher device performance.

[0004] However, calibrating the duty cycle of a device can be challenging. Measuring the duty cycle during manufacturing can allow for fine-tuning of device configurations, but requires larger design tolerances, increasing costs and reducing device performance. Furthermore, measuring the duty cycle during manufacturing requires accounting for potential changes in environmental conditions before they occur, which may be less accurate and necessitate additional margins. Other duty cycle calibration methods require the storage device to stop operating to run through different training sequences, preventing its use until reconfiguration is complete.

[0005] Therefore, in the prior art there is a need for a data storage device with a clock cycle that can be dynamically calibrated.

[0006] US 2009 / 0183046 A1 relates to a circuit for measuring clock jitter, wherein an internal clock signal and a single-pulse signal are generated, delayed clock signals are generated, and the single-pulse signal is registered synchronously with the delayed clock signals by latches. US 2017 / 0255223 A1 relates to a clock monitoring circuit for safety applications. US 2018 / 0011142 A1 relates to methods and devices for characterizing clock signals in an application-specific integrated circuit (ASIC). SUMMARY OF THE REVELATION

[0007] According to the invention, a storage device and a method for operating a storage device with the features of the independent claims are provided; dependent claims relate to preferred embodiments. A method and a device for dynamically monitoring, measuring, and adjusting a clock duty cycle of an operating storage device are disclosed. A storage device includes a measuring circuit comprising a plurality of flip-flop registers coupled to a first input line, each flip-flop register having a first input and a second input. One or more delay taps are coupled to each flip-flop register and are arranged on a second input line. While the device is operating, a clock signal is fed directly into the first input of each flip-flop register via the first input line.Simultaneously, the clock signal is fed into the second input of the flip-flop register via one or more delay taps on the second input line. The flip-flop registers are then read to determine the clock duty cycle of the device, and the clock frequency is set as needed.

[0008] In one embodiment, a storage device comprises one or more storage units, a controller coupled to the one or more storage units, and a measurement circuit coupled to the controller. The measurement circuit comprises a plurality of successive delay taps and a plurality of flip-flop registers. Each flip-flop register of the plurality of flip-flop registers comprises a first input and a second input. The measurement circuit further comprises a first input line that is directly coupled to the first input of each flip-flop register of the plurality of flip-flop registers.The measurement circuit further comprises a second input line coupled via successive delay taps of the multiple successive delay taps to the second input of each flip-flop register of the plurality of flip-flop registers, each successive delay tap having a constant delay, and a measurement signal configured to enable measurement of a clock duty cycle of the measurement circuit.

[0009] In a further embodiment, a method for operating a storage device comprises inputting a first signal into a plurality of flip-flop registers of a measurement circuit, wherein the first signal is directly inputted to a first input of each of the flip-flop registers of the plurality. The method further comprises simultaneously inputting a second signal into a plurality of delay taps. One or more delay taps are coupled to each of the flip-flop registers of the plurality. The second signal passes through each of the one or more delay taps to a second input of each flip-flop register of the plurality. The method further comprises reading the plurality of flip-flop registers to measure a clock duty cycle and calibrating the clock duty cycle in response to the measurement during operation of the storage device.

[0010] In a further embodiment, a method for operating a storage device comprises switching the storage device into an active state, measuring a clock duty cycle of the storage device using a measuring circuit consisting of a plurality of flip-flop registers coupled to a chain of delay taps, determining a value that the clock cycle has changed, determining a configuration value for calibrating the clock cycle, calibrating the clock cycle, and measuring the clock cycle using the measuring circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] To clarify how the features of the present disclosure set forth above can be understood in detail, a more comprehensive description of the disclosure, which is briefly summarized above, may be given with reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings only depict typical embodiments of this disclosure and should therefore not be considered as limiting its scope of protection, since the disclosure may permit other equally effective embodiments. Fig. Figure 1 illustrates a schematic storage system according to one embodiment. Fig. Figure 2 represents an illustrative example of a data storage system according to a further embodiment. Fig. Figure 3A illustrates a measuring circuit arranged in a storage device according to one embodiment. Fig. Figure 3B illustrates a variable delay circuit arranged in a measuring circuit, according to one embodiment. Fig. Figure 4 illustrates a method of using a measuring circuit to monitor and measure a duty cycle of a storage device, according to one embodiment.

[0012] For clarity, identical reference numerals have been used, where possible, to denote identical elements common to the figures. It is considered that the elements disclosed in one embodiment can advantageously be applied to other embodiments without specific enumeration. DETAILED DESCRIPTION

[0013] The following refers to embodiments of the disclosure. However, it should be understood that the disclosure is not limited to specific described embodiments. Instead, any combination of the following features and elements, whether or not they relate to different embodiments, is considered for the implementation and practice of the disclosure. Even if embodiments of the disclosure may offer advantages over other possible solutions and / or the prior art, the fact that a particular embodiment offers a special advantage or not does not constitute a limitation of the disclosure. The following aspects, features, embodiments, and advantages are therefore only illustrative and are not considered elements or limitations of the appended claims unless they are expressly mentioned in one or more claims.Likewise, any reference to “the disclosure” shall not be construed as a generalization of any inventive subject matter disclosed herein, nor shall it be regarded as an element or limitation of the attached claims, unless expressly stated in a claim or claims.

[0014] A method and a device for dynamically monitoring, measuring, and adjusting the clock duty cycle of an operating storage device are disclosed. The storage device includes a measuring circuit comprising a plurality of flip-flop registers coupled to a first input line, each flip-flop register having a first input and a second input. One or more delay taps are coupled to each flip-flop register and are arranged on a second input line. While the device is operating, a clock signal is directly inputted to the first input of each flip-flop register via the first input line. Simultaneously, the clock signal is also injected into the second input of the flip-flop register via one or more delay taps on the second input line.The flip-flop registers are then read to determine the clock duty cycle of the device, and the clock frequency is adjusted as needed.

[0015] Fig. Figure 1 illustrates a schematic storage system 100 according to one embodiment. The storage system 100 comprises a host device 104 coupled to a storage device 102. The host device 104 can store and / or retrieve data on and / or from one or more storage devices, such as the storage device 102. As shown in Fig. As shown in Figure 1, the host device 104 can communicate with the storage device 102 via a host interface bus 108, such as a host interface bus. The host device 104 can be any of a large number of devices, including computer servers, NAS (Network Attached Storage) units, desktop computers, notebook computers (i.e., laptops), tablet computers, peripheral devices, mobile phone handsets such as "smartphones" or "smart pads," televisions, cameras, display devices, digital media players, video game consoles, video streaming devices, and the like.

[0016] The storage device 102 comprises a controller 106, which is communicatively coupled to the host device 104 via the host interface bus 108. The controller 106 of the storage device 102 is further connected via an NVM interface bus 112 to a non-volatile memory (NVM) 110, for example, flash memory devices or matrices. The NVM interface bus 112 (i.e., the storage interface) comprises a data bus. In one embodiment, the NVM interface bus 112 comprises a flash interface data bus. In some examples, the storage device 102 may include additional components that are described in Fig. 1. For clarity, the storage device 102 may include a printed circuit board (PCB) to which components of the storage device 102 are mechanically attached and which contains electrically conductive traces that electrically connect components of the storage device 102 or the like. In some examples, the physical dimensions and connection configurations of the storage device 102 may conform to one or more standard form factors. Some examples of standard form factors include, but are not limited to, a 3.5-inch data storage device (e.g., a hard disk drive or SSD), a 2.5-inch data storage device, a 1.8-inch data storage device, a Peripheral Component Connection (PCI), PCI Extended (PCI-X), PCI Express (PCIe) (e.g., PCIe x1, x4, x8, x16, PCIe Mini Card, MiniPCI, etc.).In some examples, the storage device 102 can be directly coupled to a mainboard of the host device 104 (e.g., directly soldered).

[0017] The host interface bus 108 of the storage device 102 can include a data bus for data exchange with the host device 104 and / or a control bus for exchanging commands with the host device 104. The host interface bus 108 can operate according to a suitable protocol. For example, the host interface bus 108 can operate according to one or more of the following protocols: Advanced Technology Attachment (ATA) (e.g., Serial ATA (SATA) and Parallel ATA (PATA)), Fibre Channel Protocol (FCP), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), PCI and PCIe, Non-Volatile Memory Express (NVMe), or the like. The electrical connection of the host interface bus 108 (e.g.,The data bus, the control bus, or both are electrically connected to the controller 106 and establish an electrical connection between the host device 104 and the controller 106, allowing data to be exchanged between them. In some examples, the storage device 102 can also draw power from the host device 104 via the electrical connection of the host interface bus 108.

[0018] The storage device 102 includes NVM 110, which can include a variety of storage devices. NVM 110 can be configured to store and / or retrieve data. For example, a storage device of NVM 110 can receive data and a message from controller 106 instructing the storage device to store the data. Similarly, the storage device of NVM 110 can receive a message from controller 106 instructing the storage device to retrieve the data. In some examples, each of the storage devices can be referred to as a matrix. In some examples, a single physical chip can contain a variety of matrices (i.e., a variety of storage devices). In some examples, each storage device can be configured to store relatively large amounts of data (e.g.,128 MB, 256 MB, 412 MB, 1 GB, 2 GB, 3 GB, 8 GB, 16 GB, 32 GB, 24 GB, 128 GB, 256 GB, 412 GB, 1 TB, etc.).

[0019] In some examples, each NVM 110 storage device can include any type of non-volatile storage device, such as flash storage devices, phase-change memory devices (PCM devices), resistive random-access memory devices (ReRAM devices), magnetoresistive random-access memory devices (MRAM devices), ferroelectric random-access memory (FRAM), holographic storage devices, and any other type of non-volatile storage device.

[0020] The NVM 110 can include one or more flash memory devices. Flash memory devices can be NAND-based or NOR-based and can store data based on a charge contained in a floating gate of a transistor for each flash memory cell. In some flash memory devices, such as NAND-based flash memory devices, the flash memory device can be divided into multiple blocks, which can be further subdivided into multiple pages. Each block can contain 128 KB of data, 256 KB of data, 2 MB of data, 8 MB of data, and so on. In some cases, each page can contain 1 kilobyte (KB) of data, 3 KB of data, 8 KB of data, and so on.

[0021] The controller 106 of the storage device 102 can manage one or more operations of the storage device 102. For example, the controller 106 can manage reading data from and / or writing data to the NVM 110 via the NVM interface bus 112. In some embodiments, when the storage device 102 receives a write command from the host device 104, the controller 106 can initiate a data store command to store data in the NVM 110 and monitor the progress of the data store command. The controller 106 can determine at least one operating characteristic of the storage system 100 and store this operating characteristic in the NVM 110. The controller 106 further includes a measurement circuit 114. The measurement circuit 114 is configured to monitor, measure, and adjust a clock duty cycle of the storage device 102.

[0022] Fig. Figure 2 presents an illustrative example of a data storage system 200 according to a further embodiment. The data storage system 200 includes a data storage device 202 coupled to a host device 270. The data storage device 202 can access the storage device 102 from Fig. 1 and the host device 270 can access the host device 104 from Fig. Be 1.

[0023] The data storage device 202 can include a storage unit, such as a storage unit 203. The storage unit 203 can contain one or more storage matrices (e.g., one storage matrix, two storage matrices, eight storage matrices, or any other number of storage matrices). The storage unit 203 contains a memory 204, for example, a non-volatile memory of memory elements contained in a storage matrix of the storage unit 203. The memory 204 can be assigned to the NVM 110. Fig. 1. For example, Memory 204 can include flash memory, such as NAND flash memory, or resistive memory, such as resistive random access memory (ReRAM), as illustrative examples. Memory 204 can have a three-dimensional (3D) memory configuration. Alternatively, Memory 204 can have a different configuration, such as a two-dimensional (2D) memory configuration or a non-monolithic 3D memory configuration (e.g., a stacked matrix 3D memory configuration).

[0024] The memory 204 can contain one or more areas of memory elements (here also referred to as memory cells), such as a memory area 208 for storing data 206. An example of a memory area is a block, such as a NAND flash erase group of memory elements. Another example of a memory area 208 is a word line of memory elements. Each memory element of the memory 204 can be programmable into a state (e.g., a threshold voltage in a flash configuration or a resistance state in a resistive memory configuration) that indicates one or more bit values.

[0025] The memory device 203 further includes a read / write circuit 210. The read / write circuit 210 is configured to program values ​​onto memory elements of the memory 204 and to sample values ​​from memory elements of the memory 204. The memory device 203 may also include a circuit 216 (e.g., one or more data buffers, one or more control buffers, or a combination thereof).

[0026] The data storage device 202 may further include a controller 230. The controller 230 may include a first interface 238 (e.g., a host interface), an error correction code (ECC) engine 234, a timing device 236, a second interface 232 (e.g., a memory interface), and one or more voltage regulators 242. For further illustration, the first interface 238 may include one or more intermediate storage devices for receiving data and commands from the host device 270, and the second interface 232 may include one or more bus drivers for sending data and commands to the circuitry 216 of the storage device 203. The controller 230 may store (or access) a file table 240, such as a file allocation table (FAT). The controller 230 also includes a measuring circuit 214. The measuring circuit 214 may include the measuring circuit 114. Fig. 1. The measuring circuit 214 is configured to monitor and measure a clock duty cycle of the data storage device 202.

[0027] The host device 270 can contain a circuit 272. For example, the circuit 272 can contain one or more bus drivers. The circuit 272 can be integrated into or coupled to a processor or controller of the host device 270, such as in a host processing device 274 (e.g., an application processor).

[0028] The data storage device 202 and the host processing device 274 are coupled via a connection 250 (e.g., a bus). The connection 250 can be the host interface bus 108. Fig. Be 1. For example, illustrates Fig. 2, that the connection 250 can contain one or more data lines 251, one or more control lines 252, and one or more time signal lines 253. The connection 250 is coupled to the first interface 238 and to the circuit 272.

[0029] The storage device 203 and the controller 230 are coupled via a connection 220 (e.g., a bus). The connection 220 can be the NVM interface bus 112. Fig. Be 1. For example, illustrates Fig. 2, that connection 220 can contain one or more data lines 221, one or more control lines 222, and one or more time signal lines 223. Connection 220 is coupled to circuit 216 and to the second interface 232.

[0030] In one illustrative implementation, the data storage system 200 further includes a power supply connection 273 (e.g., a "rail" to provide a power supply voltage, such as VDD, VCC, or both). The power supply connection 273 can be coupled to the storage device 203, the controller 230, and the host processing device 274. Depending on the specific implementation, the power supply connection 273 can be powered by a battery (e.g., a battery of a mobile device) or by a power supply device (e.g., a transformer) coupled to a main power supply. In other implementations, the storage device 203, the controller 230, and / or the host processing device 274 are connected by separate power supply connections.

[0031] During operation, the controller 230 is configured to receive data and instructions from the host device 270 using the first interface 238. For example, the controller 230 can receive data 260 from the host device 270 via the first interface 238. To further illustrate, the data 260 can be received via one or more data lines 251 in conjunction with a write access request 262 sent via one or more control lines 252. The data 260 and the request 262 can be received by the controller 230 based on a timing signal 264 (e.g., one or more clock signals, one or more sample signals, or one or more read enable signals) received via one or more timing signal lines 253.For example, the first interface 238 can include one or more intermediate storage devices to receive the data 260 based on the timing signal 264. Although... Fig. Figure 2 illustrates a single timing signal 264; it should be noted that more than one timing signal 264 can be used (e.g., a differential pair of timing signals).

[0032] The ECC Engine 234 can be configured to receive the Data 260 and generate one or more ECC codewords based on the Data 260. The ECC Engine 234 can include a Hamming encoder, a Reed Solomon (RD) encoder, a Bose Chaudhuri Hecquenghem (PHICH) encoder, a Low Density Parity Check (LDPC) encoder, a turbo encoder, an encoder configured to encode data according to one or more other ECC schemes, or a combination thereof.

[0033] The controller 230 is configured to send data and commands to the memory device 203 using the second interface 232 and to receive data from the memory device 203 using the second interface 232. For example, the controller 230 is configured to send data (e.g., one or more ECC codewords generated by the ECC engine 234) and a write command (e.g., a command 224) to cause the memory device 203 to store the data at a specified address of the memory 204. The write command can specify a physical address of a section of the memory 204 that is to store the data.

[0034] To further illustrate, the controller 230 can send the data 228 to the storage device 203 via one or more data lines 221 in conjunction with a write command sent via one or more control lines 222. The storage device 203 can receive the data 228 and the write command 224 based on a clock signal 226 (e.g., one or more clock signals) provided by the controller 230 via one or more timing control signal lines 223. For example, the circuit 216 can include one or more intermediate storage locations configured to receive the data 228 based on the timing control signal 264. The storage device 203 can cause the read / write circuit 210 to write the data 206 to the storage location 204 based on the timing control signal 226. Data 260, data 228 and data 206 can all be the same data at different locations within system 200.Although . Fig. Figure 2 illustrates a single timing signal 226; however, it should be noted that more than one timing signal 226 can be used (e.g., a differential pair of timing signals). Furthermore, in some cases, the timing signal 226 may contain a signal generated by the storage device 203, such as a read enable signal.

[0035] The controller 230 is configured to send a read command (e.g., command 224) to the memory device 203 to access data from a specified address of the memory 204. For example, the controller 230 can send the read command to the memory device 203 in response to receiving a read access request from the host device 270. The read command can specify the physical address of a section of the memory 204. For example, the read command can specify the physical address of a section of the memory 204 that stores the data 206. In response to the read command, the memory device 203 can cause the read / write circuit 210 to sample the section of the memory 204 that stores the data 206 in order to generate captured data (e.g., a representation of the data, which may differ from the data due to one or more bit errors).

[0036] The controller 230 is configured to receive the acquired data from the storage device 203 via the second interface 232. The controller 230 can input the acquired data into the ECC engine 234 to initiate a decoding process to correct one or more bit errors in the acquired data (if any) up to a certain error correction capability of the specific ECC technique. Following decoding of the acquired data, the ECC engine 234 can output the data 260. The controller 230 can provide the data 260 to the host device 270 using the first interface 238.

[0037] Fig. Figure 3A illustrates a measuring circuit 300 that is arranged in a storage device, such as the storage device 102 from Fig. 1 or the storage device 202 from Fig. 2, according to one embodiment. The measuring circuit 300 is firmware-controlled and is configured to dynamically monitor and measure a clock duty cycle of the storage device during operation. The measuring circuit 300 can be configured in the controller 106 of Fig. 1 arranged measuring circuit 114 or the one in the control 230 of Fig. 2 arranged measuring circuit 214.

[0038] The measuring circuit 300 comprises a plurality of flip-flop registers 302a–302n coupled to a chain of delay taps 304. In one embodiment, the measuring circuit 300 includes 128 flip-flop registers 302a–302n. The chain of delay taps 304 comprises a plurality of consecutive delay taps 306a–306n. Each delay tap 306a–306n in the chain of delay taps 304 has the same or constant delay. One or more delay taps 306a–306n are coupled between each of the flip-flop registers 302a–302n. In one embodiment, a delay tap 306a–306n is coupled between each of the flip-flop registers 302a–302n.

[0039] Each flip-flop register 302a–302n has a first input 308 and a second input 310. The first input 308 can be a data input, and the second input 310 can be a clock input. A clock signal 312 (labeled Clk) is split into a first input line 314 and a second input line 316. Thus, the first input line 314 and the second input line 316 are the same clock signal 312. The first input line 314 is directly coupled to the first input 308 of each flip-flop register 302a–302n. The second input line 316 is coupled to the second input 310 of each flip-flop register 302a–302n via the chain of delay taps 304. Thus, the second input line 316 is directly coupled to the chain of delay taps 304. The chain of delay taps 304 is then coupled via the second input line 316 to the second input 310 of each flip-flop register 302a - 302n.The second input line 316, coupled to the chain of delay taps 304, which comprises the plurality of successive delay taps 306a–306n, each with a constant delay, causes the clock signal 312 to be delayed by a predetermined, known duration. Therefore, the delayed clock signal from the second input line 316 is fed into the second input 310 of each flip-flop register 302a–302n after the first input line 314 has been fed into the first input of each flip-flop register 302a–302n.

[0040] The measuring circuit 300 further includes a measuring signal 318 (labeled En) and a clearing signal 320 (labeled Clr). The clearing signal 320 is configured to reset or clear each of the flip-flop registers 302a–302n before the clock signal 312 is input. Once the flip-flop registers 302a–302n have been reset, the measuring signal 318 is enabled, and the clock signal 312 is passed through the circuit 300. Once the clock signal 312 has propagated through the multiple flip-flop registers 302a–302n, the measuring signal 318 is configured to allow measurement through the flip-flop registers 302a–302n for one clock cycle. The device's firmware is then configured to read flip-flop registers 302a - 302n to determine the clock duty cycle of the storage device.

[0041] Based on the reading of each flip-flop register 302a–302n, a value by which the clock duty cycle is offset, or the value by which the clock frequency should be adjusted, can be determined during operation. For example, a control of the storage device is configured based on the measurement signal 318 to dynamically determine whether the clock frequency (i.e., the high-time value and / or the low-time value of the clock duty cycle) needs to be adjusted and by how much. The clock frequency can be adjusted to achieve an optimal 50% clock duty cycle (i.e., a 50 / 50 balance between the high-time value and the low-time value), as shown by the clock cycle illustrated by the optimal register content readout 324.

[0042] In one embodiment, the measuring circuit 300 further comprises a variable delay circuit 322, which is coupled to the second input line 316. In such an embodiment, the variable delay circuit 322 is arranged upstream of the first delay tap 306a in the chain of delay taps 304. The variable delay circuit 322 can be used to delay the start of the sampling window of the clock duty cycle in order to measure slower clocks.

[0043] Fig. Figure 3B illustrates a variable delay circuit 322 arranged in a measuring circuit according to one embodiment. The variable delay circuit 322 comprises a chain of adjustable delay taps 354. The chain of adjustable delay taps 354 includes a plurality of delay taps 356a–356n configured to adjust the delay amount. The plurality of adjustable delay taps 356a–356n of the variable delay circuit 322 can delay the clock signal 312 by a smaller or larger value than the chain of delay taps 304 of the measuring circuit 300. The delay value added by the chain of adjustable delay taps 354 varies depending on the time of the clock cycle being measured.The delay of each adjustable delay tap 356a–356n in the chain of adjustable delay taps 354 can be set to suit the measured clock cycles. A different delay may be required for each clock period, and adding a different delay amount allows for the selection of a different clock period. The chain of adjustable delay taps 354 is coupled to a multiplexer 360, which is then coupled to the chain of delay taps 304 in the measurement circuit 300. The variable delay circuit 322 adds an incremental delay to the clock cycle measurement, shifting the sampling window of the cycle so that the entire clock cycle can be captured in a few sampling cycles.Thus, for slower clock speeds, the sampling point is delayed, allowing the clock transition to be detected without increasing the number of flip-flop registers 302a–302n used in the measuring circuit 300. By using the variable delay circuit 322, larger sampling windows can be measured with the same measuring circuit 300.

[0044] Fig. Figure 4 illustrates a method 400 for using a measuring circuit to monitor, measure, and calibrate a duty cycle of a storage device according to one embodiment. Method 400 can be combined with the measuring circuit 300 from Fig. 3A can be used. For the sake of clarity, procedure 400 will be used. Fig. 4 with reference to the measuring circuit 300 from Fig. 3A described.

[0045] During operation 402, the storage device is switched to an active state. An active state is a state in which the storage device is operating, e.g., reading and writing to and from the non-volatile memory. The measuring circuit 300 is used to monitor and measure the clock duty cycle while the storage device is active and operational.

[0046] Once the storage device is in active mode, procedure 400 proceeds to operation 404, in which the clock duty cycle is measured. Measuring the clock duty cycle first involves resetting the multitude of flip-flop registers 302a–302n using the clear signal 320. Resetting the multitude of flip-flop registers 302a–302n ensures that each flip-flop register 302a–302n starts in the same initial state, for example, all set to 0. The measurement signal 318 is then enabled for a single clock cycle. The clock signal 312 is then input, with the clock signal 312 being passed through the first input line 314 directly to the first input 308 of each flip-flop register 302a - 302n and through the second input line 316 through one or more successive delay taps 306a - 306n to the second input 310 of each flip-flop register 302a and - 302n.

[0047] Since the second input line 316 propagates through one or more successive delay taps 306a–306n before being fed into the second input 310 of each flip-flop register 302a–302n, the clock signal 312 of the second input line 316 is delayed, thus reaching the plurality of flip-flop registers 302a–302n after the clock signal 312 of the first input line 314. Therefore, when the clock signal 312 of the first input line 314 reaches each flip-flop register 302a–302n, the flip-flop registers 302a–302n are switched to a second state, such as 1 (i.e., switched from 0 to 1). When the clock signal 312 of the second input line 316 reaches each flip-flop register 302a - 302n after being input through the chain of delay taps 304, one or more flip-flop registers 302a - 302n are switched back to the first state (i.e., switched from 1 to 0).The clock signal 312 propagates through the chain of delay taps 304, thereby triggering the sequential switching of the flip-flop registers 302a - 302n. At the end of the clock cycle, each flip-flop register 302a-302n holds the final state of the clock for the delay tap time until it is reset.

[0048] During operation 406, each flip-flop register 302a–302n is read to determine whether the clock duty cycle is within the desired tolerances. If the clock duty cycle is within the desired tolerances, procedure 400 returns to operation 404, and the measuring circuit 300 continues monitoring and measuring the clock duty cycle. If it is determined that the clock cycle is outside the tolerance, procedure 400 proceeds to operation 408.

[0049] Operation 408 improves and / or calibrates the configuration of the storage device. The transition of the clock duty cycle from within to outside the tolerances can be determined based on the readings of flip-flop registers 302a–302n. For example, the first flip-flop register of the set of flip-flop registers 302a–302n, which could not return to its initial state after receiving the clock signal 312 from the second input line 316, can indicate where the transition occurred. Therefore, improving the configuration based on the transition can include determining the amount by which the clock duty cycle is offset and a calibration value required to adjust the clock duty cycle and improve signal integrity. The calibration value can be the amount by which the clock signal frequency should be adjusted to achieve the optimal 50% clock cycle.Furthermore, based on the transition point and the reading of the multitude of flip-flop registers 302a - 302n, the setup and hold times can also be continuously monitored.

[0050] The clock duty cycle is then dynamically calibrated during operation based on the calibration value, while the storage device is still in the active state. Calibrating the storage device may include adjusting the clock frequency. The operation of the storage device does not need to be stopped to calibrate the clock cycle. Once the clock cycle is calibrated, procedure 400 returns to operation 404, and the measurement circuit 300 continues to monitor and measure the clock cycle. Because storage devices are sensitive to environmental changes, such as temperature and supply voltage, the devices may need to be continuously monitored. Thus, procedure 400 can be repeated once or several times to continuously monitor the clock duty cycle without interrupting the operations of the storage device.

[0051] The use of the measurement circuit, consisting of numerous flip-flop registers and delay taps, enables continuous monitoring and measurement of a storage device's clock cycle while the device operates without any performance degradation. If the clock duty cycle is determined to be outside tolerances, the transition point can be identified, allowing the time of the fault to be determined with relative accuracy. The storage device can then be dynamically and accurately configured using a calibration value based on the transition point. Additionally, the measurement circuit, comprised of numerous flip-flop registers and delay taps, allows for continuous measurements of setup and hold times per signal while the storage devices operate under normal conditions.

[0052] Because the duty cycle is monitored, any environmental changes that could affect the duty cycle or cause errors related to it do not need to be individually monitored. This allows for support of multiple fault sources without increasing fault tolerances or costs. Therefore, the storage device's measurement circuitry enables the duty cycle to be dynamically monitored, measured, and adjusted as needed without interrupting the device's operation.

[0053] In one embodiment, a storage device comprises one or more storage units, a controller coupled to the one or more storage units, and a measurement circuit coupled to the controller. The measurement circuit comprises a plurality of successive delay taps and a plurality of flip-flop registers. Each flip-flop register of the plurality of flip-flop registers comprises a first input and a second input. The measurement circuit further comprises a first input line that is directly coupled to the first input of each flip-flop register of the plurality of flip-flop registers.The measurement circuit further comprises a second input line coupled via successive delay taps of the multiple successive delay taps to the second input of each flip-flop register of the plurality of flip-flop registers, each successive delay tap having a constant delay, and a measurement signal configured to enable measurement of a clock duty cycle of the measurement circuit.

[0054] The measurement circuit can be configured to measure the duty cycle of the storage device. The measurement circuit can be configured to adjust the clock frequency of the storage device. The measurement circuit can further include a variable delay circuit. The variable delay circuit can be coupled to the second input line. The second input line can be coupled to successive delay taps via the variable delay circuit. The variable delay circuit can have multiple delay taps. The variable delay circuit can be configured to increase the delay of an input signal to the second input line. The same clock signal can be input to both the first and second input lines.

[0055] In a further embodiment, a method for operating a storage device comprises inputting a first signal into a plurality of flip-flop registers of a measurement circuit, wherein the first signal is directly inputted to a first input of each of the flip-flop registers of the plurality. The method further comprises simultaneously inputting a second signal into a plurality of delay taps. One or more delay taps are coupled to each of the flip-flop registers of the plurality. The second signal passes through each of the one or more delay taps to a second input of each flip-flop register of the plurality. The method further comprises reading the plurality of flip-flop registers to measure a clock duty cycle and calibrating the clock duty cycle in response to the measurement during operation of the storage device.

[0056] The method may further include resetting the plurality of flip-flop registers before the input of the first signal. The measurement circuit may further include a variable delay circuit coupled to the plurality of delay taps. The plurality of flip-flop registers can be measured using a measurement signal from the measurement circuit. The first and second signals may be clock signals. The method may further include switching the storage device to an active state before the input of the first signal. Calibrating the clock cycle may include setting a clock frequency for the storage device.

[0057] In a further embodiment, a method for operating a storage device comprises switching the storage device into an active state, measuring a clock duty cycle of the storage device using a measuring circuit consisting of a plurality of flip-flop registers coupled to a chain of delay taps, determining a value that the clock cycle has changed, determining a configuration value for calibrating the clock cycle, calibrating the clock cycle, and measuring the clock cycle using the measuring circuit.

[0058] The measurement circuit can further include a first clock signal directly coupled to the first input of each flip-flop register of the plurality of flip-flop registers and a chain of delay taps comprising a plurality of delay taps. One or more delay taps in the chain of delay taps can be coupled to each flip-flop register of the plurality of flip-flop registers. The measurement circuit can further include a second clock signal coupled, via the chain of delay taps, to the second input of each flip-flop register of the plurality of flip-flop registers. The first clock signal and the second clock signal can be the same clock signal. The measurement circuit can further include a measurement signal and a variable delay circuit coupled to the beginning of the chain of delay taps.The method may further include continuously monitoring the clock duty cycle while the storage device is in the active state. Calibrating the clock cycle may include setting a clock frequency for the storage device.

[0059] While the foregoing relates to embodiments of the present disclosure, other and further embodiments of the disclosure may be elaborated without deviating from the basic scope of protection, and the scope of protection is determined by the following claims.

Claims

[1] Storage device (102, 202), comprising: one or more storage devices (110, 203); a controller (106, 230) coupled to one or more storage devices; and a measuring circuit (114, 214, 300) coupled to the controller, the measuring circuit comprising the following: a multitude of successive delay taps (306a - 306n); a plurality of flip-flop registers (302a - 302n), wherein each flip-flop register of the plurality of flip-flop registers has a first input (308) and a second input (310); a first input line (314) that is directly coupled to the first input of each flip-flop register of the plurality of flip-flop registers; a second input line (316) coupled to the second input of each flip-flop register of the plurality of flip-flop registers via successive delay taps of the plurality of successive delay taps, each successive delay tap having a constant delay; and a measurement signal (318) configured to measure a clock duty cycle to enable the measuring circuit; wherein the measuring circuit further comprises a variable delay circuit (322), wherein the second input line is coupled to the successive delay taps via the variable delay circuit; and where the same clock signal (312) is input into both the first input line and the second input line. [2] Storage device according to claim 1, wherein the measuring circuit (114, 214, 300) is configured to measure a clock cycle of the storage device. [3] Storage device according to claim 2, wherein the measuring circuit (114, 214, 300) is configured to set a clock frequency of the storage device. [4] Storage device according to claim 1, wherein the variable delay circuit (322) is coupled to the second input line. [5] Storage device according to claim 1, wherein the variable delay circuit (322) comprises a plurality of delay taps (356a - 356n). [6] Storage device according to claim 5, wherein the variable delay circuit (322) is configured to increase a delay for a signal input into the second input line. [7] Method for operating a storage device (102, 202), comprising: Inputting a first signal into a plurality of flip-flop registers (302a - 302n) of a measurement circuit (114, 214, 300), wherein the first signal is directly inputted into a first input (308) of each of the flip-flop registers of the plurality of flip-flop registers; Simultaneous input of a second signal into a plurality of delay taps (306a - 306n), wherein one or more delay taps are coupled to each of the flip-flop registers of the plurality of flip-flop registers, and wherein the second signal passes through each of the one or more delay taps to a second input (310) of each flip-flop register of the plurality of flip-flop registers; Reading the multitude of flip-flop registers to measure a clock duty cycle (404); and Calibrating the duty cycle in response to the measurement during operation of the storage device; furthermore, including the input of a variable delay to the second signal; and where the first signal and the second signal are a clock signal. [8] Method according to claim 7, further comprising resetting the plurality of flip-flop registers (302a - 302n) prior to inputting the first signal. [9] Method according to claim 7, wherein the plurality of flip-flop registers (302a - 302n) is read using a measurement signal. [10] Method according to claim 7, further comprising switching the storage device into an active state (402) before the first signal is entered. [11] Method according to claim 7, wherein the calibration of the duty cycle comprises setting a clock frequency of the storage device. [12] Method for operating a storage device (102, 202), comprising: Switching the storage device to an active state (402); Measuring a clock duty cycle of the storage device using a measuring circuit (114, 214, 300) consisting of a plurality of flip-flop registers (302a-302n) coupled to a chain of delay taps (306a - 306n); Determining a value that the clock cycle has changed; Determining a configuration value to calibrate the clock duty cycle; Calibrating the duty cycle; and Measuring the duty cycle using the measuring circuit; wherein the measuring circuit further comprises the following: a first clock signal that is directly coupled to a first input (308) of each flip-flop register of the plurality of flip-flop registers (302a - 302n); the chain of delay taps (306a - 306n) comprising a plurality of delay taps, wherein one or more delay taps from the chain of delay taps are coupled to each flip-flop register of the plurality of flip-flop registers; a second clock signal coupled to a second input of each flip-flop register of the plurality of flip-flop registers via the chain of delay taps, wherein the first clock signal and the second clock signal are the same clock signal (312); a measurement signal; and a variable delay circuit (322) coupled to the beginning of the chain of delay taps. [13] Method according to claim 12, further comprising continuously monitoring the duty cycle while the storage device is in the active state. [14] Method according to claim 12, wherein calibrating the duty cycle comprises setting a clock frequency of the storage device.

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