Display device with different types of thin-film transistors and methods for their manufacture

Abstract

Display device, which includes the following: a substrate (110); a pixel control circuit (PDC) on the substrate (PDC); and a display unit (710) connected to the pixel control circuit (PDC), wherein the pixel control circuit (PDC) comprises a first thin-film transistor (TR1) and a second thin-film transistor (TR2), wherein the first thin-film transistor (TR1) comprises: a first gate electrode (G1) on the substrate (110), a first active layer (A1) that is spaced apart from the first gate electrode (G1) and overlaps with at least part of the first gate electrode (G1), a first source electrode (S1) connected to the first active layer (A1); and a first drain electrode (D1) which is spaced apart from the first source electrode (S1) and connected to the first active layer (A1), and the second thin-film transistor (TR2) contains the following: a second active layer (A2) on the substrate (110), and a second gate electrode (G2) that is spaced apart from the second active layer (A2) and partially overlaps with at least part of the second active layer (A2), wherein the first gate electrode (G1) is arranged between the substrate (110) and the first active layer (A1), the second active layer (A2) is arranged between the substrate (110) and the second gate electrode (G2), and the first gate electrode (G1) and the second gate electrode (G2) are arranged on opposite sides with respect to the second active layer (A2), wherein the display device further comprises a first insulating intermediate layer (171) on the first active layer (A1), wherein the first source electrode (S1) and the first drain electrode (D1) are arranged directly on the first insulating intermediate layer (171) and are connected to the first active layer (A1) by contact holes (CH3, CH4).

Description

BACKGROUND Area of ​​Revelation

[0001] The present disclosure relates to a display device, and in particular to a display device comprising various types of thin-film transistors, and a method for its manufacture. Although the present disclosure is suitable for a wide range of applications, it is especially suitable for ensuring a sufficient capacitor area when several thin-film transistors need to be arranged in the display device, and a method for their manufacture. Background description

[0002] A thin-film transistor can be manufactured on a glass substrate or a plastic substrate; consequently, the thin-film transistor has been extensively used as a switching device or driver in a display device such as a liquid crystal display device or an organic light emission device.

[0003] Depending on the material used for the active layer, the thin-film transistor can be predominantly categorized into a thin-film transistor with amorphous silicon and an active layer of amorphous silicon, a thin-film transistor with polycrystalline silicon and an active layer of polycrystalline silicon, and an oxide semiconductor thin-film transistor with an active layer of oxide semiconductor.

[0004] Amorphous silicon can be deposited as an active layer in a short time; consequently, the thin-film transistor with amorphous silicon (i.e., a-Si-TFT) offers the advantages of short fabrication time and low manufacturing costs. However, it has disadvantages such as inferior current drive efficiency due to low mobility and a variable threshold voltage. Therefore, it is difficult to use the thin-film transistor with amorphous silicon for an active-matrix organic light-emitting device (AMOLED).

[0005] The thin-film transistor with polycrystalline silicon (poly-Si-TFT) can be obtained by depositing amorphous silicon and crystallizing the deposited amorphous silicon. Thin-film transistors with polycrystalline silicon offer advantages such as high electron mobility and stability, the ability to achieve a thin profile, high resolution, and high power efficiency. Thin-film transistors with polycrystalline silicon can be either low-temperature polysilicon (LTPS) or polysilicon thin-film transistors. However, the process for manufacturing thin-film transistors with polycrystalline silicon inevitably requires a step for crystallizing the amorphous silicon. Consequently, manufacturing costs can increase due to the increased number of production steps. It also has the disadvantage of requiring high-temperature crystallization.Consequently, it is difficult to apply the polycrystalline silicon thin-film transistor to a large-sized display device.

[0006] The oxide semiconductor thin-film transistor (oxide semiconductor TFT), which exhibits high mobility and a large resistance change depending on the oxygen content, is advantageous because desired properties can be easily achieved. An active oxide layer forms even at a relatively low temperature during the manufacturing process, thus reducing production costs. Due to the properties of oxide, an oxide semiconductor is also transparent, making it suitable for transparent display devices. However, compared to a polycrystalline silicon thin-film transistor, the oxide semiconductor thin-film transistor exhibits relatively low stability and electron mobility.

[0007] Recently, with the advancement of high-quality, high-resolution displays, a high-density thin-film transistor has been integrated into the display device. Consequently, a large number of thin-film transistors are arranged in a limited area, resulting in a large number of contact holes, making it difficult to ensure sufficient capacitor area. Therefore, a method for ensuring sufficient capacitor area in a display device with a large number of thin-film transistors is required. US 2018 / 0062105 A1 describes a display device comprising a substrate, a first transistor, a second transistor, and a first capacitor electrode. The first transistor is positioned above the substrate and includes a first semiconductor layer, a first gate electrode, and a first gate insulator layer.The second transistor is located above the substrate and comprises a second semiconductor layer and a second gate electrode. US 2008 / 0116457 A1 describes a drive device for a unit pixel of an organic light-emitting display, wherein the drive device for a unit pixel comprises a switching thin-film transistor (TFT) and a driver TFT formed on a substrate and interconnected, the switching TFT having a bottom-gate structure and the driver TFT having a top-gate structure. US 2018 / 0138258 A1 describes a display device with two or more transistors in a pixel, and the two or more transistors comprise a first transistor in which a channel semiconductor layer is made of polycrystalline silicon and a second transistor in which a channel semiconductor layer is an oxide semiconductor. SUMMARY

[0008] The present disclosure was made in view of the above problems and its purpose is to provide a display device that makes it easier to ensure a sufficient capacitor area even in the case of the arrangement of several thin-film transistors, and a method for its manufacture.

[0009] The present disclosure also aims to provide a display device that makes it easier to ensure a sufficient capacitor area by reducing the number of contact holes for an electrical connection of a thin-film transistor, even in the case of the arrangement of several thin-film transistors, and a method for its manufacture.

[0010] Furthermore, the present disclosure aims to provide a method for manufacturing a display device that makes it easier to reduce the number of structuring processes, and a display device manufactured by the same method.

[0011] The problems are solved by the features of the independent claims. Preferred embodiments are given in the dependent claims.

[0012] According to one aspect of the present disclosure, the above and other aspects can be accomplished by creating a display device comprising a substrate, a pixel drive circuit on the substrate, and a display unit connected to the pixel drive circuit, wherein the pixel drive circuit comprises a first thin-film transistor and a second thin-film transistor, the first thin-film transistor comprising a first gate electrode on the substrate, a first active layer configured to be spaced apart from the first gate electrode and overlapping with at least a portion of the first gate electrode, a first source electrode connected to the first active layer, and a first drain electrode configured to be spaced apart from the first source electrode and connected to the first active layer.and wherein the second thin-film transistor comprises a second active layer on the substrate and a second gate electrode configured to be spaced apart from the second active layer and overlapping with at least part of the second active layer, the first gate electrode being arranged between the substrate and the first active layer, and the second active layer being arranged between the substrate and the second gate electrode.

[0013] With regard to the second active layer, the first gate electrode and the second gate electrode can be located on opposite layers.

[0014] The second active layer can be located in the same layer as the first source electrode and the first drain electrode. This means that these layers are provided in the same processing step.

[0015] The display device also features a first insulating intermediate layer on the first active layer.

[0016] The first source electrode and the first drain electrode are arranged on the first insulating intermediate layer.

[0017] Preferably, the first source electrode and the first drain electrode can be connected to the first active layer by contact holes.

[0018] The display device may also include an etch stopper on the first active layer.

[0019] The etch stopper can be arranged in the same layer as the first insulating intermediate layer.

[0020] The etch stopper can be made of the same material as that of the first insulating intermediate layer.

[0021] The second active layer can be arranged on top of the first insulating intermediate layer.

[0022] The second active layer can be made of an oxide semiconductor material.

[0023] Preferably, the first source electrode and the first drain electrode can be made of the same oxide semiconductor material as that of the second active layer.

[0024] The first active layer and / or the second active layer can comprise a first oxide semiconductor layer and a second oxide semiconductor layer on top of the first oxide semiconductor layer.

[0025] The display device may also include a data line and a control voltage line.

[0026] Preferably, the data line and the control voltage line can be arranged in the same layer as the first gate electrode.

[0027] The display device may further comprise a second insulating intermediate layer on the first source electrode and the first drain electrode.

[0028] Preferably, the display device can further comprise a planarization layer on the second insulating intermediate layer, wherein the display unit can be arranged on the planarization layer.

[0029] The display unit can include a first electrode on the planarization layer.

[0030] Preferably, the first electrode can be connected to any of the first source electrode and the first drain electrode through a contact hole provided in the second insulation layer and the planarization layer.

[0031] The display device may also include a storage capacitor connected to the first thin-film transistor.

[0032] Preferably, the storage capacitor can comprise a first capacitor electrode, which is designed as a body with the first source electrode, and a second capacitor electrode, which is designed as a body with the first gate electrode.

[0033] The storage capacitor may further comprise a third capacitor electrode configured to be spaced apart from the first capacitor electrode and located on the second insulating intermediate layer.

[0034] The first thin-film transistor can function as a driver transistor to control the display unit. The second thin-film transistor can function as a switching transistor.

[0035] According to another aspect of the present disclosure, a method for manufacturing a display device is provided, comprising the sequential deposition of a first layer of conductive material, a first insulating material layer, and a first layer of active material on a substrate; the formation of a first gate electrode from the first layer of conductive material, a first gate insulating film from the first insulating material, and a first active layer from the first active material by a selective etching process; the formation of a first insulating intermediate layer on the first active layer; the formation of a second layer of active material with multiple patterns on the first insulating intermediate layer; and the formation of a second gate insulating film and a second gate electrode on at least a portion of the second layer of active material.and includes making the second layer of active material conductive in the area that does not overlap with the second gate electrode.

[0036] According to another aspect of the present disclosure, a pixel control circuit for a display device comprises a first gate electrode on a substrate; a first active layer spaced apart from the first gate electrode and overlapping with at least a part of the first gate electrode; a first source electrode connected to the first active layer; a first drain electrode spaced apart from the first source electrode and connected to the first active layer; and a second active layer on the substrate.and a second gate electrode spaced from the second active layer and overlapping with at least part of the second active layer, wherein the first gate electrode, the first active layer and the first source / drain electrodes form a drive transistor of the pixel drive circuit, and the second gate electrode, the second active layer and the second source / drain electrodes form a switching transistor of the pixel drive circuit, and wherein the first gate electrode is arranged between the substrate and the first active layer, the second active layer is arranged between the substrate and the second gate electrode, and the first gate electrode and the second gate electrode are arranged on opposite sides with respect to the second active layer.

[0037] A first source electrode and a first drain electrode can be formed while spaced apart from each other and connected to the first active layer in the process of making it conductive.

[0038] An etch stop can be provided between the first source electrode and the second source electrode.

[0039] The etch stopper can be made of the same material as that of the first insulating intermediate layer.

[0040] A portion of the first source electrode and a portion of the first gate electrode, overlapping each other, can form the storage capacitor.

[0041] The method may further include forming a second insulating intermediate layer on the first source electrode and forming a third capacitor electrode, which overlaps with at least part of the first source electrode, on the second insulating intermediate layer.

[0042] According to one aspect of the present disclosure, the thin-film transistor of the lower gate type can be used together with the thin-film transistor of the upper gate type in the display device, so that it is possible to ensure the capacitor area in the display device sufficiently.

[0043] According to another aspect of the present disclosure, the lower-gate thin-film transistor can be used together with the upper-gate thin-film transistor in the display device, thus making it possible to reduce the number of contact holes used for the electrical connection of the thin-film transistor. Consequently, it is possible to ensure an adequate capacitor area in the display device.

[0044] According to another aspect of the present disclosure, the thin-film transistor of the lower gate type can be used together with the thin-film transistor of the upper gate type in the display device, thus reducing the number of structuring processes, consequently making it possible to simplify a manufacturing process and reduce manufacturing costs.

[0045] In addition to the effects of the present disclosure, as mentioned above, further advantages and features of the present disclosure are clearly understandable to the person skilled in the field from the description of the present disclosure. SHORT DESCRIPTION

[0046] The above and other aspects, features and other advantages of the present disclosure are more clearly understood from the following detailed description in conjunction with the accompanying drawings; they show: Fig. 1 a schematic view representing a display device according to one aspect of the present disclosure; Fig. 2 a top view representing a pixel unit used in the display device of Fig. 1 is included; Fig. 3 a top view showing any pixel of Fig. 1 represents; Fig. 4. A circuit diagram for the pixel of Fig. 3; Fig. 5 a cross-sectional view along II' of Fig. 3; Fig. 6A a top view showing any pixel unit in a display device in accordance with the prior art; Fig. 6B a cross-sectional view showing a storage capacitor, a drive transistor and a switching transistor included in a display device according to the prior art; Fig. 7 a cross-sectional view representing a pixel of a display device according to another aspect of the present disclosure; Fig. 8 a circuit diagram representing a pixel of a display device according to another aspect of the present disclosure; Fig. 9A, Fig. 9B, Fig. 9C, Fig. 9D, Fig. 9E, Fig. 9F, Fig. 9G, Fig. 9H and Fig. 9I Cross-sectional views illustrating a method for manufacturing a display device according to one aspect of the present disclosure; Fig. 10A, Fig. 10B, Fig. 10C and Fig. 10D plan views illustrating a method for manufacturing a display device according to one aspect of the present disclosure; and Fig. 11 a diagram comparing a process for manufacturing a display device according to an aspect of the present disclosure with a process for manufacturing a display device according to the prior art. DETAILED DESCRIPTION

[0047] The advantages and features of the present disclosure and its implementation methods are illustrated by the following aspects, which are described with reference to the accompanying drawings. However, the present disclosure can be embodied in various forms and should not be considered limited to the aspects presented here. Rather, these aspects are provided to ensure that this disclosure is thorough and complete, fully conveying the scope of protection of the present disclosure to the person skilled in the field. Furthermore, the present disclosure is defined solely by the scope of protection of the claims.

[0048] The shapes, sizes, ratios, angles, and numbers disclosed in the drawings to describe aspects of the present disclosure are merely examples, and consequently, the present disclosure is not limited to the details shown. The same reference numerals consistently refer to the same elements. If, in the following description, it is determined that a detailed description of the relevant known function or configuration would unnecessarily obscure the important point of the present disclosure, the detailed description will be omitted.

[0049] In cases where the terms "comprise," "exhibit," and "include," as described in this patent description, are used, another part may also be present if "only" is not used. Terms in a singular form may include plural forms unless otherwise stated.

[0050] When considering an element, the element is interpreted as encompassing an error area, even though there is no explicit description of it.

[0051] When describing a positional relationship, for example, when the positional sequence is described as "on," "above," "below," and "next to," the case of no contact between them can be included unless "straight" or "directly" is used. When it is mentioned that a first element is positioned "on" a second element, it does not mean that the first element is essentially positioned above the second element in the figure. The upper and lower parts of an object in question can change depending on the object's orientation. Consequently, the case in which a first element is positioned "on" a second element includes the case in which the first element is positioned "below" the second element, as well as the case in which the first element is positioned "above" the second element in the figure or in an actual configuration.

[0052] When describing a temporal relationship, for example, when the temporal sequence is described as "after", "following", "next" and "before", a case that is not continuous may be included if "straight ahead" or "directly" is not used.

[0053] It is self-evident that, although the terms "first," "second," etc., may be used here to describe different elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. A first element, for example, could be called a second element, and likewise a second element could be called a first element, without departing from the scope of protection of the present disclosure.

[0054] The terms “first horizontal axis direction”, “second horizontal axis direction”, and “vertical axis direction” should not be interpreted solely on the basis of a geometric relationship in which the respective directions are perpendicular to each other, and may be meant as directions with broader directional dependencies within the range in which the components of the present disclosure can operate functionally.

[0055] Naturally, the term "at least one" encompasses all combinations relating to any element. For example, "at least one from a first element, a second element, and a third element" can include all combinations of two or more elements selected from the first, second, and third elements, as well as each element of the first, second, and third elements.

[0056] Features of different aspects of this disclosure may be partially or completely coupled or combined and may be operated together in various ways and technically, as a person skilled in the art can reasonably understand. The aspects of this disclosure may be carried out independently of one another or together in a mutually dependent relationship.

[0057] In the drawings, the same or similar elements are designated with the same reference symbols, even if they are shown in different drawings.

[0058] In the aspects of this disclosure, a source electrode and a drain electrode are distinguished from one another for the convenience of description. However, the source electrode and the drain electrode are used interchangeably. Consequently, the source electrode can be the drain electrode, and the drain electrode can be the source electrode. The source electrode in one aspect of this disclosure can also be the drain electrode in another aspect of this disclosure, and the drain electrode in one aspect of this disclosure can be the source electrode in another aspect of this disclosure.

[0059] In one or more aspects of this disclosure, for the sake of clarity, a source region is distinguished from a source electrode, and a drain region is distinguished from a drain electrode. However, aspects of this disclosure are not limited to this structure. For example, a source region may be a source electrode, and a drain region may be a drain electrode. A source region may also be a drain electrode, and a drain region may be a source electrode.

[0060] Below, a display device 100 is described in accordance with one aspect of the present disclosure with reference to Fig. 1, Fig. 2, Fig. 3, Fig. 4 to Fig. 5 described in detail.

[0061] The display device 100 according to one aspect of the present disclosure comprises a substrate 110, a pixel drive circuit (PDC) on the substrate 110, and a display unit 710 connected to the pixel drive circuit (PDC). The pixel drive circuit (PDC) comprises thin-film transistors (TR1, TR2).

[0062] Fig. Figure 1 is a schematic view representing the display device 100 according to one aspect of the present disclosure.

[0063] As in Fig. As shown in Figure 1, the display device 100 according to one aspect of the present disclosure comprises a pixel (P) on the substrate 110, a gate driver 220, a data driver 230 and a control unit 240.

[0064] The substrate 110 contains gate lines (GL) and data lines (DL), and the pixel (P) is located at the intersection of the gate line (GL) and the data line (DL). The pixel (P) comprises the display unit 710 and the pixel control circuit (PDC) for controlling the display unit 710. An image is displayed by controlling the pixel (P). Several pixels (P) can form a pixel unit (PG).

[0065] The control unit 240 controls the gate driver 220 and the data driver 230.

[0066] The control unit 240 outputs a gate control signal (GCS) to control the gate driver 220 and a data control signal (DCS) to control the data driver 230 using a vertically / horizontally synchronized signal and clock signal supplied by an external system (not shown). The control unit 240 also samples input video data supplied by the external system, then re-aligns the sampled video data and supplies the re-aligned digital video data (RGB) to the data driver 230.

[0067] The gate control signal (GCS) comprises a gate start pulse (GSP), a gate shift clock (GSC), an output enable signal (GOE), a start signal (Vst), and a gate clock (GCLK). Control signals for controlling a shift register can also be included in the gate control signal (GCS).

[0068] The data control signal (DSC) includes a source start pulse (SSP), a source shift clock signal (SSC), a source output enable signal (SOE), and a polarity control signal (POL).

[0069] The data driver 230 supplies a data voltage to the data lines (DL) on the substrate 110. Specifically, the data driver 230 converts the video data (RGB) supplied by the control unit 240 into an analog data voltage and supplies the analog data voltage to the data lines (DL).

[0070] The gate driver 220 sequentially supplies a gate pulse (GP) to the gate lines (GL) for one frame period. Here, "one frame" indicates the period in which an image is output through the display. The gate driver 220 also supplies a gate-off signal to the gate line (GL) to switch off the switching device for the remaining frame period during which the gate pulse (GP) is not supplied. Hereinafter, the gate pulse (GP) and the gate-off signal (Goff) are collectively referred to as the sampling signals (SS).

[0071] According to one aspect of the present disclosure, the gate driver 220 can be provided on the substrate 110. A structure for directly providing the gate driver 220 on the substrate 110 can be referred to as a gate-in-field (GIP) structure.

[0072] Fig. Figure 2 is a top view showing the pixel unit PG, which is 100 in the display unit. Fig. 1 is included.

[0073] With reference to Fig. 1 and Fig. 2. A pixel unit (PG) can contain three pixels (P). Each pixel (P) within a pixel unit (PG) can emit red, green, or blue light. The pixel unit (PG) can express different colors by using pixels (P) to emit red, green, and blue light.

[0074] Fig. 3 is a top view showing any pixel (P) of Fig. 1 represents, Fig. 4 is a circuit diagram for pixel (P) of Fig. 3 and Fig. 5 is a cross-sectional view along II' of Fig. 3.

[0075] The circuit diagram of Fig. 4 corresponds to an equivalent circuit diagram for a pixel (P) in an organic light emission display device with an organic light-emitting diode (OLED) as the display unit 710.

[0076] The pixel (P) of display unit 100, which is in Fig. Figure 4 shows an organic light-emitting diode (OLED), corresponding to a display unit 710, and a pixel control circuit (PDC) for controlling the display unit 710. The display unit 710 is connected to the pixel control circuit (PDC).

[0077] On substrate 110 are signal lines (DL, EL, GL, PL, SCL, RL) for supplying a control signal to the pixel control circuit (PDC). The pixel control circuit (PDC) comprises thin-film transistors (TR1, TR2, TR3, TR4).

[0078] The pixel control circuit (PDC) of Fig. 4 further includes the first thin-film transistor (TR1), which corresponds to a drive transistor, the second thin-film transistor (TR2), which corresponds to a switching transistor, the third thin-film transistor (TR3), which corresponds to a reference transistor, and the fourth thin-film transistor (TR4), which corresponds to an emission control transistor.

[0079] Specifically, the first thin-film transistor (TR1) corresponds to the drive transistor, which is configured to control a level of the current output to the display unit 710 according to a data voltage (Vdata) transmitted by the second thin-film transistor (TR2); the second thin-film transistor (TR2) corresponds to the switching transistor, which is connected to a gate line (GL) and a data line (DL); the third thin-film transistor (TR3) corresponds to the reference transistor, which is configured to detect features of the first thin-film transistor (TR1); and the fourth thin-film transistor (TR4) corresponds to the emission control transistor, which is configured to control the emission time by controlling the first thin-film transistor (TR1).

[0080] The data voltage (Vdata) is supplied to the data line (DL), a sampling signal (SS) is supplied to the gate line (GL), a drive voltage (VDD) for controlling the pixel is supplied to a drive voltage line (PL), a reference voltage (Vref) is supplied to a reference line (RL), an emission control signal (EM) is supplied to an emission control line (EL), and a detection control signal (SCS) is supplied to a detection control line (SCL).

[0081] With reference to Fig. 4 is when the gate line of the (n)th pixel (P) is designated as “GLn”, the gate line of the adjacent (n-1)th pixel (P) is “GLn-1” and the gate line of the (n-1)th pixel (P) serves as the acquisition control line (SCL) of the (n)th pixel (P).

[0082] A storage capacitor (Cst) is arranged between the display unit 710 and a gate electrode (G1) of the first thin-film transistor (TR1). Specifically, the storage capacitor (Cst) is formed between a first node (n1), which is connected to the display unit 710, and a second node (n2), which is connected to the gate electrode (G1) of the first thin-film transistor (TR1).

[0083] The second thin-film transistor (TR2) is switched on by the sampling signal (SS) supplied to the gate line (GL), and the second thin-film transistor (TR2) transmits the data voltage (Vdata) supplied to the data line (DL) to the gate electrode (G1) of the first thin-film transistor (TR1).

[0084] When the second thin-film transistor (TR2) is switched on, the data voltage (Vdata) supplied via the data line (DL) is applied to the gate electrode (G1) of the first thin-film transistor (TR1). The storage capacitor (Cst) is then charged with the data voltage (Vdata).

[0085] When the first thin-film transistor (TR1) is switched on, a current is supplied to a display unit 710 through the first thin-film transistor (TR1) by the drive voltage (Vdd) to control the pixel, consequently light is emitted from the display unit 710.

[0086] The third thin-film transistor (TR3) is connected to the reference line (RL), is turned on or off by the sensing control signal (SCS), and is configured to sensing the characteristics of the second thin-film transistor (TR2), which corresponds to the drive transistor, for one sensing period.

[0087] The fourth thin-film transistor (TR4) transmits the drive voltage (Vdd) to the first thin-film transistor (TR1) or interrupts the drive voltage (Vdd) according to the emission control signal (EM). When the fourth thin-film transistor (TR4) is switched on, current is supplied to the first thin-film transistor (TR1), consequently light is emitted from the display unit 710.

[0088] The amount of current supplied to the organic light-emitting diode (OLED) according to the display unit 710 by the first thin-film transistor TR1 is controlled according to the data voltage (Vdata), consequently it is possible to control a gray level of the light emitted by the display unit 710.

[0089] With reference to Fig. 5 is the pixel control circuit (PDC) located on substrate 110.

[0090] Substrate 110 can be made of glass or plastic. Substrate 110 can be made of flexible plastic, for example polyimide (PI).

[0091] The pixel control circuit (PDC) includes the first thin-film transistor (TR1) and the second thin-film transistor (TR2).

[0092] The first thin-film transistor (TR1) comprises a first gate electrode (G1) on the substrate 110, a first active layer (A1) provided such that it is spaced apart from the first gate electrode (G1) and overlaps with at least part of the first gate electrode (G1), a first source electrode (S1) connected to the first active layer (A1), and a first drain electrode (D1) provided such that it is spaced apart from the first source electrode (S1) and connected to the first active layer (A1).

[0093] The second thin-film transistor (TR2) comprises a second active layer (A2) on the substrate 110 and a second gate electrode (G2) which is provided such that it is spaced apart from the second active layer (A2) and partially overlaps with at least part of the second active layer (A2).

[0094] With reference to Fig. 5 are the first gate electrode (G1), the data line (DL) and the drive voltage line (PL) arranged on the substrate 110.

[0095] The first gate electrode (G1), the data line (DL) and the drive voltage line (PL) can be made of the same material and can be manufactured by the same process.

[0096] The first gate electrode (G1), the data line (DL), and the drive voltage line (PL) can comprise at least one of the following metals: aluminum-based (e.g., aluminum or an aluminum alloy), silver-based (e.g., silver (Ag) or a silver alloy), copper-based (e.g., copper (Cu) or a copper alloy), molybdenum-based (e.g., molybdenum or a molybdenum alloy), chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The first gate electrode (G1), the data line (DL), and the drive voltage line (PL) can have a multilayer structure with at least two layers exhibiting different physical properties.

[0097] Part of the first gate electrode (G1) becomes a second capacitor electrode (CE2).

[0098] A first gate insulating film 121 is arranged on the first gate electrode (G1). The first gate insulating film 121 can comprise at least one silicon oxide and one silicon nitride and can also include a metal oxide or a metal nitride. The first gate insulating film 121 can have a single-layer or a multi-layer structure.

[0099] An insulating film, the same as the first gate insulating film 121, is located on the data line (DL) and the drive voltage line (PL). According to one aspect of the present disclosure, the insulating film arranged on the data line (DL) and the drive voltage line (PL) is also referred to as the first gate insulating film 121.

[0100] The first active layer (A1) is arranged on the first gate insulation film 121. The first active layer (A1) partially overlaps with a certain area of ​​the first gate electrode (G1).

[0101] The first active layer (A1) is formed from a first active material. The first active material can be an oxide semiconductor material. According to one aspect of the present disclosure, the first active layer (A1) is an oxide semiconductor layer.

[0102] The first active layer (A1) can, for example, comprise at least one oxide semiconductor based on IZO(InZnO), an oxide semiconductor based on IGO(InGaO), an oxide semiconductor based on ITO(InSnO), an oxide semiconductor based on IGZO(InGaZnO), an oxide semiconductor based on IGZTO(InGaZnSnO), an oxide semiconductor based on GZTO(GaZnSnO), an oxide semiconductor based on GZO(GaZnO), an oxide semiconductor based on GO(GaO), and an oxide semiconductor based on ITZO(InSnZnO). However, one aspect of the present disclosure is not limited to the above. The first active layer (A1) can be formed from other oxide semiconductor materials that are generally known to those skilled in the art.

[0103] A first insulating layer 171 is arranged on the first active layer (A1). The first insulating layer 171 can be made of an organic or an inorganic insulating material. The first insulating layer 171 serves as an etch stop (ES) for the first active layer (A1) of the first thin-film transistor (TR1). Consequently, the first thin-film transistor (TR1) can be referred to as the BCE-structured thin-film transistor with the etch stop (ES).

[0104] Specifically, according to one aspect of this disclosure, the first thin-film transistor (TR1) includes the etch stopper (ES). The etch stopper (ES) is located in the same layer as the first insulating layer 171 on the first active layer (A1) and can be made of the same material as that of the first insulating layer 171. The etch stopper (ES) protects a channel region of the first active layer (A1).

[0105] A second active layer (A2) is arranged on the first insulating intermediate layer 171.

[0106] The second active layer (A2) is formed from a second active material. The second active material can be an oxide semiconductor material. According to one aspect of the present disclosure, the second active layer (A2) is an oxide semiconductor layer.

[0107] The second active layer (A2) can be made of the same oxide semiconductor material as that of the first active layer (A1) or can be made of a different oxide semiconductor material than that of the first active layer (A1).

[0108] The second active layer (A2) can, for example, comprise at least one oxide semiconductor based on IZO(InZnO), an oxide semiconductor based on IGO(InGaO), an oxide semiconductor based on ITO(InSnO), an oxide semiconductor based on IGZO(InGaZnO), an oxide semiconductor based on IGZTO(InGaZnSnO), an oxide semiconductor based on GZTO(GaZnSnO), an oxide semiconductor based on GZO(GaZnO), an oxide semiconductor based on GO(GaO), and an oxide semiconductor based on ITZO(InSnZnO). However, one aspect of the present disclosure is not limited to the above. The second active layer (A2) can be formed from other oxide semiconductor materials that are generally known to those skilled in the art.

[0109] According to one aspect of the present disclosure, a first source electrode (S1), a first drain electrode (D1), a second source electrode (S2) and a second drain electrode (D2) are arranged on the first insulating intermediate layer 171.

[0110] The first source electrode (S1), the first drain electrode (D1), the second source electrode (S2) and the second drain electrode (D2) can be formed from the second active material.

[0111] A second gate insulation film 122 is arranged on the second active layer (A2), and a second gate electrode (G2) is arranged on the second gate insulation film 122. Consequently, the second thin-film transistor (TR2) is completed with the second gate electrode (G2), the second active layer (A2), the second source electrode (S2), and the second drain electrode (D2).

[0112] According to one aspect of the present disclosure, after the second layer of active material is formed on the first insulating intermediate layer 171, a portion of the second layer of active material that does not overlap with the second gate electrode (G2) is selectively made conductive to form the first source electrode (S1), the first drain electrode (D1), the second source electrode (S2), and the second drain electrode (D2). Other areas of the second layer of active material that overlap with the second gate electrode (G2) become the second active layer (A2) without being made conductive. In the present disclosure, "making conductive" means that a portion of an active material is made a conductor.

[0113] The second active material for forming the second active layer (A2) is the oxide semiconductor material; consequently, the second active material can be made conductive by plasma treatment or hydrogen treatment.

[0114] The conductive section of the second layer of active material can be called a conductive section. Multiple conductive sections can be formed by making the second layer of active material conductive.

[0115] Among the conductive sections, each section connected to the first active layer (A1) becomes the first source electrode (S1) and the first drain electrode (D1). The first drain electrode (D1) is connected to the first active layer (A1) through a third contact hole (CH3) provided in the first insulating intermediate layer 171. The first source electrode (S1) is connected to the first active layer (A1) through a fourth contact hole (CH4) provided in the first insulating intermediate layer 171. With reference to Fig. The etch stop (ES) is also located between the third contact hole (CH3) and the fourth contact hole (CH4). Consequently, the first thin-film transistor (TR1) is completed with the first gate electrode (G1), the first active layer (A1), the first source electrode (S1), and the first drain electrode (D1).

[0116] According to one aspect of the present disclosure, contact holes do not need to be completely filled with the second active material. For example, each of the first source electrode (S1) and the first drain electrode (D1) may have a recess in the contact hole (CH4, CH3). Subsequently, the first source electrode (S1) and the first drain electrode (D1) are made conductive by plasma treatment or hydrogen treatment.

[0117] According to one aspect of the present disclosure, part of the first source electrode (S1) becomes a first capacitor electrode (CE1). The first capacitor electrode (CE1) together with a second capacitor electrode (CE2) forms a first capacitor (C1).

[0118] Among the several conductive sections, the conductive section connected to the second active layer (A2) also becomes the second source electrode (S2) and the second drain electrode (D2). According to one aspect of the present disclosure, the second source electrode (S1) and the second drain electrode (D2) are formed as a single body with the second active layer (A2).

[0119] The second source electrode (S2) is connected to the data line (DL) via a first contact hole (CH1) provided in the first gate insulating film 121 and the first insulating intermediate layer 171. The second drain electrode (D2) is also connected to the first gate electrode (G1) via a second contact hole (CH2) provided in the first gate insulating film 121 and the first insulating intermediate layer 171. As described above, a portion of the first gate electrode (G1) becomes the second capacitor electrode (CE2). Corresponding to the connection of the second drain electrode (D2) to the first gate electrode (G1), the second drain electrode (D2) is also connected to the second capacitor electrode (CE2).

[0120] According to another aspect of the present disclosure, each of the conducting sections configured to be separated from one another and connected to the second active layer (A2) can be referred to as the source region and drain region, respectively. However, the source region and the source electrode are not distinguished from one another, and the source region can be referred to as the source electrode. Similarly, the drain region and the drain electrode are not distinguished from one another, and the drain region can be referred to as the drain electrode.

[0121] A second insulating layer 172 is arranged on the first thin-film transistor (TR1) and the second thin-film transistor (TR2). The second insulating layer 172 can be made of an organic insulating material or an inorganic insulating material.

[0122] The gate line (GL), the emission control line (EL), a drive voltage connection line (PLB) and a third capacitor electrode (CE3) are arranged on the second insulating intermediate layer 172.

[0123] With reference to Fig. 3 One end of the control voltage connection line (PLB) is connected to the control voltage line (PL) through contact holes (CH11, CH12) and the other end of the control voltage connection line (PLB) is connected to the fourth thin-film transistor (TR4) through a contact hole (CH13), consequently the control voltage is supplied to the fourth thin-film transistor (TR4), which corresponds to the emission control transistor of each pixel (P).

[0124] The third capacitor electrode (CE3) is connected to the second drain electrode (D2) via a fifth contact hole (CH5) provided in the second insulating layer 172. Consequently, the third capacitor electrode (CE3) can be connected to the second capacitor electrode (CE2) via the second drain electrode (D2). Therefore, the third capacitor electrode (CE3) is supplied with the same voltage as the second capacitor electrode (CE2). The third capacitor electrode (CE3) overlaps with the first capacitor electrode (CE1) to form the second capacitor (C2). The first capacitor (C1) and the second capacitor (C2) together form the storage capacitor (Cst).

[0125] A planarization layer 173 is arranged on the gate line (GL), the emission control line (EL), the drive voltage link line (PLB), and the third capacitor electrode (CE3). The planarization layer 173 is configured to planarize the top surface of the first thin-film transistor (TR1) and the top surface of the second thin-film transistor (TR2), and also to protect the first thin-film transistor (TR1) and the second thin-film transistor (TR2).

[0126] A first electrode 711 of the display unit 710 is arranged on the planarization layer 173. The first electrode 711 of the display unit 710 can be connected to any of the first source electrode (S1) and the first drain electrode (D1) contained in the first thin-film transistor (TR1) via a sixth contact hole (CH6) provided in the planarization layer 173 and the second insulating intermediate layer 172. Fig. In step 5, the first electrode 711 is connected to the first source electrode (S1) of the first thin-film transistor (TR1). However, it is not limited to this configuration. The first electrode 711 can also be connected to the first drain electrode (D1) of the first thin-film transistor (TR1).

[0127] A bank layer 750 is arranged at the edge of the first electrode 711. The bank layer 750 defines an emission area of ​​the display unit 710.

[0128] An organic emission layer 712 is arranged on the first electrode 711 and a second electrode 713 is arranged on the organic emission layer 712; consequently, the display unit 710 is completed. The in Fig. The display unit 710 shown in Figure 5 corresponds to the organic light-emitting diode (OLED). Consequently, the display device 100 corresponds to the organic light emission display device according to one aspect of the present disclosure.

[0129] According to one aspect of the present disclosure, the first thin-film transistor (TR1) is a bottom-gate thin-film transistor in which the first gate electrode (G1) is located below the first active layer (A1). Meanwhile, the second thin-film transistor (TR2) is a top-gate thin-film transistor in which the second gate electrode (G2) is located above the second active layer (A2).

[0130] With reference to Fig. In the first thin-film transistor (TR1), the first gate electrode (G1) is located between the substrate 110 and the first active layer (A1). In the second thin-film transistor (TR2), the second active layer (A2) is located between the substrate 110 and the second gate electrode (G2).

[0131] With respect to the second active layer (A2), the first gate electrode (G1) and the second gate electrode (G2) are also arranged on opposite layers.

[0132] Specifically, the first gate electrode (G1) is positioned closer to substrate 110 compared to the second active layer (A2). Therefore, as shown in the drawings, the first gate electrode (G1) is located on the lower layer compared to the second active layer (A2).

[0133] Meanwhile, the second gate electrode (G2) is positioned further away from substrate 110 compared to the second active layer (A2). Therefore, as shown in the drawings, the second gate electrode (G2) is located on the upper layer compared to the second active layer (A2).

[0134] The second active layer (A2) is also arranged in the same layer as the first source electrode (S1) and the first drain electrode (D1). According to one aspect of the present disclosure, the second active layer (A2) is formed from the oxide semiconductor material, and the first source electrode (S1) and the first drain electrode (D1) can be formed from the same oxide semiconductor material as that of the second active layer (A2). However, the second active layer (A2) is the non-conductive layer, and the first source electrode (S1) and the first drain electrode (D1) are the conductive layers.

[0135] The display device 100 according to one aspect of the present disclosure also includes the storage capacitor (Cst) which is connected to the first thin-film transistor (TR1). The storage capacitor (Cst) comprises the first capacitor (C1) and the second capacitor (C2).

[0136] Specifically, the storage capacitor (Cst) comprises the first capacitor electrode (CE1), which is designed as a body with the first source electrode (S1), and the second capacitor electrode (CE2), which is designed as a body with the first gate electrode (G1). The first capacitor electrode (CE1) and the second capacitor electrode (CE2) together form the first capacitor (C1).

[0137] The storage capacitor (Cst) further comprises the third capacitor electrode (CE3), which is arranged at a distance from and on top of the first capacitor electrode (CE1). Here, the first capacitor electrode (CE1) is arranged between the second capacitor electrode (CE2) and the third capacitor electrode (CE3). The first capacitor electrode (CE1) and the third capacitor electrode (CE3) form the second capacitor (C2).

[0138] According to one aspect of the present disclosure, the storage capacitor (Cst) comprises the first capacitor (C1) and the second capacitor (C2), which are arranged in the same area. The first capacitor (C1) and the second capacitor (C2) are formed in different layers or stacked on top of each other to form the storage capacitor (Cst). Consequently, it is possible to increase the capacitance of the storage capacitor (Cst). In the high-resolution display device with the high-density integrated thin-film transistor, it is therefore possible to increase the capacitance of the storage capacitor (Cst) without increasing the area of ​​the storage capacitor (Cst).

[0139] In the case of the top-gate thin-film transistor with the oxide semiconductor layer, there is generally no need for the process of making the oxide semiconductor layer conductive, nor is there a need for the contact area of ​​the source electrode and the drain electrode; consequently, it has limitations in the size and thickness of the gate insulating film.

[0140] In one aspect of the present disclosure, the first thin-film transistor (TR1) for driving the display unit 710 is of the bottom-gate type. The first active layer (A1) of the first thin-film transistor (TR1) is also formed from the oxide semiconductor, and there is no need for the process of making the oxide semiconductor layer conductive. Consequently, the size and thickness of the first gate insulating film 121 contained in the first thin-film transistor (TR1) can be increased if necessary.

[0141] If the thickness of the first gate insulation film 121 is increased, the s-factor (room for error below the threshold: s-factor) of the first thin-film transistor (TR1) can be increased.

[0142] The s-factor can be obtained by taking the inverse of the slope in a graph of a gate voltage to a drain current for a portion of the threshold voltage (Vth) of the thin-film transistor. As the s-factor increases, the rate of change of a drain-source current (IDS) to the gate voltage decreases for that portion of the threshold voltage (Vth), thus facilitating control of the drain-source current (IDS) level by controlling the gate voltage.

[0143] A pixel gray level can be controlled by controlling the drain-source current (IDS). If controlling the level of the drain-source current (IDS) makes it easier to control the pixel gray level.

[0144] According to one aspect of the present disclosure, it facilitates the increase of the thickness of the first gate insulation film 121 of the bottom-gate thin-film transistor (TR1), consequently facilitating the increase of the s-factor of the first thin-film transistor (TR1). If the first thin-film transistor (TR1) is used as a thin-film driver transistor (TR1) according to one aspect of the present disclosure, it consequently facilitates the expression of the pixel grayscale.

[0145] According to one aspect of the present disclosure, the first gate electrode (G1), the first gate insulating film 121 and the first active layer (A1) can be formed together by the same etching process for the same manufacturing step; consequently, it is possible to simplify a manufacturing process and reduce manufacturing costs.

[0146] According to one aspect of the present disclosure, the first thin-film transistor (TR1) of the lower gate type is used together with the second thin-film transistor (TR2) of the upper gate type, making it possible to reduce the number of contact holes used for the electrical connection between the thin-film transistor and the leads. Reducing the number of contact holes decreases the area occupied by the contact holes, thus making it possible to relatively increase the area available for the storage capacitor (Cst). Consequently, according to one aspect of the present disclosure, it is possible to ensure an adequate capacitor area in the display device 100.

[0147] Fig. 6A is a top view showing any pixel unit in a display device according to the state of the art. Fig. Figure 6B is a cross-sectional view showing a storage capacitor, a drive transistor, and a switching transistor contained in a prior art display device. Fig. 6A comprises one pixel unit of three pixels.

[0148] With reference to Fig. 6A and Fig. 6B are both a thin-film switching transistor and a thin-film driver transistor, constructed from thin-film transistors of the upper grade type. With reference to Fig. 6A is therefore known to have many contact holes provided to electrically connect thin-film transistors to conductors.

[0149] In the case of the display device 100 according to one aspect of the present disclosure, the number of contact holes provided in a pixel unit (PG) is relatively smaller than the number of contact holes provided in a pixel unit of the display device according to the prior art. The pixel unit of Fig. For example, 6A comprises 39 contact holes. Meanwhile, the pixel unit (PG) of the display device 100 comprises 26 contact holes according to one aspect of the present disclosure. According to the present disclosure, the number of contact holes in the pixel drive circuit is reduced; consequently, the area of ​​the storage capacitor (Cst) is increased by the reduced number of contact holes.

[0150] Fig. Figure 7 is a cross-sectional view representing a pixel (P) of a display device 200 according to another aspect of the present disclosure. A repeated description for the same parts is omitted below to avoid unnecessary repetition.

[0151] According to another aspect of the present disclosure, a first active layer (A1) and / or a second active layer (A2) comprise a first oxide semiconductor layer and a second oxide semiconductor layer on top of the first oxide semiconductor layer.

[0152] With reference to Fig. 7. The first active layer (A1) comprises a first oxide semiconductor layer (A1a) and a second oxide semiconductor layer (A1b) on top of the first oxide semiconductor layer (A1a). The first oxide semiconductor layer (A1a) serves as a support layer for the second oxide semiconductor layer (A1b), and the second oxide semiconductor layer (A1b) serves as a channel layer. A channel of the first active layer (A1) is generally formed in the second oxide semiconductor layer (A1b).

[0153] The first oxide semiconductor layer (A1a), which serves as a support layer, exhibits high film stability and good mechanical properties. For high film stability, the first oxide semiconductor layer (A1a) can comprise gallium (Ga), where gallium (Ga) forms a stabilized bond with oxygen, and gallium oxide exhibits good film stability.

[0154] The first oxide semiconductor layer (A1a) can, for example, comprise at least one IGZO(InGaZnO)-based oxide semiconductor material, one IGO(InGaO)-based oxide semiconductor material, one IGTO(InGaSnO)-based oxide semiconductor material, one IGZTO(InGaZnSnO)-based oxide semiconductor material, one GZTO(GaZnSnO)-based oxide semiconductor material, one GZO(GaZnO)-based oxide semiconductor material, and one GO(GaO)-based oxide semiconductor material.

[0155] The second oxide semiconductor layer (A1b) can, for example, comprise at least one oxide semiconductor material based on IZO(InZnO), an oxide semiconductor material based on IGO(InGaO), an oxide semiconductor material based on ITO(InSnO), an oxide semiconductor material based on IGZO(InGaZnO), an oxide semiconductor material based on IGZTO(InGaZnSnO), an oxide semiconductor material based on GZTO(GaZnSnO), and an oxide semiconductor material based on ITZO(InSnZnO). However, one aspect of the present disclosure is not limited to the above. The second oxide semiconductor layer (A1b) can be formed from other oxide semiconductor materials that are generally known to those skilled in the art.

[0156] The second active layer (A2) can also comprise a first oxide semiconductor layer (A2a) and a second oxide semiconductor layer (A2b) on top of the first oxide semiconductor layer (A2a). The first oxide semiconductor layer (A2a) serves as a support layer for the second oxide semiconductor layer (A2b), and the second oxide semiconductor layer (A2b) serves as a channel layer. A channel of the second active layer (A2) is generally formed within the second oxide semiconductor layer (A2b).

[0157] The first oxide semiconductor layer (A2a), which serves as a support layer, exhibits high film stability and good mechanical properties. For high film stability, the first oxide semiconductor layer (A2a) can comprise gallium (Ga), where gallium (Ga) forms a stabilized bond with oxygen, and gallium oxide exhibits good film stability.

[0158] The first oxide semiconductor layer (A2a) can, for example, comprise at least one IGZO(InGaZnO)-based oxide semiconductor material, one IGO(InGaO)-based oxide semiconductor material, one IGTO(InGaSnO)-based oxide semiconductor material, one IGZTO(InGa-ZnSnO)-based oxide semiconductor material, one GZTO(GaZnSnO)-based oxide semiconductor material, one GZO(GaZnO)-based oxide semiconductor material, and one GO(GaO)-based oxide semiconductor material.

[0159] The second oxide semiconductor layer (A2b) can, for example, comprise at least one oxide semiconductor material based on IZO(InZnO), an oxide semiconductor material based on IGO(InGaO), an oxide semiconductor material based on ITO(InSnO), an oxide semiconductor material based on IGZO(InGaZnO), an oxide semiconductor material based on IGZTO(InGaZnSnO), an oxide semiconductor material based on GZTO(GaZnSnO), and an oxide semiconductor material based on ITZO(InSnZnO). However, one aspect of the present disclosure is not limited to the above. The second oxide semiconductor layer (A2b) can be formed from other oxide semiconductor materials that are generally known to those skilled in the art.

[0160] Fig. Figure 8 is a circuit diagram representing a pixel of a display device 300 according to another aspect of the present disclosure. Fig. Figure 8 is an equivalent circuit diagram for a pixel (P) of an organic light emission display device.

[0161] The pixel (P) of the display unit 300, which is in Fig. Figure 8 shows an organic light-emitting diode (OLED), corresponding to a display unit 710, and a pixel control circuit (PDC) for controlling the display unit 710. The display unit 710 is connected to the pixel control circuit (PDC).

[0162] The pixel (P) contains signal lines (DL, GL, PL, RL, SCL) for supplying a signal to the pixel control circuit (PDC).

[0163] A data voltage (Vdata) is supplied to a data line (DL), a sampling signal (SS) is supplied to a gate line (GL), a drive voltage (VDD) for driving the pixel is supplied to a drive voltage line (PL), a reference voltage (Vref) is supplied to a reference line (RL), and a capture control signal (SCS) is supplied to a capture control line (SCL).

[0164] With reference to Fig. 8 is when the gate line of the (n)th pixel (P) is designated as “GLn”, the gate line of the adjacent (n-1)th pixel (P) is “GLn-1” and the gate line of the (n-1)th pixel (P) serves as the acquisition control line (SCL) of the (n)th pixel (P).

[0165] The pixel control circuit (PDC) comprises a second thin-film transistor (TR2, switching transistor) connected to the gate line (GL) and the data line (DL), a first thin-film transistor (TR1, drive transistor) configured to control a level of current supplied to the display unit 710 according to the data voltage (Vdata) transmitted by the second thin-film transistor (TR2), and a third thin-film transistor (TR3, reference transistor) configured to detect the characteristics of the first thin-film transistor (TR1).

[0166] A storage capacitor (Cst) is arranged between the display unit 710 and a gate electrode (G1) of the first thin-film transistor (TR1).

[0167] The second thin-film transistor (TR2) is switched on by the sampling signal (SS) supplied to the gate line (GL), and the second thin-film transistor (TR2) transmits the data voltage (Vdata) supplied to the data line (DL) to the first gate electrode (G1) of the first thin-film transistor (TR1).

[0168] The third thin-film transistor (TR3) is connected to the reference line (RL) and a first node (n1) between the display unit 710 and the first thin-film transistor (TR1). The third thin-film transistor (TR3) is switched on or off by the sensing control signal (SCS) and senses the characteristics of the first thin-film transistor (TR1), which corresponds to the drive transistor, for one sensing period.

[0169] A second node (n2), connected to the first gate electrode (G1) of the first thin-film transistor (TR1), is connected to the second thin-film transistor (TR2). The storage capacitor (Cst) is formed between the second node (n2) and the first node (n1).

[0170] When the second thin-film transistor (TR2) is switched on, the data voltage (Vdata), supplied via the data line (DL), is applied to the first gate electrode (G1) of the first thin-film transistor (TR1). The storage capacitor (Cst), which is formed between the first source electrode (S1) and the first gate electrode (G1) of the first thin-film transistor (TR1), is charged with the data voltage (Vdata).

[0171] When the first thin-film transistor (TR1) is switched on, current is supplied to the display unit 710 through the first thin-film transistor (TR1) by the drive voltage (Vdd) to control the pixel, consequently light is emitted from the display unit 710.

[0172] The pixel control circuit (PDC) according to another aspect of this disclosure can be implemented in various structures in addition to the structure described above. For example, the pixel control circuit (PDC) can comprise five or more thin-film transistors.

[0173] Below is a method for manufacturing the display device 100 according to one aspect of the present disclosure with reference to Fig. 9A to 9I and Fig. Described in sections 10A to 10D.

[0174] Fig. Figures 9A to 9I are cross-sectional views illustrating the method for manufacturing the display device 100 according to one aspect of the present disclosure, and Fig. Figures 10A to 10D are top views illustrating the method for manufacturing the display device 100 according to one aspect of the present disclosure.

[0175] With reference to Fig. In step 9A, a first layer 115 of conductive material, a first insulating material layer 120, and a first layer 130 of active material are sequentially deposited on the first substrate 110. Here, the conductive layer 115 is formed from a first conductive material, the insulating material layer 120 is formed from a first insulating material, and the active material layer 130 is formed from a first active material.

[0176] According to one aspect of the present disclosure, the first active material is an oxide semiconductor material, and the first layer 130 of active material is an oxide semiconductor layer. The first layer 130 of active material can comprise at least one oxide semiconductor material based on IZO(InZnO), an oxide semiconductor material based on IGO(InGaO), an oxide semiconductor material based on ITO(InSnO), an oxide semiconductor material based on IGZO(InGaZnO), an oxide semiconductor material based on IGZTO(InGaZnSnO), an oxide semiconductor material based on GZTO(GaZnSnO), an oxide semiconductor material based on GZO(GaZnO), an oxide semiconductor material based on GO(GaO), and an oxide semiconductor material based on ITZO(InSnZnO).

[0177] With reference to Fig. 9A also forms a photoresist layer 310 on the first layer 130 made of active material. The photoresist layer 310 can be formed from a negative photoresist material (PR material) or a positive photoresist material (PR material). According to one aspect of the present disclosure, the photoresist layer 310 can be formed from the positive photoresist material (PR material).

[0178] A pattern mask 610 is placed on the photoresist layer 310 and light (L) is emitted through the pattern mask 610, consequently an exposure is carried out for the photoresist layer 310.

[0179] A mesh etching mask can be used for pattern mask 610. With reference to Fig. 9A is the pattern mask 610, the reticular etching mask with a transparent section 611, a semi-transparent section 612 and a light-shielding section 613.

[0180] The photoresist layer 310 is selectively exposed by means of the pattern mask 610. The light-shielding layer 613 of the pattern mask 610 corresponds to the area to be provided with the first active layer (A1). The semi-transparent section 612 of the pattern mask 610 corresponds to the area to be provided with the first gate electrode (G1), the data line (DL), and the drive voltage line (PL). The transparent section 611 of the pattern mask 610 corresponds to the area from which the first conductive layer 115, the first insulating layer 120, and the first active layer 130 are completely removed.

[0181] With reference to Fig. In step 9B, the selectively exposed photoresist layer 310 is developed to form photoresist patterns 310a, 310b and 310b.

[0182] With reference to Fig. 9C the first gate electrode (G1) from the first conductive material, the first gate insulating film 121 from the first insulating material and the first active layer (A1) from the first active material are formed by a selective etching process.

[0183] Specifically, an etching process is performed using the photoresist patterns 310a, 310b, and 310c, such that the first active layer (A1) is formed by structuring the first layer 130 of active material, the first gate insulating film 121 is formed by structuring the first insulating material layer 120, and the first gate electrode (G1) is formed by structuring the first layer 115 of conductive material. The data line (DL) and the drive voltage line (PL) are also formed by structuring the first layer 115 of conductive material.

[0184] Fig. 9C corresponds to 10A in the plane.

[0185] As described above, a first masking process (MASK1) is performed to form a first gate electrode (G1) and the first active layer (A1).

[0186] With reference to Fig. In step 9D, the first insulating layer 171 is formed on the first active layer (A1). The contact holes are formed in the first insulating layer 171 and the first gate insulating film 121. Specifically, the first contact hole (CH1) is formed in the first insulating layer 171 and the first gate insulating film 121, exposing part of the data line (DL); the second contact hole (CH2) is formed in the first insulating layer 171 and the first gate insulating film 121, exposing part of the first gate electrode (G1); and the third contact hole (CH3) and the fourth contact hole (CH4) are formed in the first insulating layer 171, partially exposing the first active layer (A1).

[0187] To form the contact holes in the first insulating intermediate layer 171 and in the first gate insulating film 121, a second masking process (MASK2) is carried out.

[0188] The etch stop (ES) is also formed on the first active layer (A1) for the process of forming the contact holes (CH1, CH2, CH3, CH4). The etch stop (ES) is formed between the third contact hole (CH3) and the fourth contact hole (CH4) and is configured to protect the channel region of the first active layer (A1).

[0189] With reference to Fig. In step 9E, a second active material 151, 152 and 153 is formed on the first insulating intermediate layer 171. The second layer 151, 152 and 153 of active material comprises several patterns.

[0190] A third masking process (MASK3) is carried out to form the second layer 151, 152 and 153 from active material.

[0191] Fig. 9E corresponds to 10B in the plane.

[0192] The oxide semiconductor material can be used for the second active material. According to one aspect of the present disclosure, the second layer 151, 152 and 153 of active material corresponds to the oxide semiconductor layer.

[0193] The second layer 151, 152 and 153 of active material can be formed from the same semiconductor material as that of the first layer 130 of active material, or it can be formed from a different semiconductor material than that of the first layer 130 of active material.

[0194] The second layer 151, 152 and 153 of active material can, for example, comprise at least one of the following oxide semiconductor materials: IZO(InZnO)-based, IGO(InGaO)-based, ITO(InSnO)-based, IGZO(InGaZnO)-based, IGZTO(InGaZnSnO)-based, GZTO(GaZnSnO)-based, GZO(GaZnO)-based, GO(GaO)-based, and ITZO(InSnZnO)-based.

[0195] With reference to Fig. 9F the second gate insulation film 122 and the second gate electrode (G2) are formed on at least part of the second layer 151, 152 and 153 of active material.

[0196] Fig. 9°F corresponds to 10°C in the plane.

[0197] A fourth mask process (MASK4) is performed to form the second gate insulation film 122 and the second gate electrode (G2).

[0198] After the formation of the second gate insulation film 122 and the second gate electrode (G2), a portion of the second layer 151, 152, and 153 of active material, which does not overlap with the second gate electrode (G2), is made conductive. Consequently, it is possible to form the first source electrode (S1), the first drain electrode (D1), the second source electrode (S2), and the second drain electrode (D2).

[0199] Plasma treatment or hydrogen treatment can be performed for the process of making the material conductive.

[0200] The second active material for forming the second active layer (A2) is the oxide semiconductor material; consequently, the second active material is made conductive by plasma treatment or hydrogen treatment.

[0201] The conductive sections of the second layer 151, 152, and 153 made of active material can be referred to as conductive sections. These multiple conductive sections can be formed through the process of making the second layer 151, 152, and 153 conductive.

[0202] For the conductive process, the second gate electrode (G2) acts as a mask. Consequently, the area of ​​the second active layer that overlaps with the second gate electrode (G2) is made non-conductive. This non-conductive area of ​​the second active layer, while overlapping with the second gate electrode (G2), becomes the second active layer (A2). Therefore, it is possible to construct the second thin-film transistor (TR2) with the second gate electrode (G2), the second active layer (A2), the second source electrode (S2), and the second drain electrode (D2).The second source electrode (S2) is connected to the data line (DL) through the first contact hole (CH1) provided in the first gate insulation film 121 and in the first insulating intermediate layer 171, and the second drain electrode (D2) is connected to the first gate electrode (G1) through the second contact hole (CH2) provided in the first gate insulation film 121 and in the first insulating intermediate layer 171.

[0203] The first source electrode (S1) and the first drain electrode (D1) are formed while spaced apart from each other and are connected to the first active layer (A1) through the conductivity step.

[0204] With reference to Fig. 9F, the region of conductive sections connected to the first active layer (A1) becomes the first source electrode (S1) and the first drain electrode (D1). For example, the region of conductive sections connected to the first active layer (A1) becomes the first source electrode (S1), and the region spaced from the first source electrode (S1) and connected to the first active layer (A1) becomes the first drain electrode (D1). Specifically, the first drain electrode (D1) is connected to the first active layer (A1) through the third contact hole (CH3) provided in the first insulating intermediate layer 171. The first source electrode (S1) is connected to the first active layer (A1) through the fourth contact hole (CH4) provided in the first insulating intermediate layer 171. With reference to Fig. Step 5 also forms the etch stop (ES) between the third contact hole (CH3) and the fourth contact hole (CH4). Consequently, the first thin-film transistor (TR1) is formed with the first gate electrode (G1), the first active layer (A1), the first source electrode (S1), and the first drain electrode (D1).

[0205] With reference to Fig. 9F also form the first capacitor (C1) by a certain area of ​​the first source electrode (S2) and a certain area of ​​the first gate electrode (G1) that overlap with each other. Specifically, the first capacitor (C1) is formed by the first capacitor electrode (CE1), which is designed as a single body with the first source electrode (S1), and the second capacitor electrode (CE2), which is designed as a single body with the first gate electrode (G1).

[0206] The storage capacitor (Cst) includes the first capacitor (C1).

[0207] With reference to Fig. In step 9G, the second insulating layer 172 is formed on the first thin-film transistor (TR1), the second thin-film transistor (TR2), and the first capacitor (C1). The second insulating layer 172 can be made of an organic or inorganic insulating material. The fifth contact hole (CH5) is formed in the second insulating layer 172, consequently exposing part of the second drain electrode (D2).

[0208] To form the fifth contact hole (CH5) in the second insulating intermediate layer 172, a fifth masking process (MASK5) is carried out.

[0209] With reference to Fig. In 9H, the gate line (GL), the emission control line (EL), the drive voltage connection line (PLB), and the third capacitor electrode (CE3) are formed on the second insulating layer 172. The gate line (GL), the emission control line (EL), the drive voltage connection line (PLB), and the third capacitor electrode (CE3) are referred to as the upper lines.

[0210] Fig. 9H corresponds to Fig. 10D in the plane.

[0211] A sixth masking process (MASK6) is executed to form the upper lines, such as the gate line (GL), the emission control line (EL), the drive voltage link line (PLB), and the third capacitor electrode (CE3). Consequently, the pixel drive circuit (PDC) is formed.

[0212] According to one aspect of the present disclosure, the pixel control circuit (PDC) is formed by the six mask processes.

[0213] With reference to Fig. In step 9H, the second insulating layer 172 is formed on the first source electrode (S1), and the third capacitor electrode (CE3) is partially overlapped with at least part of the first source electrode (S1) on the second insulating layer 172. The third capacitor electrode (CE3) is connected to the second drain electrode (D2) through the fifth contact hole (CH5) provided in the second insulating layer 172. Consequently, the third capacitor electrode (CE3) can be connected to the second capacitor electrode (CE2) through the second drain electrode (D2).

[0214] The third capacitor electrode (CE3) together with the first capacitor electrode (CE1) forms the second capacitor (C2). The first capacitor (C1) and the second capacitor (C2) form the storage capacitor (Cst).

[0215] With reference to Fig. 9I then arranges the planarization layer 173 on the gate line (GL), the emission control line (EL), the drive voltage connection line (PLB), and the third capacitor electrode (CE3). The first electrode 711 of the display unit 710 is arranged on the planarization layer 173, the organic emission layer 712 is arranged on the first electrode 711, and the second electrode 713 is arranged on the organic emission layer 712, thereby completing the display device 100. The first electrode 711 is connected to the source electrode (S1) of the first thin-film transistor (TR1) through the sixth contact hole (CH6) provided in the planarization layer 173 and the second insulating intermediate layer 172.

[0216] Fig. Figure 11 is a diagram comparing a process for manufacturing a display device according to one aspect of the present disclosure with a process for manufacturing a display device according to the prior art.

[0217] In detail, it compares Fig. 11 the number of mask processes that are executed until the pixel control circuit (PDC) in the display device is completed, according to the display device according to one aspect of the present disclosure with the number of mask processes that are executed until a pixel control circuit in the display device according to the prior art is completed.

[0218] According to one aspect of the present disclosure, six mask processes are required to form the pixel control circuit (PDC).

[0219] Specifically, according to one aspect of the present disclosure, the first masking process (MASK1) is performed to form the first gate electrode (G1) and the first active layer (A1), the second masking process (MASK2) is performed to form the contact hole in the first insulating intermediate layer 171, the third masking process (MASK3) is performed to form the second layer of active material, and the fourth masking process (MASK4) is performed to form the second gate electrode (G2). The conductive process for the second layer of active material is performed during the fourth masking process (MASK4) and can be carried out using the second gate electrode (G2) as a mask. The fifth masking process (MASK5) is also performed to form the contact hole in the second insulating intermediate layer 172, and the sixth masking process (MASK6) is performed to form the upper conductors, such as...to form the gate line (GL), the emission control line (EL), the drive voltage connection line (PLB) and the third capacitor electrode (CE3).

[0220] Meanwhile, seven mask processes are required to train the pixel control circuit (PDC) of the display device according to the state of the art, which is described in Fig. 6A and Fig. 6B is shown.

[0221] Specifically, according to the prior art, the first mask process (MASK1) is carried out to form a lower metal pattern 116, the second mask process (MASK2) is carried out to form a contact hole in a buffer layer 125, the third mask process (MASK3) is carried out to form layers of active material (ACT1, ACT2), and the fourth mask process (MASK4) is carried out to form gate electrodes (TG1, TG2). The conductive process for the active material layers (ACT1, ACT2) is carried out for the fourth mask process (MASK4). The fifth mask process (MASK5) is also carried out to form an upper capacitor electrode (CE3), the sixth mask process (MASK6) is carried out to form a contact hole in a second insulating intermediate layer 172, and the seventh mask process (MASK7) is carried out to form upper conductors such as...to form a gate line (GL), an emission control line (EL), a control voltage connection line (PLB) and a third capacitor electrode (CE3).

[0222] The number of masking processes required to form the pixel control circuit (PDC) according to one aspect of the present disclosure is smaller than the number of masking processes required to form the pixel driver with a similar structure according to the prior art. Consequently, according to the present disclosure, it is possible to simplify the manufacturing process and also to reduce manufacturing costs and manufacturing time.

Claims

[1] Display device comprising the following: a substrate (110); a pixel control circuit (PDC) on the substrate (PDC); and a display unit (710) connected to the pixel control circuit (PDC), wherein the pixel control circuit (PDC) comprises a first thin-film transistor (TR1) and a second thin-film transistor (TR2), wherein the first thin-film transistor (TR1) comprises: a first gate electrode (G1) on the substrate (110), a first active layer (A1) that is spaced apart from the first gate electrode (G1) and overlaps with at least part of the first gate electrode (G1), a first source electrode (S1) connected to the first active layer (A1); and a first drain electrode (D1) which is spaced apart from the first source electrode (S1) and connected to the first active layer (A1), and the second thin-film transistor (TR2) contains the following: a second active layer (A2) on the substrate (110), and a second gate electrode (G2) that is spaced apart from the second active layer (A2) and partially overlaps with at least part of the second active layer (A2), wherein the first gate electrode (G1) is arranged between the substrate (110) and the first active layer (A1), the second active layer (A2) is arranged between the substrate (110) and the second gate electrode (G2), and the first gate electrode (G1) and the second gate electrode (G2) are arranged on opposite sides with respect to the second active layer (A2), wherein the display device further comprises a first insulating intermediate layer (171) on the first active layer (A1), wherein the first source electrode (S1) and the first drain electrode (D1) are arranged directly on the first insulating intermediate layer (171) and are connected to the first active layer (A1) by contact holes (CH3, CH4). [2] Display device according to claim 1, wherein the second active layer (A2) is arranged at the same layer as the first source electrode (S1) and the first drain electrode (D1). [3] Display device according to one of the preceding claims, wherein each of the first source electrode (S1) and / or the first drain electrode (D1) has a recess in the contact hole (CH3, CH4) and / or each of the first source electrode (S1) and the first drain electrode (D1) directly contacts the first active layer (A1) through the contact hole (CH3, CH4). [4] Display device according to claim 1, 2 or 3, further comprising an etch stopper (ES) on the first active layer (A1), preferably the etch stopper (ES) being arranged on the same layer as the first insulating intermediate layer (171) and / or being made of the same material as the first insulating intermediate layer (171). [5] Display device according to one of claims 1 to 4, wherein the second active layer (A2) is arranged on the first insulating intermediate layer (171). [6] Display device according to one of the preceding claims, wherein the second active layer (A2), the first source electrode (S1) and the first drain electrode (D1) are formed from an oxide semiconductor material. [7] Display device according to any of the preceding claims, wherein the first active layer (A1) and / or the second active layer (A2) comprise: a first oxide semiconductor layer (A1a, A2a); and a second oxide semiconductor layer (A1b, A2b) that is arranged on top of the first oxide semiconductor layer (A1a, A2a). [8] Display device according to one of the preceding claims, further comprising a data line (DL) and a control voltage line (PL), wherein the data line (DL) and the control voltage line (PL) are arranged on the same layer as the first gate electrode (G1). [9] Display device according to any one of the preceding claims 1 to 8, further comprising: a second insulating intermediate layer (172) on the first source electrode (S1) and the first drain electrode (D1); and a planarization layer (173) on the second insulating intermediate layer (172), wherein the display unit (710) is arranged on the planarization layer (173). [10] Display device according to one of the preceding claims, further comprising a storage capacitor (Cst) connected to the first thin-film transistor (TR1), wherein the storage capacitor (Cst) comprises: a first capacitor electrode (CE1) formed as a body with the first source electrode (S1); and a second capacitor electrode (CE2) formed as a body with the first gate electrode (G1). [11] Display device according to claim 10, wherein the storage capacitor (Cst) further comprises a third capacitor electrode (CE3) which is spaced apart from the first capacitor electrode (CE1) and / or is arranged on the second insulating intermediate layer (173). [12] Display device according to one of the preceding claims, wherein a part of the first source electrode (S1) and a part of the first gate electrode (G1) overlap vertically and form a storage capacitor (Cst). [13] A method for manufacturing a display device comprising: sequential deposition of a first layer (115) of conductive material, a first insulating material layer (120) and a first layer (130) of active material on a substrate (110); Forming a first source electrode (S1) and a first drain electrode (D1) that are spaced apart from each other and connected to the first layer (130) of active material; Formation of a first gate electrode (G1) from the first layer (115) of conductive material, a first gate insulating film (121) from the first insulating material layer (120) and a first active layer (A1) from the first layer (130) of active material by a selective etching process; Formation of a first insulating intermediate layer (171) on the first active layer (A1); Forming a second layer (151) of active material with multiple patterns on the first insulating intermediate layer (171); Forming a second gate insulation film (122) and a second gate electrode (G2) on at least part of the second layer (151) of active material; and Making the second layer (151) of active material conductive in the area that does not overlap with the second gate electrode (G2), wherein the first source electrode (S1) and the first drain electrode (D1) are formed directly on the first insulating intermediate layer (171) and are connected to the first active layer (A1) by contact holes (CH3, CH4). [14] The method of claim 13, further comprising: Formation of a second insulating intermediate layer (172) on the first source electrode (S1); and Forming a third capacitor electrode (CE3) that overlaps at least part of the first source electrode (S1) on the second insulating intermediate layer (172).

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