DYNAMIC RANGE EXTENSION DEVICE

Abstract

Dynamic Range Extender (DRE) device (500) receiving an input signal (d[n]) and providing a DRE output signal (a[n]) comprising the following: an error correction circuit (502) that is configured to have an error correction factor (d e [n]) to apply to the input signal (d[n]) such that the DRE output signal (a[n]) provided by the device (500) is differentiated from the input signal (d[n]) and the error correction factor (d e [n]) depends; where the error correction factor (d e [n]) represents a fault produced by the device (500).

Description

[0001] The present disclosure relates to a device for dynamic range extension. In particular, the disclosure relates to a device for dynamic range extension that includes an error correction circuit. BACKGROUND

[0002] Dynamic Range Extension (DRE) is a technique used to suppress errors in a signal path. DRE amplifies a signal before a processing step that introduces errors into the signal and then attenuates the signal after the processing step.

[0003] Fig. Figure 1 shows a diagram of a DRE system 100, which comprises an amplifier circuit 102, a processing circuit 104, and an attenuator circuit 106. A signal path is formed from a signal path input 108 to a signal path output 110. In the DRE system 100, the signal path input 108 corresponds to an input of the amplifier circuit 102, and the signal path output 110 corresponds to an output of the attenuator circuit 106. In the DRE system 100 of Fig. For example, the amplifier circuit 102 can provide a gain of +12 dB and the attenuator circuit 106 can provide a gain of -12 dB.

[0004] During operation, a signal is received at the input of amplifier 102. The signal is then amplified by a gain of +12 dB before being passed through the processing circuit 104.

[0005] The processing circuit 104 comprises a processing block 112 and a summing circuit 114. The processing block 112 represents a processing step performed on the signal by the processing circuit 104, and the summing circuit 114 represents the addition of an error 116 to the signal as it passes through the processing circuit 104. The processing circuit 104 outputs the signal to the attenuating circuit 106, which attenuates the signal by a gain of -12 dB before the signal is provided at the output of the attenuating circuit 106. The error 116, which is added to the signal as it passes through the processing circuit 104, is suppressed by 12 dB when referenced to either the signal path input 108 or the signal path output 110.

[0006] Fig. Figure 2 shows a DRE circuit 200, which corresponds to an alternative diagram of the DRE system 100, which is in Fig. As shown in 1, this corresponds to common components between Fig. 1 and Fig. 2 use common reference symbols and variables. Amplifier circuit 102 receives a digital input signal d[n] at signal path input 108. Amplifier circuit 106 applies a dynamic digital gain g. d [n] to the digital input signal d[n]. The processing circuit 104 includes a digital-to-analog converter (DAC) 202 to convert a digital signal to an analog signal.

[0007] The summing circuit 114 and the processing block 112 were in Fig. 2 is omitted; however, it will be acknowledged that the DAC 202 incorporates these components, since the DAC 202 is susceptible to error 116 and the DAC 202 provides a digital-to-analog conversion function, as can be represented by the processing block 112. For the processing circuit 104, which includes the DAC 202, error 116 can result, for example, from random noise and / or power supply disturbances.

[0008] The DAC 202 has an impulse response h[n]. The impulse response h[n] describes how the DAC 202 responds to receiving a signal over a certain time frame. The attenuator circuit 106 applies a dynamic analog gain g. d [n] and outputs an analog output signal a[n] at signal path output 110.

[0009] The signal path of the DRE circuit 200 can be described as a D / A signal path, which, with the inclusion of the DAC 202, means that a digital input signal is converted to an analog output signal.

[0010] The DRE 200 circuit also provides a model for the signal path, which can be mathematically represented as shown in equation (1). The analog output signal a[n] is shaped as follows: a[n]=((d[n]⋅gd[n])*h[n])⋅ga[n], where the symbols have the meanings described above. n is a time index, and therefore equation (1) is in the time domain. The time index n has discrete values. A multiplication of two time-varying sequences, namely the digital input signal d[n] and the digital gain g dIn the time domain, the DRE circuit 200 becomes nonlinear, such that it can exhibit undesirable behavior. The DRE circuit 200 can display nonlinear behavior even for a relatively small digital input signal d[n].

[0011] Fig. 3(a) and Fig. 3(b) show simulation results for the DRE circuit 200 of Fig. 2. The simulations were performed using parameters that represent a practical implementation of the DRE circuit 200.

[0012] Fig. 3(a) shows the dynamic digital amplification g d [n] 300 and the dynamic analog gain g d [n] 302, as they vary over time. Fig. Figure 3(b) shows the analog output signal a[n] 304 as it varies over time. Before a time t1, the gains g d [n] 300, g d[n] 302 equals one and the analog output signal a[n] 304 equals 0.25 V.

[0013] It should be noted that the units that represent the x-axis of Fig. 3(a) are assigned, seconds (s) are and the units that correspond to the x-axis of Fig. 3(b) are assigned microseconds (µs).

[0014] At time t1, the gain g increases d [n] 300 to 2 to and the amplification g d [n] 302 decreases to 0.5. Because the processing circuit 104 has a finite bandwidth, the change in gain at time t1 results in a transient output error in the analog output signal a[n] 304, which resembles a decaying pulse. The error is shown by the drop in the analog output signal a[n] 304 and its gradual increase as the analog output signal a[n] 304 decays back to its initial value.

[0015] It will be acknowledged that if processing circuit 104 was omitted, the gains g d [n], g d [n] have not introduced any error into the signal path.

[0016] Fig. Figure 4 shows curve 400 of the Fourier transform of the analog output signal a[n] 304, to which no gain was applied, and curve 402 of the Fourier transform of the analog output signal a[n], to which a gain change was applied. Curve 402 shows the Fourier transform of the analog output signal a[n] when a 6 dB step is applied to the input signal d[n] by amplifier circuit 102 and a corresponding -6 dB step is applied by amplifier circuit 106.

[0017] Since the Fourier transform of a decaying impulse is a low-pass filter, the error is flat at low frequencies and rolls off at high frequencies, as can be observed in curve 400. "Flat" means that the error retains an essentially constant value at low frequencies, and "rolls off" means that the error decreases at high frequencies as the frequency increases.

[0018] It will be acknowledged that the low-pass filter characteristics shown by curve 400 are a result of the impulse response h[n] of the DAC 202 being a low-pass filter, however, other filter types can be used.

[0019] For DRE audio applications, the flat response of the error at low frequencies means that the gain change can lead to a particularly undesirable audible click.

[0020] Document US 10 090 854 B1 concerns a gain mismatch correction between individual segments for segmented digital-to-analog converters (DACs).

[0021] Publication US 2003 / 0 102 994 A1 relates to a high dynamic range digital converter, in particular a variable gain digital converter system suitable for digitizing signals that have a high dynamic range, such as signals in photon detection systems or other various applications. SUMMARY

[0022] It is desirable to provide a dynamic range extension device that can reduce errors during dynamic range extension gain changes compared to the prior art.

[0023] According to a first aspect of the disclosure, a dynamic range extension (DRE) device is provided which receives an input signal and provides a DRE output signal, comprising an error correction circuit configured to apply an error correction factor to the input signal such that the DRE output signal provided by the device depends on the input signal and the error correction factor, wherein the error correction factor represents an error generated by the device.

[0024] Optionally, the device includes a DRE circuit, wherein the error correction circuit is configured to receive the input signal and provide a corrected signal based on the input signal and the error correction factor, and the DRE circuit is configured to receive the corrected signal and provide the DRE output signal based on the received corrected signal.

[0025] Optionally, the DRE circuit comprises an amplifier circuit configured to amplify the corrected signal, a processing circuit configured to receive the corrected signal from the amplifier circuit and process the corrected signal, and an attenuator circuit configured to receive the corrected signal from the processing circuit, attenuate the corrected signal, and provide the corrected signal as an output signal of the attenuator circuit, wherein the DRE output signal corresponds to the corrected signal output by the attenuator circuit.

[0026] Optionally, the processing circuit includes a digital-to-analog converter (DAC) configured to receive the corrected signal from the amplifier circuit, wherein processing the corrected signal includes converting the corrected signal from digital to analog using the DAC.

[0027] Optionally, the error correction circuit includes a summing circuit configured to generate the corrected signal by adding or subtracting the error correction factor to or from the input signal, with the corrected signal being provided at an output of the error correction circuit.

[0028] Optionally, the device includes a sigma-delta modulator that incorporates the error correction circuit, wherein the sigma-delta modulator is configured to reduce the resolution of the corrected signal before the corrected signal is received by the processing circuit.

[0029] Optionally, the sigma-delta modulator includes a loop filter and a quantizer configured to reduce the resolution of the corrected signal before the corrected signal is received by the processing circuit, wherein the loop filter includes a first input for receiving the corrected signal and an output coupled to the quantizer, and the quantizer has an output coupled to the processing circuit and a second input of the loop filter.

[0030] Optionally, the output of the quantizer is coupled to the processing circuit via the amplifier circuit.

[0031] Optionally, the loop filter is coupled to the quantizer via the amplifier circuit, and the output of the quantizer is coupled to the second input of the loop filter via a second amplifier circuit.

[0032] Optionally, the device includes a sigma-delta modulator that incorporates the error correction circuit, wherein the sigma-delta modulator is configured to reduce the resolution of the corrected signal before the corrected signal is received by the processing circuit.

[0033] Optionally, the error correction circuit comprises a loop filter including a first input for receiving the input signal, and a summing circuit including a first input for receiving the error correction factor and an output coupled to the second input of the loop filter, and the sigma-delta modulator includes a quantizer, wherein the loop filter includes an output coupled to the quantizer, the corrected signal being provided at the output of the loop filter, and the quantizer having an output coupled to the processing circuit and a second input of the summing circuit.

[0034] Optionally, the output of the quantizer can be coupled to the processing circuit via the amplifier circuit.

[0035] Optionally, the loop filter is coupled to the quantizer via the amplifier circuit, and the output of the quantizer is coupled to the second input of the loop filter via a second amplifier circuit.

[0036] Optionally, the device includes a memory element configured to store the error correction factor and provide the error correction factor to the error correction circuit.

[0037] Alternatively, the error correction factor is derived by calculating the error generated by the device.

[0038] Optionally, the device includes an error correction factor generator configured to detect the error produced by the device, generate the error correction factor using the detected error, and provide the error correction factor to an error correction circuit.

[0039] Optionally, the device comprises a DRE circuit, which includes the error correction circuit, an amplifier circuit configured to amplify the input signal, a processing circuit configured to receive the input signal from the amplifier circuit and process the input signal, and an attenuation circuit configured to receive the input signal from the processing circuit, attenuate the input signal, and provide the input signal as an output signal of the attenuation circuit, wherein the DRE output signal corresponds to the input signal output by the attenuation circuit, and the input signal is adjusted by the error correction circuit based on the error correction factor before being output by the attenuation circuit as the DRE output signal.

[0040] Optionally, the attenuation circuit includes the error correction circuit, and the error correction circuit is configured to adjust the attenuation applied by the attenuation circuit based on the received error correction factor.

[0041] Alternatively, the error generated by the device results from a change in gain and / or a delay.

[0042] Optionally, the error correction circuit is configured to receive the error correction factor.

[0043] According to a second aspect of the disclosure, a dynamic range extension (DER) method is provided using a device comprising an error correction circuit, wherein the method comprises receiving an input signal at the device, applying an error correction factor to the input signal using the error correction circuit, and providing a DRE output signal, wherein the DRE output signal provided by the device depends on the input signal and the error correction factor, and the error correction factor represents an error generated by the device.

[0044] It will be acknowledged that the procedure of the second aspect may involve the provision and / or use of the components set out in the first aspects and may include further components as described here. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The revelation is described in more detail below, using examples and referring to the accompanying drawings; these show: Fig. 1. A diagram of a DRE system; Fig. 2 a diagram of a DRE circuit, which is an alternative diagram of the DRE system of Fig. 1 corresponds to; Fig. 3(a) Simulation results of the dynamic gains of the DRE circuit of Fig. 2 and Fig. 3(b) Simulation results of the analog output signal of the DRE circuit of Fig. 2; Fig. 4 a graph of the Fourier transform of the analog output signal, which is in Fig. 3(b) is shown, with and without applied gain change; Fig. 5(a) a diagram of a device according to a first embodiment of the present disclosure, Fig. 5(b) a diagram of a device according to a second embodiment of the present disclosure, Fig. 5(c) a diagram of a device according to a third embodiment of the present disclosure and Fig. 5(d) a diagram of a device according to a fourth embodiment of the present disclosure; Fig. 6(a) a diagram of a device according to a fifth embodiment of the present disclosure, Fig. 6(b) a diagram of a device according to a sixth embodiment of the present disclosure and Fig. 6(c) a diagram of a device according to a seventh embodiment of the present disclosure; Fig. 7(a) a diagram of a device according to an eighth embodiment of the present disclosure and Fig. 7(b) a diagram of a device according to a ninth embodiment of the present disclosure; Fig. 8 a diagram of a device according to a tenth embodiment of the present disclosure; Fig. 9 a diagram of a device according to an eleventh embodiment of the present disclosure; Fig. 10 a diagram of a device according to a twelfth embodiment of the present disclosure; Fig. 11 Simulation results of the Fourier transform of the output signal of the device of Fig. 2, wherein the device comprises a DAC which acts as an IIR filter; Fig. 12 Simulation results of the Fourier transform of the output signal of the device of Fig. 6(a) wherein the device comprises a DAC which acts as an IIR filter; Fig. 13 a diagram of a device according to a thirteenth embodiment of the present disclosure; and Fig. 14 a diagram of a device according to a fourteenth embodiment of the present disclosure. DETAILED DESCRIPTION

[0046] Error 116, which is responsible for Fig. As described in section 1, this is achieved by including a dynamic range extension circuit (DRE circuit), e.g., of the type described in section 1. Fig. As shown in Figure 2, the present disclosure provides a device that can reduce errors arising from the inclusion of the DRE circuit itself. In particular, the disclosure relates to the reduction of errors arising from the gain change associated with the DRE circuit.

[0047] Fig. Figure 5(a) shows a dynamic range extension (DRE) device 500 according to a first embodiment of this disclosure. The device 500 is configured to receive an input signal d[n] and provides a DRE output signal a[n].

[0048] The device 500 creates an error correction circuit 502. The error correction circuit 502 is configured to have an error correction factor d. e [n] to apply to the input signal d[n] such that the DRE output signal a[n] provided by the device 500 is differentiated from the input signal d[n] and the error correction factor d e [n] is dependent. The error correction factor d e [n] represents a fault produced by the device 500.

[0049] Fig. 5(b) shows an embodiment of the dynamic range extension (DRE) device 500, which is described in Fig. 5(a) is shown according to a second embodiment of this disclosure. The device 500 is configured to receive an input signal d[n] and to provide a DRE output signal a[n].

[0050] The device (500) includes the error correction circuit 502 and a DRE circuit 504.

[0051] The error correction circuit 502 is configured, the input signal d[n] and the error correction factor d e [n] to receive and a corrected signal 510, which is the input signal d[n] and the error correction factor d e [n] is used as a basis to provide. The DRE circuit 504 is configured to receive the corrected signal 510 and to provide the DRE output signal a[n] based on the received corrected signal 510. The error correction factor d e [n] represents a fault produced by the device 500, and in particular represents the fault produced by the DRE circuit 504.

[0052] The term "error correction signal d" e [n]” can be used to refer to the error correction factor d e [n] to refer to when the error correction factor d e [n] is received by the error correction circuit 502.

[0053] The signal path is formed from an input of the error correction circuit 502, which receives the input signal d[n], to an output of the DRE circuit 504, which provides the DRE output signal a[n].

[0054] The input signal d[n] can be the digital input signal d[n], which is used for Fig. 2 is described, and the DRE output signal a[n] can correspond to the analog output signal a[n], which is used for Fig. 2 as described.

[0055] The error correction circuit 502 enables the error caused by the gain change of the DRE circuit 504 to be essentially removed from the signal path of the device 500. The error correction signal d e [n] can represent the error that arose due to the gain change of the DRE circuit 504.

[0056] The error correction signal d e[n] can be derived by calculating the error generated by the device 500, and in particular by calculating the error generated by the DRE circuit 504, e.g., by calculating the error expected from the gain change of the DRE circuit 504. The expected error can be calculated taking into account the circuit components of the DRE circuit 504. Alternatively, the error correction signal d can be e [n] can be estimated simply without a precise derivation of the expected error.

[0057] Fig. Figure 5(c) shows a device 501 according to a third embodiment of this disclosure. The device 501 corresponds to the device 500, however, in this particular embodiment, the device 501 comprises a storage element 503 configured to store the error correction signal d. e [n] to store and the error correction signal d to the error correction circuit 502 e[n] to provide. Common elements between different figures are represented by common reference symbols and common variables.

[0058] Fig. Figure 5(d) shows a device 505 according to a fourth embodiment of this disclosure. The device 505 corresponds to the device 500, except that in this particular embodiment, the device 505 comprises an error correction signal generator 506. A feedback loop is formed from the DRE circuit 504 to the error correction circuit 502 by means of the error correction signal generator 506. Using the error correction signal generator 506, the error correction signal d e[n] during the operation of the DRE circuit 504. The error correction signal generator 506 is configured to detect the error generated by the device 500 (in particular the error generated by the DRE circuit 504) and to generate a suitable error correction signal d e [n] to generate using the detected error. The error correction signal generator 506 then provides the error correction signal d to the error correction circuit 502. e [n] ready. Common elements between different figures are represented by common reference symbols and common variables.

[0059] It will be acknowledged that other methods exist to correct the error correction signal d e [n] to be determined according to the understanding of qualified persons.

[0060] Fig. Figure 6(a) shows a device 600 according to a fifth embodiment of this disclosure. The device 600 corresponds to the device 500, but with specific implementations of the error correction circuit 502 and the DRE circuit 504. The specific implementations use components common to the DRE system 100 and the DRE circuit 200. Common components between different figures are represented by common reference numerals and common variables.

[0061] The input signal d[n] is corrected by the error correction circuit 502 based on the error correction signal d e [n] adapted to provide the corrected signal 510. Specifically, the error correction circuit 502 includes a summing circuit 602 configured to provide the corrected signal 510 by adding or subtracting the error correction signal d e[n] from the input signal d[n]. The corrected signal 510, generated by the error correction circuit 502, is provided to the DRE circuit 504 at an output of the error correction circuit 502. In the present embodiment, the corrected signal 510 is obtained by subtracting the error correction signal d e [n] is generated from the input signal d[n].

[0062] The DRE circuit 504 comprises the amplifier circuit 102, the processing circuit 104, which includes the DAC 202, and the attenuation circuit 106. The amplifier circuit 102 is configured to apply the corrected signal 510 to the dynamic digital gain g. d [n] to amplify. The amplifier circuit 102 receives the corrected signal 510 from the error correction circuit 502.

[0063] The processing circuit 104 is configured to receive the corrected signal 510 from the amplifier circuit 102 and to process the corrected signal 510. In this particular embodiment, the DAC 202 is configured to receive the corrected signal 510 from the amplifier circuit 102, and the processing of the corrected signal 510 includes converting the corrected signal 510 from digital to analog using the DAC 202. The attenuating circuit 106 is configured to receive the corrected signal 510 from the processing circuit 104 and to apply the dynamic analog gain g to the corrected signal 510. d[n] to attenuate and provide the corrected signal 510 as an output of the attenuation circuit 106. In this particular embodiment, the attenuation circuit 106 is configured to receive the corrected signal 510 from the DAC 202. The DRE output signal a[n] corresponds to the corrected signal 510 output by the attenuation circuit 106.

[0064] Device 600 also shows a model for the signal path, which can be represented mathematically and with reference to the corresponding transfer functions, as shown in equation (2). The DRE output signal a[n] is as follows: a[n]=(((d[n]−de[n])⋅gd[n])*h[n])⋅ga[n]

[0065] It is possible to derive an error correction signal d from equation (2). e [n] to derive the error that is generated during the gain change. The error correction signal d e[n] can then be referenced as a digital signal to the input of the signal path to compensate for the error that occurred during the gain change. In device 600, the error correction signal d represents e [n] the time-varying error sequence related to the input. Subtracting the error correction signal d e [n] at the input of the signal path can reduce the error from the DRE output signal a[n] and can essentially eliminate it. In this particular embodiment, the error correction signal d e [n] is subtracted from the input signal d[n] using the summing circuit 602. The corrected signal 510, which is output by the summing circuit 602, therefore corresponds to the input signal d[n] minus the error correction signal d. e [n].

[0066] An ideal DRE output signal a[n] is given by equation (3): a[n]=d[n]*h[n]

[0067] The ideal DRE output signal a[n] is the DRE output signal a[n] if no gain change occurs.

[0068] The error correction signal d e [n] can be derived by combining equations (2) and (3) and is given by equation (4): de[n]=d[n]−((d[n]*h[n])ga[n]*h−1[n])1gd[n]

[0069] Therefore, by providing an error correction signal d e [n] to the error correction circuit 502, as derived using equation (4), it is possible to reduce the error resulting from a change in gain in the signal path, and it is possible to reduce the error in the DRE output signal a[n].

[0070] It will be acknowledged that the processing circuit 104 of the embodiments described in this disclosure may alternatively comprise a circuit component, element, or device other than the DAC 202, which possesses an impulse response h[n], according to the understanding of qualified persons. For example, the processing circuit 104 may comprise an analog-to-digital converter (ADC).

[0071] Fig. Figure 6(b) shows a device 604 according to a sixth embodiment of this disclosure. The device 604 comprises the device 600 and a sigma-delta modulator 606. The sigma-delta modulator 606 comprises a loop filter 608 and a quantizer 610. Common components between different figures are represented by common reference numerals and common variables. The sigma-delta modulator 606 is configured to reduce the resolution of the input signal d[n] before the input signal d[n] is received by the processing circuit 104.

[0072] The loop filter 608 includes a first input corresponding to the signal path input 108. The first input of the loop filter 608 is configured to receive the input signal d[n]. The loop filter 608 includes an output coupled to the quantizer 610. The quantizer 610 has an output coupled to the processing circuit 104 and a second input of the loop filter 608. The output of the quantizer 610 is coupled to the processing circuit 104 via the error correction circuit 502 and the amplifier circuit 102.

[0073] The quantizer 610 is configured to reduce the resolution of the input signal d[n] before the input signal d[n] is received by the processing circuit 104.

[0074] During operation, the quantizer 610 receives the input signal d[n] after it has been filtered by the loop filter 608, and converts the input signal d[n] from a medium to high resolution digital signal to a low resolution digital signal.

[0075] Reducing the resolution of the input signal d[n] allows the DAC 202 to process the corrected signal 510 more easily. However, reducing the resolution of the input signal d[n] results in the generation of an error known as quantization noise.

[0076] The loop filter 608 operates on the difference between the signals received at its inputs, namely the input signal d[n] received at the first input, and the low-resolution digital signal output by the quantizer 610. The low-resolution digital signal output by the quantizer 610 corresponds to the input signal d[n] after passing through the loop filter 608 and the quantizer 610.

[0077] The loop filter 608 operates on the difference between the input signal d[n] and the low-resolution digital signal in such a way that the quantization noise is shaped outside the band by the quantizer 610 according to normal sigma-delta modulator operating principles, as will be clear to experts.

[0078] The spectral manipulation of quantization noise by the 608 loop filter using this technique is often referred to as "noise shaping." Low-frequency quantization noise is essentially removed, as desired, and higher-frequency quantization noise can be easily filtered out. The noise-shaping characteristics of sigma-delta modulators mean they are particularly useful in low-bandwidth applications such as audio.

[0079] Fig. Figure 6(c) shows a device 612 according to a seventh embodiment of this disclosure. The device 612 comprises the device 604, wherein a particular implementation of the loop filter 608 is shown. Common components between different figures are represented by common reference numerals and common variables.

[0080] The loop filter 608 includes a summing circuit 614 configured to subtract the output of the quantizer 608 (the low-resolution digital signal) from the input signal d[n]. The loop filter 608 further includes an integrator circuit 616 configured to operate on the difference between the input signal d[n] and the low-resolution digital signal such that the quantization noise from the quantizer 608 is shaped outside the band, as previously discussed.

[0081] It will be acknowledged that, according to the understanding of qualified persons, further implementations of loop filters 608 for sigma-delta modulators are available, which include, but are not limited to, multiple feedforward paths, multiple feedback paths, multiple integrators and multiple modulators (such as MASH structures).

[0082] Fig. Figure 7(a) shows a device 700 according to an eighth embodiment of this embodiment. The device 700 corresponds to the device 500, but with specific implementations of the error correction circuit 502 and the DRE circuit 504. The specific implementations use components common to the DRE system 100 and the DRE circuit 200. Common components between different figures are represented by common reference numerals and common variables.

[0083] The device 700 comprises a sigma-delta modulator 702. The sigma-delta modulator 702 includes the error correction circuit 502. The sigma-delta modulator 702 is configured to reduce the resolution of the corrected signal 510 before the corrected signal 510 is received by the processing circuit 104.

[0084] In this particular embodiment, the error correction circuit 502 comprises a loop filter 704, a summing circuit 706, and the summing circuit 602. The loop filter 704 includes a first input corresponding to the signal path input 108. The first input of the loop filter 704 is configured to receive the input signal d[n]. The summing circuit 706 includes a first input for receiving the error correction signal d e [n] and an output that is coupled to a second input of the loop filter 704.

[0085] In this particular embodiment, the summing circuit 706 is configured to take the signal received from a quantizer 708 and use it as the error correction signal d. e [n] to add and provide the resulting signal to the second input of the loop filter 704. Alternatively, in another embodiment, the summing circuit 706 can be configured to provide the error correction signal d e[n] to be subtracted from the signal received by the quantizer 708, according to the understanding of qualified persons.

[0086] The sigma-delta modulator 702 includes the quantizer 708. The loop filter 704 includes an output that is coupled to the quantizer 708. The corrected signal 510 is provided at the output of the loop filter 704.

[0087] The quantizer 708 has one output which is coupled to the processing circuit 104 via the amplifier circuit 102 and the summing circuit 602. The output of the quantizer 608 is coupled to the second input of the summing circuit 706 via the summing circuit 602. The summing circuit 602 subtracts the error correction signal d. e [n] from the signal received from the output of the quantizer 708.

[0088] The quantizer 708 is configured to reduce the resolution of the corrected signal 510 before the corrected signal 510 is received by the processing circuit 104.

[0089] It will be acknowledged that the device 700 is mathematically equivalent to the device 604, since the summing circuit 602 has merely been moved into the feedback loop formed by the quantizer 708 to the second input of the loop filter 704, using the further summing circuit 706, the error correction signal d e [n] to remove from the feedback loop before it is received by the loop filter 704.

[0090] It will be acknowledged that the summing circuits 602, 706 may, according to the understanding of qualified persons, be located in a further part of the device 700.

[0091] As previously described for device 600, it is possible to provide an error correction signal d e [n] for the error correction circuit 502 of the device, as derived using equation (4), it is possible to reduce the error resulting from a change in gain in the signal path, and it is therefore possible to reduce the error in the DRE output signal a[n].

[0092] Fig. Figure 7(b) shows a device 710 according to a ninth embodiment of this disclosure. Device 710 corresponds to device 700, except that the error correction expression as part of the feedforward path of the sigma-delta modulator 200 has been removed, as can be seen from the removal of the summing circuit 602. Common elements between different figures are represented by common reference numerals and common variables.

[0093] For a D / A signal path that includes a sigma-delta modulator, the input signal d[n] can be a high-speed, low-resolution digital signal. In this case, subtracting an error correction signal d e [n] with high resolution of the signal output by the quantizer 610, 708, as shown e.g. in devices 600, 700, may be difficult and may result in further errors in the signal path.

[0094] To solve this problem, the summing circuit 602 was removed, such that the subtraction of the error correction signal d e[n] is removed from the feedforward path of 700. Removing the summing circuit 602 introduces an additional error with respect to the other devices; however, this additional error will be "shaped" by the sigma-delta modulator 702, and its feedback loop includes the loop filter 704 as part of the noise-shaping process, as previously discussed.

[0095] For typical sigma-delta modulator designs, the additional error resulting from the removal of the summing circuit 602 will be negligible compared to the quantization noise introduced by the quantizer 708.

[0096] During operation, the quantizer 708 receives the corrected signal 510 and converts it from a medium- to high-resolution digital signal to a low-resolution digital signal. Reducing the resolution of the corrected signal 510 makes it easier for the DAC 202 to process. However, this reduction in resolution introduces an error known as quantization noise.

[0097] Fig. Figure 8 shows a device 800 according to a tenth embodiment of this disclosure. The device 800 corresponds to the device 500, but with specific implementations of the error correction circuit 502 and the DRE circuit 504. The specific implementations use features common to the DRE system 100, the DRE circuit 200, the device 600, and the device 710. Common components between different figures are represented by common reference numerals and common variables.

[0098] The device 800 includes the sigma-delta modulator 702. The sigma-delta modulator 702 includes the error correction circuit 502. The sigma-delta modulator 702 is configured to reduce the resolution of the corrected signal 510 before the corrected signal 510 is received by the processing circuit 104, as discussed for the quantizer 708 for the device 710.

[0099] The sigma-delta modulator 702 comprises the loop filter 704 and the quantizer 708. The loop filter 704 has a first input for receiving the corrected signal 510 from the summing circuit 602, and an output coupled to the quantizer 708. The quantizer 708 has an output coupled to the processing circuit 104 and a second input of the loop filter 704. The output of the quantizer 708 is coupled to the processing circuit 104 via the amplifier circuit 102.

[0100] For the purpose of deriving the error correction signals d e [n] the transfer function of the sigma-delta modulator, specifically the signal transfer function (STF), is preferably taken into account in the impulse response h[n] in equation (4).

[0101] Fig. Figure 9 shows a device 900 according to an eleventh embodiment of this disclosure. The device 900 corresponds to the device 500, but with specific implementations of the error correction circuit 502 and the DRE circuit 504. The specific implementations use components common to the DRE system 100, the DRE circuit 200, the device 600, and the device 710. Common components between different figures are represented by common reference numerals and common variables.

[0102] In this particular embodiment, the loop filter 704 is coupled to the quantizer 708 via the amplifier circuit 102. The output of the quantizer 708 is coupled to the second input of the loop filter 704 via an amplifier circuit 902. The amplifier circuit 902 can provide a gain of 1 / g. d [n] exhibit, where g d [n] is the amplification of amplifier circuit 102.

[0103] Fig. Figure 10 shows a device 1000 according to a twelfth embodiment of this disclosure. The device 1000 corresponds to the device 500, but with certain implementations of the error correction circuit 502 and the DRE circuit 504. The certain implementations use components common to the DRE system 100, the DRE circuit 200, the device 600, the device 710, and the device 900. Common components between different figures are represented by common reference numerals and common variables.

[0104] In this particular embodiment, the loop filter 704 is coupled to the quantizer 708 via the amplifier circuit 102. The output of the quantizer 708 is coupled to the second input of the loop filter via the amplifier circuit 902.

[0105] The DAC 202 can operate as a filter exhibiting an infinite impulse response (IIR) or a finite impulse response (FIR). An IIR means that the impulse response h[n] does not decay to zero after a sufficiently long period, whereas an FIR means that the impulse response h[n] decays to zero after a sufficiently long period. The DAC 202 can exhibit an IIR response or an FIR response when modeled in discrete time, or an IIR response when modeled in continuous time. This disclosure can be applied to a DAC 202 exhibiting either an IIR response or an FIR response. It will be acknowledged that this disclosure can be applied to any suitable circuit component, circuit element, or circuit device that can be modeled as exhibiting an IIR response or an FIR response.

[0106] The appropriate error correction signal d e [n], to reduce the error signal that occurs due to the gain change for a DAC 202 operating as an IIR filter, can be derived as follows.

[0107] An example IIR filter with impulse response h[n] has a transfer function H(z) given by equation (5). In this section, z is the known variable representing the discrete-time frequency domain, and α is a function of the IIR filter pole frequency. Square brackets are used to indicate time indices, and parentheses are used to indicate frequency indices. H(z)=1−α1−αz−1

[0108] Using equation (5) an output y[n] of the IIR filter for an input x[n] can be derived as in equation (6). y[n]=(1−α)×[n]+αy[n−1]

[0109] The inverses of equations (5) and (6) are given by equations (7) and (8), respectively. Equation (8) is used to derive a suitable error correction signal d. e [n] required, as previously described in relation to equation (4). H−1(z)=1−αz−11−α y[n]=11−α×[n]−α1−α×[n−1]

[0110] The reinforcements g d [n], g d [n] are modeled as changing from a first gain G1 to a second gain G2 when the time index n is zero, and with inverted magnitude step sizes relative to each other, as shown by equations (9) and (10). gd[n]={G1,n<0G2,n≥0 ga[n]={1G1,n<01G2,n≥0

[0111] The dynamic digital amplification g d [n] is equal to the first gain G1 when the time index n is less than zero, and the dynamic digital gain g d[n] is equal to the second digital gain G2 when the time index n is greater than or equal to zero. The dynamic analog gain g d [n] is equal to one above the first gain G1 when the time index n is less than zero, and the dynamic analog gain g d [n] is equal to one above the second digital gain G2 when the time index n is greater than or equal to zero.

[0112] With regard to equation (4), if the time index n is less than zero (n < 0), the gains g d [n], g d [n] both equal to one, since the first gain G1 equals one. The gains g d [n], g d [n] are modeled as being equal to one since the beginning of time. For time index n less than zero, the input signal d[n] is simply replaced by both the impulse response h[n] and its inverse h. -i [n] is routed and the error correction signal d e [n] is equal to zero.

[0113] Regarding equation (4), when the time index n is much larger than zero (n >> 0), the gain change has settled into a state such that d e [n] is also equal to zero.

[0114] Regarding equation (4), when the time index n is equal to zero (n = 0), the error correction signal d e [n] given by equation (11) as follows: de[0]=−(1−G1G2)α1−α(d*h)[−1]

[0115] The inverse h -1 [n] of the impulse response in this example is a first-order difference, which means that only the expressions at n = -1 and n = -2 of (d * h)[n], g d [n] and g d [n] contribute to equation (11). Therefore, when the time index n = 1, the course of the gain change is no longer significant and d e[1] = 0; this means that for a single-pole IIR response, only a single expression is required to correct for the effects of the gain change: d e [0], as given by equation (11).

[0116] Providing the error correction signal d e [0], which is given by equation (11), for the error correction circuit 502 of one of the embodiments of this disclosure will substantially cancel the effects of the gain change resulting from DRE, provided that the impulse response h[n] of the DAC 202 and the gain changes are consistent with those used for the IIR filter analysis presented using equations (5)-(11).

[0117] Provided the DAC IIR coefficients are optimized as discussed above, no digital multiplier is required. Therefore, a reduction in power requirements and costs compared to state-of-the-art circuits is possible.

[0118] The analysis above for an IIR filter was performed for the impulse response h[n], where h[n] is a transfer function with a single pole. It will be acknowledged that the analysis can be repeated for any transfer function with any number of poles. The resulting error correction signal d e [n] will have a number of expressions equal to the number of poles in the transfer function.

[0119] Fig. Figure 11 shows simulation results for the DRE circuit 200, where the DAC 202 acts as an IIR filter and no error correction signal d e[n] is applied. The simulations were performed using parameters that are representative for a practical implementation of the DRE circuit 200.

[0120] Fig. Figure 11 shows a curve 1100 of the Fourier transform of the output signal a[n] and a curve 1102 of the Fourier transform of the signal received by the amplifier circuit 102 at the DAC 202.

[0121] Curve 1102 shows a 6 dB step applied to the input signal d[n] by amplifier circuit 102. The flat section of the output signal a[n] 1100 at low frequencies is due to the error resulting from the change in gain.

[0122] Fig. Figure 12 shows simulation results for the device 600, where the DAC 202 operates as an IIR filter and the error correction signal d e[n] is applied. The simulations were performed using parameters representative of a practical implementation of the device 600. The error correction signal d e [n] corresponds to the error correction signal d e [0], which can be derived using equation (11).

[0123] Fig. Figure 12 shows a curve 1200 of the Fourier transform of the output signal a[n] and a curve 1202 of the Fourier transform of the corrected signal 510, which is received by the amplifier circuit 102 at the DAC 202.

[0124] The flat section of the corrected signal 510 received by the DAC 202 is due to the fact that the error correction signal d e[n] with the same magnitude and opposite sign compared to the error that arises due to the gain change of the DRE circuit 504 has been added to the input signal d[n]. Therefore, the output signal a[n] is essentially free of errors that arise due to the gain change associated with the DRE circuit 504.

[0125] The appropriate error correction signal d e [n], to reduce the error that arises due to the gain change for a DAC 202 operating as an FIR filter, is given by equation (12). de[n]=−(1−1G1ga[n−1]∑i=n−M+1n−1d[i]+1G1ga[n−1]d[n−M])−1G((d[n]*h[n])ga[n]×h−1[n−M]), where G is an amplification, i is an integer, and M is an integer. The derivation of equation (12) will be clear to qualified persons.

[0126] Fig. Figure 13 shows a device 1300 according to a thirteenth embodiment of the disclosure. The device 1300 corresponds to the device 600 with an arbitrary delay 1302 (represented by Δ) that can be introduced into the corrected signal 510 during processing by the processing circuit 104. The delay 1302 can be constant over the frequency and is characteristic of most practical implementations of a DRE circuit.

[0127] In the present embodiment, the delay 1302 can be changed by modifying the impulse response h[n], which is used to calculate the error correction signal d e[n] to determine in order to account for the delay 1302, are compensated. Therefore, the corrected signal 510 takes into account both the error due to the gain change and the error that arises due to the delay 1302. It will be recognized that, according to the understanding of qualified persons, one or both of these errors can be compensated using the present embodiment.

[0128] Fig.Figure 14 shows a device 1400 according to a fourteenth embodiment of the disclosure. The device 1400 corresponds to the device 500, but with certain implementations of the error correction circuit 502 and the DRE circuit 504. Common components between different figures are represented by common reference numerals and common variables. In the device 1400, the DRE circuit 504 comprises the error correction circuit 502. The input signal d[n] is adjusted by the error correction circuit 502 based on an error correction factor before being output by the damping circuit 106 as the DRE output signal a[n].

[0129] In this particular embodiment, the damping circuit 106 comprises the error correction circuit 502. The error correction circuit 502 is configured to adjust the damping performed by the damping circuit 106 based on the error correction factor, wherein the error correction factor is a transfer function h. a [n] includes.

[0130] The damping effect of the damping circuit is dependent on the dynamic analog gain g. d [n] dependent. In this particular embodiment, the error correction factor is representative of the error generated by the DRE circuit 504, and in particular the error resulting from the delay 1302.

[0131] The error correction circuit 502 applies the error correction factor to the input signal d[n] by applying the transfer function h a [n] on the dynamic analog gain g d[n] applies and thereby adjusts the gain applied to the input signal d[n] received by the amplification circuit 106.

[0132] In fact, the error correction circuit 502 and the error correction factor include the transfer function h a [n] a delay (which matches the delay 1302) for dynamic analog gain g d [n] adds, thereby compensating for the delay of 1302.

[0133] In this embodiment, the error correction circuit 502 can be implemented using an analog or digital circuit arrangement. The delay 1302 does not introduce any additional error when the gain is changed, and the delay provided by the transfer function h a [n] is provided, can be made any size within the limitations of the device 1400.

[0134] It can be observed that the error also occurs in the device 1400 using the summing circuit 602 and the error correction signal d e [n] is compensated. It will be acknowledged that one or both of these error correction techniques can be applied in a single embodiment. Additionally, the method for correcting the error due to delay 1302, as understood by qualified persons, can be applied to one of the embodiments presented here.

[0135] In general, the procedure of applying the error correction signal d e [n] to the feedback loop of the sigma-delta modulator (e.g., the sigma-delta modulator 702 of device 710) according to the understanding of qualified persons for A / D or D / A signal paths. For example, the processing circuit 104 for an A / D signal path may include an ADC.

[0136] When a DRE is used, the input signal d[n] can be sufficiently small such that adding the error correction signal d e [n] to the feedback loop of the sigma-delta modulator (e.g. the sigma-delta modulator 702 of the device 710) does not endanger the stability of the device.

[0137] The embodiments described here can improve the dynamic range performance of a DRE circuit without the usual power penalty for lower thermal noise. Device 600, described for the fifth embodiment, can be used in all high-resolution signal paths employing a DRE circuit. Devices incorporating a sigma-delta modulator can be used in all signal paths incorporating both a sigma-delta modulator and a DRE circuit.

[0138] The embodiments disclosed herein can, according to the understanding of qualified persons, be generalized for use in both audio input and audio output signal paths.

[0139] The embodiments of the present disclosure can only be applied in the digital domain, in particular when DRE is applied to a D / A signal path. With a digital implementation, the circuit can be tested, verified in production testing, and easily transferred to different technologies.

[0140] The embodiments of the present disclosure do not rely on an analog / digital feedback loop for correction. Using a feedforward method instead of a feedback method, there are no concerns regarding the stability of large analog / digital feedback loops. Additionally, the addition of the error correction signal d does not compromise the stability of the system. e[n] to a sigma-delta modulator loop does not provide stability.

[0141] Various improvements and changes can be made to the above description without altering the scope of the disclosure.

Claims

[1] Dynamic Range Extender (DRE) device (500) receiving an input signal (d[n]) and providing a DRE output signal (a[n]) comprising: an error correction circuit (502) that is configured to have an error correction factor (d e [n]) to apply to the input signal (d[n]) such that the DRE output signal (a[n]) provided by the device (500) is differentiated from the input signal (d[n]) and the error correction factor (d e [n]) depends; where the error correction factor (d e [n]) represents a fault produced by the device (500). [2] Device according to claim 1, comprising the following: a DRE circuit (504); wherein the error correction circuit (502) is configured to receive the input signal (d[n]) and generate a corrected signal (510) based on the input signal (d[n]) and the error correction factor (d e[n]) to provide; and the DRE circuit (504) is configured to receive the corrected signal (510) and to provide the DRE output signal (a[n]) based on the received corrected signal (510). [3] Device according to claim 2, wherein the DRE circuit (504) comprises: an amplifier circuit (102) configured to amplify the corrected signal (510); a processing circuit (104) configured to receive the corrected signal (510) from the amplifier circuit (102) and to process the corrected signal (510); and an attenuation circuit (106) configured to receive the corrected signal (510) from the processing circuit (104), to attenuate the corrected signal (510) and to provide the corrected signal (510) as an output signal of the attenuation circuit (106); wherein the DRE output signal (a[n]) corresponds to the corrected signal (510) output by the damping circuit (106). [4] Device according to claim 3, wherein the processing circuit (104) comprises: a digital / analog converter (202), DAC, configured to receive the corrected signal (510) from the amplifier circuit (102), wherein processing the corrected signal (510) includes converting the corrected signal (510) from digital to analog using the DAC (202). [5] Device according to claim 3 or 4, wherein the error correction circuit (502) comprises a summing circuit (602) configured to correct the signal (510) by adding or subtracting the error correction factor (d). e [n]) to generate to or from the input signal (d[n]), wherein the corrected signal (510) is provided at an output of the error correction circuit (502). [6] Device according to any one of claims 3 to 5, comprising a sigma-delta modulator (702) comprising the error correction circuit (502), wherein the sigma-delta modulator (702) is configured to reduce the resolution of the corrected signal (510) before the corrected signal (510) is received by the processing circuit (104). [7] Device according to claim 6, wherein the sigma-delta modulator (702) comprises: a loop filter (704); and a quantizer (708) configured to reduce the resolution of the corrected signal (510) before the corrected signal (510) is received by the processing circuit (104); wherein the loop filter (704) includes a first input for receiving the corrected signal (510) and an output that is coupled to the quantizer (708) and The quantizer (708) has an output that is coupled to the processing circuit (104) and a second input of the loop filter (704). [8] Device according to claim 7, wherein the output of the quantizer (708) is coupled to the processing circuit (104) via the amplifier circuit (102). [9] Device according to claim 7, wherein the loop filter (704) is coupled to the quantizer (708) by means of the amplifier circuit (102) and the output of the quantizer (708) is coupled to the second input of the loop filter (704) by means of a second amplifier circuit (902). [10] Device according to claim 3 or 4, comprising a sigma-delta modulator (702) comprising the error correction circuit (502), wherein the sigma-delta modulator (702) is configured to reduce the resolution of the corrected signal (510) before the corrected signal (510) is received by the processing circuit (104). [11] Device according to claim 10, wherein the error correction circuit (502) comprises: a loop filter (704) comprising a first input for receiving the input signal (d[n]); and a summing circuit (602) which has a first input for receiving the error correction factor (d e [n]) and an output coupled to the second input of the loop filter (704); and The sigma-delta modulator (702) comprises the following: a quantizer (708); wherein the loop filter (704) includes an output coupled to the quantizer (708), the corrected signal (510) being provided at the output of the loop filter (704); and The quantizer (708) has an output that is coupled to the processing circuit (104) and a second input of the summing circuit (602). [12] Device according to claim 11, wherein the output of the quantizer (708) is coupled to the processing circuit (104) by means of the amplifier circuit (102). [13] Device according to claim 11, wherein the loop filter (704) is coupled to the quantizer (708) by means of the amplifier circuit (104) and the output of the quantizer (708) is coupled to the second input of the loop filter (704) by means of a second amplifier circuit (902). [14] Device according to claim 1, wherein the device (500) comprises a DRE circuit (504) comprising the following: the error correction circuit (502); an amplifier circuit (102) configured to amplify the input signal (d[n]); a processing circuit (104) configured to receive the input signal (d[n]) from the amplifier circuit (102) and to process the input signal (d[n]); and a damping circuit (106) configured to receive the input signal (d[n]) from the processing circuit (104), to attenuate the input signal (d[n]) and to provide the input signal (d[n]) as an output signal of the damping circuit (106); wherein the DRE output signal (a[n]) corresponds to the input signal (d[n]) output by the attenuating circuit (106); and the input signal (d[n]) is corrected by the error correction circuit (502) based on the error correction factor (d e [n]) is adjusted before it is output as the DRE output signal (a[n]) by the damping circuit (106). [15] Device according to claim 14, wherein the damping circuit (106) includes the error correction circuit (502) and the error correction circuit (502) is configured, the damping applied by the damping circuit (106) is based on the error correction factor (de [n]) to adapt. [16] Device according to any one of claims 1 to 15, wherein the error produced by the device (500) results from a change in gain and / or a delay (1302). [17] Device according to any one of claims 1 to 16, wherein the error correction circuit (502) is configured to adjust the error correction factor (d e [n]) to receive. [18] Device according to any one of claims 1 to 17, comprising a storage element (503) configured to store the error correction factor (d e [n]) to store and to store the error correction factor (d) in the error correction circuit (502). e [n]) to provide. [19] Device according to any one of claims 1 to 18, wherein the error correction factor (d e [n]) is derived by calculating the error produced by the device (500). [20] Device according to any one of claims 1 to 19, comprising an error correction factor generator (506) configured, to detect the fault produced by the device (500); the error correction factor (d e [n]) using the detected error and the error correction factor (d e [n]) to provide an error correction circuit (502). [21] Dynamic Range Extension Method, DRE, using a device (500) comprising an error correction circuit (502), wherein the method comprises the following steps: Receiving an input signal (d[n]) at the device (500); Applying an error correction factor (d e [n]) to the input signal (d[n]) using the error correction circuit (502) and Providing a DRE output signal (a[n]); wherein the DRE output signal (a[n]) provided by the device (500) from the input signal (d[n]) and the error correction factor (d e [n]) depends and the error correction factor (d e [n]) represents a fault produced by the device (500).

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