Battery charger with constant current control loop

Abstract

Battery charger that features: a constant current control loop configured to control a charging current provided for charging a battery; a digital voltage limiter configured to detect and digitize a battery voltage to drive a digital control device; and the digital control device configured to calculate a dynamic control signal for controlling the constant current control loop, wherein the battery charger is configured to use only the constant current control loop for an entire charging cycle without requiring a constant voltage control loop, and wherein the constant current control loop is configured to control the charging current both before and after reaching a desired peak charging voltage.

Description

Background area

[0001] The present disclosure relates generally to battery chargers and, more particularly, to battery chargers having a constant current control loop. background

[0002] Conventional battery chargers use a charging profile with a “constant current - constant voltage (CC-CV)” control loop, as described in Fig. 1, with the structure of Fig. 2. It should be noted that a smaller battery pack has disadvantages, including unexpectedly increasing charging time and a noise-sensitive transition from CC to CV.

[0003] Fig. 1, Fig. 100, shows when the voltage of a battery pack V BAT 115 below a threshold voltage V CV to enter CV of CC, the charger regulates the charging current I CHG 120. During a CC charge, an equivalent capacity C BATcharged in the battery cell 125 and I CHG increased V BAT at a constant rate. If V BAT below the threshold voltage V CC is to enter CC from a summons, I CHG a charging rate of 0.1C. For V BAT about V CC (and under V CV ) has I CHG a charging rate of 1C. The value C varies according to the battery capacity and is defined by the equation C [A] = (battery capacity) [Ah] / 1 [h]. Pre-charging, a part of CC charging, occurs when the battery requires a lower charging current and V BAT < V CC in 110.

[0004] After V BAT V CV reached, V BAT on V CV regulated. During CV loading, I CHG due to the equivalent series resistance R ESR in the battery cell 125 and the equivalent capacity C BAT decreases exponentially. After I CHGis reduced to its target, the charging cycle is terminated.

[0005] Fig. 2, Fig. Figure 200 shows a CC-CV charger. The charger has CC and CV control circuits, and each circuit operates independently of the other. The CC control circuit controls the gate voltage V G of the power device gate (M MAIN) to I CHG to be controlled by monitoring the mirrored current of I CHG , using the charging current detector provided by the detecting device (M SENSE ) flows. The circuit is activated when the V detected by the voltage detector BAT under V CV The voltage detector measures V BAT .

[0006] If V BAT V CV approaches, the CV control circuit is activated to control via V G and the CC control circuit is deactivated. During CV loading, V G controlled to find suitable I CHGto the battery to bridge the gap between V CV and V BAT to reduce. As a result, V BAT Independent of the CC and CV charging, V G (and indirectly I CHG ) as a controlled input for the feedback system.

[0007] The Fig. 3A (3 ohms) and 3B (6 ohms) are graphical representations showing how a larger R ESR the CV range and the resulting charging time increases when the V BAT -Voltage (315, 335) around R ESR × I CHG (320, 340). It should be noted that in case of a longer loading time R ESR 330 of a smaller battery is greater than R ESR 310 a larger battery, and that an older battery R ESR also increased. V CELL (325, 345) represents the voltage of the battery cell across R ESR .

[0008] In the case of the transition from CC to CV, a smaller battery requires a smaller current than a larger battery. This leads to a higher difficulty to enter CV from CC. The difficulty of the circuit in Fig. 2 results from the control of V G for both CC and CV charging and from an architecture where the CC and CV circuits operate independently, which is evident during the CC to CV transition.

[0009] The Fig. 4A, Fig. 4B and Fig. 4C are a circuit diagram and voltage / current diagrams showing a discontinuity in the battery charging current during the transition from CC to CV charging in 420 due to the use of independent CC 425 and CV 430 control circuits in 410. The CV control circuit may detect an overcurrent 455 (I CHG > 1C) as shown in 440, where I CHGexceeds the CC charging current 1C at the beginning of a CV charge. During the period when I CHG > 1C, the battery will be overcharged (ie V CELL exceeds V CV ) and can be damaged.

[0010] Fig. 5, Fig. 500, shows another charging profile that uses the CC-CV structure of Fig. 2. Here, the transition state called PRE-CV relaxes the transition from CC to CV from Fig. 4B, because the transition point is moved to a lower charging current point than the 1C value. PRE-CV is a part of CC, where the charger digitally changes the CC setting to a lower value before entering CV, reducing the risk of overcharging (> 1C) at the transition point between CC and CV. The battery pack voltage is V BAT 515, the threshold voltage to enter CV of CC is V CV and the charging current I CHG is 520.

[0011] The Fig. 7A and Fig. 7B are current / voltage diagrams during a CC derate, where the battery charger digitally changes the CC setting to less than the charge termination current, introducing a further drawback. The CC derate 715 requires ΔT to be the same charge amount 730 as a normal CV setting 725 for a region A, at 710. Accordingly, the CV state is still required to ensure the increasing charge time of the CV region, especially if the system requires a smaller termination current 720 (<0.1C), at 740.

[0012] In the Fig. 7A and Fig. 7B is the loaded amount for the CV setting: ∫ICHG(t)dt=−τ⋅VBATRESR[e−tτ]T0T1

[0013] And the loaded amount for a PRE-CV setting is: ∫ICHG(T1)dt=−[VBATRESRe−T1τ⋅t]T0T2 where (1)=(2) (3) and T0=k0τ,T1=k1τ,τ=RESR⋅CBAT.

[0014] Inserting (4) into (3) ΔT=τ{ek1−k0−(1+k1−k0)} where a larger k value means deep loading.

[0015] For example, at time 1:

[0016] C BAT = 6kF, RESR = 0.1 Ohm and PRE-CV charging is from 1.00 A to 0.90 A: ΔT=τ{ek1−k0−(1+k1−k0)}=1.73[s]

[0017] For example, at time 2:

[0018] C BAT = 6 kF, RESR = 0.1 Ohm and PRE-CV charging is from 0.10 A to 0.05 A: ΔT=τ{ek1−k0−(1+k1−k0)}=92.06[s] Summary

[0019] Accordingly, it is an object of one or more embodiments of the present disclosure to provide a battery charger with a constant current control loop and no constant voltage control loop for use in linear and switching chargers.

[0020] It is a further object of one or more embodiments of the disclosure to include digital controls and a comparator in a battery charger to reduce a charging current toward the end.

[0021] Furthermore, it is an object of one or more embodiments of the disclosure to eliminate a constant voltage loop and an amplifier in a battery charger without increasing the charging time.

[0022] Furthermore, it is an object of one or more embodiments of the disclosure to simplify porting of a battery charger design to other process technology nodes and to reduce a size of the charging circuit.

[0023] Other tasks will be apparent below.

[0024] The above and other objects of the present disclosure can be achieved in the following manner. A battery charger is disclosed that includes a constant current control loop configured to provide a charging current to a battery, a digital voltage limiter configured to sense a battery voltage, and dynamic controls configured to calculate a dynamic control signal for controlling the charging current.

[0025] The above and other objects of the present disclosure can be further achieved with a method for constant current control in a battery charger. The steps include providing a battery charger with a constant current (CC) control loop. The steps also include sensing a battery voltage and digitizing the battery voltage. The steps also include calculating a dynamic control signal for controlling a charging current.

[0026] In various embodiments, the function can be used for short circuit detection, pre-charge voltage detection or recharge or re-charge voltage detection.

[0027] In various embodiments, a fixed control voltage is configured with a programmable digitized gain.

[0028] In various embodiments, a buck switching converter may be configured with a dynamic control voltage from the digital voltage limiter. Short description of the drawings

[0029] The present disclosure will become more fully understood from the following description taken in conjunction with the accompanying drawings, in which like reference numerals designate similar or corresponding elements, portions, and sections, and in which: Fig. 1 shows, when the voltage of a battery pack is below a threshold voltage to enter a constant voltage (CV) from a constant current (CC), the charger regulates the charging current. Fig. Figure 2 shows a CC-CV battery charger in which the charger has CC and CV control circuits that operate separately. Fig. 3A (3 ohms) and 3B (6 ohms) are graphs showing that a larger equivalent series resistance of a battery increases the CV range and resulting charge time as the battery voltage shifts. The Fig. 4A, Fig. 4B and Fig. 4C is a circuit diagram and voltage / current graphs showing a discontinuity in battery charging current when transitioning from CC to CV charging due to the use of independent CC and CV control circuits. Fig. Figure 5 shows another charging profile showing the CC-CV structure of Fig. 2 used. Fig. 6 includes voltage / current curves showing the present disclosure without a constant voltage (CV) control loop and a battery charging profile. The Fig. 7A and Fig. 7B are current / voltage diagrams showing that during CC derating, the battery charger digitally changes the CC setting to be less than the charge termination current, introducing another disadvantage. The Fig. 8A, Fig. 8B and Fig. 8C are circuit diagrams and a voltage / current diagram showing the proposed digital voltage limiter (DVL) of the disclosure, which replaces the prior art constant voltage (CV) control loop. The Fig. 9A and Fig. 9B show an accelerated settle down (ASD) technique to achieve the constant current control loop for the charger. The Fig. 10A and Fig. 10B include voltage curves showing how the digitized step down of the charging current in the Fig. 6 and Fig. 9 overloading is taken into account. Fig. Figure 11 shows how the switching charger may require both a buck converter and an analog-to-digital control (ADC) in the prior art. Fig. Figure 12 shows how the proposed architecture of the disclosure requires only a buck converter and no ADC in a switching charger. Fig. 13 includes the circuit of the proposed digital voltage limiter (DVL) in a battery charger of the present disclosure. The Fig. 14A and Fig. 14B include voltage / circuit curves showing how the accelerated settling charging time is calculated. Fig. 15 shows a test bench circuit that includes both the CC-CV control logic of the prior art and the CC-DVL control logic of the present disclosure. The Fig. 16A and Fig. 16B shows waveform results for the CC-CV control logic versus the CC-CC settling down logic and the CC-CV control logic versus the CC-ASD (Accelerated Settle Down) logic. The Fig. 17A and Fig. 17B show simulation results for the prior art architecture compared to that of the present disclosure when the equivalent series resistance varies. Fig. Figure 18 shows how the circuit area used for a small size solution provided by the present disclosure compares to the area used for the circuit layout for a similar battery charger according to the prior art. Fig. 19 is a flowchart of a method for constant current control in a battery charger. Detailed description

[0030] The present disclosure proposes a novel battery charger architecture that provides a constant current (CC) control loop for use in linear chargers and switch-mode battery chargers. Advantages include the use of digital controls and a comparator to reduce a charging current toward the end. The technique of the disclosure eliminates a constant voltage loop and an amplifier without increasing charging time.

[0031] The CC control loop of the present disclosure achieves a faster, more consistent charging time than conventional CC-CV chargers. Removing the constant voltage (CV) control loop reduces circuit area and simplifies design time. Furthermore, the sensitivity to changes in external parameters (R ESR , C BAT etc.) and disadvantages of the conventional CC-CV charging structure are addressed.

[0032] Fig. 6, Fig. 600 includes voltage / current curves showing how the present disclosure operates without a constant voltage (CV) control loop, and a battery charging profile. Here, (PRE-CV + CV) is replaced by a constant current (CC) control loop step-down, where the charger digitally changes the CC setting to be less than the charge termination current. The battery pack voltage is V BAT615, the transition for the voltage setting is CC-down and the charging current I CHG is 620. The battery state changes from a pre-charge to a CC phase, then to CC-CC derate and to stop charging when the charging current increases to 1C and then below its setpoint 0.1C.

[0033] The present disclosure uses two techniques to achieve the constant current control loop of the battery charger, one in the Fig. 8A, Fig. 8B and Fig. 8C and a digital voltage limiter in the Fig. 9A and Fig. The “accelerated settling” procedure shown in Figure 9B.

[0034] Fig. Figure 8B shows the digital voltage limiter (DVL) 820 of the disclosure, which includes the constant voltage (CV) control loop 810, as Fig. 8A, according to the prior art. Fig. Figure 8C includes voltage and current curves for the disclosed battery charger. D CCis the dynamic digital control for the constant current (CC) in 830, from which the value of I CHG 860. As a result of DVL loading, I CHG changed dynamically, which differs from the state-of-the-art CV logic. D CV is a digital signal used to control a feedback gain setting and is a fixed value. D CV detects a peak voltage, e.g. 4.2 V, and when the peak voltage is detected by DVL, D CC changes to change the charging current. If the system D CV in the CC area, this has the effect that V BAT 840 acts as a voltage monitor. For the specific D CV The comparator outputs a high or low signal. By sampling D CV is the voltage V BAT visible. After scanning D CV from the lower voltage reached D CV 4.2 V. For setting DCV = 4.2 V, the sequence described above is performed. The comparator used is a standard comparator.

[0035] The digital control circuit calculates D CC according to V BAT in the DVL area. D CV is a digital control signal for a specific feedback gain, and {V BAT} × {feedback gain (D CV )} = {the reference voltage} can be input into the DVL comparator. The detected V BAT is digitized by DVL and also input into the comparator. The comparator in Fig. 8B provides 1-bit output data and for a specific value of D CV There is a 1-bit comparator output. By using a D CV - value is specified that changes the comparator output from Low to High, the digitized version of V BAT The comparator output DVL OUTis fed to the dynamic controls for gate control of the power and mirror devices in Fig. 13. This then determines the required D CC from D CV to track the CC-DVL charging profile.

[0036] Similar to a Zener diode voltage clamp, the digital voltage limiter is set to a fixed V SAT The DVL does not require loop stability or a special topology for its comparator. Any topology is allowed as long as the input offset is small, which can be managed, for example, by trimming or an auto-zero function.

[0037] The Fig. 9A and Fig. 9B show an accelerated settle down (ASD) technique for achieving the constant current control loop for the charger. The ASD 910 is used during a DVL calculation of the D CC -charging in 950 and has a faster charging time, which is comparable to the current I CHG960, as a constant voltage control loop according to the prior art. By periodically increasing and decreasing the charging current, as in the Fig. 9A and Fig. 9B, the average charging current is greater than the current flowing through the Fig. 7A, resulting in a shorter charging time. The variable alpha controls the average charging current, and a higher alpha is always preferred. For a shorter charging time, a smaller delta T is needed. Therefore, by having delta T' < delta T, the present disclosure can achieve a shorter charging time. It should be noted that V CELL the voltage across the battery cell in Fig. 13 is.

[0038] The Fig. 10A and Fig. 10B include voltage curves showing how the digitized reduction of the charging current I CHG (620, 960) in the Fig. 6 and Fig. 9B takes overloading into account. For example, the calculation of I CHG 1030, in 1020, for V CELL 1025 > 4.20 V + 0.5% in 1010. The system continues charging if the digital control is too slow to complete charging, e.g. when R ESR ≈ 0. TOVER=4.221V−4.200V500uVs=42[s]

[0039] T OVER is an overcharge time that is allowed before charging is stopped to avoid damage to the battery. Equation (6) is T OVER according to the state of the art.

[0040] For example, if 10 steps are controlled by a 1 ms clock, the time is still less than T OVER . 10 steps × 1 ms = 10 [ms] < <TOVER=42[s]

[0041] In equation (7), 10 ms is arbitrarily chosen. For the present disclosure, any number of steps and clock frequency can be chosen, as long as (steps) * (1 / (clock frequency)) < 42 [s]. Importantly, there is much better control over the selected number of steps and clock frequency than in the prior art, resulting in a simpler design.

[0042] The digital voltage limiter and accelerated settling techniques used in the constant current control of the battery charger of the disclosure solve the disadvantages of the prior art CC derating and CV control loop. Additional advantages include an alternative to comparators for monitoring V BAT threshold. For example, a system-level charger IC must BATMonitor for functions involving threshold voltages. In the prior art, a comparator is required for each threshold voltage. In the present disclosure, digital voltage limiter logic replaces the comparators required for the above functions. These functions include short-circuit detection, precharge voltage detection, and recharge voltage detection.

[0043] The battery charger of the disclosure, with only a constant current (CC) control loop and the digital voltage limiter (DVL) and accelerated settle down (ASD) logic, has improved system-level robustness against variations in equivalent series resistance (ESR). This is advantageous when the ESR of a large- or small-capacity battery or an aged battery tends to be higher. In the conventional architecture, the stability of the constant voltage (CV) control loop feedback depends on the ESR value, and significant design effort is required to make the design insensitive to ESR variations. Since the proposed architecture has no voltage feedback control, there are fewer stability problems caused by ESR variations. The system can be robust against changes in ESR due to battery aging and can extend battery life.

[0044] Background calibration of the CC control loop with DVL and ASD can be used to mitigate charging current errors and errors caused by ESR fluctuations. Using the disclosed function makes current control more accurate and precise, preventing overcurrent that can damage the battery.

[0045] The present disclosure offers a versatile V BAT Monitoring through the DVL logic and can be used elsewhere as a way to monitor battery health, such as a fuel gauge. In addition, the charging profile can be adjusted with a programmable digital gain control and a charging profile configured based on the system status, such as V BATor battery temperature. For example, if a soft start is required, the charging current can be gradually increased over time. The same function can be realized in a conventional architecture, however, the flexibility is very limited due to the nature of the analog circuit. In the proposed architecture, the required change is only in the digital gain control, where less effort is required.

[0046] Fig. 11, Fig. 1100, shows how the battery charger incorporates both a step-down converter and analog-to-digital control (ADC) logic to monitor V BAT may require, in the state of the art.

[0047] Fig. 12, Fig. 1200, shows how the proposed architecture of the disclosure requires only a buck converter and no ADC in the battery charger. Here, D controls CV dynamically the V BATThe voltage in the DVL logic and the required comparators are replaced by digital voltage limiter logic for all required functions. This results in a simpler design with minimal area increase.

[0048] Fig. 13, Fig. 1300, comprises the circuitry of the proposed digital voltage limiter (DVL) in a battery charger of the present disclosure. For constant current (CC) charging, the sensing device loop consists of a charging current control device 1310 to always maintain I CHG In the proposed architecture, I CHG controlled by a control loop, in contrast to the conventional architecture of Fig. 2, where two control loops exist, ie both CC and CV controls. As a result, the possibility of an I CHG -Discontinuity between CC and CV loading is eliminated. And during loading, CC setting D CCaccording to the battery voltage V BAT updated, which is captured and digitized by the DVL logic in 1320, of the present disclosure.

[0049] During CC loading, I CHG constant, for example at a charging rate of 0.1 C for pre-charging or a charging rate of 1 C for fast charging: ICHG(t)=KDcc(n) where K is the constant value for calculating the charging current from the digital code and D CC (n) is the to-register mapping value.

[0050] During a DVL load, once the DVL logic reaches the limit of V BAT recorded, the DVL system counts OUT (= 1'b1), to N DET to reach. (∫DVL OUT = N DET ), where 1'b1 and 1'b0 are logical 1 and logical 0 binary numbers respectively and N DET the total number of DVL out occurring in a specific time period is “1”.

[0051] The charging current from (8) becomes (9) in the next step: ICHG(t1)=KDCC(n−1)

[0052] If DVL OUT 1'b1, the charging current can go to the next step to (10): ICHG(t2)=KDCC(n−2)

[0053] If DVL OUT 1'b0, it returns to (9) and sets ∫DVL OUT The logic must therefore wait until ∫VL OUT = N DET is again (10). If the charging current I CHG is reduced below the termination current rate (e.g. 0.1 C), charging is terminated.

[0054] The Fig. 14A and Fig. 14B include voltage / circuit curves showing how the charging time of the accelerated settling by I CHG ' 1460 is calculated in 1450. W L0 is fixed to 1 and N DET changes W HI . It should be noted that N DET = 1 α = 0.5 in the Fig. 14A and Fig. 14B, where the ASD duty cycle α = W HI / (W HI + W LO), whereby a higher alpha is always preferred. The "accelerated settling" logic uses pulse control via D CC to I CHG ' and: ICHG(n−1) <ICHG'<ICHG(n)

[0055] This means that the system is on R ESR × I CHG (n-1) = V BAT with a store from I CHG '[> I CHG (n-1)) so that it has the recovery time (T β - T1). The recovery time can then ensure the increase in charging time, and ultimately, it can be faster than a CV settling time for a deeper charging request.

[0056] According to (4), a CV charging according to the state of the art is given by: ΔTCV=T1−T0=τ(k1−k0)

[0057] The loading time of the accelerated settling of the revelation is determined by I CHG ' calculated: ICHG'=α⋅{ICHG(n)−ICHG(n−1)}+ICHG(n−1) (0<α<1) ΔTAC=T1−T0=CBATICHG'dV=τ⋅ek1−k0−1α⋅ek1−k0+1−α ΔTACΔTCV=1(k1−k0)⋅ek1−k0−1α⋅ek1−k0+1−α (k1−k0>0)

[0058] The initial state of the equilibrium is not so different (1420 in 1410): ΔTACΔTCV≈1α⋅(k1−k0)+1≈1 (0 <k1−k0<<1)

[0059] The deeper settling state is reduced by about 33% (1430 to 1410), comparing delta Tac for the disclosure with delta Tcv of the CV approach according to the prior art: ΔTACΔTCV≈0.67 (k1−k0=1,α=0.9)

[0060] For example: C BAT = 210F, R ESR = 3 Ohm, CV charging is from 10mA to 5mA: ΔTCV=T1−T0=τ(k1−k0)=436.7[s]=0.5: ΔTAC=T1−T0=CBATICHG'dV=420.0[s]<ΔTCV=0.9: ΔTAC=T1−T0=CBATICHG'dV=331.6[s]<ΔTCV

[0061] Fig. 15, Fig. 1500, shows a test bench circuit that includes both the CC-CV control logic 1520 of the prior art and the CC-DVL control logic 1510 of the present disclosure. The test bench circuits of Fig. 15 are used to display the waveform results of the Fig. 16A and Fig. 16B and the simulation results of the Fig. 17A and Fig. 17B for the voltage of the battery pack V BAT , the voltage of the battery cell V CELL about R ESR and the charging current I CHG to generate.

[0062] The Fig. 16A and Fig. 16B show waveform results for the CC-CV control logic compared to a CC-CC decrement logic according to the prior art, at 1610, and the CC-CV control logic compared to the CC "accelerated settling (ASD)" logic of the disclosure, at 1650. Signals 1615, 1625, and 1635 represent CC-CV signals V BAT , V CELL or I CHG, and signals 1620, 1630 and 1640 represent CC-CC down signals V SAT , V CELL or I CHG , in 1610. Signals 1655, 1665 and 1675 represent CC-CV signals V BAT , V CELL or I CHG , and signals 1660, 1670 and 1680 represent CC-ASD signals V BAT , V CELL or I CHG , in 1650.

[0063] The Fig. 17A and Fig. 17B shows simulation results for the prior art CC-CV logic architecture compared to that of the present disclosure's CC-DVL logic when the equivalent series resistance varies from 3 ohms in 1710 to 6 ohms in 1750. When the ESR is 3 ohms, the charge time for the disclosed constant current digital voltage limiter (CC-DVL) logic is 283 seconds shorter than the constant current constant voltage (CC-CV) logic. When the ESR is 6 ohms, the charge time for the disclosed CC-DVL logic is 564 seconds shorter than the CC-CV logic.

[0064] Fig. 18, Fig. 1800, shows how the circuit area used for the small-size solution provided by the present disclosure compares to the area used for the circuit layout for a similar prior art battery charger. The disclosed battery charger of 1810 achieves a 38% smaller solution than the prior art battery charger of 1850. In this example, where the two projects are comparable with approximately the same target specification for the battery charger, the disclosed battery charger uses an area of ​​1.0 mm 2 , whereas the state-of-the-art charger is 1.61 mm 2 used.

[0065] Fig. 19, Fig.1900 is a flowchart of a method for constant current control in a battery charger. The steps include 1910, providing a battery charger with a constant current (CC) control loop. The steps also include 1920, sensing a battery voltage and digitizing the battery voltage. The steps also include 1930, calculating a dynamic control signal for controlling a charging current.

[0066] The primary advantage of one or more embodiments of the present disclosure includes replacing comparator logic with digital voltage limiter logic, resulting in a simpler design with minimal area increase. Furthermore, the disclosed battery charger has improved system-level robustness to variations in equivalent series resistance. Using the disclosed functionality makes current control more accurate and precise to prevent overcurrent that can damage the battery. The charging profile can also be customized using programmable digital gain control and a charging profile configured based on system status, such as battery voltage or temperature.

[0067] While particular embodiments of the present disclosure have been shown and described, it will be apparent to those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.

[0068] The claimed invention is:

Claims

[1] Battery charger comprising: a constant current control loop configured to control a charging current provided for charging a battery; a digital voltage limiter configured to detect and digitize a battery voltage to drive a digital control device; and the digital control device configured to calculate a dynamic control signal for controlling the constant current control loop, wherein the battery charger is configured to use only the constant current control loop for an entire charging cycle without requiring a constant voltage control loop, and wherein the constant current control loop is configured to control the charging current both before and after reaching a desired peak charging voltage. [2] The battery charger according to claim 1, wherein the battery charger is configured to use accelerated setting after a constant current charging period is completed, with a duty cycle of α = W HI / (W HI + W LO ), where W LO is set to 1 and W HI is variable. [3] The battery charger according to claim 1 or 2, further comprising a power device and a mirror device controlled by a common gate voltage. [4] The battery charger of claim 3, wherein the constant current control loop is configured to provide the common gate voltage. [5] The battery charger of claim 1, wherein the digital voltage limiter comprises a comparator configured to compare the digitized battery voltage with a reference voltage. [6] The battery charger according to claim 5, wherein the digital controller is configured to receive an output of the comparator. [7] The battery charger according to any one of claims 1 to 6, wherein the digital control device is configured to provide a fixed control voltage for the digital voltage limiter. [8] The battery charger according to any one of claims 1 to 7, wherein the constant current control loop is configured to receive the dynamic control signal. [9] The battery charger according to any one of claims 1 to 8, wherein the constant current control loop is configured to set the charging current to a constant value during pre-charging or fast charging. [10] The battery charger according to any one of claims 1 to 9, wherein the constant current control loop is configured to reduce the charging current below a termination current. [11] The battery charger according to any one of claims 1 to 10, configured to monitor the battery voltage for short circuit detection, pre-charge voltage detection or recharge voltage detection. [12] The battery charger of claim 7, wherein the fixed control voltage is configured for a programmable digitized gain of the reference voltage. [13] The battery charger according to any one of claims 1 to 12, further comprising a step-down switching converter configured to provide the charging current and controlled by the digital controller. [14] A method for constant current control in a battery charger comprising the following steps: Providing a constant current (CC) control loop; Detecting a battery voltage and digitizing the battery voltage to drive a digital control device; and Calculating a dynamic control signal to control the constant current control loop, wherein the battery charger uses only the constant current control loop for an entire charging cycle without the need for a constant voltage control loop, and wherein the constant current control loop controls the charging current both before and after reaching a desired peak charging voltage. [15] The method of claim 14, wherein the constant current control loop reduces a charging current below a termination current. [16] The method according to claim 14 or 15, wherein the battery charger uses accelerated setting after a constant current charging period is completed, with a duty cycle of α = W HI / (W HI + W LO ), where W LO is set to 1 and W HI is variable. [17] The method according to any one of claims 14 to 16, wherein a common gate voltage controls a power device and a mirror device. [18] The method of claim 17, wherein the constant current control loop provides the common gate voltage. [19] The method of claim 14, wherein a comparator of the digital voltage limiter compares the digitized battery voltage with a reference voltage. [20] The method of claim 19, wherein a digital controller receives an output of the comparator. [21] The method of claim 20, wherein a digital controller provides a fixed control voltage for the digital voltage limiter. [22] The method according to any one of claims 14 to 21, wherein the constant current control loop receives the dynamic control signal. [23] The method according to any one of claims 14 to 22, wherein the constant current control loop sets the charging current to a constant value during pre-charging or fast charging. [24] The method according to any one of claims 14 to 23, wherein the constant current control loop reduces the charging current below a termination current at an end of a charging cycle. [25] The method of claim 21, wherein the fixed control voltage provides a programmable digitized gain of the reference voltage. [26] The method according to any one of claims 14 to 25, further comprising a buck switching converter that provides generation of the charging current and that is controlled by the digital controller.

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