Digital / analog circuit with reduced power consumption

Abstract

A method for converting a digital signal into an analog signal, the method comprising: Providing a digital-to-analog converter (340, 430) including an array of digital-to-analog elements (431, 432, 510) configured to operate over a plurality of time steps, each digital-to-analog element being configured to convert a digital value to an analog value in each time step; Generating a plurality of control sequences for controlling the arrangement of digital / analog elements based on the digital signal, and after identifying that the digital signal is below a threshold, shortening the control sequences; and for each time step: identifying a first set of elements and a second set of elements among the array of digital / analog elements; Applying the shortened control sequences to the first set; Deactivating the second set; and Shift the first set and the second set by one element.

Description

Technical area

[0001] The present disclosure relates to a digital-to-analog circuit. In particular, the present disclosure relates to a digital-to-analog circuit capable of operating in a low-power mode. background

[0002] Audio devices require high dynamic range combined with low harmonic distortion. These requirements often result in devices with relatively high power consumption. Audio output architectures can be implemented in several ways. A common approach is based on modulating a digital input signal with a digital pulse-width modulator to drive a series of DACs.

[0003] Most DAC topologies consist of multiple DAC elements that are either identical to each other or scaled versions of each other. The outputs of these DAC elements are summed to produce an analog output based on a digital input code. For an A-weighted dynamic range (DR) of 112 dB or greater, a DAC composed of current elements (IDAC) or resistive elements (RDAC) is often preferred over a DAC composed of switched-capacitor elements. This is due to the area penalty of precise capacitors and the need for an external storage capacitor for switched-capacitor DACs. However, current and resistive DACs introduce a small error into their output whenever their input code changes, which can degrade DAC linearity.This can occur when the change in the input code is signal-dependent, as is the case, for example, in systems that use data-weighted averaging (DWA) to reduce the effects of DAC element mismatch. For current and resistance DACs, pulse-width modulation (PWM) of the input signal is a common technique for achieving high linearity. Although the PWM DAC technique provides an analog output that varies linearly with the digital input signal, its minimum power consumption is still determined by the desired dynamic range. DAC power consumption also increases with increasing dynamic range. For example, to increase the dynamic range by 3 dB, the DAC power must be at least doubled. It is an object of the disclosure to address one or more of the above limitations.

[0004] US 2018 / 0 175 879 A1 describes in Fig. 1 illustrates a finite impulse response digital-to-analog converter having a plurality of DAC elements 106AN. The outputs of the DAC elements 106AN are summed at a summing node 110. The summing node 110 outputs a value to an output node 108, which is an analog signal representative of the digital input signal at the input node 102. The output node 108 may be coupled to other components, such as a headphone amplifier for driving the analog signal to a pair of headphones. The plurality of DAC elements 106AN receive a data element 114AN from the data frame 104, which turns each of the DAC elements 106AN on or off. The amplitude of the output signal at output node 108 increases when DAC elements 106 are turned ON and decreases when DAC elements 106 are turned OFF.When a low amplitude signal is present, such as low volume sections of music files, some of the DAC elements 106 AN are turned off to reduce power consumption. Summary

[0005] According to a first aspect of the disclosure, a method for converting a digital signal into an analog signal is provided, the method comprising: providing a digital-to-analog converter comprising an array of digital-to-analog elements operable over a plurality of time steps, each digital-to-analog element configured to convert a digital value into an analog value in each time step; generating a plurality of drive sequences for driving the array of digital-to-analog elements based on the digital signal, and upon identifying that the digital signal is below a threshold, shortening the drive sequences; and for each time step: identifying a first set of elements and a second set of elements among the array of digital-to-analog elements; applying the shortened drive sequences to the first set; deactivating the second set;and shifting the first set and the second set by one element.;

[0006] Optionally, the shortened control sequences can be concatenated. For example, a first shortened control sequence can be applied to a first subset of elements within the first set, and a second shortened control sequence can be applied to a second subset of elements within the first set, with the first subset and the second subset being arranged side by side.

[0007] Optionally, the method comprises the steps of: sampling the digital signal to obtain a series of digital samples; and modulating each digital sample to generate the plurality of drive sequences.

[0008] Optionally, deactivating the second set includes turning off the digital / analog elements of the second set.

[0009] Optionally, the digital-to-analog elements are selectively connected to an output of the converter; the method comprising: identifying a third set of elements and separating the third set from the output; and for each time step: shifting the third set by one element.

[0010] Optionally, the third quantity is switched off.

[0011] Optionally, the method comprises switching on the third set at a predetermined time before the third set is reconnected to the output.

[0012] Optionally, the method comprises applying a sequence of predefined values ​​to a predetermined set of elements for a predefined number of time steps. For example, the predefined values ​​may be hard-coded zero values. Alternatively, or in combination, the sequence of predefined values ​​may have an average of zero over time. The predefined number of time steps may be defined by an element at which the first set should begin.

[0013] Optionally, the elements in the first set, the second set, or the third set are provided in a sequential order.

[0014] Optionally, the digital-to-analog converter is a differential digital-to-analog converter and the arrangement of digital-to-analog elements comprises a first group of digital-to-analog elements and a second group of digital-to-analog elements coupled to a summing stage.

[0015] Optionally, the first group is configured to receive a plurality of first control sequences and the second group is configured to receive a plurality of second control sequences, wherein the plurality of second control sequences are identical to the plurality of first control sequences except for the opposite sign.

[0016] Optionally, the plurality of first drive sequences and the plurality of second drive sequences form a plurality of differential drive sequences, each differential drive sequence comprising a set of values, each value being either a plus-one state, a zero state, or a minus-one state; wherein shortening the drive sequences comprises identifying a shortening portion of the sequence consisting of at least one zero state.

[0017] Optionally, the first set of elements includes an opening element with a predefined position within the array. For example, in a normal operating mode, the opening element may be the first element in the array of elements. In a low-power operating mode, the opening element may be a function of the length of the shortening section.

[0018] Optionally, the method comprises: upon identifying that the digital signal has risen above a normal mode threshold, activating previously deactivated elements; setting the predefined position of the opening element as the first element in the array of digital / analog elements; and terminating the shortening of the drive sequences.

[0019] Optionally, the method includes applying a sequence of predefined values ​​to predefined elements.

[0020] Optionally, the digital / analog elements are one-bit elements.

[0021] Optionally, the digital / analog elements include current digital / analog converter elements.

[0022] According to a second aspect of the disclosure, a digital-to-analog circuit is provided, comprising: a driver configured to receive a digital input and provide a plurality of drive sequences; a digital-to-analog converter comprising an array of digital-to-analog elements operable over a plurality of time steps, each digital-to-analog element configured to convert a digital value to an analog value at each time step; and a controller coupled to the driver and the digital-to-analog converter; wherein, upon identifying that the digital signal is below a threshold, the controller is configured to: shorten the drive sequences; and for each time step: identify a first set of elements and a second set of elements among the array of digital-to-analog elements; apply the shortened drive sequences to the first set;Deactivating the second set; and shifting the first set and the second set by one element.;

[0023] Optionally, the digital-to-analog converter is a differential digital-to-analog converter comprising a first group of 1-bit elements and a second group of 1-bit elements coupled to a summing stage.

[0024] Optionally, the driver comprises a first pulse width modulator configured to provide a plurality of first drive sequences and a second pulse width modulator configured to provide a plurality of second drive sequences.

[0025] Optionally, each digital / analog element is coupled to an output of the converter via a disconnect switch.

[0026] Optionally, the controller includes a plurality of memory devices coupled to one or more multiplexers, each memory device associated with a corresponding digital / analog element.

[0027] Optionally, the circuit includes a sampler for sampling the digital signal. For example, the sampler can be a sigma-delta modulator.

[0028] The digital / analog circuit according to the second aspect of the disclosure may include any of the features described above with respect to the first aspect of the disclosure.

[0029] According to a third aspect of the disclosure, an audio device is provided comprising a digital / analog circuit according to the second aspect of the disclosure.

[0030] The third aspect of the disclosure may have features in common with the first and second aspects mentioned above and herein. Description

[0031] The disclosure is described in more detail below by way of example and with reference to the accompanying drawings, in which: Fig. 1 is a block diagram of a conventional audio output amplifier circuit; Fig. 2 a flowchart of the method for converting a digital signal into an analog signal; Fig. 3 a diagram of a circuit for implementing the method of Fig. 2; Fig. 4 an exemplary embodiment of the circuit of Fig. 3; Fig. 5 a diagram of a differential current mode DAC for use with the circuit of Fig. 4; Fig. 6 a table showing the operation of the differential DAC of Fig. 5 represents; Fig. 7 is a table showing signals received by 16 DAC elements as a function of time in a normal operating mode; Fig. Figure 8 is a table illustrating signals received by 16 DAC elements as a function of time in a low-power mode; Fig. 9a and Fig. 9b Tables showing the dynamic control of DAC elements when operating in a low-power mode according to the method of Fig. 2 are operated; Fig. 10a and Fig. 10b Tables showing the dynamic control of DAC elements to enter a low-power mode from a normal operating mode; Fig. 11a, Fig. 11b and Fig. 11c Tables showing the dynamic control of DAC elements to exit the low-power mode; Fig. Figure 12a is a diagram showing the operation of a single DAC element in normal power mode; Fig. Figure 12b is a diagram showing the operation of a single DAC element in low power mode; Fig. 13 a simulation of a current mode DAC with and without the method according to Fig. 2 is operated; Fig. 14 an exemplary embodiment of a control system for use in the circuit of Fig. 3, Fig. 4 or Fig. 5; and Fig. 15 an audio device that uses the DAC circuit of Fig. 3 includes.

[0032] Fig. Figure 1 shows a conventional PWM DAC architecture for audio output amplifiers. The system 100 includes a sigma-delta modulator 110, a digital pulse width modulator (DPWM) 120, a DAC 130, and an amplifier 140. The DAC 130 consists of a set of 1-bit DAC units, also known as finite impulse response (FIR) filters. In this example, the DAC 130 has four FIR filters. The sigma-delta modulator 110, the digital pulse width modulator (DPWM) 120, the DAC 130, and the amplifier 140 are connected in series.

[0033] In operation, the sigma-delta modulator 110 converts an M-bit digital input signal into a lower resolution K-bit digital output signal (K <M) und höherer Frequenz F s,ΣΔM The average of the K-bit output signal reflects the input signal. The DPWM modulator 120 converts the output of the sigma-delta modulator 110 into a 1-bit sequence with a higher clock frequency equal to N*F s,ΣΔM The DAC 130 then converts the DPWM output into an analog signal. Each DAC element in the DAC 130 is an analog FIR filter tap, whose output is summed with all other DAC element outputs and fed to the amplifier 140. The analog signal provided by the amplifier 140 is proportional to the digital input signal and can be used to drive a load.

[0034] The DPWM 120 provides a signal with a constant switching frequency. This eliminates the signal's dependence on switching errors. Furthermore, each DAC element receives the same input signal over time and therefore contributes equally to the output, eliminating mismatch effects. Finally, each DAC element is periodically switched, thus shaping its low-frequency noise. This approach requires a DPWM and a fast clock with a fixed multiple of the ΣΔM rate, increasing the device's size and power consumption. Additionally, the DPWM introduces nonlinearity, specifically an even-order nonlinearity, which downconverts ΣΔ noise in the band.

[0035] Fig. Figure 2 is a flow diagram of a method for converting a digital signal to an analog signal. In step 210, the digital signal is sampled to obtain a series of digital samples. In step 220, each digital sample is modulated to generate a plurality of drive sequences. In step 230, a digital-to-analog converter is provided. The digital-to-analog converter includes an array of digital-to-analog elements operable over multiple time steps, each digital-to-analog element configured to convert a digital value to an analog value in each time step. A time step may be defined by a clock cycle.

[0036] In step 240, after identifying that the digital signal is below a threshold, a series of steps is performed, including: shortening the drive sequences; and for each time step: identifying a first set of elements and a second set of elements among the array of digital / analog elements; applying the shortened drive sequences to the first set; disabling the second set; and shifting the first set and the second set by one element. Disabling the second set may include turning off the elements of the second set.

[0037] Fig. 3 shows a digital / analog circuit for implementing the method of Fig. 2. The digital-to-analog circuit 300 includes a driver 320 coupled to a DAC converter 340. A controller 350 is coupled to both the driver 320 and the DAC 340. The driver 320 has an input for receiving a digital input and an output for providing control sequences to the controller 350. The controller 350 has an input for receiving the control sequences and one or more outputs for applying the control sequences to the DAC 340.

[0038] In addition, the controller 350 has an input for receiving the digital input and one or more outputs for providing a plurality of control signals to operate the DAC in a specific operating mode. The controller 350 may also include an output for sending a control signal Sc1 to the driver 320. For example, Sc1 could be used to put the driver 320 into a low-power mode based on the level of the digital input signal. The controller 350 may include a sensor for detecting an amplitude of the digital input signal. The digital-to-analog converter 340 includes a plurality of DAC elements (not shown) for converting the drive sequences into an analog value. The controller 350 may provide a plurality of control signals to control which DAC element should receive which digital input signal at what time. A drive sequence is formed by a plurality of binary digits.The controller is configured to send the binary digits in the sequence to operate a predetermined DAC element at a predetermined time. The controller may be configured to operate the DAC either in a normal mode of operation when the digital input signal is above a predetermined threshold or in a low-power mode of operation when the digital input signal is below the threshold. The controller 350 is configured to dynamically identify different sets of DAC elements within the DAC 340. For example, the controller may be configured to identify a first set of elements for receiving the drive sequences and a second set of elements that are not needed and can be temporarily disabled. For example, the second set may be turned off and / or disconnected from the DAC output.

[0039] A set of DAC elements consists of several consecutive DAC elements. Each set is dynamic, meaning it can shift through the entire series of DAC elements. For example, at a time t1, the set may contain 10 DAC elements, including DAC 20 through DAC 29, and at a later time, the set of DAC elements may contain 10 DAC elements, including DAC 21 through DAC 30.

[0040] If the digital input signal falls below a threshold, the controller 350 shortens the drive sequences. The controller 350 then applies the plurality of drive sequences to the first set and turns off the second set. This can be achieved using the control signal Sc2. The control signal Sc2 can include multiple clock signals to control which DAC element receives which digital input at what time. The controller 350 is configured to shift the first set and the second set by one DAC element over time, for example, every clock cycle. The circuit of Fig. 3 reduces DAC power consumption while maintaining or improving dynamic range.

[0041] Fig. 4 is an exemplary embodiment of the circuit of Fig. 3. The circuit 400 includes a sigma-delta modulator 410, a driver 420, a differential DAC 430, an amplifier 440, and a controller 450. The driver 420 includes a first DPWM 421, a second DPWM 422, and an inverter 423 connected to the input of the second DPWM 422. The differential DAC 430 has two groups or arrays of 1-bit DACs, referred to as DAC elements. The DAC elements of the first group or array 431 are referred to as PDACs, and the DAC elements of the second group or array 432 are referred to as NDACs. The first DAC group 431 and the second DAC group 432 are connected to a summing stage 433 for summing the output of the first and second groups of DACs. In this example, each group 431, 432 comprises four 1-bit DACs, optionally coupled to an output. However, it should be understood that the number of 1-bit DAC elements can vary depending on the application.The controller 450 is coupled to both the driver 420 and the differential DAC 430.

[0042] The sigma-delta modulator 410 has an input for receiving a digital input signal and an output for providing a modulated digital signal to the driver 420.

[0043] The controller 450 has three inputs and multiple outputs. The three inputs include an input for receiving the digital input signal, an input for receiving a drive signal from the DPWM 421, and an input for receiving a drive signal from the DPWM 422. The outputs include one or more outputs for sending control signals Sc1 and Sc2 to the driver 420 and to the DAC 430, and one or more outputs for sending drive sequences to the DAC elements of the array 431 and 432. For example, Sc1 could be used to put the driver into a low-power mode based on the level of the digital input signal. For example, Sc1 can be used to operate the DPWM 421 at a slower clock rate at low signal levels.The controller 450 may be configured to operate the differential DAC 430 in a normal mode when the digital input signal is above a predetermined threshold, or in a low-power mode when the digital signal is below the threshold. It should be understood that the digital signal received at the input of the controller 450 may be the same signal input to the sigma-delta modulator. Alternatively, the signal input to the controller may be the signal output from the sigma-delta modulator.

[0044] The first and second DPWMs 421, 422 each have three inputs and one output for providing a drive signal to the controller 450. The first DPWM provides a drive signal denoted by dpwm_p, and the second DPWM provides a signal denoted by dpwm_n. The three DPWM inputs include a first input for receiving the output of the sigma-delta modulator 410, a second input for receiving a sampling frequency signal, and a third input for receiving the control signal Sc1 from the controller 450.

[0045] Each of the DAC elements forming DAC groups 431 and 432 has three inputs and one output for providing an analog signal. The three DAC element inputs include a first input for receiving the drive sequences from controller 450, a second input for receiving a sampling frequency signal, and a third input for receiving the control signal Sc2 from controller 450.

[0046] The summing stage 433 includes a first adder 434 coupled to the first group of DACs 431, a second adder 435 coupled to the second group of DACs 432, and a third adder 436 for providing an analog signal to the amplifier 440. It should be understood that the summing stage can be implemented in various ways. For example, if the DAC elements in DAC groups 431 and 432 are current-mode DACs, the output nodes of each element can simply be shorted to implement addition. Subtraction can be implemented by shorting the positive output of one element to the negative output of another, and vice versa.

[0047] In operation, the Sigma-Delta Modulator 410 modulates the digital input signal to produce an output signal with a lower resolution and a higher frequency, which is determined by the sampling frequency F s,sdmFor example, the digital input signal may have a frequency of 48 kHz and the sampling frequency F s,sdm can be 3 MHz. In Fig. Figure 4 shows a specific example where the digital input of sigma-delta modulator 410 is a 24-bit digital signal and its output is a 5-bit digital signal with one of 17 available values. The output of sigma-delta modulator 410, S1, is sent to driver 420. An inverter 423 is provided at the input of DPWM 422 so that DPWMs 421 and 422 receive input signals of equal amplitude but opposite signs.

[0048] For each output signal provided by the sigma-delta modulator 410, the DPWMs 421 and 422 generate a sequence of 1-bit digital signals with frequency N*F s,sdm, where N is an integer. If the sigma-delta modulator 410 has an N+1 level output, each sample is represented by a sequence of N bits. Considering an exemplary numerical example, if the signal applied to the sigma-delta modulator F s,sdmapplied sampling frequency is 3 MHz, and when N = 16, the sampling frequency applied to the DPWMs 421 and 422 and the first and second DAC groups 431, 432 is 48 MHz. The 1-bit streams provided by the DPWMs 421 and 422 are transmitted to the controller 450 and used by the controller to output drive sequences to the differential DAC 430 for driving the 1-bit DAC elements PDAC and NDAC of the first and second groups 431 and 432, respectively. The first adder 434 sums the outputs of the PDAC elements, and the second adder 435 sums the outputs of the NDAC elements. The third adder 436 subtracts the output provided by the second adder 435 from the output provided by the first adder 434. The signal provided by the differential DAC 430 is sent to the amplifier 440 to obtain an amplified analog output of the digital input signal.The digital input can be an audio signal, and the amplified analog output can be used to drive a speaker. The positive and negative DACs 431 and 432 can be implemented with various types of DAC elements, including, but not limited to, current elements (IDAC) or resistive elements (RDAC).

[0049] Fig. Figure 5 shows an exemplary embodiment of a differential DAC structure using current mode DACs used in the circuit of Fig. 4 can be used. In this particular example, a differential current mode DAC 64 is shown, which includes finite impulse response FIR taps and a fully scaled current output current I FS For clarity, only three FIR taps 510a, 510b, and 510c are shown.

[0050] Each FIR tap 510 is a 1-bit DAC element comprising an upper circuit section 530 coupled to a lower circuit section 540. The upper circuit section 530 implements a PDAC element, and the lower circuit section 540 implements an NDAC element. The upper and lower circuit sections 530 and 540 implement a differential DAC element.

[0051] Referring to the first FIR tap 510a, the upper circuit section 530 includes a current source 531 coupled to three switches 532, 533, and 534. Similarly, the lower circuit section 540 includes a current source 541 coupled to three switches 542, 543, and 544. The switches 532 and 542 are coupled to the output node A, while the switches 533 and 543 are coupled to the output node B to generate the output current I out,P or I out,NWhen all switches 532, 533, 542, and 543 are open, current sources 531 and 541 are disconnected from output nodes A and B.

[0052] Optionally, an operational amplifier 550 may be provided. In this case, switches 534 and 544 are coupled to the output of operational amplifier 550. Operational amplifier 550 has a negative feedback loop and is designed to provide a low-impedance path for current sources 531 and 541 when switches 534 and 544 are closed and switches 532, 533, 542, 543 are open (current sources switched on but not powered by I out,P and I out,N separated).

[0053] In this example, the current sources for all PDAC-FIR taps and NDAC-FIR taps are identical and provide a fixed current I FS / (2*K), where K is the number of elements. In this example, each current source supplies a current equal to I FS / 128 corresponds.

[0054] Each differential DAC element 510a, 510b, etc., is connected to the controller 590 via several control lines. The controller 590 provides six signals to control the switches of each differential DAC. For the differential DAC 510, the controller provides the pup_p and pup_n signals to control switches 534 and 544; the d_p and d_n signals to control switches 532 and 543; and the db_p and db_n signals to control switches 533 and 542.

[0055] In operation, the signals from the digital pulse width modulators (dpwm_p and dpwm_n) are fed to the controller 590 and used to open / close the switches in PDAC and NDAC to control the current at output nodes A and B. Depending on the selected operating mode, the controller can turn specific DAC elements in the array on or off and / or disconnect certain DAC elements from the output.

[0056] In the differential DAC architecture of Fig. 4 and Fig. 5, the error introduced by the DPWMs 421 and 422, which is common to both, cancels each other out in the summing stage 433. Therefore, this architecture can overcome the problems arising from the even-order nonlinearity in non-differential PWM-DAC architectures such as in Fig. 1, to a large extent.

[0057] Fig. Figure 6 is a table showing the number of DAC elements required to generate various analog signals. In this particular example, the signal driving system 500 comes from a sigma-delta modulator with a 65-level output. The first column of table 600 shows possible outputs of the sigma-delta modulator. The second, third, fourth, and fifth columns indicate the number of PDAC and NDAC elements that provide either a +1 / 128 or -1 / 128 current for respective sigma-delta modulator outputs, ΣΔM outputs. The last column of table 600 shows the number of redundant PDAC / NDAC elements for each ΣΔM output.

[0058] For example, if the average output of the sigma-delta modulator is +1, 64 PDAC elements produce a current of +1 / 128 and 64 NDAC elements produce a current of -1 / 128, so all 128 elements of the differential DAC are used. Conversely, if the average output of the sigma-delta modulator is zero, 32 PDAC elements produce a current of +1 / 128, 32 PDAC elements produce a current of -1 / 128, 32 NDAC elements produce a current of +1 / 128, and 32 NDAC elements produce a current of -1 / 128. In this case, the zero average can be achieved simply by using 32 PDAC elements producing a current of +1 / 128 and 32 NDAC elements producing a current of +1 / 128. Therefore, 32 PDAC elements and 32 NDAC elements are unnecessary. Generally, the number of unnecessary elements increases as the sigma-delta modulator signal decreases.

[0059] With reference to Fig. 5, each input audio sample is modulated by the DPWMs into sequences dpwm_p and dpwm_n and then passed to the controller 590 to generate the signals d_p[i], dB_p[i], d_n[i], and dB_n[i]. These drive sequence signals are sent to the 64 PDAC elements and the 64 NDAC elements to drive their respective switches. Since the dpwm_p and dpwm_n sequences are obtained by modulating signals of equal magnitude but opposite signs, for each ΣΔM output in the table, the number of PDAC cells outputting +Ifs / 128 (-Ifs / 128) is equal to the number of NDAC cells outputting -Ifs / 128 (+Ifs / 128). At low signal levels, most PDAC elements supply the same current as the corresponding NDAC element. When this is the case, there is no signal component at the output of this DAC element, only the noise from both, making these DACs redundant. If the differential DAC of Fig. 5 operates at low signal levels, so only a fraction of the total DAC elements are needed to output the correct signal.

[0060] Unnecessary elements can be disconnected from the output to reduce overall noise when the signal level is low and re-enabled when the signal level is high. Reducing overall noise at low signal levels improves dynamic range. Likewise, overall DAC power can be reduced while maintaining the same dynamic range capability. Furthermore, these unused DAC elements can be dynamically turned off for additional power savings. This is very beneficial in low-signal-level operating modes, since output noise is often specified without any audio input.

[0061] However, enabling and disabling elements can lead to undesirable results. If part of the DAC's element array is simply disconnected, the 1-bit data stream will no longer be passed through all elements, and highly desirable features such as mismatch and 1 / f noise mixing will no longer be achieved. Care must also be taken to ensure that transitions between low- and high-level operating modes are clean and without audible artifacts.

[0062] As mentioned above, the controller is designed to turn the individual DAC elements off / on and disconnect / connect, allowing the DAC to operate either in a normal mode when the digital signal is above a predetermined threshold, or in a low-power mode when the digital value is below the threshold. The dynamic control of the DAC elements in different operating modes will now be described with reference to Fig. 7 to 11.

[0063] Fig. Figure 7 is a table showing the operation of a DAC operating in a normal mode. In this example, a PWM sequence with N=8 is passed to a FIR tap DAC with K=16. This could, for example, be a DAC supplied to the System 500 of Fig. 5, with 16 taps instead of 64. The columns of table 700 represent DAC elements, and the rows represent time indices with increasing time from top to bottom. The values ​​in each cell of table 700 represent the pseudo-differential sequence supplied to the DAC via the controller from the DPWMs. The pseudo-differential sequence can be defined as the difference between the signal dpwm_p generated by the DPWM 421 minus the signal dpwm_n generated by the DPWM 422. In particular, the S0 sequence 710, the S1 sequence 720, and the S2 sequence 730 are each PWM sequences of N = 8 bits that encode consecutive ΣΔM samples. For example, the differential S0 sequence 710 can be S0 1 = 0, S0 2 = 0, S0 3 = -1, S0 4 = 1, S0 5 = 1, S0 6 = -1, S0 7 = 0, S0 8= 0. Sequence S0 is the PWM sequence encoding ΣΔM sample #0. Similarly, sequence S1 encodes ΣΔM sample #1, and so on. At each clock cycle, the output of individual DAC elements is summed, and the 8-bit sequences shift one step down the DAC array, i.e., to the right in this illustration. Since there are 16 cells, there is an initial delay of 16 clock cycles when the PWM signal passes through the array for the very first time (not shown in the table).

[0064] For input signals with sufficiently small magnitudes, some bits at both ends of the 8-bit sequence are zero, and the signal content (+1s or -1s) appears only in a middle part of the sequence. The magnitude threshold depends on both the signal level and the high-frequency gain of the ΣΔM.

[0065] Fig. Figure 8 is a table showing the operation of the same DAC when receiving a low-level input signal. In this case, only the middle M bits of each PWM sequence with N = 8 contain signal information, and the others are zero. In this particular example, M = 4.

[0066] The PWM DAC power can be reduced by disconnecting any unit of the PDAC and NDAC arrays known to contain a zero from the output. These would be the DAC elements corresponding to cells 810 of table 800 that show a zero. In resistance-mode architectures, disconnecting DAC elements results in an immediate reduction in power consumption. In the case of an RDAC, the output current of a DAC cell is generated by connecting a resistor between one of two reference voltages and the output node. Since there is no current source to turn it on or off, an RDAC cell only consumes power when it is supplying power. In current-mode DAC architectures such as the one shown in Fig. 5, enabling and disabling DAC elements can require many clock cycles to be performed with sufficient accuracy. In addition, significant power consumption is associated with charging and discharging the capacitance in each DAC element. Therefore, this procedure would result in significantly less power reduction for IDACs than for RDACs. In the case illustrated above, where 75% of the sequence can be truncated and a quarter of the IDAC element arrays are switched on but disconnected at any time, the theoretical power reduction for RDACs is 93.75%, but for IDACs it is only 75%. A better way to reduce PWM DAC power consumption is described in the Fig. 9a and Fig. 9b.

[0067] Fig. 9a and Fig. 9b show the operation of the circuit of Fig. 5, if the procedure of Fig. 2 is used. Table 900 of Fig. 9a (Table 900a) and Fig. Figure 9b (Table 900b) is analogous to Table 700, but shows the case of a 64-tap DAC (instead of 16) and a 16-bit PWM sequence (instead of 8). Each cell in Table 900 represents the state of a DAC element at a particular time step.

[0068] Within the element array, three sets of elements are identified at different time steps or clock cycles. For example, at clock cycle 0, one set contains elements 0 and 49 through 63; a second set 910 contains elements 17 through 48; and a third set contains elements 1 through 16. Each set then shifts by one element at each clock cycle. Thus, at clock cycle 1, the first set contains elements 0, 1, and 50 through 63; the second set 910 contains elements 18 through 49; and the third set contains elements 2 through 17. In this example, cells 910 represent off-state DAC elements, cells 920 represent disconnected but on-state DAC elements, and the remaining cells represent on-state and connected DAC elements. The number of cells 910 and cells 920 used varies depending on the application. For example, there may be fewer cells in 920 and more cells in 910 if the cells spin up faster.It is also understood that if the method is implemented with RDACs that do not need to be enabled, only a set of 920 separate cells would be used, which are considered disabled. As previously explained, for low-level signals, only the middle bits of each PWM sequence contain information, and therefore it is possible to remove the ends of the sequence without losing any information.

[0069] The PWM sequence can be truncated by truncating the ends of each PWM sequence by a preset number K bits, for example by 6 bits at each end in the example of Fig. 9, are shortened. The shortened sequences are then inserted into the array and concatenated through it. In this way, at each time step, only a predetermined section of the DAC element array is needed to transmit the signal information, and this predetermined section shifts across the array over time. The unused DACs are disconnected, and some can be switched off and on again as needed. To disconnect and switch the DAC cells on and off as needed, a controller such as controller 450 of Fig. 4 is used to send on / off signals to the DACs. For example, in a current mode implementation, as shown in Fig. 5, connect / disconnect the DAC element 510a using the switches 532, 533, 542, 543.

[0070] To maintain continuity with normal PWM DAC operation, new data bits can be inserted into the array in the same clock cycle in which they would normally appear at bit 0. The first DAC cell in the array can be kept free of data. Data can then be inserted into the array at predetermined points. The PWM sequences of Fig. 9 were truncated by 6 bits at the beginning and 6 bits at the end, leaving 4 signal bits. These four bits should be inserted at the same time they would normally appear. The number of insertion points can be determined by the ratio of the total number of DAC elements and the length of the untruncated PWM sequences. For example, the Fig. The DAC 64 / 16 shown in Figure 9 has 4 insertion points labeled 932, 934, 936, and 938, corresponding to the table coordinates (6, 6), (18, 22), (30, 38), and (42, 54), respectively. Therefore, the first insertion point is at the 6th element in the array, the second at the 18th element, the third at the 30th element, and the last at the 42nd element. If the DAC elements require multiple clock cycles to turn on, their turn-on signals may rotate before the PWM samples. For example, in table 900, it is assumed that a DAC element requires 16 PWM clock cycles to fully turn on, therefore each turned-off element (cells 910) turns on for 16 clock cycles before the first signal bit is received. This mode of operation can be configured by the controller 450 of Fig. 4 can be implemented, for example, via a rotating digital buffer with multiple insertion points.

[0071] Fig. 10a and Fig. 10b show a transition from a normal operating mode as shown in Fig. 7, to a low-power mode as shown in Fig. 9. Table 1000 of Fig. 10a (Table 1000a) and 10b (Table 1000b) are analogous to Table 900 and apply to a 64-tap DAC and a 16-bit PWM sequence. Cells 1010 represent switched-off DAC elements, cells 1020 represent disconnected but switched-on DAC elements, and the remaining cells represent switched-on and connected DAC elements. In addition, cells 1030 labeled +0 and cells 1040 labeled -0 indicate DAC elements that are hard-coded with predefined values. The predefined values ​​are added to maintain constant switching activity in the DAC, even if some of the DAC elements are not receiving any signal content. The predefined values ​​can be chosen such that their total contribution to the output is zero. For example, in a current-mode DAC such as that of Fig. 5 may be designed to send control sequences that hard-code cells 1030 with a +0 state and cells 1040 with a -0 state. The +0 state corresponds to a configuration in which switches 532 and 542 are closed, switches 533, 543, 534, 544 are open, and a current I out,P and I out,N of almost zero. The -0 state corresponds to a configuration in which switches 533 and 543 are closed, switches 532, 542, 534, 544 are open, and a current I out,P and I out,N of nearly zero. For both the +0 and -0 states, the output current is ideally zero, but a small amount of current may flow due to a mismatch between current sources 531 and 541 or other higher-order effects.

[0072] When the first sample to be clipped is sent to the DAC, the controller starts filling the unnecessary cells in the array with hard-coded +0 and -0, while the bits of the clipped sequences are inserted at the insertion points 1032, 1034, 1036 and 1038, as for Fig. 9. New hard-coded bits are inserted at the beginning of the array for M*P clock cycles, where M is the number of bits in the truncated sequence and P is the number of insertion points (in this case, 4*4 = 16 cycles). The hard-coded value shifts through the array but does not perform a complete rotation. The first M hard-coded values ​​inserted shift until they reach the first insertion point at DAC element 6, the second M hard-coded values ​​inserted shift until they reach the second insertion point at DAC element 18, and so on. After that, the system begins operating in low-power mode, as shown in Fig. 9 is shown.

[0073] Fig. 11a, Fig. 11b and Fig. 11c are tables showing a transition from a low-power mode to a normal mode. Table 1100 of Fig. 11a (Table 1100a), 11b (Table 1100b), and 11c (Table 1100c) are analogous to Table 1100 and apply to a 64-tap DAC and a 16-bit PWM sequence. Cells 1110 represent off-state DAC elements, cells 1120 represent disconnected but on-state DAC elements, and the remaining cells represent on-state and connected DAC elements. Furthermore, cells 1130 labeled +0 and cells 1140 labeled -0 represent hard-coded +0 and -0 states, respectively. Reference numerals 1161, 1162, 1163, and 1164 represent the insertion points where signal bits are applied to the array during clipping mode.

[0074] During operation, if the controller determines that a transition to normal mode is necessary, it waits until the leftmost insertion point 1161 receives a new truncated sequence. In this example, this occurs at clock 22, when the DAC receives the first bit of the truncated sequence S5. From this moment on, the controller no longer sends turn-off signals to the array of DAC elements. Instead of being turned off, the DAC elements receive a hard-coded value. The following truncated PWM sequence S6 is inserted at the DAC element of index 0 (clock 38, DAC element 0), as in normal mode, instead of being inserted at the second insertion point 1162 (clock 38, DAC element 18), where hard-coded +0 and -0 are inserted in its place.This insertion mode continues until all sequences that did not start at index 0 have completed what is called a full rotation and are removed from the array. A sequence has completed a full rotation when the sequence has been applied to every element in the array. In this example, a full rotation has been completed when the sequence has been applied to each of the 64 DAC elements in the array. After this point, operation with full sequences can begin again and the next PWM sequence, S10, is inserted at index 0 without being truncated (clock 96, DAC element 0). The maximum number of samples required to complete the transition to fully scaled operation depends on the implementation. In the example shown in . Fig. In the case illustrated in Figure 11 with 16-bit PWM sequences and 64 FIR taps, a maximum of seven samples are required. With more FIR taps, the timing at which samples should appear at element 0 may be different, and additional samples may be required before the transition is fully completed. Additionally, one or more additional insertion points may be required to prevent rotated PWM sequences in the array from colliding (for example, rotating one sequence from the last bit while attempting to insert another at bit 0).

[0075] Fig. Figure 12a shows the output of a single DAC element as a function of time when operating in normal mode. Fig. Figure 12b is a diagram showing the operation of a single DAC element operating in low-power mode. Each arrow indicates a switching event of the individual DAC element. When the PWM DAC operates in normal mode ( Fig. 12a), the average number of DAC elements that switch on each cycle is independent of the signal level of the digital input, and therefore the switching of individual DAC elements does not contribute to nonlinear errors. When the PWM DAC operates in low-power mode ( Fig. 12b), each individual DAC element switches two additional times in each cycle compared to the normal operating mode, because it has to be switched on and off, as indicated by the arrows labelled 1210 and 1220 in Fig. 12b. However, the average number of switching events in each cycle is still constant and independent of the signal level. Therefore, the additional switching could contribute to skew and gain errors, but does not affect the linearity of the PWM DAC. In contrast, when transitioning from normal mode to low-power mode, or vice versa, the average number of switching events in each cycle changes. This can lead to a small artifact at the output when entering and exiting low-power mode. However, with proper design, this effect can be made inaudible.

[0076] The with reference to Fig. 9, Fig. 10 and Fig. The method illustrated in Figure 11 allows for reducing power consumption in PWM DACs by dynamically switching cells on and off when redundant bits are present in the PWM sequences. The number of DAC cells that need to be switched on at any given time depends on how quickly they can be switched on. Depending on the number of taps in the FIR filter, this can reduce the power savings when switching off DAC elements. However, the design would still retain the benefits of isolating noise sources from the output.

[0077] Assuming that 50% of the DAC cells in an IDAC can be switched off, as in Fig. 9, Fig. 10 and Fig. As shown in Figure 11, IDACs could achieve a power reduction of 87.5%.

[0078] Fig. 13 is a simulation of a current mode DAC implemented with and without the method according to Fig. 2. The simulated device is a current-mode DAC with 64 FIR taps and identical PDAC and NDAC cells including their random noise values. Fig. Figure 13 shows three amplitude signals 1310, 1320, 1330 in decibels relative to full scale (dBFS) as a function of frequency. Signal 1310 simulates the DPWM output. Signal 1320 simulates the DAC output 1330 when using the method of Fig. 2 is used. The signal 1340 simulates the DAC output when without implementing the method of Fig. 2. The DAC receives a 16-bit PWM sequence for each ΣΔM sample and is processed according to the method of Fig. 2, assuming that 50% of the IDAC cells can be switched off, as in Fig. 9, Fig. 10 and Fig. 11. The large bump at low frequencies is the DC offset (after windowing) caused by element switching errors, both with and without clipping. At a low frequency between approximately 0.6 kHz to approximately 40 kHz, the level of signal 1330 is lower than the level of signal 1340. This indicates that when implementing the method of the disclosure, the noise level in the signal is reduced by approximately 6 dB.

[0079] Fig. 14 is a diagram of an exemplary control system 1400 used in the circuit described above by Fig. 4 and Fig. 5. The control system 1400 includes a DPWM 1410 coupled to a controller 1450 provided with an array 1420 of memory cells and a control unit 1430. The array of memory cells 1420 includes a plurality of series-coupled memory cells 1421(i) and a number of multiplexers 1422 arranged at specific locations in the array.

[0080] The memory cells can be implemented as flip-flops, and the number of memory cells can be chosen to match the number of DAC elements present in the DAC. The number of multiplexers can vary depending on the application. For example, if the DAC includes 64 DAC elements, 64 memory cells with four multiplexers could be used.

[0081] Each memory cell has a data input for receiving a digital value, a clock input coupled to the control unit 1430, and an output coupled to a corresponding DAC element. The data input of the first DAC 1421i in the array 1420 is coupled to the output of the DPWM 1410. The data input of the second memory cell is coupled to the output of the first memory cell, and so on.

[0082] Each multiplexer 1422 has a first input coupled to the DPWM 1410, a second input coupled to the output of a DAC element in the series, a select input for receiving a select signal from the control unit 1430, and an output coupled to the data input of a subsequent memory cell. The control unit 1430 is configured to generate a plurality of clock signals for clocking the memory cells and a plurality of control signals, also referred to as a select signal, for selecting a particular channel of a multiplexer.

[0083] The controller system 1400 can operate the DAC in either a normal mode or a low-power mode. In the normal mode, each DPWM sequence is passed from the DPWM 1410 to the first DAC 1421i and shifts through the array 1420, passing through all memory cells 1421. In the low-power mode, the control unit 1430 determines at which insertion point the DPWM sequence should be inserted and instructs the corresponding multiplexer 1422 to select the DPWM input instead of the output coming from the previous DAC unit. The system 1400 can be used to apply multiple sequences to a given set of DAC elements, as shown in Fig. 9, Fig. 10 and Fig. 11 is described.

[0084] Fig. 15 shows an audio device 1510 comprising a DAC circuit 300 as shown in Fig.3 above. The DAC circuit 300 receives a digital signal and provides an analog signal for driving a loudspeaker 1512.

[0085] In summary, a method and associated system were proposed to achieve power savings in PWM DACs by truncating PWM sequences and maximizing the time available to turn on a DAC cell without compromising sensitivity to element mismatch.

[0086] Those skilled in the art will recognize that variations of the disclosed arrangements are possible without departing from the disclosure. Although the DAC circuit of the disclosure has been described in the context of amplifying an audio signal, it is understood that such a system and method may be used with other types of applications. Accordingly, the above description of the specific embodiment is provided by way of example only and not for purposes of limitation. Those skilled in the art will appreciate that minor modifications may be made without substantial changes to the described operation.

Claims

[1] Method for converting a digital signal into an analog signal, the method comprising: Providing a digital / analog converter (340, 430) containing an arrangement of digital / analog elements (431, 432, 510) configured to operate over multiple time steps, each digital / analog element being designed to convert a digital value into an analog value at each time step; Generating multiple control sequences to control the arrangement of digital / analog elements based on the digital signal, and After identifying that the digital signal is below a threshold, shorten the control sequences; and for each time step: Identifying a first set of elements and a second set of elements under the arrangement of digital / analog elements; Applying the shortened control sequences to the first set; Deactivating the second set; and Shifting the first set and the second set by one element. [2] Method according to claim 1, wherein the shortened control sequences are chained together. [3] The method of claim 1 or 2, comprising: Sampling the digital signal to obtain a series of digital samples; and Modulating each digital sample to generate the multiple control sequences. [4] Method according to any of the preceding claims, wherein deactivating the second set comprises switching off the digital / analog elements of the second set. [5] A method according to any of the preceding claims, wherein the digital / analog elements are selectively connected to an output of the converter; wherein the method comprises: identifying a third set of elements and separating the third set from the output; and for each time step: Shifting the third set by one element. [6] Method according to claim 5, wherein the third quantity is eliminated. [7] Method according to claim 6, comprising switching on the third quantity at a predetermined time before the third quantity is reconnected to the output. [8] Method according to any of the preceding claims, comprising applying a sequence of predefined values ​​to a predetermined set of elements for a predefined number of time steps. [9] Method according to claim 5, wherein elements in the first set, the second set and the third set are each provided in a successive sequence. [10] Method according to any of the preceding claims, wherein the digital / analog converter is a differential digital / analog converter (430) and the arrangement of digital / analog elements comprises a first group of digital / analog elements (431) and a second group of digital / analog elements (432) coupled to a summing stage (433). [11] Method according to claim 10, wherein the first group (431) is designed to receive multiple first control sequences, and the second group (432) is designed to receive multiple second control sequences, wherein the multiple second control sequences are identical to the multiple first control sequences except for the opposite sign. [12] Method according to claim 11, wherein the multiple first control sequences and the multiple second control sequences form multiple differential control sequences, each differential control sequence comprising a set of values, each value being either a plus-one state, a zero state or a minus-one state; wherein shortening the control sequences comprises identifying a shortening section of the sequence consisting of at least one zero state. [13] Method according to any of the preceding claims, wherein the first set of elements comprises an opening element with a predefined position within the arrangement. [14] The method of claim 13, which, after identifying that the digital signal has risen above a normal operating mode threshold, comprises: Enabling previously disabled elements; Defining the predefined position of the opening element as the first element in the arrangement of digital / analog elements; and Ending the shortening of the control sequences. [15] The method of claim 14, comprising applying a sequence of predefined values ​​to predefined elements. [16] Method according to any of the preceding claims, wherein the digital / analog elements (431, 432) are one-bit elements. [17] Method according to any of the preceding claims, wherein the digital / analog elements comprise current-to-digital / analog converter elements (510). [18] Digital / analog circuit (300, 400) comprising the following: a driver (320, 420, 1410) designed to receive a digital signal and deliver multiple control sequences; a digital-to-analog converter (340, 430) comprising an array of digital-to-analog elements (431, 432, 510) configured to operate over multiple time steps, each digital-to-analog element designed to convert a digital value into an analog value at each time step; and a controller (350, 450, 590, 1450) which is connected to the driver (320, 420, 1410) and the digital / analog converter (340, 430); where the controller (350, 450, 590, 1450) is configured to do the following after identifying that the digital signal is below a threshold: to shorten the control sequences; and for each time step: to identify a first set of elements and a second set of elements under the arrangement of digital / analog elements; to apply the shortened control sequences to the first set; to deactivate the second set; and to shift the first set and the second set by one element. [19] Digital / analog circuit according to claim 18, wherein the digital / analog converter is a differential digital / analog converter (430) comprising a first group of 1-bit elements (431) and a second group of 1-bit elements (432) coupled to a summing stage (433). [20] Digital / analog circuit according to claim 18 or 19, wherein the driver (420) comprises a first pulse width modulator (421) designed to provide multiple first drive sequences and a second pulse width modulator (422) designed to provide multiple second drive sequences. [21] Digital / analog circuit according to one of claims 18 to 20, wherein each digital / analog element (510) is coupled to an output of the converter via a disconnect switch (532, 533, 542, 543). [22] Digital / analog circuit according to one of claims 18 to 21, wherein the controller (1450) comprises several storage devices (1421) coupled to one or more multiplexers (1422), each storage device being assigned to a corresponding digital / analog element. [23] Digital / analog circuit according to one of claims 18 to 22, comprising a sampler (410) for sampling the digital signal. [24] Audio device (1510) comprising a digital / analog circuit (300, 400) according to any one of claims 18 to 23.

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