Semiconductor Device Structure and Its Manufacturing Process

Abstract

Having a semiconductor device structure: a substrate (102); a dielectric fin structure (116) over the substrate (102); a semiconductor fin structure (104, 204) adjacent to the dielectric fin structure (116); a metal gate stack (150) across the dielectric fin structure (116) and the semiconductor fin structure (104, 204); a source / drain feature (134, 144) above the semiconductor fin structure (104, 204); and a source / drain spacer (138) arranged between the source / drain feature (134, 144) and the dielectric fin structure (116); a protective layer (118) directly above the dielectric fin structure (116); a gate spacer (140) along the metal gate stack (150), which partially covers the protective layer (118) and the source / drain spacer (138); and a second insulating structure (162) directly above the protective layer (118) and the dielectric fin structure (116).

Description

BACKGROUND

[0001] The electronics industry is experiencing a constantly increasing demand for smaller and faster electronic devices capable of performing a greater number of increasingly complex and sophisticated functions. Accordingly, the semiconductor industry is seeing a continuous trend toward manufacturing low-cost, high-performance, and low-energy integrated circuits (ICs). To date, these goals have been largely achieved by scaling down semiconductor IC dimensions (e.g., minimum feature size), thereby improving production efficiency and reducing associated costs. However, such miniaturization has led to increased complexity in the semiconductor manufacturing process. Therefore, implementing further advances in semiconductor ICs and devices requires similar advances in semiconductor manufacturing processes and technology.

[0002] Recently, multi-gate devices have been introduced in an attempt to improve gate control by increasing gate channel coupling, reducing the OFF state current, and mitigating short-channel effects (SCEs). One such multi-gate device is the gate-all-around transistor (GAA). The GAA device gets its name from the gate structure, which can extend around the channel region and provide access to the channel from two or four sides. GAA devices are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes, and their structure allows for aggressive scale-down while maintaining gate control and reducing SCEs. In conventional processes, GAA devices provide a channel within a silicon nanowire. However, integrating fabrics of GAA features around the nanowire can be challenging.For example, while current procedures are satisfactory in many respects, further improvements are still needed.

[0003] A fin-like field-effect transistor device is known from German patent application DE 10 2015 106 573 A1. The device comprises a first fin structure arranged over an n-FinFET region of a substrate. The first fin structure comprises a silicon layer, a silicon germanium oxide layer arranged over the silicon layer, and a germanium feature arranged over the silicon germanium oxide layer. The device also comprises a second fin structure over the substrate in a p-FinFET region. The second fin structure comprises the silicon layer, a recessed silicon germanium oxide layer arranged over the silicon layer, an epitaxial silicon germanium layer arranged over the recessed silicon germanium oxide layer, and the germanium feature arranged over the epitaxial silicon germanium layer.

[0004] The publication DE 11 2016 007 366 T5, introduced as a translation of publication WO 2018 / 101 957 A1, describes a method for fabricating a semiconductor structure, comprising the formation of a semiconductor fin projecting through a trench insulation region over a substrate, wherein the semiconductor fin has a top surface, a first end, a second end and a pair of sidewalls between the first end and the second end; the formation of several dummygate structures over the semiconductor fin and through an interlayer dielectric layer, a first of the several dummygate structures at the first end of the semiconductor fin, a second of the several dummygate structures over a region of the top surface and laterally adjacent to a region of the pair of sidewalls of the semiconductor fin, and a third of the several dummygate structures separated from each other at the second end of the semiconductor fin;Removing the first and third of the multiple dummygate structures, but not the second of the multiple dummygate structures, wherein the removal forms a first trench in the ILD layer at the first end of the semiconductor fin and forms a second trench in the interlayer dielectric layer at the second end of the semiconductor fin; forming a first dielectric plug in the first trench and a second dielectric plug in the second trench, wherein the forming of the first and second dielectric plugs comprises; forming a first dielectric along the sidewalls and bottoms of the first and second trenches; and forming a second dielectric between the first dielectric along the sidewalls of the first and second trenches and at the first dielectric layer at the bottoms of the first and second trenches, wherein the second dielectric is different from the first dielectric. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figures 1A to 1M are perspective views illustrating the formation of a semiconductor device at various intermediate stages, according to some embodiments of the disclosure. Fig. Figures 1A-1 to 1M-1 are cross-sectional views of semiconductor structures along line II in Fig. 1A to 1M according to some embodiments of the disclosure. Fig. Figures 1E-2 to 1M-2 are cross-sectional views of semiconductor structures along line II-II in Fig. 1A to 1M according to some embodiments of the disclosure. Fig. Figures 1F-3 to 1M-3 are cross-sectional views of the semiconductor structure along line III-III in Fig. 1A to 1M according to some embodiments of the disclosure. Fig. Figures 2A to 2E are perspective views illustrating the formation of a semiconductor device in various intermediate stages, according to some embodiments of the disclosure. Fig. Figures 2A-1 to 2E-1 are cross-sectional views of semiconductor structures along line II in Fig. 2A to 2E according to some embodiments of the disclosure. Fig. Figures 2B-2 to 2E-2 are cross-sectional views of semiconductor structures along line II-II in Fig. 2A to 2E according to some embodiments of the disclosure. Fig. Figures 2B-3 to 2E-3 are cross-sectional views of semiconductor structures along line III-III in Fig. 2A to 2E according to some embodiments of the disclosure. DETAILED DESCRIPTION

[0006] The following disclosure provides many different embodiments or examples of the implementation of various features of the provided content. Specific examples of the components and arrangements are described below to simplify the present disclosure. For example, the formation of a first feature or a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and it may also include embodiments in which further features can be formed between the first and second features, so that the first and second features do not have to be in direct contact. Furthermore, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition serves for simplicity and clarity and does not in itself dictate a relationship between the various designs and / or configurations discussed.

[0007] Several variations of embodiments are described. In the different views and illustrative embodiments, the same reference numbers are used to denote identical elements. It should be understood that further operations may be provided before, during, and after the method, and that some of the described operations may be substituted or eliminated for other embodiments of the method.

[0008] The gate-all-around transistor (GAA) structures described below can be structured using any suitable method. For example, the structures can be structured using one or more photolithography processes, including dual-structuring or multiple-structuring processes. In general, dual-structuring or multiple-structuring processes combine photolithography and self-aligning processes, allowing the creation of structures with, for example, smaller spacing than would otherwise be possible using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and structured using a photolithography process. Spacers are formed along with the structured sacrificial layer using a self-aligning process.The sacrificial layer is then removed and the remaining spacers can then be used to structure the GAA structure.

[0009] Embodiments of a semiconductor device structure are provided. The semiconductor device structure can comprise a semiconductor fin structure, an insulation structure, source / drain spacers, and a source / drain feature. The insulation structure includes a vertical section surrounding the semiconductor fin structure. The source / drain spacers are formed directly above the vertical section of the insulation structure. The source / drain feature is located between the source / drain spacers. Because the source / drain spacers restrict the lateral growth of the source / drain feature, the source / drain feature can be shaped with a narrower width. As a result, the parasitic capacitance of the semiconductor device can be reduced, thereby improving the operating speed of the semiconductor device.

[0010] Fig. Figures 1A to 1M are perspective views illustrating the formation of a semiconductor device 100 in various intermediate stages, according to some embodiments of the disclosure. Fig. Figures 1A-1 to 1M-1 are cross-sectional views of semiconductor structures along line II in Fig. 1A to 1M according to some embodiments of the disclosure. Fig. Figures 1E-2 to 1M-2 are cross-sectional views of semiconductor structures along II-II in Fig. 1A to 1M according to some embodiments of the disclosure. Fig. Figures 1F-3 to 1M-3 are cross-sectional views of semiconductor structures along line III-III in Fig. 1A to 1M according to some embodiments of the disclosure.

[0011] A substrate 102 is provided according to some embodiments, as in Fig. 1A and 1A-1 are shown. Semiconductor fin structures 104 are formed above the substrate 102 according to some embodiments.

[0012] In some embodiments, the substrate 102 is a semiconductor substrate, such as a silicon substrate. In some embodiments, the substrate 102 comprises an elemental semiconductor such as germanium; a compound semiconductor such as gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) and / or indium antimonide (InSb); an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof.

[0013] In some embodiments, the substrate 102 comprises an epitaxial layer (epi-layer) formed thereon. In some embodiments, the substrate 102 is a semiconductor-on-insulator (SOI) substrate comprising a semiconductor substrate, a sunken oxide layer above the substrate, and a semiconductor layer above the sunken oxide layer.

[0014] According to some embodiments, the semiconductor fin structures 104 are arranged in the X-direction and extend in the Y-direction. According to some embodiments, the semiconductor fin structures 104 each comprise a lower section 104L and an upper section 104U. According to some embodiments, the lower section 104L of the semiconductor fin structure 104 is formed by a section of the substrate 102. The upper section 104U of the semiconductor fin structure 104 is formed by a stacked semiconductor structure, which, according to some embodiments, comprises first semiconductor layers 106 and second semiconductor layers 108, which are stacked alternately over the lower section 104L.

[0015] As explained in detail below, the first semiconductor layers 106 of the semiconductor fin structures 104 are removed, so that the second semiconductor layers 108 of the semiconductor fin structures 104, according to some embodiments, form nanowire structures extending between source / drain features. According to some embodiments, the nanowire structure of the second semiconductor layers 108 is surrounded by gate stacks to serve as a channel region of the semiconductor device. For example, the embodiments illustrated in Fig. 1A to 1M-3 describe processes and materials that can be used to form nanowire structures with a GAA design for n-FinFETs and / or p-FinFETs.

[0016] In some embodiments, the formation of the semiconductor fin structures 104 includes forming a stacked semiconductor structure comprising a first semiconductor material for the first semiconductor layers 106 and a second semiconductor material for the second semiconductor layers 108 over the substrate 102.

[0017] The first semiconductor material for the first semiconductor layers 106 is a material which, according to some embodiments, has a different lattice constant than that of the second semiconductor material for the second semiconductor layers 108. In some embodiments, the first semiconductor layers 106 are made of SiGe, wherein the germanium (Ge) content in the SiGe is in the range of approximately 20 atomic percent to approximately 50 atomic percent, and the second semiconductor layers 108 are made of silicon. In some embodiments, the first semiconductor layers 106 are Si 1-x Ge x, where x is more than approximately 0.3 or Ge (x=1.0) and the second semiconductor layers are Si or Si 1-y Ge y , where y is less than approximately 0.4, and x > y.

[0018] In some embodiments, the first semiconductor material and the second semiconductor material are formed using low-pressure chemical vapor deposition (LPCVD), an epitaxial growth process, another suitable method, or a combination thereof. In some embodiments, the epitaxial growth process includes molecular steel epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), or gas-phase epitaxy (VPE).

[0019] In some embodiments, the thickness of each of the first semiconductor layers 106 is in the range of approximately 1.5 nanometers (nm) to approximately 20 nm. In some embodiments, the first semiconductor layers 106 are essentially uniform in thickness. In some embodiments, the thickness of each of the second semiconductor layers 108 is in the range of approximately 1.5 nm to approximately 20 nm. In some embodiments, the second semiconductor layers 108 are essentially uniform in thickness.

[0020] Subsequently, the stacked semiconductor structure, comprising the first semiconductor material and the second semiconductor material, and the underlying substrate 102 are structured into the fin structures 104.

[0021] In some embodiments, the structuring process comprises the formation of two-layer hard mask layers (including hard mask layers 110 and 112) over the stacked semiconductor structure and the etching of the stacked semiconductor structure and the underlying substrate 102 by the two-layer hard mask layers. In some embodiments, a first hard mask layer 110 is a pad oxide layer of silicon oxide formed by thermal oxidation or CVD. In some embodiments, the second hard mask layer 112 is made of silicon nitride formed by CVD, such as LPCVD or plasma-enhanced CVD (PECVD).

[0022] In some embodiments, the etching process of the structuring process removes sections of the stacked semiconductor structure that are not covered by the two-layer hard mask layers and further cuts out the substrate 102 to form trenches 105.

[0023] In some embodiments, after the etching process, the substrate 102 has sections that protrude from between the grooves 105 to form the lower sections 104L of the semiconductor fin structures 104. In some embodiments, the remaining sections of the stacked semiconductor structure directly above the lower sections 104L form the upper sections 104U of the semiconductor fin structures 104.

[0024] According to some embodiments, the insulating material 114 is formed conformally along the semiconductor fin structures 104 and the substrate 102, as shown in Fig. Figures 1B and 1B-1 are shown. According to some embodiments, the insulating material 114 is further formed along the two-layer hard mask layers. According to some embodiments, the insulating material 114 covers the upper surface of the substrate 102, the sidewalls of the semiconductor fin structures 104, and the upper surfaces and sidewalls of the two-layer hard mask layers. According to some embodiments, the grooves 105 are partially filled by the insulating material 114.

[0025] In some embodiments, the insulating material 114 comprises silicon oxide, silicon nitride, silicon oxynitride (SiON), another suitable insulating material, or a combination thereof. In some embodiments, the insulating material is formed using LPCVD, PECVD, high-density plasma CVD (HDP-CVD), a high aspect ratio process (HARP), flowable CVD (FCVD), ALD, another suitable process, or a combination thereof.

[0026] Dielectric fin structures 116 are formed according to some embodiments to fill remaining sections of the trenches 105, as in Fig. Figures 1C and 1C-1 are shown. According to some embodiments, the dielectric fin structures 116 are adjacent to the semiconductor fin structures 104 and formed above the insulating material 114. According to some embodiments, the dielectric fin structures 116 are formed by the insulating material 114 at a distance from the semiconductor fin structures 104. According to some embodiments, the dielectric fin structures 116 are arranged in the X-direction and extend in the Y-direction. In some embodiments, the upper surfaces of the dielectric fin structures 116 are on a plane below the upper surfaces of the semiconductor fin structures 104.

[0027] In some embodiments, the dielectric fin structures 116 are made of a dielectric having a dielectric constant of less than about 7. In some embodiments, the dielectric for the dielectric fin structures 116 is SiN, SiCN, SiOC, SiOCN, or a combination thereof. In some embodiments, the formation of the dielectric fin structures 116 comprises the deposition of a dielectric over the insulating material 114 and the filling of the grooves 105, followed by a back-etching process. In some embodiments, the deposition process is LPCVD, PECVD, HDP-CVD, HARP, FCVD, ALD, another suitable method, or a combination thereof. In some embodiments, the back-etching process is an isotropic etching process, such as dry chemical etching or wet etching, or an anisotropic etching process, such as dry plasma etching.

[0028] According to some embodiments, the protective layers 118 are formed to fill remaining sections of the trenches 105, as in Fig. Figures 1C and 1C-1 are shown. According to some embodiments, the protective layers 118 are formed directly over the dielectric fin structures 116 in the grooves 105. According to some embodiments, the remaining sections of the grooves 105 are essentially completely filled with the protective layers 118.

[0029] In some embodiments, the protective layers 118 are made of a dielectric having a dielectric constant greater than approximately 7. In some embodiments, the dielectric for the protective layers 118 is Al₂O₃, HfO₂, ZrO₂, HfAlO, HfSiO₂, or a combination thereof. In some embodiments, the formation of the protective layers 118 comprises the deposition of a dielectric over the dielectric fin structures 116 and the filling of the grooves 105, followed by a back-etching process. In some embodiments, the deposition process is LPCVD, PECVD, HDP-CVD, HARP, FCVD, ALD, another suitable method, or a combination thereof. In some embodiments, the back-etching process is an isotropic etching process, such as dry chemical etching or wet etching, or an anisotropic etching process, such as dry plasma etching.

[0030] The insulating material 114, which is formed over the semiconductor fin structures 104, is removed in some embodiments to expose the upper surfaces of the semiconductor fin structures 104, as in Fig. 1C and 1C-1 are shown. The two-layer hard mask layers (including layers 110 and 112) are also removed according to some embodiments. In some embodiments, the removal process is a chemical-mechanical polishing (CMP) process or a re-etching process. In some embodiments, the insulating material 114 and the protective layers 118 are essentially coplanar after planarization of the upper surfaces of the semiconductor fin structures 104.

[0031] According to some embodiments, the insulating material 114 is cut out to form gaps 122, as in Fig. Figures 1D and 1D-1 are shown. In some embodiments, each of the gaps 122 is formed between a semiconductor fin structure 104 and a dielectric fin structure 116. In some embodiments, the gaps 122 expose the sidewalls of the upper sections 104U of the semiconductor fin structures 104, the sidewalls of the dielectric fin structures 116, and the sidewalls of the protective layers 118. In some embodiments, the cutting process includes dry etching, wet etching, or a combination thereof.

[0032] After the cutting process, the remaining sections of the insulating material 114 form an insulating structure 120 according to some embodiments. According to some embodiments, the insulating structure 120 comprises vertical sections 120V and horizontal sections 120H.

[0033] In some embodiments, the vertical sections 120V of the insulating structure 120 surround the lower sections 104L of the semiconductor fin structures 104. In some embodiments, the vertical sections 120V of the insulating structure 120 also surround the lower sections of the dielectric fin structures 116. In some embodiments, each of the vertical sections 120V of the insulating structure 120 is inserted between one of the semiconductor fin structures 104 and one of the dielectric fin structures 116.

[0034] According to some embodiments, the horizontal sections 120H of the insulating structure 120 extend along the upper surface of the substrate 102 between two adjacent semiconductor fin structures 104. According to some embodiments, the dielectric fin structures 116 are formed over the horizontal sections 120H of the insulating structure 120.

[0035] According to some embodiments, dummy gate structures 124 are formed over the semiconductor fin structures 104 and the dielectric fin structures 116, as shown in Fig. Figures 1E, 1E-1, and 1E-2 are shown. According to some embodiments, the dummy gate structures 124 are arranged in the Y-direction and extend in the X-direction. According to some embodiments, the dummy gate structures 124 fill the gaps 122. According to some embodiments, the dummy gate structures 124 cover the upper surfaces and sidewalls of the semiconductor fin structures 104, the sidewalls of the dielectric fin structures 116, and the upper surfaces and sidewalls of the protective layers 118.

[0036] In some embodiments, the dummy gate structures 124 define the source / drain regions and the channel region of a semiconductor device.

[0037] According to some embodiments, the dummy gate structures 124 comprise dummy gate dielectric layers 126 and dummy gate electrode layers 128. In some embodiments, the dummy gate dielectric layers 126 are made of one or more dielectrics, such as silicon oxide, silicon nitride, silicon oxynitride (SiON), HfO₂, HfZrO, HfSiO₂, HfTiO₂, HfAlO₂, or a combination thereof. In some embodiments, the dielectric is formed using thermal oxidation, CVD, ALD, physical vapor deposition (PVD), another suitable method, or a combination thereof.

[0038] In some embodiments, the dummy gate electrode layers 128 are made of a conductive material. In some embodiments, the conductive material comprises polycrystalline silicon (poly-Si), polycrystalline silicon germanium (poly-SiGe), metallic nitrides, metallic silicides, metals, or a combination thereof. In some embodiments, the conductive material is formed using CVD, PVD, or a combination thereof.

[0039] In some embodiments, the formation of the dummy gate structures 124 comprises the conformal formation of a dielectric for the dummy gate dielectric layers 126 along the substrate 102, the semiconductor fin structures 104, the dielectric fin structures 116 and the protective layers 118; the formation of a conductive material for the dummy gate electrode layers 128 over the dielectric; and the formation of two-layer hard mask layers 130 over the conductive material.

[0040] In some embodiments, the formation of the two-layer hard mask layers 130 comprises forming an oxide layer (e.g. silicon oxide) over the conductive material, forming a nitride layer (e.g. silicon nitride) over the oxide layer, and structuring the oxide layer into layers 132 and the nitride layer into layers 134 using photolithography and etching processes.

[0041] In some embodiments, the formation of the dummy gate structures 124 also includes etching the dielectric and conductive material through the two-layer hard mask layers 130 to remove the dielectric and conductive material exposed by the two-layer hard mask layers 130. After the etching process, the source / drain regions of the semiconductor fin structures 104 are exposed. In some embodiments, the etching process includes one or more dry etching processes, wet etching processes, or a combination thereof.

[0042] According to some embodiments, a dielectric 136 is applied globally over the semiconductor structure. Fig. 1E formed, as in Fig. Figures 1F, 1F-1, 1F-2, and 1F-3 are shown. According to some embodiments, the dielectric 136 is conformally formed along the upper surfaces and sidewalls of the two-layer hard mask layers 130, the sidewalls of the dummy gate structures 124, the upper surfaces of the semiconductor fin structures 104, and the upper surfaces of the protective layers 118. According to some embodiments, the dielectric 136 is filled into the gaps 122 to cover the sidewalls of the semiconductor fin structures 104, the sidewalls of the protective layers 118, the sidewalls of the dielectric fin structures 116, and the upper surfaces of the vertical sections 120 V of the insulating structure 120. In some embodiments, the gaps 122 are substantially completely filled by the dielectric 136.

[0043] In some embodiments, the dielectric 136 has a dielectric constant greater than 7. For example, the dielectric 136 is Al₂O₃, HfO₂, ZrO₂, HfAlO, HfSiO₂, or a combination thereof. In some embodiments, the dielectric 136 is formed using LPCVD, PECVD, HDP-CVD, HARP, FCVD, ALD, another suitable method, or a combination thereof.

[0044] The dielectric 136 is etched according to some embodiments to form source / drain spacers 138 as shown in Fig. Figures 1G, 1G-1, 1G-2, and 1G-3 are shown. In some embodiments, the etching process is an isotropic etching process, such as dry chemical etching or wet etching, or an anisotropic etching process, such as dry plasma etching. According to some embodiments, the etching process removes portions of the dielectric 136 formed over the semiconductor fin structures 104 and the protective layers 118. After the etching process, according to some embodiments, upper portions of the sidewalls of the dummy gate structures 124, the upper surfaces of the semiconductor fin structures 104, and the upper surfaces of the protective layers 118 are exposed.

[0045] According to some embodiments, remaining sections of the dielectric 136 stay in the gaps 122 to form the source / drain spacers 138. In some embodiments, the source / drain spacers 138 are formed directly above the vertical sections 120V of the insulating structure 120 and between the semiconductor fin structures 104 and the dielectric fin structures 116. In some embodiments, the source / drain spacers 138 are formed along lower sections of the side walls of the dummy gate structures 124. The source / drain spacers 138 are used to restrict the lateral growth of the subsequently formed source / drain features, thereby forming the source / drain features with a desirable profile.

[0046] Gate spacers 140 are formed along side walls of the dummy gate structures 124 according to some embodiments, as shown in Fig. 1H, 1H-1, 1H-2 and 1H-3 are shown. According to some embodiments, the gate spacers 140 are further formed along the sidewalls of the two-layer hard mask layers 130. According to some embodiments, the gate spacers 140 partially cover the semiconductor fin structures 104, the source / drain spacers 138 and the protective layers 118.

[0047] In some embodiments, the gate spacers 140 are made of a dielectric material such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxide carbon nitride (SiOCN), or a combination thereof. In some embodiments, the gate spacers 140 are formed using a deposition process followed by an etching process. In some embodiments, the deposition process includes CVD (such as PECVD, LPCVD, or HARP) and / or ALD. In some embodiments, the etching process is an anisotropic etching process, such as a dry plasma etching process.

[0048] According to some embodiments, the semiconductor fin structures 104 are cut out to form source / drain cutouts 142, as shown in Fig. Figures 1I, 1I-1, 1I-2, and 1I-3 are shown. The etching process cuts out the semiconductor fin structures 104, which are exposed by the gate spacers 140, the dummy gate structures 124, and the two-layer hard mask layers 130. According to some embodiments, the source / drain cutouts 142 are formed between the source / drain spacers 138 and expose the upper surface of the lower sections 104L of the semiconductor fin structures 104. In some embodiments, the cutout process comprises a dry etching process, a wet etching process, or a combination thereof.

[0049] During the etching process of cutting out the semiconductor fin structures 104, the etchant also etches the dielectrics of the semiconductor structures, according to some embodiments. During the etching process, the etch rate of the dielectric with a higher dielectric constant (such as the source / drain spacers 138 and the protective layers 118) is, according to some embodiments, lower than the etch rate of the dielectric with a lower dielectric constant (such as the dielectric fin structures 116). As a result, the source / drain spacers 138 and the protective layers 118 can protect the dielectric fin structures 116 during the etching process.

[0050] In some embodiments, the etching process partially removes upper sections of the source / drain spacers 138, which are exposed by the gate spacers 140. After the etching process, the cut-out source / drain spacers 138 exhibit, in some embodiments, protruding sections 138P on their upper surfaces, which are covered by the gate spacers 140.

[0051] The etching process also removes the protective layers 118, which are exposed by the gate spacers 140, the dummy gate structures 124, and the two-layer hard mask layers 130. According to some embodiments, the upper surfaces of the dielectric fin structures 116 are exposed after the etching process.

[0052] Source / drain features 144 are formed in the source / drain cutouts 142 according to some embodiments, as shown in Fig. Figures 1J, 1J-1, 1J-2, and 1J-3 are shown. According to some embodiments, the source / drain features 144 are formed directly above the lower sections 104L of the semiconductor fin structures 104. According to some embodiments, the source / drain features 144 are formed between and projecting from the source / drain spacers 138.

[0053] In some embodiments, the source / drain features 144 are made of any suitable material for an n-type semiconductor device and a p-type semiconductor device, such as Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, SiC, SiCP, or a combination thereof. In some embodiments, the source / drain features 144 are formed using an epitaxial growth process, such as MBE, MOCVD, VPE, another suitable epitaxial growth process, or a combination thereof.

[0054] In some embodiments, the source / drain features 144 are doped in situ during the epitaxial growth process. For example, the source / drain features 144 can be epitaxially built SiGe doped with boron (B). For example, the source / drain features 134 can be epitaxially built Si doped with carbon to form silicon:carbon (Si:C) source / drain features, phosphorus to form silicon:phosphorus (Si:P) source / drain features, or carbon and phosphorus to form silicon:carbon:phosphorus (SiCP) source / drain features. In some embodiments, the source / drain features 144 are doped in one or more implantation processes after the epitaxial build-up process.

[0055] Because the source / drain feature 144 is built up between the source / drain spacers 138, the lateral growth of the source / drain feature 144 is limited by the source / drain spacers 138 according to the invention. Therefore, the source / drain feature 144 has a body section 144B between the source / drain spacers 138 according to the invention. The body section 144B, which is limited by the source / drain spacer 138, has a columnar profile according to some embodiments.

[0056] According to some embodiments, the source / drain feature 144 extends beyond the source / drain spacer 138. Therefore, according to the invention, the source / drain feature 144 has a head section 144H that projects out of (protrudes from) the source / drain spacers 138. In some embodiments, the head section 144H is laterally formed and has a faceted profile, without being restricted by the source / drain spacers 138.

[0057] According to the invention, the body section 144B has a width W1 at its lower surface, measured in the X-direction. In some embodiments, the width W1 ranges from approximately 8 nm to approximately 70 nm. According to the invention, the body section 144B has a width W2 at its mid-height, measured in the X-direction. In some embodiments, the width W2 ranges from approximately 8 nm to approximately 70 nm. In some embodiments, the body section 144B has a width W3 at its upper end (or at the position of the upper surface of the source / drain spacer 138), measured in the X-direction. In some embodiments, the width W3 ranges from approximately 8 nm to approximately 70 nm. In some embodiments, the width W1 is equal to or less than the width W2. In some embodiments, the width W2 is equal to or less than the width W3.That said, body segment 144B may have a substantially uniform width or a width that tapers upwards.

[0058] In some embodiments, body section 144B has a height H1 measured in the Z-direction. In some embodiments, the height H1 ranges from approximately 40 nm to approximately 80 nm. In some embodiments, the ratio of height H1 to width W1 ranges from approximately 0.5 to approximately 10.

[0059] In some embodiments, the head section 144H has a maximum width W4 measured in the X direction. In some embodiments, the width W4 ranges from approximately 14 nm to approximately 90 nm. In some embodiments, the ratio of width W4 to width W1 ranges from approximately 1.2 to approximately 1.8.

[0060] In some embodiments, the head section 144H has a height H2 measured in the Z-direction. In some embodiments, the height H2 ranges from approximately 14 nm to approximately 90 nm. In some embodiments, the ratio of height H1 to height H2 ranges from approximately 0.8 to approximately 3.

[0061] Because the source / drain spacers 138 restrict the lateral growth of the source / drain features 144, the source / drain features 144 can have a slimmer column profile (i.e., a higher ratio of height H1 to width W1) than if the source / drain spacers were not formed.

[0062] According to some embodiments, a contact etch stop layer (CESL) 146 is applied over the semiconductor structure. Fig. 1J formed, as in Fig. 1K, 1K-1, 1K-2 and 1K-3 are shown. An interlayer dielectric (ILD) layer 148 is formed over the CESL 146 according to some embodiments.

[0063] According to some embodiments, the CESL 146 is conformally formed along the faceted surfaces of the head sections 144H of the source / drain features 144, the upper surfaces of the source / drain spacers 138, the upper surfaces of the dielectric fin structures 116, the side walls of the protruding sections of the source / drain spacers 138, the side walls of the protective layers 118, and the side walls of the gate spacers 140.

[0064] In some embodiments, the CESL 146 is made of a dielectric, such as silicon nitride, silicon oxide, silicon oxynitride, another suitable dielectric, or a combination thereof. In some embodiments, the dielectric for the CESL 146 is globally distributed over the semiconductor structure. Fig. 1J deposited. The deposition process includes CVD (such as PECVD, HARP or a combination thereof), ALD, another suitable method or a combination thereof.

[0065] In some embodiments, the ILD layer 148 is made of a dielectric such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass (USG), or doped silicon oxide such as boron phosphosilicate glass (BPSG), fluoride-doped silicate glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), and / or another suitable dielectric. In some embodiments, the dielectric for the ILD layer 148 is formed using CVD (such as HDP-CVD, PECVD, or HARP), ALD, another suitable method, or a combination thereof.

[0066] Subsequently, according to some embodiments, a planarization process such as CMP or a back-etching process is performed on dielectric materials for the CESL 146 and the ILD layer 148. The dielectrics formed over the dummy gate structures 124 are removed, according to some embodiments, to eliminate the top surfaces of the dummy gate electrode layers 128. According to some embodiments, the planarization process also removes the two-layer hard mask layers 130.

[0067] According to some embodiments, the dummy gate structures 124 are replaced with metal gate stacks 150, as in Fig. 1L, 1L-1, 1L-2 and 1L-3 are shown. According to some embodiments, the replacement process includes removing the dummy gate structures 124, removing the first semiconductor layers 106 of the semiconductor fin structure 104, and forming the metal gate stacks 150 to surround the second semiconductor layers 106.

[0068] In some embodiments, the dummy gate structures 124 (including the dummy gate electrode layers 128 and the dummy gate dielectric layers 126) are removed to form trenches (not shown) between the gate spacers 140. The removal process includes one or more etching processes. For example, if the dummy gate electrode layers 128 are polysilicon, a wet etchant such as tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the dummy gate electrode layers 128. For example, the dummy gate dielectric layers 126 can then be removed using plasma dry etching, dry chemical etching, and / or wet etching.

[0069] In some embodiments, first semiconductor layers 106 of the semiconductor fin structure 104 are removed to form gaps (not shown) between the second semiconductor layers 108 and between the bottommost of the second semiconductor layer 108 and the lower section 104L. After removal of the first semiconductor layers 106, according to some embodiments, four main faces (a top face, two side faces, and a bottom face) of each of the second semiconductor layers 108 are exposed. According to some embodiments, the exposed second semiconductor layers 108 form nanowire structures that serve as a channel region of the emerging semiconductor device and are surrounded by the metal gate stacks 150.

[0070] In some embodiments, the etching process includes a selective wet etching process, such as an APM (e.g., ammonium hydroxide-hydrogen peroxide-water mixture) etching process. In some embodiments, the wet etching process uses etchants such as ammonium hydroxide (NH4OH), TMAH, ethylenediaminepyrocatechol (EDP), and / or potassium hydroxide (KOH) solutions.

[0071] In some embodiments, an interface layer 152, a gate dielectric layer 154, and a gate electrode layer 156 are successively formed in the trenches and gaps where the dummy gate structures 124 and the first semiconductor layers 106 are removed. According to some embodiments, the interface layer 152, the gate dielectric layer 154, and the gate electrode layer 156 together function as the metal gate stacks 150.

[0072] In some embodiments, the metal gate stacks 150 surround the nanowire structures of the second semiconductor layers 108. In some embodiments, the metal gate structures 150 are arranged in the Y-direction and extend in the X-direction. In some embodiments, the metal gate stacks 150 extend over the semiconductor fin structures 104 and the dielectric fin structure 116.

[0073] In some embodiments, the interface layer 152 is formed conformally along the main surfaces of the second semiconductor layers 108 in order to surround the second semiconductor layers 108. In some embodiments, the interface layer 152 is formed from a chemically formed silicon oxide.

[0074] In some embodiments, the gate dielectric layer 154 is conformally formed on the interface layer 152 to surround the second semiconductor layers 108. In some embodiments, the gate dielectric layer 154 is further formed along the upper surfaces and sidewalls of the protective layers 118, the sidewalls of the dielectric fin structures 116, the upper surfaces of the insulating structure 120, and the upper surfaces of the lower section 104L of the semiconductor fin structures 104. In some embodiments, the gate dielectric layer 154 is also formed along the upper surface of the ILD layer 148.

[0075] In some embodiments, the gate dielectric layer 154 is made from one or more layers of a dielectric such as HfO₂, HfSiO₂, HfSiON₂, HfTaO, HfTiO₂, HfZrO₂, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO₂-Al₂O₃) alloy, another suitable high k-value dielectric, or a combination thereof. In some embodiments, the gate dielectric layer 154 is formed using CVD, ALD, another suitable method, or a combination thereof.

[0076] According to some embodiments, the gate electrode layer 156 is formed on the gate dielectric layer 154. According to some embodiments, the remaining sections of the trenches and gaps, in which the dummy gate structures 124 and the first semiconductor layers 106 are removed, are essentially completely filled by the gate electrode layer 156.

[0077] In some embodiments, the gate electrode layer 156 is made from one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, another suitable material, or a combination thereof. In some embodiments, the gate electrode layer 156 is formed using CVD, ALD, electroplating, another suitable process, or a combination thereof.

[0078] Subsequently, according to some embodiments, a planarization process such as CMP or a back-etching process is performed on the metal gate stacks 150 to remove the metal gate stacks 150 that are formed above the ILD layer 148. After the planarization process, the upper surface of the ILD layer 148 is exposed according to some embodiments.

[0079] According to the invention, an insulation structure 162 is formed by the ILD 148 and the metal gate stacks 150, as shown in Fig. Figures 1M, 1M-1, 1M-2, and 1M-3 are shown. According to some embodiments, the insulation structure 162 extends in the Y-direction. According to the invention, the insulation structure 162 is formed directly above the dielectric fin structure 116 and the protective layers 118.

[0080] In some embodiments, the insulating structure 162 is made of an insulating material. In some embodiments, the insulating material for the insulating structure 162 comprises SiO2, SiON, SiN, SiC, SiOC, SiOCN or a combination thereof.

[0081] In some embodiments, the formation of the insulating structure 162 includes performing a cutting process to form a trench through the ILD layer 148 and the metal gate stacks 150. The cutting process cuts the metal gate stacks 150 into sub-metal gate stacks 151. In some embodiments, the trench exposes the top surfaces and sidewalls of the protective layers 118 and the top surface of the dielectric fin structures 116. In some embodiments, the cutting process includes photolithography and etching.

[0082] In some embodiments, an insulating material is deposited for the insulating structure 162 to fill the trench. In some embodiments, the insulating material is further deposited over the ILD layer 148 and the metal gate stacks 150.

[0083] In some embodiments, the insulating material above the ILD layer 148 and the metal gate stacks 150 are subsequently removed. In some embodiments, the removal process is CMP or a back-etching process.

[0084] In some embodiments, contact openings (not shown) are formed by the ILD layer 148 and CESL 146. In some embodiments, the contact openings are formed using a photolithography process and an etching process. According to some embodiments, the contact openings expose the upper surfaces of the source / drain features 144. In some embodiments, the etching process further excises the head section 144H of the source / drain features 144.

[0085] In some embodiments, after the etching process, the head section 144H has a width W5 on its upper surface, measured in the X direction. In some embodiments, the width W5 ranges from approximately 14 nm to approximately 90 nm. In some embodiments, the ratio of width W5 to width W1 ranges from approximately 1.2 to approximately 1.8.

[0086] In some embodiments, after the etching process, the head section 144H of the source / drain feature 144 has a height H3, measured in the Z direction. In some embodiments, the height H3 ranges from approximately 7 nm to approximately 45 nm. In some embodiments, the ratio of height H1 to height H3 ranges from approximately 1.5 to approximately 6.

[0087] According to some embodiments, silicides 158 are formed on the upper surfaces of the source / drain features 144, as shown in Fig. 1M, 1M-1, 1M-2 and 1M-3 shown.

[0088] In some embodiments, the silicides 158 are produced from WSi, NiSi, TiSi, CoSi, and / or another suitable silicide material. In some embodiments, the formation of the silicides 158 comprises the deposition of a metal material over the ILD layer 148 and along the sidewalls and bottom surfaces of the contact openings, the annealing of a metal material such that the metal material reacts with the source / drain features 144, and the etching away of the unreacted portion of the metal material. In some embodiments, the deposition process comprises CVD, ALD, PVD, and / or another suitable method. In some embodiments, the annealing process comprises a rapid temperature annealing (RTA) process. In some embodiments, the etching process comprises wet etching.

[0089] According to some embodiments, the contacts 160 are formed by the ILD layer 148 and terminate at the silicide 158, as in Fig. 1M, 1M-1, 1M-2 and 1M-3 shown.

[0090] In some embodiments, the contacts 160 are made of a conductive material such as Co, Ni, W, Ti, Ta, Cu, Al, TiN, TaN and / or another suitable conductive material. The formation of the contacts 160 comprises depositing a conductive material over the ILD layer 148 and filling the contact orifices, and removing the conductive material over the ILD layer 148. In some embodiments, the deposition process comprises CVD, ALD, PVD and / or another suitable method. In some embodiments, the removal process is CMP.

[0091] After forming the contacts 160, the semiconductor device 100 is obtained.

[0092] By forming the source / drain spacer 138 to limit the lateral growth of the source / drain feature 144, the source / drain feature 144 can have a body section 144B with a slender column profile. The narrower width of the source / drain feature 144 can reduce the parasitic capacitance between a gate stack and the source / drain feature, thereby improving the operating speed of the semiconductor device.

[0093] Furthermore, the source / drain spacers 138 are formed from the dielectric with a high dielectric constant (such as greater than 7), so that the consumption of the source / drain spacers 138 during the etching process of forming the source / drain cutouts 142 can be reduced. If the consumption of the source / drain spacers 138 is too high, the height H1 of the body section 144B of the source / drain feature 144 can decrease. Therefore, the source / drain feature 144 can be formed to have a larger proportion of body section 144B and a smaller proportion of head section 144H. That is, the ratio of height H1 to height H3 is increased. As a result, the parasitic capacitance between the gate stack and the source / drain feature can be further reduced, thus further improving the operating speed of the semiconductor device.

[0094] Even if the above in Fig. The embodiments described in sections 1A to 1M-3 can be used in the GAA device; these embodiments can also be used in the FinFET device and in Fig. 2A to 2E-3 should be described.

[0095] Fig. Figures 2A to 2E are perspective views illustrating the formation of a semiconductor device 200 in various intermediate stages, according to some embodiments of the disclosure. Fig. Figures 2A-1 to 2E-1 are cross-sectional views of semiconductor structures along line II in Fig. 2A to 2E according to some embodiments of the disclosure. Fig. Figures 2B-2 to 2E-2 are cross-sectional views of semiconductor structures along II-II in Fig. 2A to 2E according to some embodiments of the disclosure. Fig. Figures 2B-3 to 2E-3 are cross-sectional views of semiconductor structures along line III-III in Fig. 2A to 2E according to some embodiments of the disclosure.

[0096] A substrate 102 is provided according to some embodiments, as in Fig. Figures 2A and 2A-1 are shown. Semiconductor fin structures 204 are formed above the substrate 102 according to some embodiments. The semiconductor fin structures 204 are arranged in the X-direction and extend in the Y-direction according to some embodiments.

[0097] In some embodiments, semiconductor fin structures 204 are formed by a section of the substrate 102. For example, a structuring process can be performed on the substrate 102 to form the fin structures 204.

[0098] According to some embodiments, an insulating structure 120, dielectric fin structures 116, and protective layers 118 are formed over the substrate 102, as shown in Fig. 2A and 2A-1 are shown. The methods for forming the insulating structure 120, the dielectric fin structures 116, and the protective layers 118 can be the same or similar as shown above. Fig. 1B to 1D-1 described.

[0099] According to some embodiments, the insulating structure 120 comprises vertical sections 120V and horizontal sections 120H. According to some embodiments, the vertical sections 120V of the insulating structure 120 surround the lower sections of the semiconductor fin structures 204 and the lower sections of the dielectric fin structures 116. According to some embodiments, the horizontal sections 120H of the insulating structure 120 extend along the upper surface of the substrate 102 between two adjacent semiconductor fin structures 204.

[0100] According to some embodiments, the dielectric fin structures 116 are adjacent to the semiconductor fin structures 204 and formed over the horizontal sections 120H of the insulating material 114. In some embodiments, the dielectric fin structures 116 are arranged in the X-direction and extend in the Y-direction. In some embodiments, the protective layers 118 are formed directly over the dielectric fin structures 116.

[0101] According to the invention, dummy gate structures 124 are formed over the semiconductor fin structures 204 and the dielectric fin structures 116, as shown in Fig. Figures 2B, 2B-1, 2B-2, and 2B-3 are shown. According to some embodiments, the two-layer hard mask layers 130 are formed over the dummy gate structures 124. According to some embodiments, the dummy gate structures 124 are arranged in the Y-direction and extend in the X-direction. According to some embodiments, the dummy gate structures 124 are filled into the gaps 122.

[0102] Source / drain spacers 138 are formed in the gaps 122 according to some embodiments, as shown in Fig. Figures 2B, 2B-1, 2B-2, and 2B-3 are shown. According to some embodiments, the source / drain spacers 138 are formed directly above the vertical sections of the insulating structures 120 and between the semiconductor fin structures 204 and the dielectric fin structures 116. According to some embodiments, the source / drain spacers 138 are formed along lower sections of the side walls of the dummy gate structures 124.

[0103] Gate spacers 140 are formed along side walls of the dummy gate structures 124 according to some embodiments, as shown in Fig. 2C, 2C-1, 2C-2 and 2C-3 are shown. The gate spacers 140 cover the source / drain spacers 138 and the protective layers 118.

[0104] According to some embodiments, the semiconductor fin structures 204 are cut out to form source / drain cutouts. Source / drain features 144 are formed in the source / drain cutouts according to some embodiments, as shown in Fig. 2C, 2C-1, 2C-2 and 2C-3 are shown. According to some embodiments, the source / drain features 144 are formed directly above the lower sections 204L of the semiconductor fin structures 204. According to some embodiments, the source / drain features 144 are formed between and projecting from the source / drain spacers 138.

[0105] According to some embodiments, the CESL 146 is conformally formed along the faceted surfaces of the head sections 144H of the source / drain features 144, the upper surfaces of the source / drain spacers 138, the upper surfaces of the dielectric fin structures 116, the side walls of the protruding sections of the source / drain spacers 138, the side walls of the protective layers 118, and the side walls of the gate spacers 140, as shown in Fig. Figures 2D, 2D-1, 2D-2 and 2D-3 are shown. According to some embodiments, an ILD layer 148 is formed above the CESL 146.

[0106] According to some embodiments, the dummy gate structures 124 are replaced with metal gate stacks 150, as in Fig. Figures 2D, 2D-1, 2D-2 and 2D-3 are shown. According to some embodiments, the replacement process includes removing the dummy gate structures 124 by one or more etching processes and forming the metal gate stacks 150 to cover the upper sections 204U of the semiconductor fin structures 204.

[0107] According to some embodiments, the metal gate stacks 150 comprise an interface layer 152, a gate dielectric layer 154, and a gate electrode layer 156. According to some embodiments, the interface layer 152 is formed conformally along the upper surfaces and side walls of the semiconductor fin structures 204.

[0108] According to some embodiments, the gate dielectric layer 154 is formed conformally on the interface layer 152. According to some embodiments, the gate dielectric layer 154 is further formed along the upper surfaces and sidewalls of the protective layers 118, the sidewalls of the dielectric fin structures 116, and the upper surfaces of the insulating structure 120. According to some embodiments, the gate electrode layer 156 is formed on the gate dielectric layer 154.

[0109] According to the invention, an insulation structure 162 is formed by the ILD and the metal gate stacks 150, as shown in Fig. Figures 2E, 2E-1, 2E-2, and 2E-3 are shown. According to some embodiments, the insulation structure 162 extends in the Y-direction. According to the invention, the insulation structure 162 is formed directly above the dielectric fin structure 116 and the protective layers 118.

[0110] After forming the insulation structure 162, according to some embodiments the metal gate stacks 150 are cut into sub-metal gate stacks 151.

[0111] According to some embodiments, silicides 158 are formed at the source / drain features 144, as in Fig. 2E, 2E-1, 2E-2 and 2E-3 are shown. According to some embodiments, contacts 160 are formed by the ILD layer 148 and connect to the silicide 158 to form a semiconductor device 200. The methods for forming the silicides 158 and the contacts 160 can be the same or similar as shown above. Fig. 1M to 1M-3 described.

[0112] As described above, the semiconductor device structure according to the invention comprises a substrate 102, a semiconductor fin structure 104, an insulating structure 120, source / drain spacers 138, and a source / drain feature 144. According to the invention, the insulating structure 120 comprises a vertical section 120V surrounding the semiconductor fin structure 104. In some embodiments, the source / drain spacers 138 are formed directly above the vertical section 120V of the insulating structure 120. In some embodiments, the source / drain feature 144 is arranged between the source / drain spacers 138. Because the source / drain spacers 138 restrict the lateral growth of the source / drain feature 144, in some embodiments the source / drain feature 144 can be configured to have a narrower width when the source / drain spacers are not formed.As a result, according to some embodiments, the source / drain feature 144 with a narrower width can reduce the parasitic capacitance between a gate stack and the source / drain feature, thereby improving the operating speed of the semiconductor device.

[0113] Embodiments of a semiconductor device structure can be provided. The semiconductor device structure can comprise a semiconductor fin structure, an insulating structure surrounding the semiconductor fin structure, source / drain spacers above the insulating structure, and a source / drain feature located between the source / drain spacers. Because the source / drain spacers restrict the lateral growth of the source / drain feature, the source / drain feature can have a narrower width. As a result, the parasitic capacitance of the semiconductor device can be reduced, thereby improving the operating speed of the semiconductor device.

[0114] According to the invention, a semiconductor device structure is provided. The semiconductor device structure comprises a substrate and a dielectric fin structure above the substrate. The semiconductor device structure also comprises a semiconductor fin structure adjacent to the dielectric fin structure. The semiconductor device structure also comprises a metal gate stack extending over the dielectric fin structure and the semiconductor fin structure. The semiconductor device structure also comprises a source / drain feature above the semiconductor fin structure. The semiconductor device structure also comprises a source / drain spacer arranged between the source / drain feature and the dielectric fin structure.

[0115] According to the invention, a semiconductor device structure is provided. The semiconductor device structure comprises a substrate and a semiconductor fin structure above the substrate. The semiconductor device structure also comprises an insulating structure comprising a vertical section surrounding the semiconductor fin structure and a horizontal section along the substrate. The semiconductor device structure also comprises a dielectric fin structure above the horizontal section of the insulating structure. The semiconductor device structure also comprises source / drain spacers directly above the vertical section of the insulating structure. The semiconductor device structure also comprises a source / drain feature arranged between the source / drain spacers.

[0116] According to the invention, a method for forming a semiconductor device structure is provided. The method comprises forming a semiconductor fin structure over a substrate. The method also comprises conformally forming an insulating material along the semiconductor fin structure and the substrate. The method also comprises forming a dielectric fin structure adjacent to the semiconductor fin structure and located over the insulating material. The method also comprises cutting out the insulating material to form a gap between the semiconductor fin structure and the dielectric fin structure. The method also comprises forming a first dielectric over the semiconductor fin structure and the dielectric fin structure and filling the gap.The process also includes etching a first section of the first dielectric over the semiconductor fin structure and the dielectric fin structure to form a source / drain spacer in the gap. The process also includes etching an upper section of the semiconductor fin structure, thereby exposing a lower section of the semiconductor fin structure. The process also includes forming a source / drain feature over the lower section of the semiconductor fin structure.

Claims

[1] Having a semiconductor device structure: a substrate (102); a dielectric fin structure (116) over the substrate (102); a semiconductor fin structure (104, 204) adjacent to the dielectric fin structure (116); a metal gate stack (150) across the dielectric fin structure (116) and the semiconductor fin structure (104, 204); a source / drain feature (134, 144) above the semiconductor fin structure (104, 204); and a source / drain spacer (138) arranged between the source / drain feature (134, 144) and the dielectric fin structure (116); a protective layer (118) directly above the dielectric fin structure (116); a gate spacer (140) along the metal gate stack (150), which partially covers the protective layer (118) and the source / drain spacer (138); and a second insulation structure (162) directly above the protective layer (118) and the dielectric fin structure (116). [2] Semiconductor device structure according to claim 1, further comprising: a first insulating structure (120) surrounding the dielectric fin structure (116) and the semiconductor fin structure (104, 204), wherein the first insulating structure (120) comprises: - a vertical section (120V) arranged between the dielectric fin structure (116) and the semiconductor fin structure (104, 204); and - a horizontal section (120H) along an upper surface of the substrate (102). [3] Semiconductor device structure according to claim 2, wherein: the source / drain spacer (138) is placed directly above the vertical section (120V) of the first insulation structure (120), and the dielectric fin structure (116) is placed above the horizontal section (120H) of the first insulation structure. [4] Semiconductor device structure according to any one of the preceding claims, wherein: the source / drain spacer (138) is made of Al2O3, HfO2, ZrO2, HfAlO, or HfSiO, and the dielectric fin structure (116) is formed from SiN, SiCN, SiOC or SiOCN. [5] Semiconductor device structure according to one of the preceding claims, wherein the protective layer (118) 118 is made of Al2O3, HfO2, ZrO2, HfAlO or HfSiO. [6] Semiconductor device structure according to one of the preceding claims, wherein the source / drain spacer (138) has a protruding section (138P) which is covered by the gate spacer (140) and is located on an upper surface of the source / drain spacer (138). [7] Semiconductor device structure according to any of the preceding claims, further comprising: a nanowire structure over the semiconductor fin structure (104, 204) and surrounded by the metal gate stack (150). [8] Having a semiconductor device structure: a substrate (102); a semiconductor fin structure (104, 204) over the substrate (102); an insulation structure (120, 162) comprising a vertical section (120V) surrounding the semiconductor fin structure (104, 204) and a horizontal section (120H) along the substrate (102); a dielectric fin structure (116) over the horizontal section (120H) of the insulation structure (120, 162); Source / drain spacer (138) directly above the vertical section (120V) of the insulation structure (120, 162); and a source / drain feature (134, 144) arranged between the source / drain spacers (138), the source / drain feature (134, 144) comprising: a body section (144B) between the source / drain spacers (138); and a head section (144H) extending from the source / drain spacer (138), wherein the body section (144B) has: a first width at a mean height of the body segment (144B); and a second width on a lower surface of the body section (144B), wherein the second width is equal to or greater than the first width. [9] Semiconductor device structure according to claim 8, wherein: the body section (144B) has a first height, the head section (144H) has a second height, and The ratio of the first height to the second height is 1.5 to 6. [10] Semiconductor device structure according to claim 8 or 9, further comprising: a contact etch stop layer along the head section (144H) of the source / drain feature (134, 144) and the source / drain spacer (138); and an ILD layer (148) above the contact etch stop layer. [11] Semiconductor device structure according to any one of the preceding claims 8 to 10, wherein: the source / drain spacers (138) are formed from a first dielectric with a dielectric constant of more than 7, and the dielectric fin structure (116) is formed from a second dielectric with a dielectric constant of less than 7. [12] Method for forming a semiconductor device structure, comprising: Forming a semiconductor fin structure (104, 204) over a substrate (102); conformal formation of an insulating material (114) along the semiconductor fin structure (104, 204) and the substrate (102); Forming a dielectric fin structure (116) adjacent to the semiconductor fin structure (104, 204) and over the insulating material (114); Cutting out the insulating material (114) to form a gap (122) between the semiconductor fin structure (104, 204) and the dielectric fin structure (116); Forming a first dielectric over the semiconductor fin structure (104, 204) and the dielectric fin structure (116) and filling the gap (122); Etching of a first section of the first dielectric over the semiconductor fin structure (104, 204) and the dielectric fin structure (116) to form a source / drain spacer (138) in the gap (122); Etching an upper section of the semiconductor fin structure (104, 204), thereby exposing a lower section of the semiconductor fin structure (104, 204); and Forming a source / drain feature (134, 144) over the lower section of the semiconductor fin structure (104, 204), further comprising: Before forming the first dielectric, a dummy gate structure (124) is formed across the semiconductor fin structure (104, 204) and the dielectric fin structure (116), wherein: the first dielectric is further formed along the dummy gate structure (124), and etching a first section of the first dielectric further comprises etching a second section of the first dielectric formed along the dummy gate structure (124). [13] Method for forming the semiconductor device structure according to claim 12, wherein: the first dielectric has a first dielectric constant, and The dielectric fin structure is formed from a second dielectric with a second constant that is less than the first dielectric constant. [14] Method for forming the semiconductor device structure according to claim 12 or 13, further comprising: Forming a gate spacer (140) along the dummy gate structure (124) that partially covers the source / drain spacer (138); and Replacing the dummy gate structure (124) with a metal gate stack (150). [15] Method for forming the semiconductor device structure according to claim 14, further comprising: Forming an insulating structure (120, 162) through the metal gate stack (150) and directly above the dielectric fin structure (116). [16] Method for forming the semiconductor device structure according to one of claims 12 to 15, wherein the upper section of the semiconductor fin structure (104, 204) comprises a stack in which first semiconductor layers alternate with second semiconductor layers.

Images