SELF-ALIGNING CONTACT ARRANGEMENT

Abstract

Procedure comprehensive: Forming a first gate (42) over a substrate (20), wherein the first gate has a first gate electrode (40) between first gate spacer elements (26); Forming a first dielectric layer (34) over the substrate (20) and surrounding the first gate; Forming a first hard mask layer (46) over the first gate, wherein the first hard mask exhibits a first etch selectivity; Deepening the first hard mask layer (46) to expose the upper surfaces of the first gate spacer elements, Recessing the upper surfaces of the first gate spacer elements (26) so that the upper surfaces of the first gate spacer elements are arranged below the upper surfaces of the first hard mask layer (46); and Form a second hard mask layer (52) over the first hard mask layer (46) such that it extends downwards along the side walls of the first hard mask layer (46) and contacts the upper surfaces of the first gate spacer elements (26), wherein the second hard mask has a second etch selectivity which is greater than the first etch selectivity.

Description

BACKGROUND

[0001] Semiconductor devices are used in a wide variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate and structuring the various material layers using lithography to form circuit components and elements on them.

[0002] The semiconductor industry is constantly working to improve the integration density of various electronic components (e.g. transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size that allows more components to be integrated into a given area.

[0003] Especially as the design shrinks, short circuits can occur in conductive elements that connect to layers above and below if the conductive element is misaligned. This generally happens when the etching process through the layer misaligns the conductive element in such a way that it exposes portions of an adjacent conductive element on the layer below. US 2017 / 0288031A1 discloses methods for fabricating self-aligning contacts of a semiconductor assembly. US 9064801B1 discloses a semiconductor assembly with a two-layer mask over a gate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various elements are not shown to scale. In fact, the dimensions of the various elements may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 shows a perspective view of a FinFET device in accordance with some embodiments. Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15 to Fig. Figure 16 shows cross-sectional views of intermediate steps in the manufacture of a semiconductor device in accordance with some embodiments. Fig. 17, Fig. 18, Fig. 19, Fig. 20, Fig. 21, Fig. 22, Fig. 23 to Fig. Figure 24 shows cross-sectional views of intermediate steps in the manufacture of a semiconductor device in accordance with some embodiments. Fig. 25, Fig. 26, Fig. 27, Fig. 28, Fig. 29, Fig. 30 to Fig. Figure 31 presents cross-sectional views of intermediate steps in the manufacture of a semiconductor device in accordance with some embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides numerous different embodiments, or examples, for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not to be interpreted as limitations. For example, the formation of a first element above or on top of a second element in the following description may include embodiments in which the first element and the second element are formed in direct contact with each other, and may also include embodiments in which additional elements may be formed between the first element and the second element, such that the first element and the second element may not be in direct contact with each other. Furthermore, the present disclosure may repeat reference numerals and / or symbols in the various examples.This repetition serves the purpose of simplification and clarity, and does not in itself prescribe any relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, terms describing spatial relationships, such as "below," "underneath," "lower," "above," "upper," and the like, may be used herein for the purpose of simplifying the description of the relationship between an element or feature depicted in the figures and another element(s) or feature(s). These terms describe spatial relationships to encompass various orientations of the device during use or operation, in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the terms describing spatial relationships used herein may be interpreted accordingly.

[0007] The following describes embodiments in a specific context, namely a self-aligning arrangement. The self-aligning arrangement uses multiple mask layers positioned over conductive elements of the lower layers to protect the conductive elements from unintentional exposure during etching processes to open contacts.

[0008] The embodiments discussed herein relate to field-effect transistors (FETs) fabricated using a gate-load process. Other embodiments may employ a gate-first process. Furthermore, some embodiments consider aspects used in planar devices, such as planar FETs, or fin devices, such as FinFETs.

[0009] Fig. Figure 1 shows an example of a FinFET in a three-dimensional view consistent with some embodiments. The FinFET has a fin 21 on a substrate 20 (e.g., a semiconductor substrate). Insulation regions 23 are arranged in the substrate 20, and the fin 21 extends beyond and between adjacent insulation regions 23. Although the insulation regions 23 are described / shown as being separate from the substrate 20, the term "substrate" herein may also be used to refer either only to the semiconductor substrate or to a semiconductor substrate including insulation regions. Furthermore, although the fin 21 is shown as a single, continuous material with the substrate 20, the fin 21 and / or the substrate 20 may comprise a single material or a plurality of materials.In this context, fin 21 refers to a section that extends between the adjacent isolation areas 21.

[0010] A dielectric gate layer 22 is arranged along side walls and over an upper surface of the fin 21, and a gate electrode 24 is arranged above the dielectric gate layer 22. Source / drain regions 30 are arranged on sides of the fin 21 opposite the dielectric gate layer 22 and the gate electrode 24.

[0011] Fig. Figure 1 further shows reference cross-sections, which are used in later figures. Cross-section AA is arranged along a longitudinal axis of the gate electrode 24 and in a direction, for example, perpendicular to the direction of current flow between the source / drain regions 30 of the FinFET. Cross-section BB is arranged perpendicular to cross-section AA and along a longitudinal axis of the fin 21 and, for example, in a direction of current flow between the source / drain regions 30 of the FinFET. Cross-section CC is arranged parallel to cross-section AA and extends through a source / drain region of the FinFET.

[0012] Some embodiments discussed herein relate to FinFETs formed using a gate-last process. In other embodiments, a gate-first process can be used. Furthermore, some embodiments consider aspects used in planar devices, such as planar FETs.

[0013] Now referring to Fig. 2, shows Fig. 2 a substrate 20, dummy gate stacks 28A and 28B, and source / drain regions 30. The substrate 20 can be a semiconductor substrate, such as a basic semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p- or n-type dopant) or undoped. The substrate 20 can be a wafer, such as a silicon wafer. In general, an SOI substrate has a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide layer (BOX layer), a silicon oxide layer, or the like. The insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, may also be used.In some embodiments, the semiconductor material of substrate 20 may comprise silicon; germanium; a compound semiconductor comprising silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor comprising SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof.

[0014] Corresponding basins can be formed in substrate 20. For example, a P basin can be formed in the first area of ​​substrate 20, and an N basin can be formed in a second area of ​​substrate 20.

[0015] The various implantation steps for the different trays can be achieved by using a photoresist or other masks (not shown). For example, a photoresist is formed and structured to expose the area of ​​substrate 20 to be implanted. The photoresist can be formed using a spin-coating technique and can be structured using acceptable photolithography techniques. After the photoresist has been structured, n- and / or p-impurity implantation is performed in the exposed area, and the photoresist can act as a mask to essentially prevent the impurities from being implanted into the masked area. The n-impurities can be phosphorus, arsenic, or the like, up to a concentration equal to or less than 10 18 cm -3 , such as in the range of approximately 10 17 cm -3up to about 10 18 cm -3 , are implanted into the first area. The p-impurities can be boron, BF2, or the like, which are present at concentrations equal to or less than 10 18 cm -3 , such as in an area of ​​approximately 10 17 cm -3 up to about 10 18 cm -3 , are implanted into the first area. After implantation, the photoresist is removed, for example by a suitable ashing process.

[0016] Following the implantation of the trays, annealing can be performed to activate the implanted p- and / or n-impurities. In some embodiments, the substrate can have 20 epitaxially grown regions which are doped in situ during growth, potentially eliminating the need for implantation; however, in situ doping and implantation doping can also be used together.

[0017] The substrate 20 can accommodate active and passive devices (in Fig. (2 not shown). As the average person with expertise in this field will recognize, a wide variety of devices, such as transistors, capacitors, resistors, combinations thereof, and the like, can be used to meet the structural and functional requirements of the semiconductor device. The devices can be formed using any suitable method. Only a section of substrate 20 is shown in the figures, as this is sufficient to fully describe the illustrative embodiments.

[0018] Substrate 20 may also feature metallization layers (not shown). These metallization layers may be formed over the active and passive devices / components and designed to connect the various components to form a functional circuit. The metallization layers may be formed from alternating layers of dielectric (e.g., low k-dielectric material) and conductive material (e.g., copper) and may be formed by any suitable process (such as deposition, damascus, double damascus, or the like).

[0019] In some embodiments, the substrate 20 may have one or more fins that project above and between adjacent insulation areas. For example, the cross-sectional view of Fig. 2 along a longitudinal axis of a fin, for example along the cross-sectional view BB of Fig. The fin(s) can be arranged in a single plane. This fin or fins can be formed in several different processes. In one example, the fins can be formed by etching trenches into a substrate to form semiconductor strips; the trenches can be filled with a dielectric layer; and the dielectric layer can be deepened such that the semiconductor strips protrude from the dielectric layer to form fins. In another example, a dielectric layer can be formed over a top surface of a substrate; trenches can be etched through the dielectric layer; homoepitaxial structures can be grown epitaxially in the trenches; and the dielectric layer can be deepened such that the homoepitaxial structures protrude from the dielectric layer to form fins. In yet another example, heteroepitaxial structures can be used for the fins.For example, the semiconductor strips can be recessed, and a material different from the semiconductor strips can be epitaxially grown in their place. In yet another example, a dielectric layer can be formed over a top surface of a substrate; trenches can be etched through the dielectric layer; heteroepitaxial structures can be epitaxially grown in the trenches using a material different from the substrate; and the dielectric layer can be recessed such that the heteroepitaxial structures protrude from the dielectric layer to form fins.In some embodiments where homoepitaxial or heteroepitaxial structures are epitaxially grown, the grown materials can be doped in situ during growth, which can eliminate the need for prior and subsequent implantations. Doping in situ and doping by implantation can also be used together. Furthermore, it can also be advantageous to epitaxially grow a material in an NMOS region that differs from the material in a PMOS region. In various embodiments, the fins can be silicon-germanium (Si. x Ge 1-x, where x can be approximately between 0 and 100), silicon carbide, pure or essentially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, the available materials for forming a III-V compound semiconductor include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like.

[0020] The gate stacks 28 (comprising 28A and 28B) are formed over the substrate 20. The gate stacks 28 can include a dummy gate dielectric 22, a hard mask (not shown), and a dummy gate electrode 24. The dielectric dummy gate layer (not shown) can be formed by thermal oxidation, chemical vapor deposition (CVD), sputtering, or any other method known in the art for forming a gate dielectric. In some embodiments, the dielectric dummy gate layer comprises dielectric materials with a high dielectric constant (k-value), for example, greater than 3.9. The dielectric dummy gate materials include silicon nitrides, oxynitrides, and metal oxides such as HfO₂ and HfZrO₂. x , HfSiOx, HfTiO x , HfAlO x , the like, or combinations and multiple layers thereof.

[0021] The dummy gate electrode layer (not shown) can be formed over the dielectric dummy gate layer. The gate electrode layer can comprise a conductive material and can be selected from the group consisting of polycrystalline silicon (polysilicon), polycrystalline silicon-germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals. In one embodiment, amorphous silicon is deposited and recrystallized to produce polysilicon. The dummy gate electrode layer can be deposited / applied by physical vapor deposition (PVD), continuous vapor deposition (CVD), sputtering, or other techniques known in the art and used for depositing conductive materials.After deposition, the top surface of the dummy gate electrode layer typically exhibits a non-planar surface and can be planarized before structuring the dummy gate electrode layer or gate etching, for example, by a chemical-mechanical polishing (CMP) process. Ions may or may not be introduced into the dummy gate electrode layer at this stage. Ions can be introduced, for example, using ion implantation techniques.

[0022] A hard mask layer (not shown) is formed over the dummy gate electrode layer. The hard mask layer can be made of SiN, SiON, SiO2, the like, or a combination thereof. The hard mask layer is then patterned. Patterning of the hard mask layer can be achieved by depositing / applying mask material (not shown), such as a photoresist, over the hard mask layer. The mask material is then patterned, and the hard mask layer is etched according to the pattern to form hard masks. The dummy gate electrode layer and the dielectric dummy gate layer can be patterned to form the dummy gate electrodes 24 and the dummy gate dielectrics 22, respectively. The gate patterning process can be achieved by using the hard masks as a single structure and etching the dummy gate electrode layer and the dielectric dummy gate layer to form the gate stack 28.

[0023] After the formation of the gate stack 28, source / drain regions 30 can be formed in the substrate 20. These source / drain regions 30 can be doped by performing an implantation process to introduce suitable dopants that supplement the dopants already present in the substrate 20. In another embodiment, the source / drain regions 30 can be formed by creating wells (not shown) in the substrate 20 and growing material epitaxially in these wells. The source / drain regions 30 can be doped either by an implantation process as discussed above or by in-situ doping during material growth. In this embodiment, epitaxial source / drain regions 30 can comprise acceptable material suitable, for example, for n-FETs and / or p-FETs.If the substrate 20 is silicon in an n-configuration, for example, the epitaxial source / drain regions 30 can comprise silicon, SiC, SiCP, SiP, or the like. If the substrate 20 is silicon in an n-configuration, for example, the epitaxial source / drain regions 30 can comprise SiGe, SiGeB, Ge, GeSN, or the like. The epitaxial source / drain regions 30 can have raised surfaces and facets above the top surface of the substrate 20.

[0024] In one embodiment, the gate stack 28 and the source / drain regions 30 can form transistors, such as metal-oxide-semiconductor FETs (MOSFETs). In these embodiments, the MOSFETs can be implemented in a PMOS or an NMOS configuration. In a PMOS configuration, the substrate 20 is doped with n-type dopants and the source / drain regions 30 are doped with p-type dopants. In an NMOS configuration, the substrate is doped with p-type dopants and the source / drain regions 30 are doped with n-type dopants.

[0025] Gate spacer elements 26 are formed on opposite sides of the gate stacks 28. The gate spacer elements 26 are formed by depositing a spacer element layer (not shown) over the entire surface of the previously formed gate stacks 28.

[0026] In one embodiment, the gate spacers have a spacer separator layer, also referred to as a gate sealing spacer. The spacer separator layer can be made of SiN, SiC, SiGe, oxynitride, oxide, the like, or a combination thereof. The spacer layer can comprise SiN, oxynitride, SiC, SiON, oxide, combinations thereof, or the like, and can be formed by processes used to form such a layer, such as CVD, plasma-enhanced CVD (PECVD), low-pressure CVD (LPCVD), atomic layer deposition (ALD), sputtering, the like, or a combination thereof. The gate spacers 26 are then structured, for example, by anisotropic etching to remove the spacer layer from horizontal surfaces, such as the top surfaces of the gate stack 28 and a top surface of the substrate 20.

[0027] In another embodiment, the source / drain regions 30 can have a lightly doped region (sometimes referred to as an LDD region) and a heavily doped region. In this embodiment, before the gate spacers 26 are formed, the source / drain regions 30 are lightly doped by an implantation process using the gate stacks 28 as masks. After the gate spacers 26 have been formed, the source / drain regions 30 can then be heavily doped by an implantation process using the gate stacks 28 and the gate spacers 26 as masks. This creates lightly doped regions and heavily doped regions. The lightly doped regions are primarily located below the gate spacers 26, while the heavily doped regions are located outside the gate spacers along the substrate 20.

[0028] As in Fig. As shown in Figure 2, the gate stack 28B has a width that is greater than the widths of the dummy gate stacks 28A. Furthermore, the distance between the dummy gate stack 28B and the nearest dummy gate stack 28A is greater than the distance between the dummy gate stacks 28A. The positions of these different types of gate stacks 28 are intended to show different configurations of the disclosed embodiments, and the positions of the different gate stacks are not strictly limited to these positions.

[0029] Fig. Figure 3 shows the formation of an etch stop layer 32 over the substrate 20, the gate stacks 28, the gate spacers 26, and the source / drain regions 30. The etch stop layer 32 can be conformally applied / deposited over components on the substrate 20. In some embodiments, the etch stop layer 32 can be silicon nitride, silicon carbide, silicon oxide, low-k dielectrics such as carbon-doped oxides, extremely low-k dielectrics such as porous carbon-doped silicon dioxide, the like, or a combination thereof, and can be applied by CVD, PVD, ALD, a dielectric spin-on process, the like, or a combination thereof.

[0030] In Fig. 4 an intermediate layer dielectric (ILD) 34 is placed over the in the Fig. The structure shown in Figure 2 is applied. In one embodiment, the ILD 34 is a flowable film formed by a flowable CVD. In some embodiments, the ILD 34 is formed from oxides, such as silicon oxide, phosphorus silicate glass (PSG), boron silicate glass (BSG), boron-doped phosphorus silicate glass (BPSG), undoped silicate glass (USG), low k dielectrics, such as carbon-doped oxides, extremely low k dielectrics, such as porous carbon-doped silicon dioxide, a polymer, such as polyimide, the like, or a combination thereof. The low k dielectric materials can have k values ​​of less than 3.9. The ILD 34 can be applied by any suitable process, such as CVD, ALD, a spin-on dielectric (SOD) process, the like, or a combination thereof.

[0031] Furthermore, in Fig. 4. A planarization process, such as a CMP process, is performed to align the upper surface 34S of the ILD 34 with the upper surfaces 24S of the dummy gate electrodes 24 and the upper surfaces 32S of the etch stop layer 32. The CMP process can also remove any hard masks present on the dummy gate electrodes 24. Consequently, the upper surfaces 24S of the dummy gate electrodes 24 are exposed through the ILD 34.

[0032] In Fig. In step 5, the dummy gate electrodes 24 and the dummy gate dielectrics 22, which are arranged directly beneath the dummy gate electrodes 24, are removed in one or more etching steps, forming depressions 36. Each of the depressions 36 exposes a channel region of a corresponding FET in the embodiment in which MOSFETs are formed. Each of the channel regions is arranged between adjacent pairs of the source / drain regions 30. During removal, the dummy gate dielectrics 22 can be used as an etch stop layer when the dummy gate electrodes 24 are etched. The dummy gate dielectrics 22 can then be removed after the dummy gate electrodes 24 have been removed. The depressions 36 are defined by the exposed surfaces 20S of the substrate 20 and the exposed inner surfaces 26S of the gate spacer elements 26.

[0033] In Fig. 6. Dielectric gate layers 38 and gate electrodes 40 for replacement gates are formed. The dielectric gate layers 38 are conformally formed in recesses 36, such as on the upper surface of the substrate and on side walls of the gate spacer elements 26, and on an upper surface of the ILD 34. In some embodiments, the dielectric gate layers 38 comprise silicon oxide, silicon nitride, or multiple layers thereof. In other embodiments, the dielectric gate layers 38 comprise a high k-value dielectric material, and in these embodiments, the dielectric gate layers 38 may have a k-value greater than approximately 7.0 and may comprise a metal oxide or silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The methods for forming the dielectric gate layers 38 may include molecular beam deposition (MBD), ALD, PECVD, and the like.

[0034] Next, gate electrodes 40 are applied / deposited over the dielectric gate layers 38 and fill the remaining sections of the wells 36. The gate electrodes 40 can be made of a metal-containing material, such as TiN, TaN, TaC, Co, Ru, Al, combinations thereof, or multiple layers thereof. After the gate electrodes 40 have been filled, a planarization process, such as a CMP process, can be performed to remove the excess sections of the dielectric gate layers 38 and the material of the gate electrodes 40 that protrudes above the top surface of the ILD 34. The resulting remaining sections of the material of the gate electrodes 40 and the dielectric gate layers 38 thus form replacement gates 42.

[0035] In a complementary MOS implementation (CMOS implementation) with both NMOS and PMOS devices on the substrate 20, the formation of the dielectric gate layers 38 can take place simultaneously in both the PMOS and NMOS regions, so that the dielectric gate layers 38 are made of the same materials in both the PMOS and NMOS regions, and the formation of the gate electrodes 40 can take place simultaneously in both the PMOS and NMOS regions, so that the gate electrodes 40 are made of the same materials in both the PMOS and NMOS regions.In other embodiments, the dielectric gate layers 38 in the NMOS region and those in the PMOS region can be formed by different processes, so that the dielectric gate layers 38 in the NMOS region and those in the PMOS region can be made of different materials, and the gate electrodes 40 in the NMOS region and those in the PMOS region can be formed by different processes, so that the gate electrodes 40 in the NMOS region and those in the PMOS region can be made of different materials. When using different processes, several masking steps can be used to mask and expose appropriate regions.

[0036] In Fig. 7. In one or more etching steps, the gate electrodes 40 and the gate dielectrics 38 are recessed, forming depressions 44. These depressions 44 allow subsequently formed hard masks to be created within them to protect the replacement gates 42. The depressions 44 are defined by the exposed inner surfaces 26S of the gate spacers 26 and the recessed upper surfaces 40S and 38S of the gate electrodes 40 and the gate dielectrics 38, respectively.

[0037] Furthermore, the lower surfaces of the recesses 44 can have a flat surface, a convex surface, a concave surface (for example, a crown), or a combination thereof, as shown. The lower surfaces of the recesses 44 can be formed flat, convex, and / or concave by appropriate etching. The gate electrodes 40 and the gate dielectrics 38 can be recessed using an acceptable etching process, for example, a process that is selective for the materials of the gate electrodes 40 and the gate dielectrics 38.

[0038] In Fig. 8 A first hard mask layer 46 is formed over the ILD 34 and within the recesses 44 over the gate electrodes 40 and the gate dielectrics 38. The first hard mask layer 46 can be formed from SiN, SiON, SiO2, the like, or a combination thereof. The first hard mask layer 46 can be formed by CVD, PVD, ALD, a dielectric spin-on process, the like, or a combination thereof.

[0039] Fig. Figure 9 shows the recessing of the first hard mask layer 46 to form the recesses 50. The first hard mask layer 46, the etch stop layer 32 and the gate spacer elements 26 are recessed such that the upper surfaces 46S, 26T and 32S of the first hard mask layer 46, the etch stop layer 32 and the gate spacer elements 26 respectively are arranged below upper surfaces 34S of the ILD 34.

[0040] Furthermore, the lower surfaces of the depressions 50 can have a flat surface, a convex surface, a concave surface (for example, a bulge), or a combination thereof, as shown. The lower surfaces of the depressions 50 can be formed flat, convex, and / or concave by appropriate etching. The first hard mask layer 46 can be deepened using an acceptable etching process, such as one that is selective for the materials of the first hard mask layer 46, the etch stop layer 32, and the gate spacer element 26. An etching process can, for example, involve the formation of a reactive species from an etching gas using a plasma. In some embodiments, the plasma can be a remote plasma.In some embodiments, the etching gas may have a fluorocarbon chemistry, such as CH3F / CH2F2 / CHF3 / C4F6 / CF4 / C4F8 and NF3 / O2 / N2 / Ar / H2 / CH4 / CO / CO2 / COS, or a combination thereof. In some embodiments, the etching gas may be supplied to the etching chamber with a total gas flow rate of approximately 5 to approximately 1000 sccm (standard cubic centimeters). In some embodiments, the pressure of the etching chamber during the etching process is between approximately 1.33 Pa and approximately 6.66 Pa (approximately 10 mTorr to approximately 50 mTorr). In some embodiments, the etching gas may comprise between approximately 5 and approximately 95 percent hydrogen gas. In some embodiments, the etching gas may comprise between approximately 5 and approximately 95 percent inert gas.

[0041] In another embodiment, the etching can be a wet etching process using a suitable etchant, such as H3PO4 or the like. In such embodiments, a further mask (not shown) can be structured and used over the ILD 34 to provide protection for the ILD 34 during the etching process. While the mask layer 46 is etched and its thickness reduced, a lateral etch can extend from the mask layer 46 outwards over the gate electrodes 40 to remove exposed sections of the gate spacers 26 and the etch stop layer 32. In some embodiments, the lateral etch can extend partially into the sidewalls of the ILD 34.

[0042] In Fig. 10 A second hard mask layer 52 is formed over the first hard mask layer 46, the gate spacer elements 26, the etch stop layer 32, and the ILD 34, and within the recesses 50. The second hard mask layer 52 provides a surface during the subsequent self-aligning contact etching (see Fig. 13) provides protection for the first hard mask layer 46, the gate spacers 26, and the etch stop layer 32 to ensure that the self-aligning contact does not short-circuit any of the gate electrodes 40 with the relevant source / drain region 30, and to reduce leakage current between the self-aligning contact and the gate electrode 40. The second hard mask layer 52 can be made of silicon oxide, silicon nitride, a metal, a metal oxide, a metal nitride, a metal carbide, pure silicon, the like, or a combination thereof. Some examples of the metal oxides, metal nitrides, and metal carbides are TiO₂, HfO₂, AlO₂, ZrO₂, ZrN, WC, the like, or a combination thereof.

[0043] The material composition of the second hard mask layer 52 differs from the material of the first hard mask layer 46. When the recesses for the self-aligning contacts have been formed (see Fig. 13) The etch selectivity for the first hard mask layer 46 can be low. Thus, selecting a material with high etch selectivity for the second hard mask layer 52 provides less degradation of the protective layers over the gate electrodes 40 during etching of the recesses for the self-aligning contacts. In some embodiments, for example, the etch selectivity ratio of the first hard mask layer 48 can be less than 8, while the etch selectivity ratio of the second hard mask layer 52 can be greater than 15. The use of the second hard mask layer 52 enables improved protection of the gate electrodes 40. The second hard mask layer 52 can be formed by CVD, PVD, ALD, a dielectric spin-on process, the like, or a combination thereof.

[0044] In Fig. 11. A planarization process, such as a CMP process, can be performed to align the upper surface 34S of the ILD 34 with the upper surfaces 52S of the second hard mask layer 52. Consequently, the upper surfaces 34S of the ILD 34 are exposed. After planarization, the thickness of the second hard mask layer 52 can be between approximately 0.5 nm and approximately 10 nm, for example, approximately 5 nm.

[0045] In Fig. 12 will be an ILD 54 above the in Fig. The structure shown in Figure 11 is applied. In one embodiment, the ILD 54 is a flowable film formed by a flowable CVD. In some embodiments, the ILD 54 is formed from oxides, such as silicon dioxide, PSG, BSG, BPSG, USG, low k dielectrics, such as carbon-doped oxides, extremely low k dielectrics, such as porous carbon-doped silicon dioxide, a polymer, such as polyimide, the like, or a combination thereof. The low k dielectric materials may have k values ​​of less than 3.9. The ILD 54 can be applied by any suitable process, such as CVD, ALD, an SOD process, the like, or a combination thereof. In some embodiments, the ILD 54 is planarized by a CMP process or an etching process to form a substantially planar top surface.

[0046] Furthermore, in Fig. 12. A hard mask layer 56 is formed and structured over the ILD 54. The hard mask layer 56 can be formed from SiN, SiON, SiO2, TiN, TaN, WC, metal oxide, the like, or a combination thereof. The hard mask layer 56 can be formed by CVD, PVD, ALD, an SOD process, the like, or a combination thereof. The hard mask layer 56 is then structured. Structuring the hard mask layer 56 can be achieved by depositing / applying mask material (not shown), such as a photoresist, over the hard mask layer 56. The mask material is then structured, and the hard mask layer 56 is etched according to the structure to form a structured hard mask layer 56.

[0047] Fig. Figure 13 shows the formation of the openings 58 by the ILD 54 and by the ILD 34 using the structured hard mask layer 56 as a mask for exposing sections of the substrate 20. In the embodiment shown, the openings 58 expose surface sections 30S of the source / drain regions 30. Although sections of the opening 58 extend over the upper surfaces of the gate stacks 42, the second hard mask layer 52 and the etch stop layer 32 align the opening 58 between adjacent gate stacks 42 themselves onto the substrate 20. The openings 58 can be formed by using acceptable etching techniques. In one embodiment, the openings 58 are formed by an anisotropic dry etching process. For example, the etching process can include a dry etching process in which a reaction gas is used that selectively etches the ILD 54 and 34 without etching the second hard mask layer 52.As mentioned above, the etch selectivity ratio of the second hard mask layer 52 can be greater than 15, while the etch selectivity ratio of the first hard mask layer 46 can be less than 8. Thus, without the second hard mask layer 52, the first hard mask layer 48 would be etched during the formation of the openings 58, and could subsequently cause leakage currents or short circuits from the gate electrode 40 to the subsequently formed contact.

[0048] The etching process for forming the openings 58 may involve the formation of a reactive species from an etching gas using a plasma. In some embodiments, the plasma may be a remote plasma. The etching gas may have a fluorocarbon chemistry, such as CH3F / CH2F2 / CHF3 / C4F6 / CF4 / C4F8 and NF3 / O2 / N2 / Ar / H2 / CH4 / CO / CO2 / COS, the like, or a combination thereof. In some embodiments, the etching gas may be supplied to the etching chamber with a total gas flow rate of approximately 5 to approximately 1000 sccm (standard cubic centimeters). In some embodiments, the pressure of the etching chamber during the etching process is between approximately 1.33 Pa and approximately 6.66 Pa (approximately 10 mTorr and approximately 50 mTorr). Due to the high etch selectivity of the second hard mask layer 52, the second hard mask layer 52 acts as an etch stop layer and advantageously prevents damage to underlying elements (e.g.of the gate spacer element 26, the first hard mask layer 46, and the gate stack 42). If a second hard mask layer 52 is not present, the gate spacers 26, the first hard mask layers 46, and the gate stack 42 can be inadvertently damaged by the etching process. In some embodiments, the etching process used for the self-aligning aperture 58 can remove certain upper sections of the second hard mask layer 52 but does not completely etch through the second hard mask layer 52, so that the first hard mask layer 46, the gate spacers 26, and the covered sections of the etch stop layer 32 remain protected during the etching process. As shown in... Fig. As can be seen in Figure 13, other sections of the second hard mask layer 52, which are not located in the opening 58, are not etched. Thus, the second hard mask layer 52 can have different heights above the gate electrode after the etching process.

[0049] Fig. Figure 14 shows the formation of a conductive layer 60 in the openings 58. The conductive layer 60 in the opening 58 contacts the exposed surface of the substrate 20 and is arranged along exposed surfaces of the etch stop layer 32, the ILDs 34 and 54, and the upper surfaces of the second hard mask layer. In the embodiment shown, the conductive layer 60 in the openings 58 contacts the exposed surfaces of the source / drain regions 30.

[0050] In some embodiments, the conductive layer 60 includes a barrier layer 61. The barrier layer 61 helps to block diffusion of the subsequently formed conductive layer 60 into adjacent dielectric materials, such as the ILDs 34 and 54. The barrier layer 61 can be made of titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, cobalt, cobalt oxide, cobalt nitride, nickel, nickel oxide, nickel nitride, silicon carbide, oxygen-doped silicon carbide, nitrogen-doped silicon carbide, silicon nitride, aluminum oxide, aluminum nitride, aluminum oxynitride, a polymer such as polyimide, polybenzoxazole (PBO), the like, or a combination thereof. The barrier layer 61 can be formed by CVD, PVD, PECVD, ALD, SOD, the like, or a combination thereof. In some embodiments, the barrier layer 61 is omitted.

[0051] The conductive layer 60 can be made of tungsten, copper, aluminum, the like, or a combination thereof. The conductive layer 60 can be formed by a deposition process, such as electrochemical plating, PVD, CVD, the like, or a combination thereof. In some embodiments, the conductive layer 60 is formed on a copper-containing seed layer, such as AlCu.

[0052] In some embodiments, the conductive layer 60 is formed such that it has excess material arranged above an upper surface of the ILD 54. In these embodiments, the conductive layer 60 is planarized by a grinding process, such as a CMP process, to form conductive elements 601, 602, and 603 in the openings 58. In some embodiments, the upper surfaces of the conductive elements 601, 602, and 603 are arranged at the same level as the upper surfaces of the ILD 54 after the planarization process.

[0053] Fig. Figure 15 shows the removal of the ILD 54, the second hard mask layer 52, and the portion of the ILD 34 and the conductive layer 60 in planes above the upper surfaces of the first hard mask layer 46. This removal can be achieved by one or more etching and / or grinding processes, such as a CMP process. After the removal process, the conductive layer 60 is divided into the conductive elements 601, 602, and 603. Furthermore, after the removal process, the upper surfaces of the conductive elements 601, 602, and 603 are at the same level as the upper surfaces of the ILD 34 and the first hard mask layer 46.

[0054] Fig. Figure 16 shows the formation of an etch stop layer 62 over the structure of Fig. 15. The etch stop layer 62 is formed over the ILD 34, the etch stop layer 32, the first hard mask layer 46, and the gate spacers 26. The etch stop layer 62 can be conformally applied / deposited over these components. In some embodiments, the etch stop layer 62 can be silicon nitride, silicon carbide, silicon oxide, low-k dielectrics such as carbon-doped oxides, extremely low-k dielectrics such as porous carbon-doped silicon dioxide, the like, or a combination thereof, and can be applied by CVD, PVD, ALD, a dielectric spin-on process, the like, or a combination thereof.

[0055] Furthermore, in Fig. 16. An ILD 64 is applied over the etch stop layer 62. In one embodiment, the ILD 64 is a flowable film formed by a flowable CVD. In some embodiments, the ILD 64 is formed from oxides, such as silicon dioxide, PSG, BSG, BPSG, USG, low k dielectrics, such as carbon-doped oxides, extremely low k dielectrics, such as porous carbon-doped silicon dioxide, a polymer, such as polyimide, the like, or a combination thereof. The low k dielectric materials can have k values ​​of less than 3.9. The ILD 64 can be applied by any suitable process, such as CVD, ALD, an SOD process, the like, or a combination thereof.

[0056] Furthermore, in Fig. 16 The contacts 661, 662, and 663 (together the conductive layer 66) are formed by the ILD 64 and the etch stop layer 62 to electrically and physically contact the respective conductive elements 601, 602, and 603. The openings for the contacts 661, 662, and 663 can be formed by using acceptable etching techniques. In one embodiment, the openings are formed by an anisotropic dry etching process. These openings are filled with the material of the conductive layer 66.

[0057] In some embodiments, a separating layer 65 can be applied to line the openings. The separating layer 65 can be used to provide protection against subsequently formed gate contacts (see Fig. 30). The separating layer 65 can be conformally applied / deposited over the ILD 64 and in the openings of the conductive layer 66. In some embodiments, the separating layer 65 can be silicon nitride, silicon carbide, silicon oxide, low-k dielectrics such as carbon-doped oxides, extremely low-k dielectrics such as porous carbon-doped silicon dioxide, the like, or a combination thereof, and can be applied by CVD, PVD, ALD, a dielectric spin-on process, the like, or a combination thereof. After the formation of the separating layer 65, an anisotropic etching process can remove a lower portion of the separating layer 65 to expose the upper surface of the conductive elements 601, 602, and 603.

[0058] In some embodiments, the conductive layer 66 includes a barrier layer (not shown). The barrier layer helps to block diffusion of the subsequently formed conductive layer 66 into adjacent dielectric materials, such as the ILD 64 and the etch stop layer 62. The barrier layer can be made of titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, cobalt, cobalt oxide, cobalt nitride, nickel, nickel oxide, nickel nitride, silicon carbide, oxygen-doped silicon carbide, nitrogen-doped silicon carbide, silicon nitride, aluminum oxide, aluminum nitride, aluminum oxynitride, a polymer such as polyimide, PBO, the like, or a combination thereof. The barrier layer can be formed by CVD, PVD, PECVD, ALD, SOD, the like, or a combination thereof. In some embodiments, the barrier layer is omitted.

[0059] The conductive layer 66 can be made of tungsten, copper, aluminum, the like, or a combination thereof. The conductive layer 66 can be formed by a deposition process, such as electrochemical plating, PVD, CVD, the like, or a combination thereof. In some embodiments, the conductive layer 66 is formed on a copper-containing seed layer, such as AlCu.

[0060] In some embodiments, the conductive layer 66 is formed such that it has excess material arranged above an upper surface of the ILD 64. In these embodiments, the conductive layer 66 is planarized by a grinding process, such as a CMP process, to form the contacts 661, 662, and 663. In some embodiments, after the planarization process, the upper surfaces of the conductive element contacts 661, 662, and 663 are arranged at the same level as the upper surface of the ILD 64.

[0061] Fig. 17, Fig. 18, Fig. 19, Fig. 20, Fig. 21, Fig. 22, Fig. 23 to Fig. Figure 24 shows intermediate steps in the formation of a self-aligning contact in accordance with some embodiments. The in Fig. The structure shown in 17 results from the process described above in relation to the Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7 to Fig. Figure 8 is shown, followed by additional processes. Fig. Figure 17 shows the deepening of the first hard mask layer 46 of Fig. 8 for forming the depressions 50. The first hard mask layer 46, the etch stop layer 32 and the gate spacer elements 26 are recessed such that the upper surfaces 46S, 26T and 32S of the first hard mask layer 46, the etch stop layer 32 and the gate spacer elements 26 respectively are arranged below upper surfaces 34S of the ILD 34.

[0062] Furthermore, the lower surfaces of the depressions 50 can have a flat surface, a convex surface, a concave surface (for example, a crown), or a combination thereof, as shown. The lower surfaces of the depressions 50 can be formed flat, convex, and / or concave by appropriate etching. The first hard mask layer 46 can be deepened using an acceptable etching process, such as one that is selective for the materials of the first hard mask layer 46, the etch stop layer 32, and the gate spacer element 26. An etching process can, for example, involve the formation of a reactive species from an etching gas using a plasma. In some embodiments, the plasma can be a remote plasma.In some embodiments, the etching gas may have a fluorocarbon chemistry, such as CH3F / CH2F2 / CHF3 / C4F6 / CF4 / C4F8 and NF3 / O2 / N2 / Ar / H2 / CH4 / CO / CO2 / COS, or a combination thereof. In some embodiments, the etching gas may be supplied to the etching chamber with a total gas flow rate of approximately 5 to approximately 1000 sccm (standard cubic centimeters). In some embodiments, the pressure of the etching chamber during the etching process is between approximately 1.33 Pa and approximately 6.66 Pa (approximately 10 mTorr to approximately 50 mTorr). In some embodiments, the etching gas may comprise between approximately 5 and approximately 95 percent hydrogen gas. In some embodiments, the etching gas may comprise between approximately 5 and approximately 95 percent inert gas.

[0063] In another embodiment, the etching can be a wet etching process using a suitable etchant, such as H3PO4 or the like. In such embodiments, a further mask (not shown) can be structured and used over the ILD 34 to provide protection for the ILD 34 during the etching process. While the mask layer 46 is etched and its thickness reduced, a lateral etch can extend from the mask layer 46 outwards over the gate electrodes 40 to remove exposed sections of the gate spacers 26 and the etch stop layer 32. In some embodiments, the lateral etch can extend partially into the sidewalls of the ILD 34.

[0064] Furthermore, the exposed upper surfaces of the gate spacer elements 26 (and in some embodiments, the etch stop layer 32) can be recessed below an upper surface of the first hard mask layer 46 by prolonged etching of these layers and / or by changing the etching gas or process conditions. In some embodiments, the distance between the upper surface of the first hard mask layer 46 and the upper surface of the gate spacer element 26 can be between approximately 0.5 nm and approximately 10 nm, for example, approximately 4 nm. Recessing the upper surface of the gate spacer element 26 provides space for a subsequently formed second hard mask layer, which surrounds an upper portion of the first hard mask layer 46 to provide additional protection for the first hard mask layer 46 and the gate electrode 40, which is located beneath the first hard mask layer 46.

[0065] In Fig. 18 A second hard mask layer 52 is formed over the first hard mask layer 46, the gate spacer elements 26, the etch stop layer 32 and the ILD 34 and within the recesses 50. Fig. 18 is similar Fig. 10, where the same reference numbers denote the same elements which are formed using these processes.

[0066] In Fig. 19. A planarization process, such as a CMP process, can be performed to align the upper surface 34S of the ILD 34 with the upper surfaces 52S of the second hard mask layer 52. Consequently, the upper surfaces 34S of the ILD 34 are exposed. After planarization, the thickness of the second hard mask layer 52 above the first hard mask layer 46 can be between approximately 0.5 nm and approximately 10 nm, for example, approximately 5 nm. Thus, the thickness of the second hard mask layer 52 above the gate spacer element 26, as a result of the outer legs of the second hard mask layer 52 extending downwards along the sidewalls of the first hard mask layer 46, can be between approximately 1 nm and approximately 20 nm, for example, approximately 9 nm.

[0067] In Fig. 20 will see an ILD 54 above the in Fig. The structure shown in 19 is applied, and a hard mask layer 56 is formed and structured over the ILD 54. Fig. 20 is similar Fig. 12, where the same reference numbers denote the same elements which are formed using these processes.

[0068] Fig. Figure 21 shows the formation of the openings 58 by the ILD 54 and by the ILD 34 using the structured hard mask layer 56 as a mask to expose sections of the substrate 20. Fig. 21 is similar Fig. 13, where the same reference numerals denote the same elements formed using these processes. However, it should be noted that the downward-extending legs of the second hard mask layer 52 provide better protection for the first hard mask layer 46 than the second hard mask layer 52, which is in Fig. 13 is shown.

[0069] Fig. Figure 22 shows the formation of a conductive layer 60 in the openings 58. Fig. 22 is similar Fig. 14, where the same reference numbers denote the same elements which are formed using the same processes.

[0070] Fig. Figure 23 shows the removal of the ILD 54, sections of the second hard mask layer 52, and the section of the ILD 34 and the conductive layer 60 in planes above the upper surfaces of the first hard mask layer 46. This removal can be achieved by one or more etching and / or grinding processes, such as a CMP process. After the removal process, the conductive layer 60 is divided into the conductive elements 601, 602, and 603. Furthermore, after the removal process, the upper surfaces of the conductive elements 601, 602, and 603 are arranged at the same level as the upper surface of the ILD 34 and the first hard mask layer 46. In some embodiments, as in Fig. As shown in Figure 23, sections of the second hard mask layer 52 can remain on both sides of the first hard mask layer 46 above an upper surface of the gate spacer elements 26 and an upper surface of the etch stop layer 32. In other embodiments, these sections of the second hard mask layer 52 can be removed by the removal process of Fig. 23, that is, the removal of the first hard mask layer 46 and the second hard mask layer 52 until the second hard mask layer 52 has been completely removed.

[0071] Fig. Figure 24 shows the formation of an etch stop layer 62 over the structure of Fig. 23. Furthermore, in Fig. 24 an ILD 64 is applied over the etch stop layer 62, and the contacts 661, 662 and 663 are formed by the ILD 64 and the etch stop layer 62 to electrically and physically contact the respective conductive elements 601, 602 and 603. Fig. 24 is similar Fig. 16, where the same reference numbers denote the same elements which are formed using these processes.

[0072] Fig. 25, Fig. 26, Fig. 27, Fig. 28, Fig. 29, Fig. 30 to Fig. Figure 31 shows a process of forming a mask layer over contacts 661, 662, and 663 to provide protection for contacts 661, 662, and 663 during a subsequent process of forming gate contacts. The Fig. 25, Fig. 26, Fig. 27, Fig. 28, Fig. 29, Fig. 30 to Fig. The process shown in 31 is based on the one in Fig. 16 shown structure, although it is understood that the process also depends on the structure as shown in Fig. 24 shown, is, can be done. In Fig. 25 The upper surfaces of contacts 661, 662 and 663 are recessed. The contacts 661, 662 and 663 can be recessed using a suitable etching technique to remove a section of the conductive material of contacts 661, 662 and 663 and to form the recesses 70.

[0073] In Fig. 26 A first hard mask layer 72 is formed over the ILD 64 and within the recesses 70 over the contacts 661, 662 and 663. The first hard mask layer 72 can be formed from SiN, SiON, SiO2, the like, or a combination thereof. The first hard mask layer 72 can be formed by CVD, PVD, ALD, a dielectric spin-on process, the like, or a combination thereof.

[0074] In Fig. 27 The first hard mask layer 72 can be deepened to form the depressions 74. The lower surfaces of the depressions 74 can have a flat surface, a convex surface, a concave surface (for example, a camber), or a combination thereof, as shown. The lower surfaces of the depressions 74 can be formed flat, convex, and / or concave by appropriate etching. The first hard mask layer 72 can be deepened using an acceptable etching process, such as one that is selective for the materials of the first hard mask layer 72. The etching can be carried out using processes and materials similar to those discussed above with respect to the first hard mask layer 46.

[0075] In Fig. 28 A second hard mask layer 76 is formed over the first hard mask layer 72 within the recesses 74. The second hard mask layer 76 provides protection for the contacts 661, 662, and 663 during the formation of a self-aligning gate contact to prevent the gate contact from short-circuiting with the contacts 661, 662, and 663. The second hard mask layer 76 can be formed using similar processes and materials to those described above in relation to the second hard mask layer 52 of Fig. 10 are described, are formed.

[0076] In Fig. 29 the second hard mask layer 76 can be recessed, for example, using a planarization process, so that the upper surface of the second hard mask layer is at the same level as an upper surface of the ILD 64.

[0077] In Fig. In section 30, an ILD 78 is applied over the ILD 64 and structured to form openings for the gate contacts 80. It is understood that although the gate contact 80 is shown in this cross-section, it can be arranged in other cross-sections. As shown in Fig. As shown in Figure 30, the second hard mask 76 prevents the opening that is formed from exposing the contact 662. The gate contact 80 subsequently formed can have a section of the second hard mask 76 embedded within the gate contact 80. The separating layer 65 also provides sidewall protection for the contact 662 during the formation of the opening for the gate contact 80.

[0078] Gate contact 80 can be formed using any suitable process. For example, gate contact 80 can be formed using similar processes and materials to those discussed above regarding the formation of contacts 661, 662, and 663. It is also understood, however, that the Fig. 30 serves only as an illustration, and additional gate contacts can be formed simultaneously. As in Fig. As shown in Figure 30, a separating layer 65 can be used which is similar to the one discussed above in relation to the formation of contacts 661, 662 and 663.

[0079] In some embodiments, the gate contact 80 is formed such that it has excess material arranged above an upper surface of the ILD 78. In these embodiments, the gate contact 80 is planarized by a grinding process, such as a CMP process, to form the individual gate contacts. In some embodiments, the upper surfaces of the gate contacts 80 are arranged at the same level as the upper surface of the ILD 78 after the planarization process.

[0080] Fig.Figure 31 shows the removal of the ILD 78, the second hard mask layer 76, the first hard mask layer 72, a section of the ILD 64, and an upper section of the gate contacts 80 to bring the upper surfaces of the ILD 64 and the gate contacts 80 to the same level as the upper surfaces of the contacts 661, 662, and 663. This removal can be carried out by one or more etching and / or grinding processes, such as a CMP process.

[0081] Embodiments of the present disclosure provide a self-aligning contact formation process which employs a second hard mask layer protecting a first hard mask layer. The second hard mask layer exhibits greater etch selectivity compared to the first hard mask layer and therefore provides better protection during the formation of the self-aligning contact opening. A similar process can be used to provide a series of hard mask layers over the source / drain contact to protect the source / drain contact during a gate-drain self-aligning contact process.

[0082] One embodiment is a method comprising forming a first gate over a substrate, forming a first dielectric layer over the substrate and around the first gate, and forming a first hard mask layer over the first gate. The first hard mask exhibits a first etch selectivity. A second hard mask layer is formed over the first hard mask layer, the second hard mask exhibiting an etch selectivity greater than the first. A second dielectric layer is formed over the first gate and the first dielectric layer. A first opening is etched through the second dielectric layer and the first dielectric layer to expose a first source / drain region adjacent to the first gate and a second source / drain region adjacent to the first gate, the second etch selectivity of the second hard mask layer protecting the first hard mask from being etched.The first opening is filled with a conductive material. The second hard mask layer, the conductive material, and the second dielectric layer are recessed to bring the upper surfaces of the first hard mask layer, the conductive material, and the first dielectric layer to the same level, with the recessed conductive material forming a first conductive contact with the first source / drain region and a second conductive contact with the second source / drain region.

[0083] Another embodiment is a method comprising forming a first metal gate over a substrate, the first metal gate having first gate spacers on opposite side walls of the first metal gate. A first dielectric layer is formed over the substrate and adjacent to the first metal gate. The first metal gate is recessed to have an upper surface beneath an upper surface of the first dielectric layer. A first hard mask layer is formed on the recessed upper surface of the first metal gate. The first hard mask layer and the first gate spacers are recessed to have upper surfaces beneath the upper surface of the first dielectric layer. The first gate spacers are recessed to have upper surfaces beneath the upper surface of the first hard mask layer.A second hard mask layer is applied to the recessed upper surfaces of the first hard mask layer and the first gate spacer elements, with the second hard mask layer extending downwards along a side wall of the first hard mask layer.

[0084] Another embodiment comprises a device comprising a first gate, the first gate comprising a gate dielectric, a gate electrode, and first gate spacers arranged on opposite sides of the gate electrode. The device also comprises a first hard mask layer over the gate electrode, wherein the first gate spacers extend along a first section of the sidewalls of the first hard mask layer. The device further comprises a second hard mask layer arranged over the first gate spacers, wherein the second hard mask layer is formed of a different material than the material of the first hard mask layer, and the second hard mask layer extends along a second section of the sidewalls of the first hard mask layer. The device also comprises a first source / drain contact adjacent to the first gate spacers.

Claims

[1] Procedure encompassing: Forming a first gate (42) over a substrate (20), wherein the first gate has a first gate electrode (40) between first gate spacer elements (26); Forming a first dielectric layer (34) over the substrate (20) and surrounding the first gate; Forming a first hard mask layer (46) over the first gate, wherein the first hard mask exhibits a first etch selectivity; Deepening the first hard mask layer (46) to expose the upper surfaces of the first gate spacer elements, Recessing the upper surfaces of the first gate spacer elements (26) so that the upper surfaces of the first gate spacer elements are arranged below the upper surfaces of the first hard mask layer (46); and Form a second hard mask layer (52) over the first hard mask layer (46) such that it extends downwards along the side walls of the first hard mask layer (46) and contacts the upper surfaces of the first gate spacer elements (26), wherein the second hard mask has a second etch selectivity which is greater than the first etch selectivity. [2] The method of claim 1, further comprising: Forming a second dielectric layer (54) over the first gate and the first dielectric layer; Etching a first opening (58) through the second dielectric layer and the first dielectric layer to expose a first source / drain region (30) adjacent to the first gate and a second source / drain region adjacent to the first gate, wherein the second etch selectivity of the second hard mask protects the first hard mask from being etched; Filling the first opening with a conductive material (60); and Recessing the second hard mask layer (52), the conductive material and the second dielectric layer to bring the upper surfaces of the first hard mask layer (46), the conductive material and the first dielectric layer to the same height, wherein the recessed conductive material forms a first conductive contact (601) to the first source / drain region and a second conductive contact (602) to the second source / drain region. [3] Method according to claim 1 or 2, wherein the second hard mask layer (52) is arranged on the upper surfaces of the first gate spacer elements (26). [4] Method according to claim 1, 2 or 3, wherein the upper surfaces of the first gate spacer elements are arranged 0.5 nm to 10 nm below the upper surfaces of the hard mask layer (46, 52, 56). [5] Method according to any of the foregoing claims, further comprising: Forming an etch stop layer (32) over the first gate spacer elements, wherein etching the first opening exposes the etch stop layer (32) at the first gate spacer elements. [6] Method according to any of the preceding claims, wherein the second hard mask layer (52) comprises silicon, a metal oxide or tungsten carbide. [7] Method according to any of the foregoing claims, further comprising: Forming a third conductive contact above the first conductive contact; Deepening the third conductive contact; Forming a third hard mask layer over the third conductive contact; and Forming a fourth hard mask layer over the third conductive contact. [8] Procedure encompassing: Forming a first metal gate (42) over a substrate (20), the first metal gate having first gate spacer elements (26) on opposite side walls of the first metal gate (42); Forming a first dielectric layer (34) over the substrate (20) and adjacent to the first metal gate; Recessing the first metal gate (42) such that it has an upper surface below an upper surface of the first dielectric layer (34); Forming a first hard mask layer (46) on the recessed upper surface of the first metal gate; Recessing the first hard mask layer (46) and the first gate spacer elements (26) such that these have upper surfaces below the upper surface of the first dielectric layer; Recessing the first gate spacer elements (26) such that their upper surfaces are below the upper surface of the first hard mask layer (46); and Deposition of a second hard mask layer (52) on the recessed upper surfaces of the first hard mask layer (46) and the first gate spacer elements (26), wherein the second hard mask layer (52) extends downwards along a side wall of the first hard mask layer (46). [9] The method of claim 8, further comprising: Leveling the second hard mask layer (52) such that it has an upper surface at the same height as the upper surface of the first dielectric layer (34). [10] Method according to claim 8 or 9, wherein the second hard mask layer (52) comprises silicon, a metal oxide or tungsten carbide. [11] Method according to any one of claims 8 to 10, wherein the first hard mask layer (46) comprises silicon nitride. [12] Method according to any one of claims 8 to 11, wherein the first metal gate (42) comprises a dielectric gate layer (38) with high k on the substrate (20) and along inner side walls of the first gate spacer elements and a metal gate electrode on the dielectric gate layer (38) with high k. [13] Method according to any one of claims 8 to 12, further comprising: Forming a second dielectric layer (54) over the second hard mask layer (52) and the first hard mask layer (46); Etching a first opening (58) through the second and the first dielectric layer to expose a section of the substrate (20), exposing an upper surface of the second hard mask layer (52) in the first opening; Filling the first opening with a conductive material (60); and Removing the second dielectric layer (54) and the second hard mask layer (52) and the sections of conductive material as well as the second and first dielectric layers above the first hard mask layer (46) to form a first conductive contact in the first dielectric layer. [14] The method of claim 13, further comprising: after removing the second dielectric layer (54) and the second hard mask layer (52) and the sections of conductive material as well as the second and the first dielectric layer above the first hard mask layer (46), forming a third dielectric layer above the first hard mask layer (46) and the first dielectric layer; and Formation of a second conductive contact through the third dielectric layer to the first conductive contact. [15] The method of claim 14, further comprising: Deepening of an upper surface of the second conductive contact; Forming a third mask layer over the second conductive contact; and Forming a fourth mask layer over the third mask layer, wherein the fourth mask layer comprises silicon, a metal oxide or tungsten carbide. [16] Device comprising: a first gate (42), the first gate comprising a gate dielectric (38), a gate electrode (40) and first gate spacer elements (26) arranged on opposite sides of the gate electrode; a first hard mask layer (46) over the gate electrode, wherein the first gate spacer elements (26) extend along a first section of side walls of the first hard mask layer (46) to a height below the top surface of the first hard mask layer (46); a second hard mask layer (52) arranged over the first gate spacer elements (26), wherein the second hard mask layer is made of a different material than the material of the first hard mask layer, and wherein the second hard mask layer has outer legs which extend along a second section of the side walls of the first hard mask layer and contact the upper surfaces of the first gate spacer elements (26). [17] Device according to claim 16, further comprising a first source / drain contact adjacent to the first gate spacer elements. [18] Device according to claim 17, wherein the first source / drain contact is in contact with the second hard mask layer (52). [19] Device according to claim 17 or 18, further comprising: a dielectric intermediate layer (ILD layer) arranged over the first gate; and a second source / drain contact embedded in the ILD layer, wherein the second source / drain contact is electrically and physically coupled to the first source / drain contact and the second source / drain contact is in physical contact with the second hard mask layer (52). [20] Device according to any one of claims 16 to 19, wherein the second hard mask layer comprises silicon, a metal oxide or tungsten carbide.

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