Multi-stage preloading of bit line

Abstract

a memory circuit comprising: a bit cell (202) that responds to a bit line signal line (BL) and a bit line bar signal line (BLB) configured to store a data bit; a preload circuit (108) configured to load one bit from the bit line signal line and the bit line bar signal line prior to the next read operation, wherein the preload circuit (108) comprises: - a first preload component (210); and - a second preload component (212); wherein the first preload component (210) and the second preload component (212) are individually controllable for loading the bit line signal line (BL) and the bit line bar signal line (BLB), wherein the bit cell is a component of a first memory bank; wherein the first preload component (210) is also configured to act as a second preload component for a second memory bank.

Description

BACKGROUND A bit cell of a memory (e.g., an SRAM device) can take the form of two cross-coupled inverters acting as latch memory elements and two switches connecting the two inverters with complementary bit lines to communicate data to or from the bit cell. The switches (e.g., NMOS pass transistors) are controlled by a word line. When the switches are off, the bit cell maintains one of its two possible steady states. To write data to a bit cell, the value to be written and its complement are placed on the bit lines, and simultaneously, the word line is raised. To read a value from the bit cell, both bit lines are pre-charged high, and the word line is raised. The bit line begins to discharge relative to the bit cell node containing a zero value, providing distinct signals that can be captured and output from the memory.From US 2011 / 0 149 662 A1, a storage circuit with a bit cell is known that responds to a bit line signal line and a bit line bar signal line and is configured to store a data bit. The storage circuit further includes a preload circuit configured to load one bit from the bit line signal line and the bit line bar signal line before the next read operation. Similar devices and methods are also disclosed in US 2017 0 040 052 A1, US 2016 / 0 307 618 A1, and US 2019 / 0 147 924 A1. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with standard industry practice, several features are not drawn to scale. In fact, the dimensions of the various features may have been enlarged or reduced arbitrarily for clarity. Fig. 1 is a block diagram showing a memory containing a multi-stage preload circuit according to one exemplary embodiment. Fig. 2 is a diagram showing a bit cell and a multi-stage preload circuit according to embodiments. Fig. 3 provides timing diagrams associated with exemplary operations in embodiments of the disclosure.Figure 4 is a block diagram showing a preload module for controlling a first preload component and a second preload component of a preload circuit according to embodiments. Figure 5 shows exemplary preload components according to embodiments. Figure 6 is a diagram showing another exemplary preload circuit according to one embodiment. Figure 7 is a diagram showing the operation of control signals for limiting a certain order of magnitude of word line coupling according to embodiments. Figure 8 is a diagram showing a memory circuit in which a first preload component also serves as a second preload component for another memory bank, according to embodiments. Figure 9 is a flowchart showing a method for controlling a multi-stage preload circuit for loading a bit line and bit line bar signal line associated with a bit cell prior to a read operation according to embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments or examples of the implementation of various features of the subject matter. Specific examples of the components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on top of a second feature in the description that follows may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features are formed between the first and second features, so that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplification and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed. Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and the like may be used herein to simplify the description and to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. It is intended that the spatially relative terms include different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may also be oriented differently (rotated by 90 degrees or other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. As mentioned above, in certain types of memory, read operations are initiated by preloading two bit lines (e.g., BL, BLB) to which a bit cell is connected at a high level. When a word line (e.g., WL) of the bit cell is activated, the bit cell pulls one of the bit lines deep. A read amplifier detects the difference between the two bit lines and outputs a corresponding data value. The bit lines are then reloaded to enable the next read operation. To enable high-speed operation, it may be desirable to start the next preload cycle immediately after the previous read is completed (e.g., starting the preload immediately after the WL has gone deep). In some cases, such as due to manufacturing process variations, the desired timing cannot be achieved in practice. Untimely signals (e.g.,A preload control signal that is activated before the word line has gone deep can result in anomalous operation. Coupling between a load bit line and a word line, for example, can result in a disturbance of the bit cell state, potentially changing a bit cell value during a read operation. Fig. 1 is a block diagram showing a memory containing a multi-stage preload circuit according to an exemplary embodiment. A memory 100 contains a two-dimensional array of SRAM bit cells. Each row 102 of bit cells is connected to a word line WL[0]...WL[n], which provides control of the bit cells of a data word. Each column 104 of bit cells is assigned to an input / output (IO) circuit 106, which contains a multi-stage preload circuit 108. The multi-stage preload circuits 108 receive first and second control signals from a preload control circuit 110, which manages preload operations in the preload circuits 108. Fig. 2 is a diagram showing a bit cell and a multi-stage preload circuit according to embodiments. As described above, a bit cell 202 comprises a pair of cross-coupled inverters formed via two NMOS and two PMOS transistors. Data is applied to the bit cell 202 by applying different signal levels to the T and C nodes of the bit cell during a write operation via BL and BLB by controlling the switching transistors 204, 206 using the WL signal. Upon deassertion of the WL signal, the applied differential signals at the T and C nodes are maintained, indicating a stored data value (e.g., 1 when T is high and C is low, and 0 when T is low and C is high, or vice versa). During a read operation, both BL and BLB are pre-charged high. When the read operation is initiated by declaration of WL, the low-state T or C node pulls its corresponding bit line through the ground node (i.e., if T is low, BL is pulled low upon declaration of WL; if C is low, BLB is pulled low upon declaration of WL). A read amplifier detects the polarity of the difference between BL and BLB and outputs the corresponding value of the bit read from bit cell 202. The low bit line must then be pre-charged (recharged) before another read operation can occur. Thus, the pre-charge time limits the rate at which data can be read from memory. An example of a two-stage pre-charge circuit is shown at 208. The pre-charge circuit includes a first pre-charge component 210, designated as a weak pre-charge, and a second pre-charge component 212. The first 210 and second 212 pre-charge components are individually controllable for charging the BL and BLB signal lines. In particular, a pre-charge control circuit, described in more detail below, provides a first control signal (BLEQB1) to the first pre-charge component 210 and a second control signal (BLEQB2) to the second pre-charge component 212. A multi-stage pre-charge circuit, such as the one illustrated in Fig. 2 at 208, can provide fast storage operation while avoiding anomalous storage operation. As mentioned above, to minimize preload-related latency, it may be desirable to start the next preload cycle as soon as possible after the completion of a read operation. Fig. 3 provides timing diagrams that correspond to exemplary operations in embodiments of the disclosure. In a first example, a preload circuit at 302 is operated depending on only a single stage (e.g., the second preload component 212 of Fig. 2). When operating in the specification, the control signal BLEQB for the single stage transitions from a high to a low level to start preloading as soon as possible after the completion of a read operation, the duration of which is indicated by the high WL signal. In particular, during the read operation, which begins when WL transitions are high, a BL / BLB signal is pulled low by the specific T / C node, which maintains a low logic level.The pulling of BL / BLB down is illustrated by the downward-sloping BL / BLB signal. At one point during the read operation (e.g., near the end of the period when WL is high), a read amplifier detects the difference between BL and BLB caused by one of the signals being pulled down, with the read amplifier outputting a corresponding captured data value for the bit cell. The BL / BLB signal that was pulled down must then be brought back to a high level (i.e., preloaded) to allow for the next read operation. Some implementations aim to initiate preloading by bringing BLEQB down as soon as the read operation is complete, when WL is low, to prepare the bit cell for the next read operation, with both BL and BLB at a high level. In practice, however, signal timing in a memory may not work exactly as intended. Process fluctuations, parasitic capacitances, or other factors can cause signals to be received at a different time than planned. An example of such anomalous signal operation is illustrated in Figure 304. Here, the preload control signal BLEQB, which was intended to transition to low immediately after WL goes low, actually goes low before WL goes low at the end of the read operation. This results in BL / BLB, which was pulled low by the read operation, being prematurely reloaded to a high level while WL is still high. The rising BL / BLB signal can result in coupling with the WL signal, as illustrated in Figure 306, which in some cases can interfere with the contents of the T / C nodes in the bit cell, as illustrated in Figure 308.Here, the levels at the T and C nodes, and consequently the content of the bit cell, are changed during a read operation, resulting in an anomalous outcome. The example at 310 illustrates the control of a multi-stage preload circuit, which in embodiments enables rapid preloading while mitigating the risk of anomalous circuit behavior. Specifically, a first preload component (e.g., Fig. 2, Fig. 210) is controlled by a first control signal BLEQB1, and a second preload component (e.g., Fig. 2, Fig. 212) is controlled by a second control signal BLEQB2. In this example, the first control signal BLEQB1 activates the first preload component at 312 before the read operation is complete and before WL goes deep. The one BL / BLB that has been pulled deep begins to preload, but more slowly than in the examples at 302 and 304. At 314, the second control signal BLEQB2 activates the second preload component after WL has gone deep at the end of the read operation. This activation increases the rate of preloading of the BL / BLB to a high level (e.g.,When the first preload component is configured to load at an initial average rate between 312 and 314, and the second preload component is configured, alone or in combination with the first preload component, to load at a second average rate after 314 (the second average rate being faster than the first average rate), although some coupling may occur between the BL / BLB signal line being loaded and the WL signal at 316, with corresponding minor disturbances at the T / C nodes between 312 and 314, these disturbances are insufficient to disrupt the bit cell data content (e.g., flip). Fig. 4 is a block diagram showing a preload module for controlling a first preload component and a second preload component of a preload circuit according to embodiments. A preload control circuit 110 responds to a timer 402 and an input signal 404 indicating that a read operation will occur (e.g., the WL signal itself or another indicator). The preload control circuit 110 includes a first preload controller 406, which outputs a first control signal (BLEQB1) for controlling a first preload component, and a second preload controller 408, which outputs a second control signal (BLEQB2) for controlling a second preload component. In one example, upon receiving a read indication signal 404, the first and second preload controllers 406 and 408 ensure that their control signals BLEQB1 and BLEQB2 are in states that prevent preloading during part or all of the read operation.Based on a known time associated with a read operation and signals from the timing circuit (e.g., a clock circuit) 402, the pre-charge control circuit 110 controls the start of pre-charging the BL / BLB line that is being pulled deep. In one example, the first pre-charge control 406 is configured to activate a first pre-charge component via BLEQB1 shortly before the read operation is completed (e.g., at 90% of the read operation duration before WL goes deep). The second pre-charge control 408 is configured to activate the second pre-charge component, which can operate alone or together with the first pre-charge component, via BLEQB2 immediately after the read operation is completed (e.g., at 110% of the read operation duration). Since the BL / BLB line is partially pre-charged when the read operation is completed, the second control signal can be explained later than in single-stage pre-charge implementations (e.g.,(not so close to the WL transition), to avoid anomalous operation, while the BL / BLB line is still immediately returned to a high level. Preload components of a preload circuit can take various forms. Fig. 5 shows exemplary preload components according to embodiments. In a first example 502, a preload component (e.g., Fig. 2, Fig. 210) has the form of an NMOS transistor positioned between a source node and a node connected to both the bit line(s), one of which is preloaded. When the first control signal BLEQ1 is high, the preload component is activated. In a second example 504, the preload component comprises two PMOS transistors connected in series between a source node and a node connected to both the bit line / bit line bar signal lines. The two transistors have gates controlled by the first control signal. When the first control signal, BLEQB1, is low, the preload component is activated. In a third example 506, the first preload component comprises two PMOS transistors connected in series between a source node and the bit line / bit line bar signal lines. The first of the two transistors has a gate controlled by the first control signal. The second of the two transistors has a gate controlled by a signal based on a signal level at a node connected to both the bit line / bit line bar signal lines. When the first control signal BLEQB1 and one of the BL / BLB signals is low, the preload component is activated. In a fourth example 508, the first preload component comprises a PMOS transistor between a second control signal and a node connected between both the bit line / bit line bar signal lines, the transistor having a gate controlled by the first control signal. When the first control signal BLEQB1 is low and the second control signal is high (e.g., when the second control signal blocks the second preload component), the preload component is enabled. Fig. 6 is a diagram showing another exemplary preload circuit according to one embodiment. In the example of Fig. 6, a preload circuit includes a first preload component 602 and a second preload component 604. The first preload component 602 comprises a PMOS transistor between a first node 606, which is connected to the bit line signal line, and a second node 608, which is connected to the bit line bar signal line, the transistor having a gate that is controlled by the first control signal BLEQB. The second preload component 604 comprises two second-stage transistors whose gates are controlled by the second control signal BLPREB, one second-stage transistor being positioned between a source node and the first node 606, and the other second-stage transistor being positioned between the source node and the second node 608. In an example of the operation of the preload circuit in Fig.6. The control signals BLEQB and BLPREB are raised to high levels close to the time (e.g., immediately before, simultaneously with, or immediately after) when the WL goes high, in order to initiate a read operation. One of BL / BLB is pulled low over time according to the state of the T and C nodes. Before the read operation ends, when the WL goes low, the first control signal, BLEQB, is pulled low to initiate preloading via the first preload component 602. The one of BL / BLB that was pulled low begins to preload high by pulling the other bit line low to some extent through matching during the remainder of the read operation. This can lead to some coupling and corresponding effects on the WL signal. However, this coupling is not sufficient to affect the state of the T / C nodes.After completion of the read operation, the second control signal BLPREB, when WL becomes low, is brought low to initiate pre-charging via the second pre-charging component 604 in combination with the first pre-charging component 602, which immediately brings BL and BLB to high states in preparation for the next read operation. As mentioned above, coupling between a pre-loaded BL / BLB and the WL signal can lead to anomalous bit cell behavior. In some embodiments, it is desirable to limit this coupling by an order of magnitude. Fig. 7 is a diagram showing the operation of control signals to limit word line coupling by an order of magnitude according to embodiments. When operating the pre-load circuit in Fig. 6, a first simulation illustrates operation of only the second pre-load component 604 via the BLPREB signal activation immediately before the WL signal goes low. In this simulation, the BLB signal was pulled low during the read operation and is reloaded at high speed when BLPREB goes low, resulting in a 124 mV disturbance of the WL line. The second 704 and the third 706 simulations both utilize preload components 602 and 604, respectively, as shown in Fig. 6. In the second simulation, 704 activates the first control signal, BLEQB, initiating preload of BLB and a corresponding deep pull of BL via compensation, which occurs when the first preload component is activated. This results in a 46 mV disturbance of the WL line, reducing the risk of anomalous bit cell behavior compared to the 124 mV disturbance in 702. The BL / BLB signals are pulled high for the remainder of the path by activating the second preload component when BLPREB goes deep, immediately before the WL goes deep. In the third simulation, 706, the first control signal, BLEQB (and the first pre-charge component), is activated earlier than in the second simulation, 704. This results in an even lower WL disturbance of 10 mV, illustrating that the timing of the activation of the first and second pre-charge components can be controlled to reduce bit line to WL coupling to an acceptable level. A first preload component can be positioned at various locations in a memory circuit. Fig. 8 is a diagram showing a memory circuit in which a first preload component also serves as a second preload component for another memory bank, according to embodiments. In particular, a BL of an upper memory bank BL_UP is connected to a BL of a lower memory bank BL_DN via a PMOS transistor controlled by a BNKEQB control signal. Similarly, a BLB of an upper memory bank BLB_UP is connected to a BLB of a lower memory bank BLB_BN via another PMOS transistor controlled by a BNKEQB control signal. During an upper bank read operation, a word line associated with the upper bank, WL_UP, goes high, and a control signal for the upper bank's preload circuit, BLEQB_UP and BNKEQB, goes high to prevent preloading during the read operation. This allows one of BL_UP / BLB_UP to be deep-pulled according to the corresponding data stored in the upper bank bit cell. Since no read operation occurs in the lower bank, BL_DN and BLB_DN have been loaded high. The connections to the upper bank, BL / BLB, via the two PMOS transistors controlled by BNKEQB, enable BL_DN and BLB_DN to be used as a source for a first-stage preload of BL_UP / BLB_UP upon completion of the upper bank read operation. Specifically, BNKEQB is de-energized towards the end of the read operation (e.g.,Before WL_UP goes deep, BL_UP is brought deep to allow some pre-charging of BL_UP / BLB_UP from the BL_DN / BLB_DN lines, so that the lower bank's pre-charging circuit 804 acts as both a first pre-charging component for the upper bank and a second pre-charging component for the lower bank. Later, BLEQB_UP is brought deep, which allows the rest of the BL_UP / BLB_UP pre-charging. Fig. 9 is a flowchart showing a method for controlling a multi-stage preload circuit for loading a bit line and bit line bar signal line associated with a bit cell prior to a read operation according to embodiments. The method is described with reference to the structures described above for better understanding, but the method is also applicable to many other structures. The method includes providing a first control signal (BLEQB1) to a first preload circuit (210), which prevents loading at least during part of a read operation at 902, whereby a word line (WL) associated with the bit cell (202) is activated during the read operation. A second control signal (BLEQB2) is provided at 904 to a second preload circuit (212), which prevents loading during at least part of a read operation.The first control signal (BLEQB1) is passed through at 906 to allow charging by the first pre-charge circuit (210) before deactivation of the word line (WL), and the second control signal (BLEQB2) is passed through at 908 to allow charging by the second pre-charge circuit (212) after the first control signal (BLEQB1) has passed. The invention is defined by the main claim and the dependent claims. Further embodiments of the invention are described by the dependent claims.

Claims

a memory circuit comprising: a bit cell (202) that responds to a bit line signal line (BL) and a bit line bar signal line (BLB) configured to store a data bit; a preload circuit (108) configured to load one bit from the bit line signal line and the bit line bar signal line prior to the next read operation, wherein the preload circuit (108) comprises: - a first preload component (210); and - a second preload component (212); wherein the first preload component (210) and the second preload component (212) are individually controllable for loading the bit line signal line (BL) and the bit line bar signal line (BLB), wherein the bit cell is a component of a first memory bank; wherein the first preload component (210) is also configured to act as a second preload component for a second memory bank. Storage circuit according to claim 1, further comprising a pre-charge control circuit (110) which is configured to provide a first control signal (BLEQB1) to the first pre-charge component (210) and a second control signal (BLEQB2) to the second pre-charge component (212). Memory circuit according to claim 2, wherein the first preload component (210) comprises a transistor between a source node and the bit line signal line / bit line bar signal line (BL, BLB), wherein the transistor has a gate which is controlled by the first control signal (BLEQB1). Memory circuit according to claim 2, wherein the first preload component (210) has two transistors connected in series between a source node and the bit line signal line / bit line bar signal line (BL, BLB), wherein the two transistors have gates which are controlled by the first control signal (BLEQB1). Memory circuit according to claim 2, wherein the first preload component (210) comprises two transistors connected in series between a source node and the bit line signal line / bit line bar signal line (BL, BLB), wherein a first of the two transistors has a gate controlled by the first control signal (BLEQB1), wherein a second of the two transistors has a gate controlled by a signal based on the bit line signal line / bit line bar signal lines (BL, BLB). Memory circuit according to claim 2, wherein the first preload component (210) has a transistor between the second control signal (BLEQB2) and the bit line signal line / bit line bar signal lines (BL, BLB), wherein the transistor has a gate which is controlled by the first control signal (BLEQB1). Memory circuit according to claim 2, wherein the first preload component (210) comprises a transistor between a first node (606) connected to the bit line signal line (BL) and a second node (608) connected to the bit line bar signal line (BLB), wherein the transistor has a gate controlled by the first control signal (BLEQB1), wherein the second preload component (212) comprises two second-stage transistors whose gates are controlled by the second control signal (BLEQB2), wherein one second-stage transistor is positioned between a source node and the first node (606) and another second-stage transistor is positioned between the source node and the second node (608). Memory circuit according to claim 2, wherein the preload control circuit (110) is configured to activate the first preload component (210) prior to a word line signal transition indicating the completion of a read operation. Memory circuit according to claim 3, wherein the preload control circuit (110) is configured to activate the second preload circuit (108) after the word line signal transition. Storage circuit according to claim 1, wherein the first pre-charge component (210) is configured to charge at a first average rate, and the second pre-charge component (212) is configured, alone or in combination with the first pre-charge component (210), to charge at a second average rate, wherein the second average rate is higher than the first average rate. Memory circuit according to one of the preceding claims, wherein the preload circuit (108) is assigned to several bit cells, each bit cell being assigned to a different data word. Memory circuit according to one of the preceding claims, wherein the preload circuit (108) contains more than two preload components (210, 212). A method for controlling a multi-stage pre-load circuit (108) comprising a first pre-load component (210) and a second pre-load component (212) for charging a word line (WL) associated with a bit cell prior to a read operation, comprising: providing a first control signal (BLEQB1) to a first pre-load circuit (108), thereby preventing charging at least during part of a read operation, wherein a word line (WL) associated with the bit cell is activated during the read operation; providing a second control signal (BLEQB2) to a second pre-load circuit (108), thereby preventing charging during at least part of a read operation; transmitting the first control signal (BLEQB1) to activate charging by the first pre-load circuit (108) prior to deactivating the word line (WL);Transition of the second control signal (BLEQB2) to activate loading by the second preload circuit (108) after transition of the first control signal (BLEQB1), wherein the bit cell is a component of a first memory bank; wherein the first preload component (210) is also configured to act as a second preload component for a second memory bank. Method according to claim 13, wherein the first pre-charging component (210) charges at a first average rate when activated, and the second pre-charging component (212) charges at a second average rate when activated, wherein the second average rate is higher than the first average rate. Method according to claim 13 or 14, wherein the second control signal (BLEQB2) is passed through after deactivation of the word line (WL). Method according to any one of the preceding claims 13 to 15, further comprising: activating the word line (WL); and deactivating the word line (WL) after the transmission of the first control signal (BLEQB1). Method according to any one of the preceding claims 13 to 16, wherein one of the bit line signal lines (BL) and the bit line bar signal lines (BLB) transitions to a low state based on a state of the bit cell during the read operation; wherein activating the first pre-load circuit (108) initializes the one of the bit line (BL) and the bit line bar signal lines (BLB) to a charged state before the next read operation. Method according to any one of the preceding claims 13 to 17, wherein the bit line signal line / bit line bar signal line (BL, BLB) is loaded without changing any state of the bit cell.

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